U.S. patent number 5,219,782 [Application Number 07/860,473] was granted by the patent office on 1993-06-15 for sublithographic antifuse method for manufacturing.
This patent grant is currently assigned to Texas Instruments Incorporated. Invention is credited to Kueing-Long Chen, David K.-Y. Liu.
United States Patent |
5,219,782 |
Liu , et al. |
June 15, 1993 |
Sublithographic antifuse method for manufacturing
Abstract
In one described embodiment of the present invention, a method
for manufacturing a sublithographic semiconductor feature is
disclosed. This method comprises: depositing a feature material on
a substrate (14); depositing and patterning a resist material (20)
over said feature material; vertically, anisotropically etching
said feature material to form a feature pattern (18) with
substantially vertical sidewalls underlying said resist material
pattern (20); isotropically etching said feature pattern (18) such
that said feature pattern (18) sidewalls are undercut from beneath
said resist material pattern (20) to form a reduced geometry
feature (18) whereby said reduced geometry feature (18) has a
geometry less than that of the overlying resist material pattern
(20). Another described embodiment comprises an antifuse formed by
the above method wherein the antifuse dielectric (24) is a
nitride-oxide (N-O) layer. The further advantage gained using this
structure is that the programming voltage required is substantially
reduced due to the asymmetric current conduction characteristics of
the N-O dielectric. This lower programming voltage enhances the
scalability of this structure to smaller processes as the need for
high voltage transistors is reduced. Other devices, systems and
methods are also disclosed.
Inventors: |
Liu; David K.-Y. (Dallas,
TX), Chen; Kueing-Long (Plano, TX) |
Assignee: |
Texas Instruments Incorporated
(Dallas, TX)
|
Family
ID: |
25333298 |
Appl.
No.: |
07/860,473 |
Filed: |
March 30, 1992 |
Current U.S.
Class: |
438/600;
257/E23.147; 438/947 |
Current CPC
Class: |
H01L
23/5252 (20130101); Y10S 438/947 (20130101); H01L
2924/0002 (20130101); H01L 2924/0002 (20130101); H01L
2924/00 (20130101) |
Current International
Class: |
H01L
23/525 (20060101); H01L 23/52 (20060101); H01L
021/70 () |
Field of
Search: |
;437/47,52,60,228,233,922,48,195,200,229 |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
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|
0091430 |
|
Jul 1981 |
|
JP |
|
0053052 |
|
Mar 1985 |
|
JP |
|
0264740 |
|
Nov 1986 |
|
JP |
|
0131576 |
|
Jun 1988 |
|
JP |
|
0293967 |
|
Nov 1988 |
|
JP |
|
Primary Examiner: Thomas; Tom
Attorney, Agent or Firm: McCormack; Brian C. Kesterson;
James C. Donaldson; Richard L.
Claims
What is claimed is:
1. A method for manufacturing a sublithographic semiconductor
antifuse, said method comprising:
a) depositing a first conductive layer on a substrate;
b) depositing and patterning a resist material;
c) anisotropically etching said first conductive layer to form a
conductive pattern with substantially vertical sidewalls underlying
said resist material pattern;
e) isotropically etching said conductive pattern such that said
conductive pattern sidewalls are undercut from beneath said resist
material pattern;
f) removing said resist material; and
g) depositing an antifuse material overlying said conductive
pattern.
2. The method of claim 1 and further comprising the step of
depositing a second conductive layer over said antifuse
material.
3. The method of claim 2 wherein said second conductive layer is
polycrystalline silicon.
4. The method of claim 2 wherein said second conductive layer is a
silicide.
5. The method of claim 2 and further comprising the step of
depositing a sidewall insulator material on sidewalls of said
conductive pattern subsequent to said step of removing said resist
material and prior to said step of depositing said antifuse
material.
6. The method of claim 5 wherein said sidewall insulator is an
oxide.
7. The method of claim 5 wherein said sidewall insulator is a
conformably-deposited oxide layer which has been isotropically
etched such that only said oxide layer which lies along the
sidewalls of said conductive pattern having a vertical depth
greater than the remainder of said oxide layer remains to form said
sidewall insulator.
8. The method of claim 3 wherein said first conductive layer is
polycrystalline silicon.
9. The method of claim 3 wherein said first conductive layer is a
silicide.
10. The method of claim 3 wherein said antifuse material is an
oxide.
11. The method of claim 3 wherein said antifuse material is an
asymmetric antifuse material.
12. The method of claim 3 wherein said antifuse material is a
nitride-oxide layer.
13. A method for manufacturing a sublithographic semiconductor
antifuse, said method comprising:
a) depositing a first conductive layer on a substrate;
b) depositing and patterning a resist material;
c) anisotropically etching said first conductive layer to form a
conductive pattern with substantially vertical sidewalls underlying
said resist material pattern;
e) isotropically etching said conductive pattern such that said
conductive pattern sidewalls are undercut from beneath said resist
material pattern;
f) removing said resist material; and
g) forming a sidewall insulator material on sidewalls of said
conductive pattern;
h) depositing an antifuse material overlying said conductive
pattern.
14. The method of claim 13 and further comprising the step of
depositing a second conductive layer over said antifuse
material.
15. The method of claim 13 wherein said sidewall insulator is an
oxide.
16. The method of claim 13 wherein said sidewall insulator is a
conformably-deposited oxide layer which has been isotropically
etched such that only said oxide layer which lies along the
sidewalls of said conductive pattern having a vertical depth
greater than the remainder of said oxide layer remains to form said
sidewall insulator.
Description
FIELD OF THE INVENTION
This invention generally relates to a method for manufacturing
sublithographic semiconductor features and more particularly a
method for manufacturing a sublithographic antifuse.
BACKGROUND OF THE INVENTION
In many types of circuits, it is desirable to be able to control
feature size to increasingly smaller dimensions. Examples of these
situations would be an element where a small interface area is
desired to minimize parasitic capacitance. As examples: in a pn
junction diode it may be desirable to decrease the junction area to
reduce parasitic capacitance; in a polysilicon to polysilicon
interconnect within an integrated circuit it may be desirable to
minimize contact area to reduce parasitic capacitance; and, in an
antifuse device it may be desirable to minimize antifuse contact
area, again to reduce parasitic capacitance. Without limiting the
scope of the invention, its background is described in connection
with antifuses.
In integrated circuit fabrication, it is often desirable to allow a
system whereby a user may customize an integrated circuit to their
particular needs. Because of the great expense involved in
designing specific integrated circuits for many specific tasks,
programmable integrated circuits have been developed which allow
the user to program the integrated circuit to their specific needs.
An emerging type of programmable device is field programmable gate
arrays (FPGAs). These devices provide large arrays of fusible type
structures which allow the user to program the functional operation
of the devices by altering the conductive state of these fusible
devices. One such fusible device is called an antifuse. An antifuse
operates in the opposite of the traditional meaning of the term
"fuse". An antifuse is programmed by providing a voltage above a
threshold determined by the characteristics of the device which
causes a large current to pass through a dielectric layer between
two conductive layers. After this threshold voltage has been
reached, a conductive connection between the two conductive layers
is permanently established. This is opposite the traditional
meaning of a fuse in that when a high current is passed through a
traditional fuse, the fuse is burned open and thus a conductive
connection is broken.
As in all integrated circuits, it is desirable to provide a circuit
which operates as rapidly as possible. Prior art antifuse
structures provide horizontal areas which are limited by the
lithography capabilities used to fabricate the integrated circuit.
These devices are in arrays with a very thin dielectric. Because
these dielectrics must be very thin to keep the programming voltage
reasonably low, a very high capacitance is provided between the
conductive leads forming the gate array. In addition, because there
are many of these devices along a particular lead, the
resistive/capacitive (RC) time constant for a particular lead is
very high. This creates a time lag from when a voltage is applied
to a certain lead until the lead is charged up to the desired
voltage. Thus in order to minimize this time lag it is desirable to
minimize the capacitive coupling provided by an antifuse
element.
SUMMARY OF THE INVENTION
In prior art devices, the disadvantage of high capacitance was
traded against programming voltage by using an antifuse layer of
increased thickness. With increased antifuse thickness, increased
programming voltage is required to activate the antifuse. As device
geometries are decreased, these devices are less able to tolerate
the high programming voltages. These programming voltages, as a
undesired side effect, are applied across dielectric layers (i.e.
gate oxide, field oxide) for which antifusing is not desired.
Therefore increased antifuse thickness presents a barrier to
reduced device geometries in the prior art.
What then is needed is a device which reduces the difficulties of
capacitive loading without corresponding increases in programming
voltage. Described embodiments of the present invention in large
measure overcome these difficulties by decreasing the area of the
antifuse by using smaller features than those possible in prior art
devices. In this manner capacitance of an unprogrammed antifuse may
be decreased without increasing the programming voltage.
In one described embodiment of the present invention, a method for
manufacturing a sublithographic semiconductor feature is disclosed.
This method comprises: depositing a feature material on a
substrate; depositing and patterning a resist material over said
feature material; vertically, anisotropically etching said feature
material to form a feature pattern with substantially vertical
sidewalls underlying said resist material pattern; isotropically
etching said feature pattern such that said feature pattern
sidewalls are undercut from beneath said resist material pattern to
form a reduced geometry feature whereby said reduced geometry
feature has a geometry less than that of the overlying resist
material pattern.
In another described embodiment of the present invention, the
method described above is applied to the manufacturing of an
antifuse. In this antifuse one electrode of the antifuse is the
above described reduced geometry semiconductor feature formed from
the feature material as described above. This antifuse is formed by
depositing an antifuse layer over the reduced geometry feature and
depositing a second electrode over the antifuse layer. In this
manner the antifuse area is reduced over that possible using
standard lithographic process and capacitance is reduced
correspondingly.
Another described embodiment comprises an antifuse wherein the
antifuse dielectric is a nitride-oxide (N 0) layer. The further
advantage gained using this structure is that the programming
voltage required is substantially reduced due to the asymmetric
current conduction characteristics of the N-O dielectric. This
lower programming voltage enhances the scalability of this
structure to smaller processes as the need for high voltage
transistors is reduced.
Another embodiment of the present invention includes an array of
antifuses arranged in rows and columns for use in programmable
logic integrated circuit devices such as a field-programmable gate
array (FPGA), comprising: a plurality of conductive features, each
formed as the reduced geometry feature described above; an
insulating layer formed on a plurality of feature sidewalls of said
first plurality of conductive features; a dielectric layer formed
over said plurality of feature sidewalls and said plurality of
conductive features; and a second plurality of conductive features
running perpendicular to said first plurality of conductive
features, said second plurality of conductive features extending
onto said dielectric layer over said first plurality of conductive
features such that an antifuse via is formed. In another embodiment
of the present invention, said first and/or second plurality of
conductive features comprise polycrystalline silicon and a
conductive material selected from the group of titanium, tungsten,
molybdenum, platinum, titanium silicide, tungsten silicide,
molybdenum silicide, platinum silicide, titanium nitride and
combinations thereof.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1, in partial cross section, illustrates a microelectronic
device formed in accordance with the prior art.
FIG. 2, in partial cross section, illustrates a microelectronic
device formed in accordance with a preferred embodiment of the
present invention, used to fabricate other embodiments of the
present invention.
FIG. 3a-3f, in partial cross section, illustrate progressive
formation of a microelectronic device formed in accordance with the
preferred embodiment of the present invention, used to fabricate
other embodiments of the present invention.
FIG. 4 is a plot of the current vs. voltage characteristics of the
N-O dielectric antifuse.
FIG. 5 is a block diagram of a Field Programmable Gate Array device
embodying the anti fuse of the invention herein disclosed.
Corresponding numerals and symbols in the different figures refer
to corresponding parts unless otherwise indicated.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
As shown in Prior Art FIG. 1, a substrate 14 is initially provided.
A first oxide layer 16 overlies the substrate 14. A first
polysilicon layer 18 overlies the first oxide layer 16. A second
oxide layer 19 overlies the first polysilicon layer 18 and is
patterned such that an area of the polysilicon remains exposed.
Antifuse dielectric material 24 overlies the exposed first
polysilicon layer 18 and a second polysilicon layer 26 is formed
over the antifuse material 24 and the second oxide layer 19.
Typical thickness of the first and second polysilicon layers is
between 2000 and 4000 .ANG.. The capacitance between first
conductor 18 and second conductor 26 of an unprogrammed device is
determined by the thickness of antifuse material 24 and interfacial
surface area between antifuse material 24 and second conductor 26.
Reductions in prior art capacitance have been limited to: using
minimum geometry lithography to form the conductive patterns; and,
increasing thickness of antifuse material 24. These two methods
have conflicting requirements. Increasing thickness of antifuse
dielectric 24 also increases programming voltages. However,
increased programming voltages present a barrier to decreasing
geometries because the higher voltages are more likely to breakdown
dielectric material in unintended areas.
A preferred embodiment of the present invention is illustrated, in
partial cross section, in FIG. 2. A first oxide layer 16 overlies
the substrate 14. A reduced geometry feature or reduced geometry
first conductor 18 overlies oxide 16. The reduced geometry first
conductor 18 has a sidewall insulator 22 about its perimeter. An
antifuse layer 24 overlies the reduced geometry conductor 18 and
its associated sidewall insulator 22. A second conductor 26
overlies the antifuse material 24 such that an antifuse is formed
between the top of the reduced geometry first conductor 18 and the
second conductor 26.
FIG. 3a, in partial cross section, illustrates a microelectronic
device 12 formed in accordance with a preferred embodiment of the
present invention after a first processing stage. As shown in FIG.
3a, a substrate 14 is initially provided. Substrate 14 may be any
of a number of materials but in this preferred embodiment comprises
crystalline silicon, thus allowing the fabrication of other devices
such as transistors and diodes. Silicon dioxide layer 16 is formed
on the surface of substrate 14 using thermal oxidation to a
thickness of approximately 5000 .ANG.. Feature material or
polycrystalline silicon layer 18 is formed on the surface of
silicon dioxide layer 16 using chemical vapor deposition.
Polycrystalline silicon layer 18 has a thickness of between 2000
and 4000 .ANG. in this preferred embodiment. To provide additional
conductivity and thus reduce the resistance of polycrystalline
silicon layer 18, additional materials such as titanium, tungsten,
molybdenum, platinum, titanium silicide, tungsten silicide,
molybdenum silicide, platinum silicide or titanium nitride may be
incorporated into polycrystalline silicon layer 18 as additional
layers or incorporated into the material itself. In addition,
combinations of these materials or other highly conductive
materials may be incorporated into polycrystalline silicon layer
18. The use of polycrystalline silicon in layer 18 is exemplary and
many other materials will become apparent to those skilled in the
art in light of this specification and are considered within the
scope of the present invention. The preferred embodiment structure
shows the feature material or polycrystalline silicon layer 18
being deposited over the oxide layer 16 to provide isolation from
underlying devices.
Referring now to FIG. 3b, a photoresist 20 has been formed and
patterned using lithographic techniques well known in the art.
Referring now to FIG. 3c, polycrystalline layer 18 is patterned to
form the bottom conductor of the antifuse. This patterning is
performed using common photolithographic techniques, typically
followed by an anisotropic dry etch to remove undefined
polysilicon. In an illustrative embodiment, this patterned
polysilicon layer 18 has a linewidth, L=0.8 .mu.m. as shown in FIG.
3c.
Referring now to FIG. 3d, the photoresist 20 is kept in place for a
subsequent isotropic etch of the polysilicon layer 18. This second
etch is monitored to stop when the desirable profile has been
achieved. By this process a reduced geometry feature or reduced
geometry patterned polysilicon layer 18 has been effected. In an
illustrative embodiment, a 0.2 .mu.m undercut has been achieved
from each side of the polysilicon, leaving a reduced geometry
linewidth, RGL=0.4 .mu.m at the top of the reduced geometry
polysilicon layer 18. If the polysilicon layer 18 is square shaped,
with equal depth into the page as reduced geometry linewidth shown,
and if a similar etch profile has been achieved in this dimension,
then a 75% reduction in the area of the top surface of the
polysilicon 18 will have been achieved, corresponding to an
unprogrammed antifuse capacitance of 1/4 the original unprogrammed
antifuse capacitance.
With reference now to FIG. 3e, a partial cross section of the
preferred embodiment device 12 is shown after removal of the
photoresist 20, deposition of a conformal insulator layer and a
subsequent vertical anisotropic etch. Due to greater vertical depth
of a conformal insulator layer over edges of the polysilicon layer
18 topography, a sidewall insulator 22 remains on the sides of the
polysilicon layer 18 after the anisotropic etch. As an alternative
process, if the roughness of the final polysilicon layer 18 is a
concern, a thin nitride layer may be deposited prior to the
insulator deposition and etch. Sidewall insulator 22 serves to
further reduce the capacitance of an unprogrammed antifuse by
reducing the exposed area of polysilicon layer 18. As an
alternative embodiment, the step of depositing sidewall insulator
22 may be eliminated altogether.
Now referring to FIG. 3f, an antifuse layer 24, and another
polysilicon layer 26 is deposited. Polycrystalline silicon layer 26
has a thickness of between 2000 and 4000 .ANG. in this preferred
embodiment. To provide additional conductivity and thus reduce the
resistance of polycrystalline silicon layer 26, additional
materials such as titanium, tungsten, molybdenum, platinum,
titanium silicide, tungsten silicide, molybdenum silicide, platinum
silicide or titanium nitride may be incorporated into
polycrystalline silicon layer 26 as additional layers or
incorporated into the material itself. In addition, combinations of
these materials or other highly conductive materials may be
incorporated into polycrystalline silicon layer 26. The use of
polycrystalline silicon in layer 26 is exemplary and many other
materials will become apparent to those skilled in the art in light
of this specification and are considered within the scope of the
present invention. The actual antifuse area is the antifuse
material interposed between the reduced top surface of the
remaining polysilicon layer 18 and the bottom surface of the
polysilicon layer 26.
Referring to the processes described in FIGS. 3a-3f, silicon
dioxide layer 16 may be formed by chemical vapor deposition or
thermal oxidation of substrate crystalline silicon layer 14. If
thermal oxidation is used, then an additional thickness of
substrate 14 must be provided to allow for consumption of this
additional area by the thermal oxidation process. In the present
embodiment, silicon dioxide layer 16 comprises approximately 2000
.ANG. of silicon dioxide. In additional embodiments, silicon
dioxide layer 16 may be other insulators or compound insulators to
provide the function of silicon dioxide layer 16. The thickness of
silicon dioxide layer 16 is provided to minimize the capacitive
coupling between conductive layers to be formed on the surface of
silicon dioxide layer 16 and underlying substrate crystalline
silicon layer 14. Preferably, the vertical anisotropic etch
processes described are accomplished using a plasma of hydrofluoric
acid to etch sidewall insulators 22 (typically SiO.sub.2) and a
plasma of carbon tetrachloride to etch polycrystalline silicon
layer 18. This carbon tetrachloride etch is carefully controlled by
controlling the flow rates, temperature and plasma energy to
provide a high rate of selectivity of polycrystalline silicon over
silicon dioxide. The precise settings of the etching process are
highly dependent upon the equipment used. This selectivity allows
the etch to stop when the etch passes through polycrystalline
silicon layer 18 to silicon dioxide layer 16. Although it is
preferable to use a highly selective etch, this step is not
critical in that silicon dioxide layer 16 is very thick and allows
for some etching of silicon dioxide layer 16.
Still referring to the processes described in FIGS. 3a-3f, the
antifuse layer 24 is preferably silicon dioxide. As an alternative
embodiment, an antifuse with asymmetric and lower voltage
programming characteristics can be utilized. This asymmetric
antifuse is formed by depositing a layer of silicon nitride on the
surface of the structure of FIG. 3e. This is accomplished using
chemical vapor deposition in an atmosphere such as silane and
ammonia. The silicon nitride layer is then subjected to thermal
oxidation in a steam ambient to provide an oxynitride layer on the
surface of the silicon nitride layer. The use of the nitride
oxynitride (N-O) dielectric provides a two way characteristic for
the breakdown of the antifuse 24.
FIG. 4 depicts the current vs. voltage characteristic for the
process of programming the N-O dielectric antifuse described above.
It is important to note that the current vs. voltage (IV)
characteristic is only for the programming step. Once the device
has been programmed, it retains new characteristics corresponding
to a highly conductive state. The "A" figure of FIG. 4 shows the IV
characteristic for the positive direction. In this instance, a
potential is applied to polycrystalline silicon layer 26 relative
to polycrystalline silicon layer 18 and antifuse layer 24 provides
a breakdown voltage of approximately 131/2 volts. The "B" figure of
FIG. 4 shows the IV characteristic for the negative direction. In
this instance, a positive potential is applied to polycrystalline
silicon layer 18 relative to the polycrystalline silicon layer 26
the breakdown voltage is approximately 101/2 volts. This breakdown
voltage is less than in prior art antifuses, and has been
accomplished without decrease in device speed or manufacturing
efficiency.
FIG. 5 depicts a Field Programmable Gate Array (FPGA) device
employing the antifuse of FIG. 2. An array of antifuse circuits 30
is constructed, each antifuse being formed as described above. A
plurality of bottom layer conductors 38 is formed in parallel rows,
an antifuse dielectric 40 is formed upon each at an intersection
point in the array, and a plurality of top layer conductors 32 is
formed in parallel to one another and perpendicular to the bottom
layer conductors 38 such than an antifuse is formed at each of the
intersections in the array. A plurality of associated universal
logic modules is formed (36,34) such that the inputs and outputs
are tied to either bottom or top level conductors feeding the
antifuse array. The user can then selectively interconnect the
logic gates in the universal logic modules by programming selected
ones of the antifuse circuits in the array, and thereby form
various functions as required by the user's application.
A few preferred embodiments have been described in detail
hereinabove. It is to be understood that the scope of the invention
also comprehends embodiments different from those described, yet
within the scope of the claims. While this invention has been
described with reference to illustrative embodiments, this
description is not intended to be construed in a limiting sense.
Various modifications and combinations of the illustrative
embodiments, as well as other embodiments of the invention, will be
apparent to persons skilled in the art upon reference to the
description. For example, although the illustrative embodiments
were described as antifuse devices, a reduced feature size
capacitor could be formed using essentially the same process, but
thickening the dielectric so it did not have antifusing
characteristics. A reduced feature area diode could be formed by
forming a doped reduced area polysilicon feature by the process
described above and by forming an oppositely doped polysilicon
layer over the reduced area polysilicon feature--eliminating the
step of forming a dielectric layer between the two polysilicon
conductive layers. It is therefore intended that the appended
claims encompass any such modifications or embodiments.
* * * * *