U.S. patent number 5,014,108 [Application Number 07/523,427] was granted by the patent office on 1991-05-07 for mesfet for dielectrically isolated integrated circuits.
This patent grant is currently assigned to Harris Corporation. Invention is credited to James D. Beasom, William E. O'Mara, Jr..
United States Patent |
5,014,108 |
O'Mara, Jr. , et
al. |
May 7, 1991 |
MESFET for dielectrically isolated integrated circuits
Abstract
A MESFET wherein a Schottky top gate which extends across the
channel region between the source and drain regions and beyond
sides of the dielectric isolation in which the device is built at
two points. The bottom gate also extends beyond the dielectric
isolation below the surface of the island and intersects the bottom
of the source and drain regions. Where a bottom gate contact region
forms an annulus encompassing the source and drain, the top gate
extends across the channel and only onto sides of the bottom gate
contact region at two points. The source and drain regions which
are formed are sufficiently spaced from the dielectric isolation so
as not to effect the I.sub.DSS resulting from variation in the
island size.
Inventors: |
O'Mara, Jr.; William E.
(Kingston, NH), Beasom; James D. (Melbourne Village,
FL) |
Assignee: |
Harris Corporation (Melbourne,
FL)
|
Family
ID: |
24084954 |
Appl.
No.: |
07/523,427 |
Filed: |
May 15, 1990 |
Current U.S.
Class: |
257/506; 257/272;
257/279; 257/280; 257/476; 257/906; 257/E21.56; 257/E29.312;
257/E29.317; 257/E29.319 |
Current CPC
Class: |
H01L
21/76297 (20130101); H01L 29/808 (20130101); H01L
29/812 (20130101); H01L 29/8124 (20130101); Y10S
257/906 (20130101) |
Current International
Class: |
H01L
21/762 (20060101); H01L 21/70 (20060101); H01L
29/66 (20060101); H01L 29/812 (20060101); H01L
29/808 (20060101); H01L 027/12 (); H01L 029/48 ();
H01L 029/56 (); H01L 029/80 () |
Field of
Search: |
;357/49,22,15 |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
|
|
|
|
|
|
|
61-018180 |
|
Jan 1986 |
|
JP |
|
1-169961 |
|
Jul 1989 |
|
JP |
|
Other References
Ziegler et al., "Self Isolating Bathtub Collector for a Planar
Transistor," IBM Tech. Discl, vol. 14, #5, 10-71, pp.
1635-1636..
|
Primary Examiner: James; Andrew J.
Assistant Examiner: Deal; Cynthia S.
Attorney, Agent or Firm: Barnes & Thornburg
Claims
What is claimed is:
1. A MESFET comprising:
an island of a first conductivity type isolated by dielectric
isolation from a substrate;
source and drain regions of said first conductivity type spaced in
said island and separated by a channel region of said island;
a bottom gate region of a second conductivity type in said island
below a top surface of said island and extending laterally in all
directions at least to said dielectric isolation to define a bottom
of said channel region;
a top gate forming a Schottky barrier with said top surface of said
island and extending across said channel beyond two opposing sides
of said dielectric isolation at two points onto said substrate.
2. A MESFET according to claim 1, wherein said island is silicon
and said top gate is metal.
3. A MESFET according to claim 1, wherein said source and drain
regions extend to said bottom gate region.
4. A MESFET according to claim 1, including a bottom gate contact
region of said second conductivity type extending down from said
top surface to said bottom gate region and being exterior said
channel region.
5. A MESFET according to claim 4, wherein said bottom gate contact
region is an annulus encompassing said source and drain
regions.
6. A MESFET according to claim 4, wherein said top gate contacts
said bottom gate contact region.
7. A MESFET according to claim 1, wherein said source and drain
regions have a higher impurity concentration than said island.
8. A MESFET comprising:
an island of a first conductivity type isolated from a
substrate;
source and drain regions of said first conductivity type spaced in
said island and separated by a channel region of said island;
a bottom gate region of a second conductivity type in said island
below a top surface of said island and extending laterally beyond
said source and drain regions to define a bottom of said channel
region;
an annular bottom gate contact region of said second conductivity
type extending down from said top surface to said bottom gate
region and encompassing said source and drain regions; and
a top gate forming a Schottky barrier with said top surface of said
island and extending across said channel and onto said bottom gate
contact region at two points.
9. A MESFET according to claim 8, wherein said source and drain
regions extend to said bottom gate region.
10. A MESFET comprising:
an island of a first conductivity type isolate by dielectric
isolation from a conductive substrate;
source and drain regions of said first conductivity type spaced in
said island and separated by a channel region of said island;
a bottom gate region of a second conductivity type in said island
below a top surface of said island to define a bottom of said
channel region;
a top gate forming a Schottky barrier with said top surface of said
island and extending across said channel beyond two opposing sides
of said dielectric isolation at two points onto said substrate;
a contact region in said substrate exterior said island; and
means for biasing said substrate sufficiently to turn off a
parasitic PMOS between said top and bottom gates.
11. A MESFET according to claim 1, wherein said bottom gate region
is spaced from a bottom surface of said island.
12. A MESFET comprising:
a first region of a first conductivity type;
source and drain regions of said first conductivity type spaced in
said first region and separated by a channel region of said first
region;
a bottom gate region of a second conductivity type in said first
region below a top surface of said first region and extending
laterally beyond said source and drain regions to define a bottom
of said channel region;
an annular bottom gate contact region of said second conductivity
type extending down from said top surface to said bottom gate
region and encompassing said source and drain regions; and
a tope gate forming a Schottky barrier with said top surface of
said first region and extending across said channel and onto said
bottom gate contact region at two points.
13. A MESFET according to claim 12, wherein said bottom gate region
is spaced from a bottom surface of said first region.
Description
BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates generally to field effect transistors
and more specifically to an improved radiation hard MESFET.
Junction isolated, junction field effect transistors (JFET)
generally include a source and drain region spaced from each other
by a channel region. Surrounding the source and drain region is a
high impurity region which acts not only as a guard ring, but as a
contact to the bottom gate region which extends below the channel
and between the source and drain regions to define the bottom of
the channel. The top gate is generally a diffused region of
opposite conductivity type to the channel region. By appropriately
biasing the top and bottom gates, the channel between the source
and drain regions is interrupted. The top gate is generally
connected to the bottom gate by extending the top gate diffusion
across the channel and into the bottom gate contact. A typical
example is shown in U.S. Pat. No. 4,187,514.
In environments which require radiation hard devices, total dose
radiation causes inversion around the top gate. This is detrimental
to the operation of the JFETs and is undesirable.
Another form of junction field effect transistors is a metal
Schottky junction field effect transistor (MESFET). The top gate is
of a material which forms a Schottky barrier with the channel
region.
Thus, it is an object of the present invention to provide a
radiation hard field effect transistor.
Another object of the present invention is to provide a MESFET
which is radiation hard.
An even further object of the present invention is to provide a
leakage free MESFET.
An even further object of the present invention is to provide a
MESFET whose operating characteristics are not effected by
variations in dielectric isolated island size.
These and other objects of the invention are attained by using a
Schottky top gate which extends across the channel region between
the source and drain regions and beyond sides of the dielectric
isolation in which the device is built at two points. The bottom
gate also extends beyond the dielectric isolation below the surface
of the island and intersects the bottom of the source and drain
regions. The length of the Schottky barrier top gate and the bottom
gate diffusion are sufficiently large so as to extend beyond the
dielectric isolation for the maximum anticipated island size which
results from the dielectric isolation process. Thus, the top and
bottom gates completely define the channel and prevent any leakage
current beyond the gates. The source and drain regions which are
formed are sufficiently spaced from the dielectric isolation so as
not to effect the I.sub.DSS resulting from variation in the island
size. A substrate contact is provided to bias the substrate and
turn off a parasitic PMOS device between the top and bottom
gates.
A bottom gate contact region may be provided extending from the
surface down to the bottom gate exterior the channel region defined
by the source and drain regions. Preferably, this bottom gate
contact region is formed as an annulus encompassing the source and
drain regions. In such an application, where it is desirable to
connect the top and bottom gates together, the Schottky top gate
need only extend across the channel and onto the bottom gate
contact region at two points. With this annulus structure, the
MESFET structure may be used in other isolated islands whether they
be junction or dielectrically isolated.
Other objects, advantages and novel features of the present
invention will become apparent from the following detailed
description of the invention when considered in conjunction with
the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cut-away perspective of a MESFET according to the
principles of the present invention.
FIG. 2 is a plan view of the MESFET of FIG. 1.
FIG. 3 is a cut-away perspective of a MESFET incorporating a bottom
gate contact region according to the principles of the present
invention.
FIG. 4 is a plan view of a MESFET including an annulus bottom gate
contact region according to the principles of the present
invention.
cl DETAILED DESCRIPTION OF THE DRAWINGS
A MESFET is shown in FIGS. 1 and 2 as being formed in a
semiconductor island 10 separated from a substrate 12 by dielectric
isolation 14. For purposes of example, the island 10 has an N
conductivity impurity type. N+ source and drain regions 16 and 18
are formed spaced in the island 10 and separated from each other by
portion 20 of the island 10 which forms the channel of the MESFET.
A P+ bottom gate region 22 is formed in and below the surface of
the island 10. The bottom gate 22 intersects the bottom of the
source and drain regions 16 and 18 and extends outside the
dielectric isolation 14. Thus, the bottom gate 22 defines the
bottom of the channel region.
The top gate 24 is of a material which forms a Schottky barrier
with the channel region 20 which is silicon. The gate material 24
would be selected from the group of two percent silicon doped
aluminum, W, Pt Si, W Si, etc. The top gate 24 extends across the
channel region 20 and outside opposed sides of the dielectric
isolation 14. Thus, the gate extends across all possible channel
regions at the surface of the island 10 and prevents any leakage or
parasitic devices.
The bottom or back gate 22 formed by the P+ implant is electrically
floating in FIGS. 1 and 2. In many applications this is
undesirable. Electrical connection can be achieved by adding a P
region 30 which extends from the substrate or island surface down
to and intersects the P+ bottom gate 22 as illustrated in FIG. 3.
Separate contact can be made to the bottom gate through bottom gate
contact region 30 and to the top gate through top gate metal
24.
If connection of the top gate to the bottom gate is desirable or
acceptable, the bottom gate contact region may be formed as an
annulus extending down to the bottom gate 22 surrounding the source
and drain regions. This is illustrated as P region 32 in FIG. 4. In
this embodiment, the Schottky top gate 24 extends across the
channel region and onto the P+ top gate annulus 32 at opposing
sides. The top gate metal 24 need not extend over the island edge
or isolation region 14 as in the other embodiments. The ring 32
should be formed inside the smallest expected or minimum location
of the dielectric isolated region 14.
Since the annulus bottom gate contact region 32 extends down to and
intersects the bottom gate 22 which itself extends and is connected
to the bottom of the source and drain region 16, 18, the bottom
gate and bottom gate contact separates the channel region 20 of the
island 10 from the remainder from the island 10. Thus, this
structure can be used with dielectric or junction isolated regions.
This structure also prevents the turning on of a parasitic PMOS of
the embodiment of the FIGS. 1-3. This PMOS would include the P+
bottom gate 22 and the Schottky top metal 24 as the source and
drain regions with the N region forming the body and the possibly
biased substrate 12 being the gate with the dielectric isolation 14
forming the gate dielectric. In these other embodiments, the
substrate 12 should be connected to a sufficiently positive
voltage, at region 34 for example in FIG. 3, such that the PMOS
does not turn on.
While the source and drain regions 16, 18 may be formed by
diffusion, the bottom gate region 22 is formed by ion implantation.
Preferably the bottom gate region of the ion implantation is formed
after the source and drain regions so as to not be effected by the
high temperature processing of the deposition and diffusion.
The present device is compatible with bipolar processing and
requires very few additional steps. These steps would include the
ion implantation for the bottom gate 22. The processing of the IC
to form the dielectrical isolation as well as preparing the island
10 for Schottky contacts is described in Piotrowski U.S. Pat. No.
4,260,431, which is incorporated herein by reference.
The size and location of the source and drain region 16, 18 are
selected so as to be displaced from the dielectric isolation 14 so
that the I.sub.DSS is not effected by the island size variation. As
is well known, the island size may vary between 14 min and 14 max
as illustrated in FIG. 2. This variation results from the
processing used to form the dielectric isolated islands 10. The
dimensions of the source and drain regions 16, 18 are selected to
assure that they maintain a distance from the dielectric isolation
edge 14 min. Similarly, to assure that the top gate 24 and the
bottom gate 22 extend out beyond the dielectric isolation 14, both
have lateral dimensions which would exceed the anticipated maximum
dielectric island dimensions 14 max.
Although the MESFET of FIGS. 1 and 2 has been described as an
N-channel device, P-channel devices may also be formed using the
same method and dimensions Also, although the top gate 24 has been
shown as extending across opposed sides of the dielectric isolation
14 and the bottom gate contact region 32, they may extend across
any two sides or one side at two points as long as they divide the
island 10 into at least two regions. Thus an L shape top gate wold
extent across adjacent edges.
Although the present invention has been described and illustrated
in detail, it is to be clearly understood that the same is by way
of illustration and example only, and is not to be taken by way of
limitation. The spirit and scope of the present invention are to be
limited only by the terms of the appended claims.
* * * * *