| Patent | Date |
|---|
PMOS depletable drain extension made from NMOS dual depletable drain extensions
Grant RE45,814 - Beasom November 24, 2 | 2015-11-24 |
Base for a NPN bipolar transistor
Grant 9,111,955 - Beasom August 18, 2 | 2015-08-18 |
Method of manufacturing a MOSFET structure
Grant RE44,730 - Beasom January 28, 2 | 2014-01-28 |
Method of manufacturing a MOSFET structure
Grant RE44,720 - Beasom January 21, 2 | 2014-01-21 |
PMOS depletable drain extension made from NMOS dual depletable drain extensions
Grant RE44,430 - Beasom August 13, 2 | 2013-08-13 |
Bipolar method and structure having improved BVCEO/RCS trade-off made with depletable collector columns
Grant RE44,140 - Beasom April 9, 2 | 2013-04-09 |
Integrated process for thin film resistors with silicides
Grant 8,338,914 - Gasner , et al. December 25, 2 | 2012-12-25 |
Bipolar method and structure having improved BVCEO/RCS trade-off made with depletable collector columns
Grant RE43,042 - Beasom December 27, 2 | 2011-12-27 |
Semiconductor device with a reduced mask count buried layer
Grant RE41,477 - Beasom August 10, 2 | 2010-08-10 |
Base For A Npn Bipolar Transistor
App 20100129975 - Beasom; James D. | 2010-05-27 |
Integrated Process For Thin Film Resistors With Silicides
App 20100117198 - Gasner; John T. ; et al. | 2010-05-13 |
Method of manufacturing a MOSFET structure
Grant 7,687,336 - Beasom March 30, 2 | 2010-03-30 |
Integrated process for thin film resistors with silicides
Grant 7,662,692 - Gasner , et al. February 16, 2 | 2010-02-16 |
Lateral DMOS structure with lateral extension structure for reduced charge trapping in gate oxide
Grant 7,655,515 - Beasom February 2, 2 | 2010-02-02 |
Method of forming an integrated circuit having a device wafer with a diffused doped backside layer
Grant 7,605,052 - Czagas , et al. October 20, 2 | 2009-10-20 |
Sealed nitride layer for integrated circuits
Grant 7,605,445 - Beasom October 20, 2 | 2009-10-20 |
Bipolar transistor having variable value emitter ballast resistors
Grant 7,564,117 - Beasom July 21, 2 | 2009-07-21 |
Method of manufacturing lateral MOSFET structure of an integrated circuit having separated device regions
Grant 7,410,860 - Beasom August 12, 2 | 2008-08-12 |
Method Of Manufacturing A Mosfet Structure
App 20080176372 - Beasom; James D. | 2008-07-24 |
Bipolar Transistor Having Variable Value Emitter Ballast Resistors
App 20080087983 - Beasom; James D. | 2008-04-17 |
Integrated process for thin film resistors with silicides
Grant 7,341,958 - Gasner , et al. March 11, 2 | 2008-03-11 |
Method Of Forming An Integrated Circuit Having A Device Wafer With A Diffused Doped Backside Layer
App 20080026595 - Czagas; Joseph A. ; et al. | 2008-01-31 |
Integrated Process For Thin Film Resistors With Silicides
App 20080026536 - Gasner; John T. ; et al. | 2008-01-31 |
Bipolar transistor for an integrated circuit having variable value emitter ballast resistors
Grant 7,314,791 - Beasom January 1, 2 | 2008-01-01 |
Integrated circuit having a device wafer with a diffused doped backside layer
Grant 7,285,475 - Czagas , et al. October 23, 2 | 2007-10-23 |
Integrated circuit with a PN junction diode
Grant 7,161,223 - Beasom January 9, 2 | 2007-01-09 |
Sealed nitride layer for integrated circuits
App 20060231864 - Beasom; James D. | 2006-10-19 |
Integrated process for thin film resistors with silicides
App 20060166505 - Gasner; John T. ; et al. | 2006-07-27 |
Sealed nitride layer for integrated circuits
Grant 7,071,111 - Beasom July 4, 2 | 2006-07-04 |
Integrated circuit with a MOS capacitor
Grant 7,042,064 - Beasom May 9, 2 | 2006-05-09 |
Bipolar transistor for an integrated circuit having variable value emitter ballast resistors
App 20060063341 - Beasom; James D. | 2006-03-23 |
Method of manufacturing lateral MOSFET structure of an integrated circuit having separated device regions
App 20060024897 - Beasom; James D. | 2006-02-02 |
Integrated circuit having a device wafer with a diffused doped backside layer
App 20060009007 - Czagas; Joseph A. ; et al. | 2006-01-12 |
Reduced mask count buried layer process
Grant 6,979,624 - Beasom December 27, 2 | 2005-12-27 |
Devices with patterned wells and method for forming same
Grant 6,979,885 - Beasom December 27, 2 | 2005-12-27 |
Method of manufacturing lateral MOSFET structure of an integrated circuit having separated device regions
Grant 6,974,753 - Beasom December 13, 2 | 2005-12-13 |
Lateral DMOS structure with lateral extension structure for reduced charge trapping in gate oxide
App 20050214995 - Beasom, James D. | 2005-09-29 |
Integrated circuit having a device wafer with a diffused doped backside layer
Grant 6,946,364 - Czagas , et al. September 20, 2 | 2005-09-20 |
Bipolar transistor for an integrated circuit having variable value emitter ballast resistors
Grant 6,946,720 - Beasom September 20, 2 | 2005-09-20 |
Integrated circuit with a MOS structure having reduced parasitic bipolar transistor action
Grant 6,902,967 - Beasom June 7, 2 | 2005-06-07 |
MOS integrated circuit with reduced on resistance
Grant 6,897,103 - Beasom May 24, 2 | 2005-05-24 |
Lateral DMOS structure with lateral extension structure for reduced charge trapping in gate oxide
Grant 6,894,349 - Beasom May 17, 2 | 2005-05-17 |
Integrated circuit having a device wafer with a diffused doped backside layer
Grant 6,867,495 - Czagas , et al. March 15, 2 | 2005-03-15 |
Lateral MOSFET structure of an integrated circuit having separated device regions
App 20050048726 - Beasom, James D. | 2005-03-03 |
Integrated circuit with a MOS capacitor
App 20050045934 - Beasom, James D. | 2005-03-03 |
Lateral MOSFET structure of an integrated circuit having separated device regions
App 20050035424 - Beasom, James D. | 2005-02-17 |
Base for a NPN bipolar transistor
App 20050029626 - Beasom, James D. | 2005-02-10 |
Integrated circuit with a MOS capacitor
Grant 6,835,628 - Beasom December 28, 2 | 2004-12-28 |
Lateral MOSFET structure of an integrated circuit having separated device regions
Grant 6,822,292 - Beasom November 23, 2 | 2004-11-23 |
Base for a NPN bipolar transistor
Grant 6,822,314 - Beasom November 23, 2 | 2004-11-23 |
Integrated circuit with a MOS structure having reduced parasitic bipolar transistor action
App 20040180485 - Beasom, James D. | 2004-09-16 |
Reduced mask count buried layer process
App 20040171229 - Beasom, James D. | 2004-09-02 |
Integrated circuit having a device wafer with a diffused doped backside layer
App 20040161905 - Czagas, Joseph A. ; et al. | 2004-08-19 |
Bipolar transistor for an integrated circuit having variable value emitter ballast resistors
App 20040159912 - Beasom, James D. | 2004-08-19 |
Integrated circuit with a MOS structure having reduced parasitic bipolar transistor action
Grant 6,765,247 - Beasom July 20, 2 | 2004-07-20 |
Base for a NPN bipolar transistor
App 20030230789 - Beasom, James D. | 2003-12-18 |
Devices with patterned wells and method for forming same
App 20030178701 - Beasom, James D. | 2003-09-25 |
Breakdown improvement method and sturcture for lateral DMOS device
Grant 6,614,088 - Beasom September 2, 2 | 2003-09-02 |
Reduced mask count buried layer process
App 20030162360 - Beasom, James D. | 2003-08-28 |
Semiconductor Device With A Reduced Mask Count Buried Layer
App 20030160296 - Beasom, James D. | 2003-08-28 |
Mos integrated circuit with reduced on resistance
App 20030157756 - Beasom, James D. | 2003-08-21 |
Self-alignment of seperated regions in a lateral MOSFET structure of an integrated circuit
App 20030096481 - Beasom, James D. | 2003-05-22 |
Integrated circuit with a MOS capacitor
App 20030087496 - Beasom, James D. | 2003-05-08 |
Sealed nitride layer for integrated circuits
App 20030080395 - Beasom, James D. | 2003-05-01 |
Integrated circuit with a MOS structure having reduced parasitic bipolar transistor action
App 20030071291 - Beasom, James D. | 2003-04-17 |
MOS integrated circuit with reduced on resistance
App 20030006482 - Beasom, James D. | 2003-01-09 |
Lateral DMOS structure with lateral extension structure for reduced charge trapping in gate oxide
App 20020185696 - Beasom, James D. | 2002-12-12 |
Devices With Patterned Wells And Method For Forming Same
App 20020158312 - BEASOM, JAMES D. | 2002-10-31 |
Integrated circuit having a device wafer with a diffused doped backside layer
App 20020072200 - Czagas, Joseph A. ; et al. | 2002-06-13 |
Biasing of island-surrounding material to suppress reduction of breakdown voltage due to field plate acting on buried layer/island junction between high and low impurity concentration regions
Grant 6,184,565 - Beasom February 6, 2 | 2001-02-06 |
Level shifter stage with punch through diode
Grant 5,929,502 - Beasom July 27, 1 | 1999-07-27 |
High frequency analog transistors, method of fabrication and circuit implementation
Grant 5,892,264 - Davis , et al. April 6, 1 | 1999-04-06 |
High frequency analog transistors method of fabrication and circuit implementation
Grant 5,807,780 - Davis , et al. September 15, 1 | 1998-09-15 |
High frequency analog transistors, method of fabrication and circuit implementation
Grant 5,668,397 - Davis , et al. September 16, 1 | 1997-09-16 |
Method of making JFET structures for semiconductor devices with complementary bipolar transistors
Grant 5,652,153 - Beasom July 29, 1 | 1997-07-29 |
Method of making an integration of high voltage lateral MOS devices in low voltage CMOS architecture using CMOS-compatible process steps
Grant 5,622,878 - Beasom April 22, 1 | 1997-04-22 |
Voltage divider and use as bias network for stacked transistors
Grant 5,493,207 - Beasom February 20, 1 | 1996-02-20 |
Self-aligned channel stop for trench-isolated island
Grant 5,436,189 - Beasom July 25, 1 | 1995-07-25 |
Formation of dual polarity source/drain extensions in lateral complementary channel MOS architectures
Grant 5,338,960 - Beasom August 16, 1 | 1994-08-16 |
Semiconductor structure within DI islands having bottom projection for controlling device characteristics
Grant 5,306,944 - Beasom April 26, 1 | 1994-04-26 |
High voltage lateral semiconductor device
Grant 5,264,719 - Beasom November 23, 1 | 1993-11-23 |
Voltage divider and use as bias network for stacked transistors
Grant 5,233,289 - Beasom August 3, 1 | 1993-08-03 |
Method of making a high breakdown active device structure with low series resistance
Grant 5,091,336 - Beasom February 25, 1 | 1992-02-25 |
Trench conductor and crossunder architecture
Grant 5,057,895 - Beasom October 15, 1 | 1991-10-15 |
MESFET for dielectrically isolated integrated circuits
Grant 5,014,108 - O'Mara, Jr. , et al. May 7, 1 | 1991-05-07 |
Isolated gate MESFET and method of trimming
Grant 5,010,377 - Beasom April 23, 1 | 1991-04-23 |
High breakdown active device structure with low series resistance
Grant 4,975,751 - Beasom December 4, 1 | 1990-12-04 |
High voltage MOS structure
Grant 4,941,027 - Beasom July 10, 1 | 1990-07-10 |
Low top gate resistance JFET structure
Grant 4,876,579 - Davis , et al. October 24, 1 | 1989-10-24 |
Conductivity-modulated FET with improved pinch off-ron performance
Grant 4,873,564 - Beasom October 10, 1 | 1989-10-10 |
High voltage lateral MOS structure with depleted top gate region
Grant 4,823,173 - Beasom April 18, 1 | 1989-04-18 |
IC which eliminates support bias influence on dielectrically isolated components
Grant 4,807,012 - Beasom February 21, 1 | 1989-02-21 |
High voltage IC bipolar transistors operable to BV.sub.CBO and method of fabrication
Grant 4,729,008 - Beasom March 1, 1 | 1988-03-01 |
Structure for high breakdown PN diode with relatively high surface doping
Grant 4,713,681 - Beasom December 15, 1 | 1987-12-15 |
Conductivity modulated semiconductor structure
Grant 4,694,313 - Beasom September 15, 1 | 1987-09-15 |
Power switched logic gates
Grant 4,567,385 - Falater , et al. January 28, 1 | 1986-01-28 |
I.sup.2 L Structure and fabrication process compatible with high voltage bipolar transistors
Grant 4,546,539 - Beasom October 15, 1 | 1985-10-15 |
Method of fabrication bipolar transistor with improved base collector breakdown voltage and collector series resistance
Grant 4,532,003 - Beasom July 30, 1 | 1985-07-30 |
Method of fabricating an isolated gate JFET
Grant 4,495,694 - Beasom January 29, 1 | 1985-01-29 |
Isolated gate JFET structure
Grant 4,456,918 - Beasom June 26, 1 | 1984-06-26 |
Kelvin-connected buried zener voltage reference circuit
Grant 4,398,142 - Beasom August 9, 1 | 1983-08-09 |
Low thermal coefficient semiconductor device
Grant 4,319,257 - Beasom March 9, 1 | 1982-03-09 |
Integrated amplifier with adjustable offset voltage
Grant 4,210,875 - Beasom July 1, 1 | 1980-07-01 |
Process of fabricating junction isolated IGFET and bipolar transistor integrated circuit by diffusion
Grant 4,120,707 - Beasom October 17, 1 | 1978-10-17 |
Process for fabricating planar SCR structure
Grant 3,986,904 - Beasom October 19, 1 | 1976-10-19 |
Fabrication of MOS devices and complementary bipolar transistor devices in a monolithic substrate
Grant 3,865,649 - Beasom February 11, 1 | 1975-02-11 |
Field Effect Transistor
Grant 3,783,349 - Beasom January 1, 1 | 1974-01-01 |
Process For Forming Buried Layers To Reduce Collector Resistance In Top Contact Transistors
Grant 3,722,079 - Beasom March 27, 1 | 1973-03-27 |
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