U.S. patent number 4,829,258 [Application Number 07/092,478] was granted by the patent office on 1989-05-09 for stabilized phase locked loop.
This patent grant is currently assigned to Intel Corporation. Invention is credited to Terry L. Baucom, Roger V. Brunt, Andrew M. Volk.
United States Patent |
4,829,258 |
Volk , et al. |
May 9, 1989 |
**Please see images for:
( Certificate of Correction ) ** |
Stabilized phase locked loop
Abstract
A dual loop phase locked loop system having a secondary loop for
controlling various circuit, environmental and process variations.
The secondary loop is comprised of a phase comparator, a filter, a
transconductance amplifier and a one-shot, wherein the output of
the one-shot is fed back as an input signal for comparison with a
reference signal at the input of the phase comparator. The filter
generates a correction voltage which is dependent on the phase
difference determined by the phase comparator, and the
transconductance amplifier generates a charging current
corresponding to the error voltage from the filter, wherein the
charging current controls the charging of the input capacitor to
the one-shot circuit for determining the duration of the pulse
width of the output of the one-shot. The one-shot based loop is
inherently stable since there is only one pole near the origin of
the S-Plane. The primary loop is comprised of a phase comparator, a
filter, a transconductance amplifier and an output means, which is
a VCO and a voltage divider. The primary loop provides the actual
phased locked loop of an input reference signal, however, it
derives compensating analog trim information from the secondary
loop. The dynamic characteristics of the primary loop are
established by the reference loop, based on the reference clock
frequency. Further, the loop response is controlled by the
reference frequency, and is immune to process, temperature and
voltage variations. In addition the loop frequency characteristics
can be programmed by adjusting the reference clock.
Inventors: |
Volk; Andrew M. (Loomis,
CA), Baucom; Terry L. (Citrus Heights, CA), Brunt; Roger
V. (San Francisco, CA) |
Assignee: |
Intel Corporation (Santa Clara,
CA)
|
Family
ID: |
22233421 |
Appl.
No.: |
07/092,478 |
Filed: |
September 3, 1987 |
Current U.S.
Class: |
327/156; 327/157;
327/159; 327/227; 331/1A; 331/25; 375/376 |
Current CPC
Class: |
H03L
1/00 (20130101); H03L 7/07 (20130101); H03L
7/0805 (20130101); H03L 7/089 (20130101) |
Current International
Class: |
H03L
7/089 (20060101); H03L 7/08 (20060101); H03L
7/07 (20060101); H03L 1/00 (20060101); H03K
005/13 (); H03K 005/22 () |
Field of
Search: |
;328/155,133,63,72
;307/262,511 ;375/119,120 ;331/DIG.2,1A,25 |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
|
|
|
|
|
|
|
0249060 |
|
Dec 1987 |
|
EP |
|
1026381 |
|
Apr 1966 |
|
GB |
|
1482586 |
|
Aug 1977 |
|
GB |
|
Other References
British Examiner's Search Report, dated Jul. 26, 1988, for British
patent application S/N 8811641-3..
|
Primary Examiner: Miller; Stanley D.
Assistant Examiner: Callahan; Timothy P.
Attorney, Agent or Firm: Blakely, Sokoloff, Taylor &
Zafman
Claims
We claim:
1. A circuit for providing a phase locked loop comprising:
a multivibrator coupled to receive a trigger signal for triggering
an output from said multivibrator;
a phase comparator coupled to receive a reference signal having a
predetermined pulse width and also coupled to receive said output
from said multivibrator as a feedback signal for comparing said
reference signal and said feedback signal;
a filter coupled to said phase comparator for filtering said
comparison of said reference and feedback signals and generating an
error voltage wherein said error voltage is proportional to the
amount of a phase difference of said comparison of said reference
and feedback signals;
a transconductance amplifier coupled to receiver said error voltage
and coupled to provide an input current to said multivibrator, said
input current being a function of said error voltage, wherein as
said error voltage changes according to said comparison, said input
current changes correspondingly to compensate for pulse width
duration of said output signal such that said output signal will
have an approximately equivalent pulse width duration as said
reference signal.
2. The circuit of claim 1, wherein said transconductance amplifier
includes a metering transistor wherein said error voltage is
coupled to the gate of said transistor such that as said error
voltage varies, conduction of said metering transistor varies
correspondingly to vary said input current to said
multivibrator.
3. The circuit of claim 2, wherein said multivibrator further
includes an input charging capacitor such that said input current
charges said capacitor to a predetermined level wherein said
multivibrator changes states when said predetermined level is
reached, said metering transistor and said input capacitor forming
a RC time constant determining pulse width duration of said output
signal.
4. The circuit of claim 3, wherein said filter has a single
dominant pole in its transfer function.
5. The circuit of claim 4, wherein said multivibrator is a
monostable multivibrator.
6. The circuit of claim 5, wherein said trigger signal and said
reference signal are derived from a reference clock pulse.
7. The circuit of claim 6, wherein said circuit is embodied in a
single integrated circuit ship.
8. A circuit for providing RC product stabilized phase locked loop
comprising:
(1) a secondary phase locked loop comprising:
(a) a multivibrator coupled to receive a trigger signal for
triggering a secondary output from said multivibrator;
(b) a first phase comparator coupled to receive a first reference
signal having a predetermined pulse width and also coupled to
receive said secondary output from said multivibrator for comparing
said first reference signal and said secondary output signal;
(c) a first filter coupled to said first phase comparator for
filtering said comparison of said first reference signal and said
secondary output signal and generating an error voltage
corresponding to said comparison;
(d) a first transconductance amplifier coupled to said first filter
and said multivibrator for receiving said error voltage signal from
said first filter and for providing (1) a first input current to
said multivibrator wherein said input current varies
correspondingly to said error voltage for determining the pulse
width duration of said secondary output from said multivibrator and
(2) an analog trim information signal;
(2) a primary phase locked loop, said primary phase locked loop
comprising;
(a) output means for providing a primary output and a feedback
signal;
(b) a second phase comparator coupled to receive an input signal
having a selective frequency and also coupled to receive said
feedback signal from said output means for comparing said input
signal and said feedback signal;
(c) a second filter coupled to said second phase comparator for
filtering said comparison of said input signal and said feedback
signal and generating a second error voltage responsive to said
comparison;
(d) a second transconductance amplifier, coupled to said second
filter and said output means, for controlling a second input
current to said output means, wherein said second input current
varies correspondingly to said second error voltage such that as
said second error voltage changes, said second input current
changes accordingly to maintain lock of said primary loop;
wherein said output means, said second phase comparator, said
second filter, and said second transconductance amplifier are each
coupled to receive said analog trim information signal from said
first transconductance amplifier for centering an operating
frequency of said output means, for controlling gain, and for
providing compensation for said primary loop such that frequency of
said primary loop is substantially independent of process and
temperature variations,
wherein compensation for said primary phase locked loop is provided
by said secondary phase locked loop.
9. The circuit of claim 8, wherein said second phase comparator
functions as a charge pump.
10. The circuit of claim 9, wherein said output means includes a
voltage controlled oscillator coupled to said second
transconductance amplifier for controlling frequency of said
primary phase locked loop.
11. The circuit of claim 10, wherein said output means further
includes a frequency divider for dividing said primary output.
12. The circuit of claim 11, wherein said primary phase locked loop
is used to provide data windows when data pulses are present on
said input signal.
13. The circuit of claim 11, wherein said primary and secondary
phase locked loops are fabricated on a same integrated circuit
semiconductor chip.
14. The circuit of claim 8, wherein said RC product is proportional
to said reference frequency and wherein said primary loop RC time
constant is adjusted by said reference frequency.
15. The circuit of claim 12, wherein said RC product is
proportional to said reference frequency and wherein said primary
loop RC time constant is adjusted by said reference frequency.
16. The circuit of claim 1, wherein said multivibrator is a
monostable multivibrator.
17. The circuit of claim 1, wherein said circuit is embodied in a
single integrated circuit chip.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of error compensating
loops and more specifically to stabilized integrated phase locked
loop systems.
2. Related Application
The present application is related to copending application Ser.
No. 092,477, filed Sept. 3, 1987, entitled "Phase Comparator for
Extending Capture Range".
3. Prior Art
Phase locked loop systems are well known in the prior art wherein
these loops are utilized to maintain stable frequency, phase and
other circuit parameters. Phase locked loops must have stable and
controlled operating characteristics, immune to voltage,
temperature and circuit fabrication variations. This is especially
so during the operation of the phase locked loop when environmental
conditions can change readily. Primary parameters which are
essential for the operation of a stable phase locked loop are loop
gain and filter characteristics.
Typically, dynamic loop characteristics of integrated phase locked
loops require off-chip adjustment to control the loop parameters.
This is achieved by adjusting the loop filter, or changing the loop
gain and are typically made with respect to an external standard
reference. Further, there are two specifications imposed on most
phase locked loop systems which by nature are diametrically
opposite to each other. These two specifications are settling time
and jitter response.
For a phase locked loop to have a satisfactory settling time the
loop should respond fast to external data changes but the response
must not be too fast in order to have a good jitter specification.
A tradeoff must be made between these two specifications and often
it is difficult to satisfy both requirements simultaneously. In
prior art, a common solution is to create a two or multiple gain
loop system in which a two gain loop is utilized. A fast mode is
used to satisfy the required settling time specification and after
the loop has achieved lock, the high gain mode is switched off.
When the high gain mode is off, the jitter specifications are
satisfied because of the low gain.
It is appreciated then that what is required is a phase locked loop
system which is capable of being independent of various circuit
process and environmental conditions without the use of external
compensation and which also is capable of having a satisfactory
settling time with a good immunity to read data jitter.
SUMMARY OF THE INVENTION
The present invention provides for a phase locked loop system using
a standard RC time constant to control the loop characteristics and
the use of an extended range logic circuit to provide dual
compensation rates for the phase locked loop. The phase locked loop
system of the present invention utilizes two loops, a primary loop
and a secondary loop. The secondary loop is comprised of an analog
based one-shot, instead of a VCO. A reference signal and the output
of the one shot are compared in a phase comparator and the phase
difference is provided to a filter which generates an error voltage
to a transconductance amplifier. Upon receiving the error voltage,
the transconductance amplifier will vary the conduction of a
metering transistor to vary the current through the transistor. The
current is provided as an input current to the one-shot wherein a
capacitor is charged to a predetermined value which determines the
duration of the one-shot. Because of the combination of the
resistance of the metering transistor and the capacitance of the
input capacitor, the RC combination determines the pulse width
duration of the output of the one-shot. The error voltage and the
input current values which provide the compensation for the
secondary loop are also transmitted to the primary loop as analog
trim signals.
The primary loop is also comprised of a phase comparator, a filter,
a transconductance amplifier and an output means. However, in this
instance the secondary loop also uses the analog trim information
to compensate for various parameter variations. The output means of
the secondary loop is a VCO and a frequency divider is also used in
the preferred embodiment. The dual loop system allows, if properly
exploited, creates a system which is to the first order immune to
process and operating environment variation. The level of stability
is provided by establishing the damping factor, settling time and
the center frequency with respect to a constant reference
frequency. The system creates a standard RC element and bases all
loop currents on the reference frequency, thus the accuracy will
depend primarily on the external reference data. Furthermore the
loop can be programmed to different data rates by adjusting the
reference clock frequency.
Further, a special phase comparator is used in the primary loop to
provide for an extended range logic circuit which is activated when
a phase slip condition is about to occur. When the phase error is
limited to a small value near the center zero phase point, a slower
settling time is used to prevent jitter. However, as the phase
difference approaches the slip point, the extended range circuit is
activated to provide a more rapid settling time to compensate for
the additional phase error to prevent slip from occurring.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram illustrating a phase locked loop
utilizing a one-shot to provide a feedback signal as used in the
present invention, as the secondary PLL.
FIG. 2 is a graphic illustration showing the various poles of the
phase locked loop circuit of FIG. 1.
FIG. 3 is a waveform diagram showing a reference signal, unlocked
feedback signal, and a locked feedback signal from the one-shot for
the phase locked loop of FIG. 1.
FIG. 4 is a schematic diagram showing a transconductance amplifier
and a one-shot of the present invention.
FIG. 5 is a graphic illustration showing the determination of a
timing duration of the one-shot of FIG. 4.
FIG. 6 is a block diagram illustration showing a dual phase locked
loop architecture of the present invention.
FIG. 7 is a transfer function block diagram illustration showing an
equivalent circuit of a primary loop of FIG. 6.
FIG. 8 is a schematic diagram showing a phase comparator as used in
the present invention.
FIG. 9 is a graphic illustration showing the phasing operation of
the phase comparator of FIG. 8.
FIG. 10 is an enhanced phase comparator of the present invention
which utilizes an extended range logic circuit.
FIG. 11 is a graphic illustration showing the phasing operation of
the circuit of FIG. 10.
FIG. 12 is a circuit schematic diagram of the extended range logic
circuit of FIG. 10 as implemented in the preferred embodiment.
FIG. 13 is a waveform diagram of the various signals used in FIG.
12.
FIG. 14 is a schematic diagram of a loop filter of the primary loop
of FIGS. 6 and 7.
FIG. 15 is a schematic diagram of a transconductor amplifier of
FIGS. 6 and 7.
DETAILED DESCRIPTION OF THE PRESENT INVENTION
The present invention describes a constant RC product stabilization
of a phase locked loop using a one-shot based secondary phase
locked loop, and the use of a phase comparator for extending
capture range. In the following description, numerous specific
details are set forth such as specific circuits, components, timing
diagrams, etc., in order to provide a thorough understanding of the
present invention. It will be obvious, to one skilled in the art
that the present invention may be practiced without these specific
details. In other instances, well-known circuits have not been
described in detail in order not to unnecessarily obscure the
present invention.
One-Shot Based Phase Locked Loop
Referring to FIG. 1, a block diagram of a phase locked loop (PLL)
utilizing a monostable multivibrator (one-shot) is shown. The PLL
10 is comprised of a phase comparator 11, filter 12,
transconductance amplifier 13 and one-shot 14. A reference clock
pulse, .THETA..sub.I, is coupled as input to phase comparator 11.
Reference clock pulse .THETA..sub.I is also coupled to one-shot
circuit 14 to provide a signal to trigger one-shot 14. Phase
comparator 11 also receives as an input the output of one-shot 14
as referenced by .THETA..sub.O.
Phase comparator 11 compares the reference clock signal
.THETA..sub.I and the output of the one-shot .THETA..sub.O by
comparing the pulse widths of the two input signals .THETA..sub.I
and .THETA..sub.O. A variety of phase comparator circuits
well-known in the prior art can be utilized to provide the pulse
width comparison achieved in the phase comparator 11 of the present
invention. Although FIG. 1 shows the same .THETA..sub.I inputs to
phase comparator 11 and one-shot 14, it is appreciated that
circuits 11 and 14 need not trigger at the same instance and that a
delay can be used at the input. A transfer function of the phase
comparator 11 is represented as K.sub.D.
The output of the phase comparator 11 is coupled to a filter 12.
Filter 12 utilizes a single capacitor C.sub.r to provide a storage
element for the phase lock loop of circuit 10 and, therefore, has a
single dominant pole as represented by the transfer function
F(s)=1/SC.sub.r. Such use of capacitor filters, especially a loop
filter within a PLL circuit, is well-known in the prior art.
The output of filter 12 is a voltage signal designated VFB and is
coupled to transconductance amplifier 13 which has a transfer
function of K.sub.T. Transconductance amplifier 13 transforms VFB
signal to a current signal IOS for controlling the turn-on duration
of one-shot 14. One-shot 14 is a monostable multivibrator which is
in its stable state until triggered by the reference clock signal
.THETA..sub.I. Once triggered, one-shot 14 generates an output
.THETA..sub.O, wherein the duration of the astable pulse of the
one-shot is determined by the vaue of IOS. One-shot 14 is
designated to have a transfer function K.sub.O.
In operation, PLL 10 is a closed loop system having one reference
input .THETA..sub.I, wherein the output .THETA..sub.O of the
one-shot provides the closed loop feedback for maintaining the
phase lock of PLL 10. When a reference pulse .THETA..sub.I is
received, one-shot 14 is triggered by .THETA..sub.I on line 15. The
output .THETA..sub.O is compared to the reference signal
.THETA..sub.I in the phase comparator 11. If the pulse width of the
reference signal .THETA..sub.I is equal to the pulse width of
.THETA..sub.O, then no adjustment is made because PLL 10 is in the
locked condition. However, if the comparison results in a
difference of the pulse widths of the two input signals, then an
error signal is generated from phase comparator 11 and processed by
filter 12, wherein filter 12 generates the error feedback voltage
VFB, the magnitude change of VFB being proportional to the amount
of the difference of the pulse widths of .THETA..sub.I and
.THETA..sub.O. In the locked condition, VFB will have a value
corresponding to zero error. When .THETA..sub.O pulse width is
shorter in duration than .THETA..sub.I, then VFB will vary in one
direction from the error free value; and when .THETA..sub.O pulse
width is longer in duration than .THETA..sub.I, then VFB will vary
in the opposite direction from the error free value.
VFB is coupled as an input to amplifier 13, wherein amplifier 13
has a transformation value of K.sub.T. VFB is amplified by a factor
of K.sub.T to provide IOS. The pulse width of one-shot 14 is
inversely proportional to the amount of current, IOS, being
provided by the transconductance amplifier 13. For example, if
.THETA..sub.O has a longer pulse width than .THETA..sub.I, phase
comparator 11 and filter 12 will increase the feedback voltage VFB
and transconductance amplifier 13 will increase IOS to reduce the
pulse width of .THETA..sub.O to coincide with .THETA..sub.I. When
.THETA..sub.O has a shorter pulse width than .THETA..sub.I, VFB and
IOS are reduced.
Referring to FIG. 2, a root locus diagram of the secondary loop
shows an advantage of the single dominant pole filter 12 of the
present invention. Filter 12, having a transfer function
F(s)=1/SC.sub.r, provides for a simple first order closed loop
system wherein a single dominant pole 20 is located at the origin.
Other poles 21 are located a considerable distance from the origin,
such that their effects are negligible and they are treated as
non-dominant poles. Prior art phase lock loop systems typically use
a voltage-controlled oscillator (VCO), wherein the closed loop
system usually has two dominant poles near the origin. Using the
single pole design provides a system which is inherently stable. In
the VCO loop which has two poles near the origin, stability must be
designed into the system.
Referring to FIGS. 1 and 3, the reference clock signal
.THETA..sub.I is shown having a pulse width PW.sub.1. The pulse
width of .THETA..sub.O will vary, but if the loop is in a locked
condition, then the pulse width PW.sub.2 of .THETA..sub.O-LOCKED
will have the same pulse width as PW.sub.1. If the pulse width of
.THETA..sub.O is not equal to PW.sub.1, then it will have a
difference of -.DELTA. if it is too short, or +.DELTA. if it is too
long. The comparison of .THETA..sub.I to .THETA..sub.O by phase
comparator 11 will generate error feedback voltage VFB from filter
12, wherein the change of the feedback voltage VFB is proportional
to the differences -.DELTA. or +.DELTA.. The pulse width adjustment
is better understood when FIG. 5 is also referenced.
FIG. 5 shows the duration of the pulse width .THETA..sub.O as time
period .tau.. Period .tau. is equivalent to the charging time of
the capacitor of one-shot 14, wherein current IOS charges this
capacitor. The capacitor commences to charge at time t.sub.0 when
one-shot 14 is triggered and stops charging when a predetermined
voltage level V.sub.1 is reached. .tau. is the time period it takes
to charge from t.sub.0 to voltage V.sub.1. If pulse widths of
.THETA..sub.O and .THETA..sub.I are equal, then slope 65 is
followed to give the desired lock condition. If .THETA..sub.O has
an error of -.DELTA., .tau. of .THETA..sub.O is represented by
slope 66. Phase comparator 11 and filter 12 will compensate by
decreasing VFB and thereby decreasing IOS. Because IOS, which is
the capacitor charging current, is decreased, .tau. shifts from
slope 66 to that of slope 65. In reverse, if .THETA..sub.O has an
error of +.DELTA., as represented by slope 67, VFB and IOS are
increased such that .tau. shifts from slope 67 to the desired slope
65.
Referring to FIG. 4, it shows a preferred circuit implementation of
the transconductance amplifier 13 and one-shot 14 of FIG. 1.
Circuit 30 is comprised of a transconductance amplifier section 31
and one-shot section 32. Circuit section 31 is included within
transconductance amplifieer 13 of FIG. 1 and section 32 is included
within one-shot 14 of FIG. 1. A voltage feedback signal VFB is
coupled as an input to the gate of M.sub.1 transistor 34. The
source of transistor 34 is coupled to ground, while the drain of
transistor 34 is coupled to node 35. The source of transistor 36 is
coupled to node 35 and the drain of transistor 36 is coupled to the
drain and gate of transistor 37. The source of transistor 37 is
coupled to Vcc.
The gate of transistor 38 is also coupled to node 35 and the gate
of transistor 39 is coupled to a reference voltage,
.alpha.V.sub.ref. The drains of transistors 38 and 39 are coupled
to ground. The source of transistor 38 is coupled to the negative
input of operational amplifier 40 and to a current source 42. The
source of transistor 39 is coupled to the positive input of
amplifier 40 and to a current source 41. In the preferred
embodiment current sources 41 and 42 are implemented by each using
a transistor operating in a saturation region to provide an
approximately steady current. The output of amplifier 40 is coupled
to the gate of transistor 36.
Circuit section 32 is comprised of input components, transistor 50
and capacitor 51, and the multivibrator stage of transistors 52-59.
Amplifier section 31 is coupled to section 32 by having the gate
and drain of transistor 37 coupled to the gate of transistor 50.
The drain of transistor 50 is coupled to the gate of transistor 52
and one side of capacitor 51. The source of transistor 50 is
coupled to Vcc, while the other side of capacitor 51 is coupled to
ground. Capacitor 51 functions as the input capacitor described in
the description of FIG. 5. The drain of transistor 52 is coupled to
the drain of transistor 57 and the gate of transistor 58. A trigger
signal which is obtained from the trigger shown in FIG. 1 is
coupled as input to the gate of transistor 59. The drain of
transistor 59 is coupled to the gate of transistor 57 and the drain
of transistor 58. Transistors 55 and 56 are coupled in series
between the drain of transistor 58 and Vcc. Transistors 53 and 54
are coupled in series between the drain of transistor 52 and Vcc.
Transistors 53-56 operate as current sources. Sources of
transistors 52, 57, 58 and 59 are coupled to ground. The output
.THETA..sub.O is taken as the output of the drain of transistor 52.
As used in the preferred embodiment, transistors 37-39, 50 and
53-56 are p-channel devices while the other transistors are
n-channel devices. Transistor 62 and inverter 63 couple trigger
signal to the gate of transistor 52 for presetting the one-shot. It
is appreciated that although a specific circuit implementation is
described, other embodiments are available to practice the
invention without departing from the spirit and scope of the
present invention.
In operation, VFB is coupled to the gate of transistor 34 such that
the value of the error feedback voltage VFB controls the gate drive
of transistor 34. Transistor 34, in this instance, has a
designation M.sub.1 and the current through the transistor is
designated I.sub.REF. Node 35 is designed to maintain a voltage
potential of .alpha.V.sub.REF, wherein .alpha.V.sub.REF is the
reference voltage which is impressed on the gate of transistor 39.
.alpha.V.sub.REF of transistor 39 is a reference potential which is
derived from an internal voltage reference source (not shown). The
potential at node 35, being coupled to the gate of transistor 38,
provides the gate drive for that transistor, and the reference
voltage .alpha.V.sub.REF provides the gate drive for transistor 39.
Amplifier 40 operates as a voltage follower to compare the
conduction of transistors 38 and 39, which is determined by the
gate drive signals .alpha.V.sub.REF and node 35. The output of
amplifier 40 is coupled to the gate of transistor 36 to control the
drive of transistor 36. The above-described circuit components
operate to maintain a voltage potential at node 35 which is
equivalent to the reference voltage .alpha.V.sub.REF. In the
preferred embodiment, .alpha. has a value such that M.sub.1 remains
in its linear range of operation to allow for .alpha.VFB to operate
in wide range.
When the phase lock loop is in a locked condition, the VFB signal
designates a no-error condition, such that when .alpha.V.sub.REF
and node 35 are equal and the pulse width of the one-shot and the
reference clock are of the same duration. If the pulse width of the
one-shot is different than the reference, then an error voltage
deviation from the locked condition having a magnitude proportional
to the amount of the pulse width difference is present at the gate
of transistor 34. The error voltage deviation causes an increase or
decrease of the gate drive of transistor 34 such that the
resistance of transistor 34 will change and cause current I.sub.REF
to vary also. The current I.sub.REF through transistor 34 varies
according to the error voltage because amplifier 40 compares
signals .alpha.V.sub.REF and node 35 voltage and provides a drive
to transistor 36 to maintain node 35 at a constant voltage of
.alpha.V.sub.REF.
Current I.sub.REF is equivalent to the current through transistor
37, and current IOS through transistor 50 is proportionately equal
to current I.sub.REF because transistors 50 and 37 operate as a
current mirror. The operation of current mirrors are well-known in
the prior art. Therefore, when the phase lock loop deviates from
the locked condition, VFB coupled to the gate of transistor 34 is
converted to a feedback current IOS, the value of IOS being
proportional to the value of VFB.
The duration of the pulse width of the one-shot section 32 is
controlled by the one-shot current IOS. Current IOS through
transistor 50 charges capacitor 51, such that when capacitor 51
charges to a predetermined voltage value V.sub.1, as shown in FIG.
5, it triggers transistor 52 to terminate the output pulse of the
one-shot. The trigger signal at the gate of transistor 59 triggers
the commencement of the pulse of the one-shot and the current IOS
charging capacitor 51 determines the duration of the pulse width
once the one-shot is triggered. The basic operation of a monostable
multivibrator as comprised by transistors 52-59 is well-known in
the prior art.
FIG. 5 shows the duration of the pulse width .THETA..sub.O as time
period .tau.. Period .tau. is equivalent to the charging time of
capacitor 51. Assuming that at time t.sub.0 multivibrator circuit
32 is triggered by a trigger signal at the gate of transistor 59.
Current IOS charges capacitor 51 at a predetermined rate until a
voltage value V.sub.1 is reached. In summary, the error voltage
causes current IOS to vary according to the changes of VFB. VFB
changes cause the conduction, and hence the resistance R.sub.M1, of
M.sub.1 to change, while amplifier 40 maintains node 35 at a
voltage potential of .alpha.V.sub.REF. I.sub.REF variations are
coupled to the one-shot circuit as proportionate IOS changes,
wherein the value of IOS determines the time period .tau. and
ultimately the pulse width of .THETA..sub.O. In simpler terms,
because IOS is a function of the resistance, R.sub.M1, of
transistor 34, .tau. is a function of a RC time constant of
R.sub.M1 and C.sub.51 (C.sub.51 being the value of capacitance of
capacitor 51).
In mathematical terms the relationship between the RC product
R.sub.M1 Cos and the one-shot period Tos can be derived as
follows.
The one-shot current is given by: ##EQU1## where ##EQU2##
Cos=capacitance of the one-shot, C51 R.sub.M1 =resistance of
M1.
The one-shot threshold is give by: ##EQU3## Tos=One-shot pulse
period.
Substituting Ios into the above equation and solving for R.sub.M1
Cos. ##EQU4##
By design it is possible to make V.sub.REF2 =V1, which
produces,
Therefore since G1 and .alpha. are established by transistor and
resistor ratios respectively, they can be controlled by design.
Moreover when the secondary loop is locked Tos=PW1 where PW1 is
derived from an external reference clock. The result of this is
that the time constant Rm1 Cos is proportional to the reference
frequency, which is the basis for PW1. Thus the time constant is
immune to power supply, temperature and process variations.
Furthermore since the secondary loop time constant depends only on
PW1 the secondary loop is programmable by the digital logic that
creates PW1.
It should be appreciated that if the secondary loop bias signals
are properly exploited that the primary loop can be made immune to
power supply, temperature and process variations. This is achieved
by using signals such as IOS1 and VFB1 to bias the primary loop.
Furthermore the primary loop filter time constant is made
proportional to R.sub.M 1 Cos by ratioing the components. The
result is a second order PLL which has dynamic characteristics
programmable by a digital reference signal. ##EQU5## wherein when
put in terms of FIG. 4:
The phase comparator transfer function K.sub.D is given by:
##EQU6## where I.sub.D is the phase comparator output current.
The loop filter transfer function is given by: ##EQU7##
The transconducting amplifier transfer function is given by:
where G.sub.1 is a current gain factor between I.sub.REF and
I.sub.OS and .beta..sub.M1 is the Beta of transistor M1,
One-shot transfer function is: ##EQU8## where Cos is the
capacitance of capacitor 51, and by design VREF=V.sub.1, is the
threshold turn-on voltage of circuit 32.
Constant RC Product Stabilization of Phase Locked Loop
A dynamic behavior of PLL systems must be well controlled to
satisfy varous system specifications. Primary parameters of concern
are the damping factor and the settling time. The dynamic loop
characteristics of integrated PLLs normally require off-chip
adjustment to control the loop parameters. This is typically
achieved by adjusting the loop filter or changing the loop gain.
These adjustments are normally made with respect to an external
standard reference.
Referring to FIGS. 6 and 7, FIG. 6 shows a block diagram of a
two-loop PLL architecture 70 of the preferred embodiment which is
implemented on a single semiconductor chip. The PLL which comprises
part of the lower portion of the figure forms a primary loop 71 and
the PLL which comprises the upper portion of the drawing forms a
secondary loop 72. Secondary loop 72 is susbstantially equivalent
to the one-shot PLL circuit of FIG. 1 and corresponding reference
numerals of FIG. 1 are utilized, but with a letter "a" attached to
the numerals. An object of the secondary loop 72 is to provide
internal compensation such that off-chip adjustment is not
necessary. If the relationship between the two loops 71 and 72 is
correctly exploited, the primary loop 71 will be positioned very
close to the center of its designed operating range when the
secondary loop 72 is in a locked condition. In addition the gain of
all elements in the primary loop is established, including the time
constant of the loop filter.
The primary loop 71 is a PLL circuit receiving analog trimming
information from secondary loop 72. FIG. 7 shows a block diagram
equivalent circuit of primary loop 71. The primary loop 71 is
comprised of phase comparator 11b, filter 12b, transconductance
amplifier 13b, VCO 73 and digital divider 75. Phase comparator 11b
also provides a charge pump function and is typically referred to
as such. Blocks 11b, 12b and 13b function basically with the
similar intent as the phase comparator 11, filter 12 and
transconductance amplifier 13 of FIG. 1, and the same reference
numerals are utilized for these respective elements in the primary
loop 71, but with the addition of letter "b". However, in the
primary loop 71, phase comparator 11b functions also as charge pump
and filter 12b includes both a pole and a zero, the zero being
required for compensation. In the primary loop 71, a voltage
controlled oscillator (VCO) 73 is used instead of a one-shot. Like
the one-shot the threshold of the VCO is established by V1. Digital
divider 75 is used to reduce the frequency of the output of the VCO
73, and in the preferred embodiment the output of the digital
divider is selected as 1/2 or 1/4 of the frequency of the output of
the VCO 73.
As used in the preferred embodiment, lower portion of FIG. 6, which
includes primary loop 71, is used to provide a control window in
reading data from a memory device, such as a floppy disk. Data
pulses from a memory are coupled as input to digital control logic
unit 74. The output of the digital divider 75 provides a data
window which is used by a memory accessing device to determine when
valid data is present for accessing.
Digital control signals from other control sources are coupled to
digital control logic 74 and digital divider 75 to provide
synchronization and control of these two blocks. Digital control
logic 74 receives data pulses from the memory device and generates
.THETA..sub.I2 whenever data is present. Control logic 74 also
generates a second reference signal .THETA..sub.REF, which provides
continuous clock pulses for synchronization when data pulses are
not present at the input. Typically, .THETA..sub.REF is two times
the data rate. Although the preferred embodiment is used to
generate a valid data window, the dual loop architecture of the
present invention can be used in various other applications.
The analog trim information from the second loop 72 is used by
various blocks of primary loop 71 to control the operation of the
primary loop 71. The primary loop 71 will use the current values
established by the secondary loop 72 to center the VCO operating
frequency and control the gain of the phase comparator 11b and the
VCO 73. VFB.sub.1 controls the filter 12b. Transconductance
amplifier 13a of secondary loop 72 provides VFB and IOS values as
analog trim information to blocks 11b, 12b, 13b and 73 of primary
loop 71. Transconductance amplifier 13a is designated to have a
current mirror gain value of G.sub.1. Value G.sub.2 is given
designating the transconductance gain of the amplifier of block
13b, and G.sub.3 is the designation for the scaling factor used in
charge pump 11b.
Analog trim information from amplifier 13a is comprised of
VFB.sub.1 and I.sub.OS1. VFB.sub.1 and I.sub.OS1 are also used to
control the primary loop 71, as well as the secondary loop 72. The
primary loop is controlled in such a way that its transfer function
is independent of process, temperature and supply voltage. Through
the use of this invention the primary loop is controlled by the
reference clock only. Furthermore the primary loop is a function of
reference frequency in such a way that the frequency response
normalized in terms of the reference frequency is independent of
reference frequency. This allows the primary loop to be adjusted
for different input data rates by simply adjusting the reference
clock frequency.
The following analysis will proceed block by block through the
primary loop 71. The intention is to demonstrate that it is
possible to control the open loop gain and the pole and zero
locations of the filter. Moreover given that it is possible to
control the open loop gain and filter characteristics, it follows
that the closed loop transfer function will also be controlled.
Charge pump 11b accepts I.sub.OS1 and generates a current equal to
G.sub.D I.sub.OS1.
The charge pump transfer function is: ##EQU9##
Y=Constant which depends on the phase comparator design, data
format and the input data pattern. ##EQU10##
Substituting I.sub.OS1 into the K.sub.D2 equation and grouping the
constants in G.sub.D results in the following: ##EQU11##
The loop filter 12b shown in FIG. 14 is comprised of a capacitor
C.sub.1 and a transistor M1f in series. VFB.sub.1 is coupled to the
gate of transistor M1f and VFB.sub.2 is at the second terminal of
the capacitor C.sub.1 which is not coupled to transistor M1f. M1f
is matched to M1 in 13a of the secondary loop, with the same gate
to source voltage VFB such that the drain to source resistance is
equal in both transistors. The filter transfer function is given
by: ##EQU12##
C.sub.1 is ratioed with respect to COS (C51 of 32).
The transconductance amplifier 13b shown in FIG. 15 accepts
VFB.sub.2 from filter 12b and is biased by VFB.sub.1 to generate
I.sub.OS2. The circuit of FIG. 15 is equivalent to components
34-38, 40, 42 and 50 of FIG. 4 and are referenced accordingly by a
prefix "2". Transistor M1t is matched and biased similarly to M1 of
circuit 21. Thus the drain to source resistance of M1t is equal to
M1. The transfer function is given by: ##EQU13## where G.sub.2 is
the current mirror gain.
The VCO is designed similarly to the one-shot with the same
threshold voltage V1 (which is designed to be equal to VREF) which
is established by the one-shot loop. The VCO output signal period
is determined by the length of time it takes IVco to charge the COS
to VREF. The VCO transfer function is given below: ##EQU14##
The primary PLL's loop gain GH is given by: ##EQU15## where N is a
digital divider term.
Plugging in the equations for K.sub.D2, F.sub.2, K.sub.T2, and
K.sub.O2 and grouping the constants into a single constant G.sub.T
produces: ##EQU16##
This equation states that the open loop transfer function has two
poles at the origin and a zero located at 1/R.sub.M1 Cos. It was
shown previously that the secondary PLL forces the R.sub.M1 Cos
time constant to be independent of process, temperature and supply
voltage, and directly proportional to the reference clock period.
This implies that the open loop transfer function is process,
temperature and supply voltage independent.
Thus it follows that the closed loop transfer function given below
is also independent. ##EQU17##
Also it can be shown that the zero is proportional to the reference
clock frequency. Furthermore the loop gain is proportional to the
square of the reference clock frequency. As stated earlier this
indicates the closed loop frequency response plotted vs the
normalized frequency is independent of the reference frequency. As
a result it is possible to tune the primary loop for different data
rates by changing the reference clock frequency.
Phase Comparator for Extending Capture Range
Referring to FIG. 8, a schematic diagram of a PLL phase comparator
circuit, which can be used in the phase comparator block 11b of
FIG. 6 is shown. UP and DOWN signals activate current sources which
either source or sink currents to the filter 12b which then causes
a respective change in the feedback voltage VFB.sub.2. Circuit 100
is a prior art circuit comprised of D type flip-flops 101, 102, 103
and NAND gate 104. Input data such as .THETA..sub.I is coupled as
input to clock flip-flops 101 and 102. Loop feedback signal,
designated as .THETA..sub.f in FIG. 6 is coupled as a clock input
to flip-flop 103. The D input of flip-flop 101 is grounded while
the D input of flip-flops 102 and 103 are coupled to Vcc. The
inverted output of flip-flop 101 is coupled to reset input of
flip-flops 102 and 103, which is an active low input. Output of
flip-flop 102 is used to generate an UP control signal while the
output of flip-flop 103 is used to generate a DOWN control signal.
UP and DOWN control signals are coupled as inputs to NAND gate 104
wherein the output of NAND gate 104 is used to reset flip-flop
101.
Functionally, when the PLL circuit is in a locked condition,
.THETA..sub.I and .THETA..sub.f will have their phases synchronized
such that flip-flops 102 and 103 will gate NAND gate 104 to
generate a reset signal from flip-flop 101 to reset flip-flops 102
and 103. However, whenever the two input signals .THETA..sub.I and
.THETA..sub.f are not in phase, the UP and DOWN signal will be
activated depending on the direction of the phase error, and the
duration of the generated signal determines the amount of the
error.
Also referring to FIG. 9, a waveform representation of the phase
error is better illustrated showing phase error as a function of a
voltage change. At zero phase error, the PLL loop is operating in a
locked condition and no phase difference is present between the two
input signals. This no error condition is shown by point 110.
Whenever the PLL circuit slips out of the phase locked condition it
moves away from point 110 along the slope of the curve 111. The
distance from point 110 determines the amount of phase error.
Whenever the accumulation of the phase error takes the circuit
along slope 111 to a slip point 112, the PLL circuit can completely
shift one whole phase as shown by arrows 113 and 114. Typically
when this occurs, the PLL circuit will lock onto the previous or
the succeeding phase and the circuit will be out of phase by .pi./2
and driving towards .pi. further away from the original lock point
resulting in increased time for capture. This slip is a typical
condition in the prior art. In order to prevent such a slip from
occurring, the preferred embodiment utilizes an extended range
logic circuit to inhibit such phase slips.
Referring to FIG. 10, an extended range logic circuit 120 is
utilized in conjunction with the phase comparator circuit of FIG.
8. Same two input signals .THETA..sub.I and .THETA..sub.f are
coupled to the extended range logic circuit 120. The UP and DOWN
output signals of the circuit of FIG. 8, now labeled as PU and PD,
respectively, are coupled as inputs to multiplexer (MUX) 121 along
with two control outputs EPU and EPD from extended range logic
circuit 120. MUX 121 selects either the PU/PD or the EPU/EPD as
output APU/APD, which provide the phase error signal to the next
stage.
Also referring to FIG. 11, a graphic illustration showing the
operation of circuit 109 of FIG. 10 is shown. Zero phase error
condition occurs at point 110a as was the case in FIG. 9. As phase
error accumulates, the PLL circuit moves along slope 111a, the
direction being dependent on the lead or lag error. When the
accumulated phase error is along slope 111a, extended range logic
circuit 120 is not utilized and circuit 109 operates as a circuit
by passing PU and PD signals through MUX 121, such that APU and APD
are equivalent to PU and PD, respectively. However, when the phase
error accumulation reaches point 117 or 118, circuit 120 is
utilized and MUX 121 selects EPU and EPD as output APU and APD.
An object of circuit 120 is to force a correction of the phase
error at a much greater magnitude than that provided by PU and PD.
That is, in the base circuit of FIG. 8, the rate of correction of a
phase error at all given points along slope 111a remains
approximately proportional to the error. As shown in FIG. 9, if the
phase error extends past the threshold level 112 before any
correcting factor can be applied, the circuit will slip one
complete phase. However, with circuit 120 of the present invention,
as the phase error accumulates along slope 111a, it will reach a
predetermined point 117 or 118 which causes circuit 120 to be
activated. When circuit 120 is activated, EPU and EPD correction
factor, which is significantly greater than the PU and PD
correction factor applied during the course of travel along slope
111a, will force the phase locked loop to return to position 110a
at a much faster rate. This faster error correction provided by
circuit 120 is shown in FIG. 11. When the phase error reaches the
point 117/118, EPU/EPD is generated by circuit 120 and passed
through MUX 121 as APU/APD, respectively. This results in an
increase in the rate of change of the loop filter voltage to
increase the charge rate of the loop filter capacitor resulting in
a faster response time of the loop. Zone 122 illustrates the area
of operation when circuit 120 is activated, and zone 122 also
exemplifies the increase in the correction voltage. Thus, as phase
error approaches a value where a complete phase shift can occur,
circuit 120 is activated to force the error to be compensated at a
much greater magnitude. The faster response rate is not used below
the limit points 117 and 118 because such a fast response rate near
point 110a is undesirable for loop stability.
The preferred embodiment provides for the fast response by
increasing the rate of change of the loop filter voltage such that
the rate of voltage change on the loop filter is four times the
change for normal operation. This is due to the fact that the
signals EPU and EPD are active four times longer, and as a result
of the increased rate of change on the filter voltage, the loop
frequency change per data period is increased. Because there is a
relationship between phase and frequency, the loop has the ability
to change phase at a greater rate when the extended capture range
is used.
Referring to FIG. 12, it shows the extended range logic circuit 120
as utilized in the preferred embodiment in reference to the primary
loop block diagram of FIG. 6 of the present invention. Also
referring to FIG. 13, it shows the various waveform diagrams of the
signals referenced in FIG. 12. The circuit 120 is comprised of slip
detection circuitry and slip compensation circuitry. D type
flip-flops 130, 131 and NAND gate 132 comprise the slip detection
circuitry. A SLIPCHK signal is coupled as an input to flip-flop 130
wherein the output is coupled to the input of D flip-flop 131 and
to one input of NAND gate 132. The other input of NAND gate 132 is
coupled to the output of D flip-flop 131. A .THETA..sub.F signal is
coupled to clock flip-flops 130 and 131. A reset signal is also
coupled to flip-flops 130 and 131 to reset these flip flops. The
output of NAND gate 132 is referenced as the SLIP signal.
In operation, data pulse inputs to digital control logic 74
generates data pulses 140. A SLIPCHK pulse, having a predetermined
duration, is generated whenever data pulse 140 is encountered. The
SLIPCHK signal is coupled as an input to flip-flop 130 wherein The
.THETA..sub.F signal clocks flip-flop 130. The timing is
established such that the output of NAND gate 132 is in a low
state, showing a non-slip condition, whenever the loop is operating
in a locked state or having a limited phase difference equivalent
to slope 111 a of FIG. 11. However, when the phase differential
enters region 122 as shown in FIG. 11, it is equivalent to the data
pulses 140 occurring at a considerable time difference from the
feedback signal .THETA..sub.F. In this instance, SLIPCHK signal
will have shifted such that when .THETA..sub.F clocks flip-flops
130 and 131, the output of NAND gate 132 is driven high showing a
slip condition, which is equivalent to the circuit extending beyond
limit points 117 and 118 in FIG. 11. The output of NAND gate 132 is
coupled as one input to NAND gate 135 and 136, as well as to one
input of NOR gate 137. The SLIP signal will activate either NAND
gate 135 or 136 depending on the direction of the slip.
The slip compensating circuitry compares .THETA..sub.I2 and
.THETA..sub.F to determine the direction of the slip and generates
appropriate correction signals for generation of EPU and EPD
signal. .THETA..sub.I2 is coupled to clock flip-flop 133, and
.THETA..sub.F is coupled to clock flip-flop 134. The inverted
outputs of each of these flip-flops are coupled to the D input of
the other respective flip-flop. The non-inverted output of
flip-flop 133 is coupled to the input of flip-flop 141. Flip-flop
141 has a level trigger, although such a requirement is not
essential to the function of a latch represented by flip-flop 141.
SLIPCHK signal is coupled through inverter 138 to reset the input
of flip-flops 133 and 134 as well as to a second input or NOR gate
137, and ENABLE signal is also coupled as a third input to NOR gate
137. The output of NOR gate 137 is coupled to flip-flop 141
directly, as well as through inverter 139 for activating flip-flop
141 to update the data.
In operation, when the loop is in a locked condition, the leading
edges of .THETA..sub.I2 and .THETA..sub.F occur approximately at
the same time as shown by the lines 142 and 143 linking the leading
edges of .THETA..sub.I2 and .THETA..sub.F in FIG. 13.
When the loop is operating in the unlocked condition, input
.THETA..sub.I2 will occur either earlier or later by a duration 144
or 145, respectively as shown in FIG. 13. Flip-flops 133 and 134
will determine the direction of the phase difference between
.THETA..sub.I2 and .THETA..sub.F, and circuit 141 will store the
direction of the phase difference, that is if it is leading or
lagging. Flip-flops 130, 131 monitor the phase error in the loop
and assert slip through 132 when the phase error exceeds the lip
threshold. Gates 137-139 restrict 141 updates to non-slip
periods.
Whenever the limit of the slip condition is reached, which is
equivalent to area 122 of FIG. 11, SLIP signal will activate NAND
gates 135 and 136 to permit magnitude data from flip-flop 141 to
pass as output EPU or EPD. Basically, devices 133-134, 137-139
function to decode the direction of the slip and is used when a
certain limit level is reached.
In the preferred embodiment, NAND gates 148 and 149 are utilized to
comprise MUX 121 of FIG. 10. EPU and PU are coupled as inputs to
NAND gate 148, and EPD and PD are coupled as inputs to NAND gate
149. When the slip condition is not encountered, NAND gates 135 and
136 are deactivated permitting signals PU or PD to pass through
NAND gates 148 and 149 to generate APU and APD signals,
respectively. However, when the slip condition occurs, NAND gates
135 and 136 are activated and one of two signals, EPU or EPD is
passed through to NAND gates 148 and 149, respectively. In this
instance, because of the duration of the EPU and EPD signals being
of significantly longer duration than PU and PD signals, the EPU or
the EPD signal will override the PU and PD signals such that the
output of NAND gate 148 and 149 will be governed by one of EPU or
EPD signals.
Thus, a dual loop phase locked loop system has been described which
also uses a dual settling time response to phase slippage. Further,
the PLL of the present invention is implemented on a single
semiconductor integrated circuit chip.
* * * * *