Multiple digit display employing single digit readout

Abstract

Display of multiple digit information is carried out in a single digit readout device by serially flashing the information digits on the readout device in a predetermined order. Each digit is shown for a fraction of a second, typically on the order of one-fourth second. After each digit is displayed, the readout device is blanked in such a manner that the duration of the blanking period provides an indication of the relationship between successive digits. Thus, the blanking periods between successive digits within a group having a common range of significance may have a first duration approximating the duration for which each digit is displayed whereas the blanking periods between the last digit within a group and the first digit within a succeeding group may have a second, longer duration, typically twice the digit display duration.

Description

This invention relates to information display and, more particularly, to a multiple digit display employing a single digit alphanumeric readout.

Displays for effecting communication of multiple digit alphanumeric information take many forms well known in the art. The prior art displays have one common characteristic; viz.: a plurality of digits, generally the complete information set, is displayed simultaneously utilizing a corresponding plurality of display digits. For example: a cash register display given a simultaneous readout of all digits in dollars and cents or other exchange medium, a digital clock display simultaneously presents hours and minutes and sometimes also seconds, and a computer console display typically includes a great deal of simultaneously presented information.

For a multitude of uses, there is no significant drawback to utilizing the general prior art approach of presenting multiple digit information with a corresponding plurality of readout digits. However, the cost of providing a multiple digit display must always be considered. In addition, certain environments and applications bring other factors into account. Space which can be dedicated to the display may be limited which requires either the utilization of undesirably small individual display elements in the display array or some other compromise such as decreasing the number of digits displayed. Power consumption is a critical factor in portable apparatus, particularly in applications where battery size is severely limited. A notable example is to be found in the field of electronic digital watches.

Thus, those skilled in the art will readily appreciate that it would be highly desirable to provide simplified means for reliably effecting multiple digit alphanumeric readout, which means occupies much less space than known readouts for effecting this function and which consumes a great deal less power.

It is therefore a broad object of my invention to provide improved multiple digit information display means.

It is another object of my invention to provide such display means which occupies a minimum of space while affording improved legibility.

In another aspect, it is an object of my invention to provide multiple digit alphanumeric readout means which affords a manifold decrease in power consumption.

Briefly, these and other objects of the invention are achieved by utilizing a single digit display on which multiple digits comprising an information set are serially flashed in a rapid burst periodically or upon interrogation. Differing blanking periods between sequential digits are introduced to provide order and grouping information.

The subject matter of the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification.

The invention, however, both as to organization and method of operation, may best be understood by reference to the following description taken in connection with the accompanying drawing of which:

FIGS. 1a and 1b, taken together, are a generalized flow diagram setting forth the method of the present invention; and

FIGS. 2a and 2b, taken together, constitute a logic diagram of an exemplary environment in which the invention may be practiced.

It will be observed from FIG. 1 that the fundamental basis of the method of the present invention lies in the realization that serially presented multiple digit information can be readily assimilated if the total number of digits is not excessive, if the type of information being conveyed is known, and if the presentation is keyed by periods during which the display is blanked for predetermined durations, More particularly, it has been found that such multiple digit information can be assimilated with accuracy similar to that achieved with parallel, simultaneous displays when the serial display rate flashes each digit for one-fourth second or less.

By way of example, six digit time (hours, minutes, seconds) may be displayed on a one digit readout according to the present invention by serially ordering the digits from most significant (tens of hours) to least significant (units of minutes) and further providing distinguishing pauses between the hours digits, between the minutes digits, and between the seconds digits. A complete display cycle is divided into 16 equal time periods of approximately one-fourth second each. The tens of hours digit is flashed on the display element for one time period. The display is then blanked for one time period after which the units of hours digit is presented for one time period. Next, the display is blanked for two time periods to indicate the separation between hours and minutes information. The two minutes digits are each flashed on for one time period separated by a single time period during which the display is blanked, and the seconds digits are similarly presented. After the units of seconds digit has been displayed for one time period, the readout is blanked for three time periods to signify the beginning of another complete display cycle.

Those skilled in the art will readily appreciate that the concept to which the present invention is directed is not limited to the readout of time or even six digits. A display for reading, for example, Social Security numbers would be given in a burst of nine figures in a three-digit, two-digit, four-digit pattern. Similarly, a telephone number would be presented in a three-digit, four-digit pattern, or if area code information were included, a three-digit, three-digit, four-digit pattern. Other patterns meaningful in presenting various information will occur to those skilled in the art.

In order to illustrate an exemplary environment in which the invention may be practiced, FIG. 2 (2a and 2b taken together), a logic diagram of a six-digit clock utilizing a single read-out element, will not be discussed. A time base signal is developed by a 60 hz generator 1. The time base generator 1 may be dependent upon power line frequency, a frequency subdivided crystal oscillator, a low frequency relaxation oscillator, or such other standard as may be appropriate. It will be understood, of course, that 60 hz is simply convenient for the specific apparatus of FIG. 2, and other time base frequencies find use in appropriate applications. Four binary frequency divider stages 2, 3, 4, and 5 reduce the 60 hz time base signal to 30, 15, 71/2 and 33/4 hz. The 71/2 hz signal is applied to the first of four additional cascaded binary frequency dividers 6, 7, 8, and 9, each of which has a "1" output when the corresponding stage is in a first state. The output from the binary divider stage 6 is applied to input terminals of logic inverters 16 and 24. Similarly, the output from binary stage 7 is applied to the input terminals of inverters 14 and 22, and the output of binary stage 8 is coupled to the input terminals of inverters 12 and 20. However, it wil be noted that the output from the divider stage 9, in addition to being directly connected to the input of inverter 18, is also connected to the input of an inverter 43 which, in turn, drives inverter 10. Assigning the mnemonic designations A0, A1, A2, and A3 to the respective outputs of divider stages 6, 7, 8, and 9, it will be seen that the output signals from inverters 16 and 24 are both A0, the output signals from inverters 14 and 22 are A1, the output signals from inverters 12 and 20 are A2, the output signals from inverter 10 is A3, and the output signal from inverter 16 is A3. Inverters 10-24 respectively drive a second array of inverters 11-25 to provide logically reinverted signals for combination with the inverted signals to develop 16 sequential time periods. Inverters 11 and 19 are not used and are shown only because they are present in the specific integrated circuits (which will be referenced below) from which the exemplary embodiment of the apparatus has been fabricated.

Each gate of an array of 16 NAND gates 26-42 inclusive is provided with four inputs. These inputs receive the outputs of the inverters 10-25 in 16 unique combinations as shown in FIG. 2. The NAND gates 26-42 will therefor sequentially issue respective output signals T0-T16. For example, the logic equation which will cause the NAND gate 26 to issue the signal T0 is A0.sup.. A1.sup.. A2.sup.. A3. Similarly, the logic combination which will cause the NAND gate 36 to issue the T10 signal is A0.sup.. A1.sup.. A2.sup.. A3.

It will be observed that the signal A0 changes logic level at a frequency of 3.75 hz. Since A1, A2, and A3 are slower by powers of 2, A0 governs the rate at which the logic pattern issued by the dividers 6, 7, 8, and 9 changes. The duration of each time period for the logic configuration of FIG. 2 is therefore 1/3.75 seconds or 266.7 milliseconds. It will be noted that the time period duration could be doubled by driving binary divider stage 6 from divider stage 4 or halved by driving stage 6 from stage 5. However, experience has shown that a 133.3 millisecond time period is too brief for best assimilation whereas 533.3 milliseconds is much longer than necessary.

A 60 hz signal from the time base generator 1 is also applied to the reference frequency input of clock chip 44. The logic within the clock chip 44 is quite complex. However, only the functions carried out by the clock chip are of direct pertinence to the present invention, and therefore no detailed analysis of the logic will be attempted. A commercially available clock chip will be referenced below to permit those skilled in the art to readily reproduce the exemplary embodiment of the invention described herein.

The clock chip 44 accepts the 60 hz time base signal and issues a multiplexed BCD output to logic inverters 45, 46, 47, and 48 to provide, respectively, the signals 2.sup.3, 2.sup.2, 2.sup.1, and 2.sup.0. The digit value signals are applied to appropriate inputs of a single digit readout device 49. The readout device 49 also includes logic circuitry which is of no direct import to an understanding of the present invention. It should be noted, however, that the exemplary embodiment utilizes a readout device which includes a 4-bit latch such that a strobe pulse is necessary to introduce new information to the display. A commercially available readout device incorporating this end and other functions to be described will be referenced below.

The clock chip 44 also issues, at any given time, one of six signals to indicate which digit of the clock presentation is currently available at the BCD outputs. These signals, after passing through inverters 50-55, are assigned the mnemonic designations HT, HU, MT, MU, ST, and SU representing tens of hours through units of seconds. The strobe pulse necessary to introduce a new digit into the readout device 49 is developed by combining certain of the clock pulses with the digit multiplex information from the clock chip 44. Thus, TO and HT are applied as the two input signals to NAND gate 56; T2 and HU signals are applied as the two inputs to NAND gate 57; and T5 and MT are applied as the two inputs to NAND gate 58. Similarly, NAND gates 59-61 are selectively enabled. All outputs from the NAND gates 56-61 are connected together and applied to the strobe input to the readout device 49.

The clock chip 44 utilized in the exemplary embodiment of the apparatus incorporates an internal multiplexing oscillator which can however be externally frequency controlled. The multiplexing frequency is not critical so long as it is well above the step frequency from time period to time period. A multiplex frequency of approximately 1 Khz has been found to be satisfactory in the exemplary embodiment. Thus, during T0, digit information from clock chip 44 will be strobed into the internal 4-bit latch of the readout device 49 only when the signal HT is present to fully enable NAND gate 56. Similarly, as another example, during T10, only the signal ST can cause a strobe pulse to be generated by fully enabling the NAND gate 60. As a result, the readout device 49 can accept only tens of seconds information from the clock chip 44 during T10.

It has been found that comprehension of the displayed information can be improved by methodically blanking the readout device 49 between the display of successive digits. Perception of the distinction between the hours and minutes and between the minutes and seconds is achieved by lengthening the blanking period between the units of hours digit and the tens of minutes digit and between the units of minutes digit and the tens of seconds digit. Further improvement in assimilation is achieved by blanking the readout device 49 for a somewhat longer period between the display of the units of seconds digit and commencement of a successive complete readout cycle starting with the tens of hours digit.

A blanking input to the readout device 49 is provided such that it is only necessary to determine during which time periods the readout device 49 is to be blanked and to suitably combine the time period signals. This function is carried out by NOR gate 62 which accepts T1, T3, T4, T6, T8, T9, T11, T13, T14, and T15 as input signals with its output coupled to the blanking input of the readout device 49.

Thus, a full 6-digit display cycle takes place as follows. During T0, the tens of hours digit is displayed. During T1, the readout device 49 is blanked to separate the tens of hours digit from the units of hours digit. During T2, the units of hours digit is displayed. During T3 and T4, the readout device is blanked to separate the units of hours and the tens of minutes digits and also, as a result of the extended blanking duration, provide an indication of the separation between the hours digit pair and the minutes digit pair. Similarly, the tens of minutes and units of minutes digits are displayed during T5 and T7, respectively, with the readout device being blanked during T6 and also during T8 and T9 to separate the minutes digit pair from the second digit pair. The seconds are read out during T10 and T12 separated by T11. Then, the display is blanked for the whole of T13, T14, and T15 to provide an indication that the entire display cycle has been completed and that a new display cycle follows.

The relationship of the time durations of the various blanking phases to the time durations during which digits are displayed has been found to be readily implemented with binary logic. That is, equal blanking duration is provided between successive digits having the same order of significance (such as the hour digits, dollar digits, etc.) while the extended duration between successive digits which constitute the last digit of a group of digits in one range of significance and the first digit in the next digit group (hours to minutes, dollars to cents, etc.) may usefully be twice as long. The duration of blanking between the end of a complete display and the institution of a succeeding display may be accommodated to a particular application. One time period increment in excess of the maximum blanking period used during a display has been found to give entirely sufficient psychological warning of the beginning of a display event.

In order to permit those skilled in the art to readily practice the invention, the following component information is provided to permit fabrication of a replica of the FIG. 2 apparatus. As previously noted, the 60 hz generator 1 may take any one of many forms well known to all skilled in the art. For high accuracy, a superior crystal oscillator and appropriate countdown logic may be utilized. Alternatively, a useful signal may be developed from a 60 hz power line of suitable frequency integrity. For simplicity, a 60 hz relaxation oscillator may be used.

The binary divider stages 2-9 are two 4-bit integrated circuit binary counters, designated 9316, manufactured by Fairchild Semiconductor. Inverters 10-25 and NAND gates 26-42 comprise two integrated circuit one-of-10 decoders utilized as one-of-8 decoders and manufactured under the disignation 9301 by Fairchild. The inverters 43, 45-55, and 63-58 available on three integrated circuits designated 9016 by Fairchild. The NAND gates 56-61 are contained on two Fairchild 9002 integrated circuits. The NOR gate 62 is contained on two Fairchild type 9007 integrated circuits. The single digit readout device 49 is a Texas Instruments type T1L311 light emitting diode unit. The clock chip 44 is a type MM5313, manufactured by The National Semiconductor Corporation. One may refer to Fairchild TTL Data Book (June, 1972), National Semiconductor Specification Sheet for MM4311/MM5311, MM4312/MM5312, MM4313/MM5313, MM4314/MM5314 Digital Clock Chip (June, 1972), and Texas Instruments Bulletin DL-S 7211653 for Type TIL311 Hexadecimal Display with Logic (March, 1972) for detail of the internal logic and circuitry of the elements employed in the exemplary apparatus. Those skilled in the art will understand that the selection of logic type and readout device type is strictly a matter of design choice and that many different choices are available to the practitioner.

In order to set the clock, switches 69, 70, and 71 are provided to provide fast slew, slow slew, and hold functions, respectively, by momentarily applying a V.sub.do signal to appropriate inputs of the clock chip 44. When switch 69 is closed, the internal logic of the clock chip 44 responds by advancing the internal time by 1 hour per second. Similarly, actuating switch 70 advances the internal time by one minute per second. Actuation of the switch 71 inhibits incrementing the internal time to effect a hold feature.

While the principles of the invention have now been made clear in an illustrative embodiment, there will be immediately obvious to those skilled in the art many modifications of structure arrangements, proportions, the elements, materials, and components used in the practice of the invention which are particularly adapted for specific environments and operating requirements without departing from those principles.

Claims

What is claimed is:

1. A method for displaying multiple digit information comprising the steps of:

A. arranging the digits in a predetermined order of significance from most significant to least significant;

B. displaying the most significant previously undisplayed digit on a single digit readout device for a period having a first predetermined duration, said first predetermined duration being in the range from one-eighth to one-half second;

C. blanking the readout device for a period having a second predetermined duration, said second predetermined duration being in the range from one-eighth second to one-half second;

D. repeating steps (B) and (C) until all digits of the information have been displayed.

2. The method of claim 1 which includes the additional steps of:

A. arranging the digits in a plurality of groups of one or more successive digits, each of the digits within a given group having a common range of significance; and

B. blanking the readout device for a period having a third predetermined duration between the last displayed digit of a group and the first displayed digit of a succeeding group.

3. The method of claim 2 in which the third predetermined duration is longer than each of the first and second durations.

4. The method of claim 3 which includes the further sequential steps of:

A. blanking the readout device for a period of longer duration than each of the first, second, and third durations after the last digit of the multiple digit information has been displayed: and

B. instituting another cycle of display by returning to step A of claim 1 and repeating the foregoing steps.

5. The method of claim 3 in which the first and second durations are equal.

6. The method of claim 5 in which the third duration is twice the first duration.