Electronic timepiece

Abstract

To facilitate acceleration or deceleration of the stepping rate of a clockwork motor responding to pulses from a frequency divider connected to a crystal-controlled oscillator, an Exclusive-OR gate is inserted between the oscillator and the divider and has another input connected to several stage outputs of the divider by way of a branched feedback circuit. The divider and its feedback circuit form a time-delay loop whose delay time corresponds to a small fraction of a cycle of the oscillator frequency whereby the pulse rates from the oscillator and from the feedback circuit are invariably added in the input of the divider. Logic gates in the several branches of the feedback circuit have inputs connected to selectively energizable terminals for enabling optional blocking and unblocking of certain branches to vary the pulse rate in the divider output.

Description

FIELD OF THE INVENTION

Our present invention relates to an electronic timepiece wherein a time-indicating display unit is driven by a clockwork including a stepping motor, or equivalent means, responsive to a train of electrical pulses derived with the aid of a binary frequency divider from a primary pulse source, such as a crystal-controlled oscillator, serving as a high-frequency standard.

BACKGROUND OF THE INVENTION

In order to increase or reduce the stepping rate of such a timepiece, it has heretofore been the practice to change a parameter in the oscillator circuit which determines its resonance frequency, e.g. by adjusting a variable capacitor. This expedient, however, does not assure a stable long-term correction since the capacitances of variable condensers are subject to drift.

OBJECT OF THE INVENTION

The object of our invention is to provide an improved electronic timepiece enabling precise and lasting adjustment of its stepping rate.

SUMMARY OF THE INVENTION

This object is realized, in accordance with our invention, by the insertion of an anticoincidence gate, such as an Exclusive-OR (hereinafter referred to as EX-OR) gate or its logical negation, between a source of standard high-frequency pulses and an associated binary frequency divider, this gate having a first input connected to the source and a second input connected to certain stage outputs of the divider through branched feedback circuitry whereby the lower-frequency pulse trains issuing from the respective divider stages are logically combined with the standard pulse train so as to modify the mean pulse rate in the divider input. Selected branches of the feedback circuitry are optionally open-circuitable and short-circuitable to vary that mean pulse rate and thereby the stepping rate of a pulse-responsive device connected to one or more stage outputs of the divider.

We have found that an anticoincidence gate, in contradistinction to AND and OR gates, invariably produces a sequence of output pulses whose mean rate or cadence is the sum of the cadences of two harmonically related pulse trains received at its inputs, provided that a certain relative phase shift exists between overlapping pulses of the two harmonically related trains so that their leading edges and their trailing edges do not exactly coincide. This phase shift, resulting in a narrow gap in what would otherwise be a broader pulse or in a narrow spike where otherwise no pulse would be generated, is achieved in accordance with a further feature of our invention by such a dimensioning of the elements of the divider and its feedback circuitry that the same form a time-delay loop with a delay time equal to a fraction of a pulse cycle of the standard source. If necessary, special delay units may be included in the feedback circuitry for this purpose.

BRIEF DESCRIPTION OF THE DRAWING

The above and other features of our invention will be described in greater detail hereinafter with reference to the accompanying drawing in which:

FIG. 1 is a circuit diagram of a pulse-train synthesizer for the adjustable stepping of a clockwork in accordance with our invention;

FIG. 2 is a set of graphs showing waveforms of pulse trains appearing at several points in the system of FIG. 1;

FIG. 3 is a circuit diagram similar to FIG. 1, showing a modified pulse-train synthesizer according to our invention;

FIGS. 4A, 4B and 5 are sets of graphs relating to the operation in the system of FIG. 3;

FIG. 6 is a perspective view of a physical realization of a terminal assembly serving to control the pulse rate in the system of FIG. 3; and

FIGS. 7, 8 and 9 are plan views of modified terminal assemblies of the type shown in FIG. 6.

SPECIFIC DESCRIPTION

In FIG. 1 we show a pulse-train synthesizer for an electronic timepiece according to our invention. FIG. 2 shows waveforms of pulse trains appearing at various points of the circuit shown in FIG. 1 where reference numeral 91 designates a crystal-controlled oscillator circuit whose operating frequency is 2.sup.21 Hz. A frequency divider 95 receives the oscillator output f.sub.S and a feedback wave f.sub.X from a circuit 93, controlling the step-down ratio of this frequency divider, through an EX-OR gate 911. A combination of stage outputs Q.sub.16 -Q.sub.21 of divider 95 work into a clockwork 96 of the electronic timepiece which includes a NAND gate 961 connected to these outputs, an electromechanical converter 97 stepped by the output of gate 961 via a pulse shaper 962, and a display 98 driven by motor 97 for indicating the time in the conventional manner. Circuit 93 has a control input 94 with selectively energizable terminals J.sub.0 -J.sub.9 connected to respective NAND gates 92 which derive low-frequency pulse trains from stages Q.sub.12 -Q.sub.21 of frequency divider 95 in response to the selected pattern of energization of the terminals J.sub.0 -J.sub.9. The output has a frequency of about 1 Hz. If the terminals J.sub.0, J.sub.1 . . . J.sub.9 are de-energized, the frequencies of the stage outputs Q.sub.21, Q.sub.20, . . . Q.sub.12 are combined by means of cascaded EX-OR gates 931 and added to the signal f.sub.S from the crystal oscillator 91 in gate 911. The signal f.sub.in thus obtained is supplied to an input terminal 912 of the frequency divider 95.

The pulse frequency f.sub.out at the output 913 of the last stage of the frequency divider 95 is given by

f.sub.out = f.sub.in .sup.. 2.sup..sup.-21

If the frequency of the output signal f.sub.S of crystal oscillator 91 be f.sub.00, then ##EQU1## The circuit shown in FIG. 1 is simple in construction but requires a series of fairly stable delay elements 910 in order to produce a phase shift .DELTA.t around the feedback loop which, as shown in FIG. 2, is a small fraction of a cycle of pulse sequence f.sub.S. This delay is essential in order that the mean pulse rate of train f.sub.in be the exact sum of the pulse rates f.sub.S and f.sub.X. The phase shift .DELTA.t results in a narrow gap in the region of the leading edge and a narrow spike in the region of the trailing edge of a pulse of train f.sub.X which, as shown, is harmonically related to train f.sub.S.

In FIG. 3 we have shown another circuit for changing the step-down ratio of a frequency divider which is simple in construction and may be used for adjusting a pulse cadence in a manner not subject to any change over a length of time. The output from an oscillator circuit 112, controlled by a crystal 111, is supplied through an EX-OR gate 113 to a frequency divider 114 constituted by a binary counter with n stages formed by flip-flops FF1-FF10.

The output terminal of the frequency divider 114 is connected to a mechanical converter such as a motor stepped by the oncoming pulses and may be operated by means of a gear mechanism or electronically to drive a display 116 for indicating the time as in the preceding embodiment. A feedback circuit for adjusting the step-down ratio has input leads 117a to 117d for selectively blocking or unblocking a group of AND gates 71 to 74 whose other inputs are connected to various stage outputs of the frequency divider 114 in the order indicated in FIGS. 3 and 5. The AND gates 71 to 74 work through an OR gate 75 into the EX-OR gate 113. According to which of the leads 117a to 117d are selectively short-circuited or open-circuited, corrective pulses are fed back to the EX-OR gate 113 at different rates to change the mean pulse cadence in the input of divider 114.

FIGS. 4A and 4B illustrate how, in gate 113, the output signal f.sub.S of the oscillator is combined with a feedback signal f.sub.X of either one-fourth or one-half the oscillator frequency to provide an input signal f.sub.in of increased mean cadence, the two pulse trains being relatively phase-shifted by a delay .theta. introduced in the feedback loop.

In FIG. 5 we have shown the phase position of the output signals from the AND gates 71 to 74 when the corresponding leads 117a to 117d are short-circuited. The AND gate 71 is connected to stage outputs Q.sub.14, Q.sub.13, Q.sub.10 and emits spaced-apart groups of four pulses.

The AND gate 72 is connected to stage outputs Q.sub.14, Q.sub.13, Q.sub.11 and emits similarly spaced pulse pairs.

The AND gates 73 and 74, respectively connected to stage outputs Q.sub.14, Q.sub.12, Q.sub.13 and Q.sub.15, Q.sub.14, Q.sub.13, Q.sub.12, emit single pulses with different recurrence periods.

In FIG. 6 we show a physical realization of the severable connections formed by leads 117a-117d in FIG. 3. A metallic holder 141 for a crystal oscillator 140 is provided at one edge with comb-shaped (ctenoid) projections or tongues forming the leads 117a to 117d extending to an integrated module 149 incorporating a frequency divider and its rate-adjusting feedback circuit, the assembly being mounted on a base plate 148 for the electronic timepiece. In the present embodiment, the lead 117b is cut while the other leads are intact.

FIG. 7 shows ctenoid leads 142 made of metal and incorporated into the electronic timepiece. The leads overlie a printed portion 143 of base plate 148.

FIG. 8 shows modified leads 144, two of them severed and two made continuous by means of solder 145.

FIG. 9 shows another embodiment with three concentric leads 151 which are selectively engageable by a sliding contact arm 150 rotatable about a center shaft. The sliding arm 150 is fixed to the shaft in its correct position by means of a screw 152.

For a more precise adjustment of the rate of the electronic timepiece, the number of leads may be increased and additional circuitry may be included to provide properly phased signal feedback.

If practice, it is preferable to effect a coarse adjustment of the electronic timepiece by means of the terminal portions shown in FIGS. 6 to 8 and a precise adjustment by means of the contact assembly shown in FIG. 9.

Claims

What is claimed is:

1. An electronic timepiece comprising:

a source of electrical pulses having a constant elevated frequency;

a multistage binary frequency divider for producing lower-frequency pulse trains at a plurality of stage outputs thereof;

pulse-responsive means connected to at least one of said stage outputs for stepping by the pulse train thereof;

an anticoincidence gate inserted between said source and said frequency divider having a first and a second input, said first input being connected to said source;

time-indicating means connected to said pulse-responsive means;

feedback means having branches coupling said second input to certain of said stage outputs for logically combining said lower-frequency pulse trains thereof with said electrical pulses; and

circuit-breaking means in said feedback means for optionally open-circuiting and short-circuiting selected branches of said feedback means to vary the stepping rate of said pulse-responsive means.

2. A timepiece as defined in claim 1 wherein said frequency divider and said feedback means form a time-delay loop with a delay time equal to a fraction of a pulse cycle of said source.

3. A timepiece as defined in claim 1 wherein said anticoincidence gate is an Exclusive-OR gate.

4. A timepiece as defined in claim 1 wherein said circuit-breaking means comprises a mechanical switch.

5. A timepiece as defined in claim 1 wherein said circuit-breaking means comprises a set of logic gates in said branches having first inputs connected to selectively energizable terminals, second inputs connected to said certain stage outputs, and outputs coupled to said second input of said anticoincidence gate.

6. A timepiece as defined in claim 5 wherein the connections between said terminals and the said first inputs of said logic gates include a multiplicity of individually severable leads.

7. A timepiece as defined in claim 6 wherein said leads are a set of ctenoid metallic tongues.