Electronic timepiece

Abstract

An electronic timepiece adjustment circuit is provided for allowing adjustment of the division ratio of the divider circuit of an electronic timepiece by external switching circuitry. An electronic timepiece includes an oscillator circuit for producing a high frequency time standard signal and a divider circuit having an adjustable division ratio to produce a low frequency time standard signal in response to a high frequency time standard signal applied thereto. Adjustment circuitry is coupled to the divider means for adjusting the division ratio of the divider circuit to produce a low frequency standard signal of a predetermined frequency in response to the high frequency signal applied thereto. Switching circuitry is adapted to produce input data signals representative of a predetermined period of time. Calculator circuitry produces signals determinative of the amount of adjustment of the division ratio in response to the application of the input data signals thereto. A memory circuit is adapted to apply the division ratio adjustment signals to the adjustment means in response to said predetermined low frequency signal for each period of said predetermined low frequency signal produced by the divider circuit.

Description

BACKGROUND OF THE INVENTION

This invention is directed to adjusting the division ratio of a divider circuit in an electronic timepiece, and in particular to circuitry for enabling the division ratio to be adjusted by manually operating a switch externally disposed on an electronic timepiece. In electronic timepieces wherein the count of the divider circuit is advanced or retarded and therefore does not produce a low frequency standard signal representative of actual time, the manner in which adjustment of the electronic circuitry is effected to produce a low frequency time standard signal of a predetermined frequency, has been less than completely satisfactory.

Most conventional high precision electronic timepieces utilize a quartz crystal oscillator circuit to produce a high frequency time standard signal. In such timepieces adjustment of the low frequency signal produced by the divider circuit requires adjustment of the frequency at which the oscillator circuit oscillates. Accordingly, highly stable period-measuring instruments are required to regulate the output of the quartz crystal oscillator circuit in order to guarantee that the low frequency time standard signal produced by the divider circuit is maintained at a predetermined frequency. Because such instruments are expensive, only certain stores which distribute electronic watches carry such instruments. Moreover, watch specialty stores cannot justify the expense of keeping such measuring instruments for adjusting the few electronic timepieces requiring such adjustments. Thus, when the frequency of the quartz crystal oscillator circuit is altered or shifted by shock or aging, adjustment of the timepiece becomes difficult. Similarly, the difficulty in adjusting the timepiece after a change of battery and furthermore, the greater accuracy of the timepiece immediately after the battery is exchanged than at the end of the battery life, render such adjustment necessary. Accordingly, it is desired to provide adjustment circuitry for allowing an operator to adjust the frequency of an electronic timepiece with the same facility that correction of the time displayed thereby is achieved.

SUMMARY OF THE INVENTION

Generally speaking, in accordance with the invention, an electronic timepiece having a switch disposed on the timepiece for effecting adjustment of the electronic circuitry to produce a low frequency time standard signal of a predetermined value is provided. The electronic timepiece includes an oscillator circuit for producing a high frequency time standard signal, a divider circuit having an adjustable division ratio for producing a low frequency time standard signal in response to a high frequency time standard signal applied thereto, and adjustment circuitry coupled to the divider circuitry to adjust the division ratio thereof to thereby produce a low frequency time standard signal of a predetermined frequency. Switching circuitry is provided for producing input data signals representative of a predetermined period of time and calculator circuitry produces signals determinative of the amounts of division ratio adjustment in response to the data signals. A memory is adapted to supply the division ratio adjustment signals to the adjustment means in response to the predetermined lower frequency signal applied thereto, the memory being adapted to apply the division ratio adjustment signals to the adjustment circuitry once during each period of the predetermined lower frequency signal produced by the divider circuit.

Accordingly, it is an object of this invention to provide an improved electronic timepiece wherein adjustment of the low frequency time standard signal produced by the divider circuit can be effected by a switch externally disposed on the timepiece.

Another object of this invention is to provide an improved electronic timepiece wherein the division ratio of the divider circuit is automatically adjusted.

Still another object of the invention is to provide an improved electronic timepiece utilizing a quartz crystal oscillator circuit wherein the low frequency time standard signal can be adjusted without affecting the oscillator circuit.

Still a further object of this invention is to provide an improved small size electronic wristwatch wherein the accuracy thereof is adjustable by the wearer.

Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.

The invention accordingly comprises the features of construction, combination of elements, and arrangement of parts which will be exemplified in the construction hereinafter set forth, and the scope of the invention will be indicated in the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

For a fuller understanding of the invention, reference is had to the following description taken in connection with the accompanying drawings, in which:

FIGS. 1 and 1A are a block circuit diagrams of an electronic timepiece adjustment circuit constructed in accordance with the instant invention;

FIG. 2 is an illustration of a binary table representative of the output signals from the counting circuit illustrated in FIG. 1;

FIG. 3 is a wave diagram of the output signals produced by the electronic timepiece circuit illustrated in FIG. 1;

FIG. 4 is a detailed circuit diagram of the counters, distribution, gating, and memory circuits illustrated in FIG. 1;

FIG. 5 is a block circuit diagram of a digital display portion of an electronic timepiece particular adapted to be utilized with the electronic timepiece illustrated in FIG. 1;

FIG. 6 is a block circuit diagram of an alternate embodiment of the adjustment circuitry utilized in an electronic timepiece constructed in accordance with the instant invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Reference is now made to FIGS. 1 and 3, wherein electronic circuitry, and signals produced thereby, particularly suited for use in an electronic digital display timepiece are depicted. An oscillator circuit 2 includes a quartz crystal vibrator 1 as a time standard for producing a high frequency time standard signal 31. A binary divider 3 is adapted to produce an output signal 32 having half the frequency of the high frequency time standard signal 31. The output signal 32 from binary divider circuit 3 is applied to a multistage divider circuit 8 formed of a plurality of series connected divider stages through an EXCLUSIVE OR gate 7, in the absence of a further signal applied to the other input of EXCLUSIVE OR gate 7. The multistage divider circuit 8 in response to the signal applied thereto produces a low frequency time standard signal 30 which is applied to the divider circuits forming the display of the electronic timepiece, more particularly illustrated in FIG. 5.

The high frequency time standard signal 31 produced by oscillator circuit 2 is additionally applied through an inverter circuit 4 to a delay flip-flop 5 as a first input. The output signal 32 from binary divider 3 is also applied to the D terminal of flip-flop 5, and in response thereto produces at the Q terminal a delayed output signal 33 which is the complement of signal 33 of FIG. 3, signal 33 having the same period as signal 32 but delayed by one half the period of signal 31. A binary divider 6, in response to the delayed output signal 33 applies a signal 34 having half the frequency and the same phase as delayed output signal 33 to AND gate 9. The other input to AND gate 9 is applied by OR gate 10, in a manner to be hereinafter discussed more fully.

When the output of OR circuit 10 is in a 1 state (1 and 0 are hereinafter utilized to denote a first and second binary condition), the output 34 of binary divider 6 is applied to EXCLUSIVE OR gate 7 through AND gate 9, and in response thereto EXCLUSIVE OR gate 7 produces an adjusted output signal 35 in which the frequency of the signal 32 from binary divider 3 is adjusted. As illustrated in FIG. 3, the output signal 35 of the EXCLUSIVE OR gate is increased by one pulse for each pulse from AND gate 9. In effect, a pulse is added to signal 32 by EXCLUSIVE OR gate 7 for each pulse in signal 34 so long as the output of OR gate 10 is 1. Thus, in response to the increase in the frequency of the signal 35 applied to the multistage divider 8, the count of the low frequency time standard signal 30 is advanced. Also, the output signal from AND gate 9 is applied to a further AND gate 11, the output of which, is, in turn, applied to a subtraction counter 12. Signal 32 from divider 3 and the complement of signal 31 comprise the other inputs to AND gate 9. Signal 36 consists of one pulse for each pulse signal 34, the start of each pulse of signal 36 being delayed relative to the start of the pulses of signal 34. When subtraction counter 12 is counted to zero, the output of OR gate 10 is changed to a 0, thereby closing AND gate 9 and causing EXCLUSIVE OR gate 7 to apply the unchanged output signal 32 of binary divider circuit 3 to the multistage divider circuit 8, thereby terminating the advancing of the frequency of the low frequency signal 30 for one period thereof. Thus, pulses are added to the signal applied to the multistage divider circuit 8 until the subtraction counter is counted to zero, whereafter, the unchanged output signal 32 from the binary divider circuit 3 is applied to the multistage divider circuit. Series connected flip-flop circuits 22 and 23 are adapted to apply a differentiated control pulse once each period of the low frequency time standard signal 30, in order to ensure that the adjustment of the division ratio is effected once during each period of the signal produced by multistage divider circuit 8. Thus, the output signal 34 from binary divider 6 is applied to the C terminal of delay flip-flop 22, the input to the D terminal of delay flip-flop 22 being the low frequency time standard signal 30 produced by the multistage divider circuit 8. Flip-flop 23 receives the output Q from delay flip-flop 22 and is reset by the high frequency time standard signal 31 to thereby produce a short pulse for each pulse of signal 33. Accordingly, the pulse signal Q from flip-flop 23 is applied to gate 19, thereby opening gate 19 and allowing adjustment quantity information stored in memory 18, as is hereinafter discussed more fully, to be applied to the subtraction counter 12, to thereby reset same. This causes adjustment of the next period of signal 30 by the addition of a number of pulses from signal 34 to signal 32 corresponding to the adjustment quantity stored in memory 18. For a predetermined low frequency time standard signal of one second, gate 19 will be opened once each second to effect a resetting of subtraction counter 12 and effect an advancing of the pulse rate by adjusting the division ratio of the divider circuitry to thereby guarantee that low frequency signal 30 has a period of one second.

It is noted, that although the instant invention is explained in an advancement mode, as illustrated by the block A, including EXCLUSIVE OR gate 7, and NAND gate 9, retarding of the division ratio in order to retard the frequency of the low frequency time standard signal can be achieved by the adjustment circuit A' illustrated in FIG. 1A, AND gate 9 being replaced by a NAND gate 9' and EXCLUSIVE OR gate 7 being replaced by a NAND gate 7'. Also, it is further noted that subtraction counter 12 and NAND gate 19 are formed from conventional presettable counters and logic circuitry, well known in electronic arts. Finally, it is noted that both advancement and retarding of the time standard signal can be achieved by including both circuit A and A', and including gating circuitry for selecting the adjustment mode by detecting whether the count of the timepiece is advanced or retarded by utilizing the circuitry presented herein.

As detailed above, the adjustment quantity for each period of the low frequency divider signal is determined by presetting the subtraction counter 12 to a state which represents the amount of advancement or retardation of the time keeping signal necessary to correct the time. Accordingly, the instant invention includes a single push button switch 29 which is capable of being pressed at the beginning of a 24 hour interval such as 7:00 o'clock in the evening and may again be pressed at the end of a particular time interval such as 24 hours later or 7:00 o'clock the next evening, the 24 hour period being utilized as a reference time period by which the adjustment quantity will be determined. Accordingly, a manually operated two positioned push button switch 29 is coupled to the D terminal of a delay flip-flop 24 which is series connected to delay flip-flop 25, which in turn is series coupled to delay flip-flop 26. An additional input to each of the C terminals of the delay flip-flops 24 through 26, is the high frequency time standard signal 31. Delay flip-flops 24 through 26 serve to differentiate the signal from switch 29 to produce a pulse for each operation thereof. The Q and Q outputs of flip-flops 24 and 25 respectively are connected to AND gate 27 to produce a 1 output at said gate for application to AND gate 21 in response to each operation of switch 29. The Q and Q outputs of flip-flops 25 and 26 respectively are connected to AND gate 28 to produce a 1 output at said gate for application to counters 13, 14 and 15 in response to each operation of switch 29. However, the output of AND gate 28 is delayed a predetermined period after the output of AND gate 27.

A calculator circuit is provided including series connected counting circuits 13, 14 and 15 coupled to the output of binary divider 3 in order to count the signal produced thereby. When the counted value in counting circuit 15 is at a predetermined value, AND circuit 20 is opened, thereby supplying a 1 to AND gate 21 to effect an opening thereof when a one is coincidently applied from AND gate 27. The coincident application of pulses from AND gate 20 and AND gate 27 to AND gate 21 effects an opening of gate 17 to thereby allow the information counted in counter 14, and processed in distribution circuit 16, which information represents the adjustment quantity necessary to be applied through gate 17 and stored in memory 18. Thereafter, an output is produced by AND gate 28, to effect a resetting of counters 13, 14 and 15 to zero.

In operation, switch 29 is pushed at a referenced time such as 7:00 o'clock in the evening in response to a referenced signal from a radio, T.V. or the like. At that time, AND circuit 20 is at 0, and accordingly, gate 17 remains closed and the information stored in memory 18 is unchanged. Closing of the switch 29 also effects a resetting of counters 13, 14 and 15 to zero. The switch 29 is again pushed at 7:00 o'clock the next evening, again simultaneous with a referenced signal from a T.V., radio or the like to guarantee that the period is exactly 24 hours. At this point, AND circuit 20 is opened, the information counted by counter 14 is gated into the memory circuit as a regulation quantity and the counting circuit is then reset. Thus, AND circuit 20 is designed to be open and produce a 1 or high level signal during a predetermined period after reset of the counters, such as 24 hours plus and minus ten minutes. It is noted that although the embodiment illustrated in FIG. 1 is directed to a 24 hour time period, any referenced time period such as a week or hour can be utilized. Accordingly, AND gate circuit 20 functions as a prohibiting gate to determine the period during which operation of switch 29 will effect resetting of the of memory circuit 18. The period during which AND circuit 20 produces a 1 output is determined by considering the variations in the frequency of the quartz crystal vibrator 1, in effect, the maximum range of errors in time standard signal 31. Accordingly, the adjustment quantity is stored in memory 18 and in the manner noted above, advancement and/or retardation of the signal is effected to apply a predetermined low frequency time standard signal of 1 second at terminal 30 to the display circuit illustrated in FIG. 5.

The display circuit illustrated in FIG. 5 is comprised of decimal divider 72 and hexadic divider 73 utilized as counting circuits, the signals counted thereby being displayed by conventional 7-bar display elements 84 and 85 by applying same through decoder circuits 78 and 79. Similarly, the minutes display includes display elements 86 and 87 energized by signals from decoder circuits 80 and 81 in response to decimal divider 74 and hexadic divider 75. Finally, display elements 88 and 89 effect the hours display in response to a time keeping signal from decimal divider 76 and binary divider 77 applied through decoders 82 and 83. Accordingly, if the accuracy of the time standard signal 30 is precise, the one second signal applied to the display portion will effect an accurate display of time.

It is noted, that the number of divider stages utilized in counter 14 determines the accuracy to which the adjustment quantity can be determined. Because the output of the counting circuit 14 in combination with distribution circuit 16 effects a calculation of the adjustment quantity, the shorter the period, or conversely the higher the frequency of the output signal from counting circuit 13, the greater the accuracy that can be obtained in the adjustment quantity. For example, if the signal produced by counting circuit 13 has a period of 0.25 seconds, the output frequency of the quartz crystal oscillator circuit is 65,536 Hz, and counting circuit 14 is formed of six series connected binary stages, maximum error per day is on the order of 0.25 sec. .times. 26 = 16 seconds per day. If the amount of adjustment required is greater than 16 seconds a day, the number of stages in the counting circuit 14 must be further increased.

By counting the pulses of the counter 13 for 24 hours, 345,600 pulses are counted (86,400 secs..times.4). Thus, when the quartz crystal vibrator has a rate of zero error, the counted values of the counting circuits 14 and 15 are the value represented in the table illustrated in FIG. 2. Taking the highest nine digits of the counter 15 as the value at which the output of AND circuit 20 is 1, the time for having information gated is four minutes. Nevertheless, since the state of several of the counters is zero during this period, the outputs of those counters are changed to 1 by inverters (not shown) to activate AND circuit 20.

When the frequency of the quartz crystal vibrator is slow or beneath the natural frequency, the period of the high frequency time standard signal 31 is retarded and the binary state of the divider stages at counting circuit 14 are not all equal to zero, as is illustrated in the case depicted in FIG. 2. The increased number of pulses per second of the output of the divider circuit 3 when the above-mentioned counting value is retarded by n, is obtained in accordance with the following formula: ##EQU1## where, f.sub.0 is the frequency of the binary divider 3, and X is the increased number of pulses per second required. Thus, if it is necessary to increase the number of pulses by 1, the period is shortened by an amount equal to 1/f.sub.o .times.1/2.times. X. Thus, even if f.sub.0 is on the order of 33 KHz, a larger error can be prevented and X =n/5. Thus, distribution circuit 16 includes a decoder to produce a binary output of n/5 in response to the input signal from a binary divider circuit of -n. Nevertheless, if the frequency of the signal to be corrected is too low then an adjustment on the order of minutes cannot be effected.

Reference is made to FIG. 4 wherein counting circuit 14, distributing circuit 16, gate 17 and memory circuit 18 are specifically illustrated and wherein the frequency of the signal to be corrected is 327,680 KHz, a frequency 10 times higher than the frequency discussed above and wherein a correcting method for the division ratio of the divider is the same as discussed below. In such a case, the adjustment quantity X is obtained by the following formula: ##EQU2## Accordingly, a binary output of 0.95n is produced with respect to a binary input signal -n. In FIG. 4, counting circuit 14 is illustrated as divider stages 37 to 42 each stage being respectively coupled to AND gates 49 through 56 and are further coupled through inverter circuits 48 to AND gates 49 through 56. In practice, 64 AND gates are required, but for purposes of illustration most have been omitted in order to simplify the drawing. OR gates 57 through 62 are adapted to receive signals from the respective AND gates 49 through 56 and apply same through inverters 64 to AND gates 63 and AND circuit 65, in coincidence with the signal from AND gate 21, to thereby gate information into the memory 18, which includes memory circuits 66 through 71. It is noted that the electronic timepiece circuit is designed so that the quartz crystal oscillator circuit 2 and the divider circuit 3 are continually in use and the count thereof is not halted during time setting period.

Reference is now made to FIG. 6 wherein an alternate embodiment of the instant invention is illustrated and wherein the manner in which the division ratio is adjusted is the same as the embodiment illustrated in FIG. 1, like reference numerals being utilized to denote like elements. A divider circuit 90 has a variable division ratio to thereby produce a low frequency time standard signal 30 of a predetermined value. The division ratio is determined by utilizing the data stored in memory 91. Accordingly, the same counter circuits and in particular counter 14 are utilized to apply the adjustment quantity through gate 92 to a divider circuit 93. Thus, if the adjustment quantity supplied by switch 29 is a multiple of 24 hours (24.times.M, where M is a positive integer), the deviation for twenty-four hours can be calculated by dividing the deviation by M. Accordingly, the deviation per hour, week etc., can be ascertained and corrected.

A multiplication circuit 94 is utilized instead of the distribution circuit illustrated in FIG. 1. The multiplication circuit information is gated through gate 95 and is thereby read into the memory circuit 91. Accordingly, when the division ratio is adjusted by applying a 1 thereto the timepiece is adjusted in accordance with the length of the period of the input signal of the divider circuit 90.

From the foregoing, it is clear the instant invention is directed to an electronic timepiece that is automatically adjusted by reliance on a accurate source for a time reference signal. Thus the instant invention is particularly advantageous when used in high precision timepieces such as quartz crystal wrist watches. Moreover, variations in the manufacture of the quartz crystals, and the ability to minimize the effect of same is achieved by the instant invention.

It will thus be seen that the objects set forth above, and those made apparent from the preceeding description, are efficiently attained and, since certain changes may be made in the above construction without departing from the spirit and scope of the invention, it is intended that all matter contained in the above description or shown in the accompanying drawings shall be interpreted as illustrative and not in a limiting sense.

It is also to be understood that the following claims are intended to cover all of the generic and specific features of the invention herein described, and all statements of the scope of the invention which, as a matter of language, might be said to fall therebetween.

Claims

What is claimed is:

1. In an electronic timepiece having oscillator means for producing high frequency time standard signals; divider means having an adjustable division ratio for producing a low frequency time standard signal in response to a high frequency time standard signal applied thereto, and adjustment means coupled to said divider means for adjusting the division ratio of said divider circuit to produce a low frequency time standard signal of a predetermined frequency, the improvement comprising input means for producing input data signals representative of a predetermined period of time, calculator means for producing signals representative of the amount of adjustment of said division ratio in response to the application of said input data signal, memory means adapted to store said division ratio signals, said memory being adapted in response to said predetermined low frequency signal to apply said division ratio adjustment signals to said adjustment means during each period of said predetermined low frequency signal.

2. An electronic timepiece as claimed in claim 1 wherein said calculator means includes counters for counting the high frequency time standard signal for a predetermined period determined by said input data signals.

3. An electronic timepiece as claimed in claim 2 wherein operating means are adapted to receive signals from said counting means, and at a time determined by said signals from said input means, operate on said signals from said counting means, and produce signal representative of the amount of division ratio adjustment effected for each period of said low frequency predetermined signal.

4. An electronic timepiece as claimed in claim 2, wherein the predetermined period of time is representative of a multiple of the time for which adjustment of the division ratio can be effected in said divider means, and including a divider means for receiving signals from said counting means and at a time determined by input signals from said input means, divides said signals from said counter by an amount equal to said multiple, for application to said memory.

5. An electronic timepiece as claimed in claim 3, wherein said input means include prohibition means coupled to said counters, said prohibition means being adapted to prevent a change in the contents stored in said memory at a time other than a predetermined range counted by said counting means.

6. An electronic timepiece as claimed in claim 5, wherein said input means includes manually operated switching means for producing said input signals, said switching means being adapted to effect a change in the contents stored in said memory during said predetermined range of said counting means.

7. An electronic timepiece as claimed in claim 6, wherein said predetermined period of time represented by said input data signals is 24 hours.

8. An electronic timepiece as claimed in claim 6, wherein said predetermined low frequency time standard signal has a period of 1 second.

9. An electronic timepiece as claimed in claim 6, wherein said counters in said calculator means are three series connected counters, said first counter producing a signal for determining the accuracy with which said adjustment is to be effected in response to said high frequency time standard signal, said second counter in response to said signal from said first counter producing signals to be applied to said operator means, said third counter in response to said signal from said second counter applying signals to said prohibition means representative of the predetermined range.

10. An electronic timepiece as claimed in claim 9, wherein actuation of said manually operated switching means effects a resetting to zero of said first, second and third counters.

11. An electronic timepiece as claimed in claim 3, wherein said adjustment means are adapted to advance the count of said divider means.

12. An electronic timepiece as claimed in claim 3, wherein said adjustment means are adapted to retard the count of the divider means.

13. An electronic timepiece as claimed in claim 11, wherein said adjustment means are also adapted to retard the count of the divider means.