Scrolling circuit for a visual display apparatus

Abstract

A circuit for row addressing a storage memory supplying coded information to a visual display. The storage capacity of the memory is greater than the instantaneous display capacity. A row address counter provides the address of the first row displayed from the memory, the address of which is loaded into a second address counter which addresses the memory. Means are provided for rolling over the address counters and for tracking a cursor row address counter with the memory address counter.

Description

BACKGROUND OF THE INVENTION

This invention generally relates to a scrolling circuit for a visual display apparatus including a character storage memory having a storage capacity exceeding the available visual display area, and more particularly relates to a scrolling circuit for such an apparatus which facilitates the selection of a segment or portion of the memory being displayed.

Various character display devices have been described which include a character storage memory wherein the characters to be displayed are stored in encoded form. The memory is capable of storing a plurality of rows of characters, the total number of which is larger than the number of rows which can be simultaneously presented upon the visual display area, usually a cathode ray tube screen. Counters are utilized to address the memory and serve to select the characters read out from the memory. The counters address the memory with respect to a particular character row and with respect to individual characters within the selected row. The encoded information is read out from the memory, decoded, and utilized to unblank the beam of the cathode ray tube as it is scanned across the screen thus writing the desired character. Necessarily, the cathode ray tube screen has a limited capacity which is frequently less than the storage capacity of the memory. Since the memory is capable of storing more rows of information than can be displayed at one time, it is necessary to include provisions for selecting which segment or portion of the memory is presented by the display at a particular moment.

For purposes of description, the display area may be considered a window with the memory text presented on a rolled scroll a portion of which is viewed through the window. To disclose the row just below the last row viewed through the window, the scroll is moved upwardly, which movement is defined as a "scroll up" operation. Conversely, to display the row contiguous and just above the first row viewed through the window, the scroll is moved downwardly which movement is termed a "scroll down" operation. A particular drawback with prior arrangements is that to view the last row of the memory when the display is presenting the first row thereof, a scroll down movement is inoperative and the operator is required to scroll upwardly through the entire memory to arrive at the last row of the stored text. It has been found convenient to permit the operator to view the last row of the memory contiguous with the first row thereof. With reference to the prior analogy, such a movement is comparable to displaying the memory text on a continuous scroll so that the scroll can be moved in a single direction to permit display of any selected portion of the memory text. Such an operation is hereinafter termed "roll over" scrolling.

To facilitate presentation, the memory may be broken up into pages or segments, each of which contain a sufficient number of text rows to fill the display screen. As an operating convenience, it is desirable for the operator to be able to recall, at will, selected segments or portions of the memory, as one would select certain pages of a book, without the necessity of scrolling through the entire memory line by line to display the desired memory segment.

For purposes of isolating an existing character on the display at a particular location or for indicating the screen location of the next character to be written, prior display devices generally include an indicating cursor. In this connection, the operator is provided manually operable keys for selectively row positioning the cursor, such keys being frequently designated "cursor up" and "cursor down". Depression of the appropriate key moves the row location of the cursor with respect to the memory while maintaining the displayed portion of the memory fixed. With respect to such an arrangement, the operator must exercise caution since it is possible to move the cursor entirely off the display screen while still maintaining its desired position with respect to the memory. The cursor is then lost from view creating a certain degree of operator confusion. Under such circumstances, the operator might assume that the cursor command has not functioned or initiate the desired entry at a wrong memory location. The illustrated embodiment overcomes such difficulties by scrolling the display in response to a cursor command in the direction necessary to maintain the cursor within view of the operator, a condition hereinafter referred to as scroll "tracking".

SUMMARY OF THE INVENTION

The illustrated embodiment is particularly suited for row addressing a storage memory which provides encoded information to a visual display. A counter provides the address of the first memory row to be displayed which is loaded into a second sequentially advanced address counter. The second counter addresses the memory and is stepped to read out successive memory rows.

The apparatus additionally includes a read only memory which is programmed to vary the address of the first memory row maintained by the first memory row counter. Each counter is capable of rolling-over the count and, in this regard, includes means responsive to a selected command and to a selected address of the counter for presetting the counter to a predetermined address. A cursor row address counter provides the row address of a cursor indicator. A comparator compares the address of the cursor row counter with the address of the first memory row or the last memory row and in response to such a comparison and a predetermined cursor movement, the segment of the memory being displayed is altered to maintain the cursor upon the display.

It is a main object of this invention to provide a display apparatus including means for selectively scrolling the text display and for tracking the display with the movement of a cursor indicator.

Other objects, advantages, and features of the invention will be more readily appreciated after reference to the following description and accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1, which consists of combined FIGS. 1A and 1B, provides a schematic diagram of a portion of a display apparatus illustrating certain features of this invention.

FIGS. 2 through 7 are logic flow diagrams illustrating certain of the operational features of the apparatus illustrated in FIG. 1.

DESCRIPTION OF THE ILLUSTRATED EMBODIMENT

General

The illustrated circuit is particularly concerned with the row address of a storage memory and means for tracking the row address with the row position of a cursor. With particular reference to FIG. 1B, the apparatus includes a display memory 10 which serves to store the encoded text. The memory is addressed with respect to a selected character row to be displayed as well as with respect to a particular character with the row. Address means for positioning the cursor along a selected row is provided by additional circuitry not shown and which does not form a part of this invention. The output from the memory 10 is utilized to control a video display unit 12.

Further details of a preferred form of CRT display system, and operating circuits for generating the display characters and the cursor are disclosed in commonly assigned copending applications of Harold D. Cook. Ser. No. 388,296 filed Aug. 14, 1973, and of Theodore J. Mau, Jr. and John L. Peterson, Ser. No. 388,286, filed Aug. 14, 1973.

The capacity of the display memory 10 is in excess of that which the video display 12 can accommodate at a given moment. For purposes of discussion, it will be assumed that the memory 10 is capable of storing seventy-two rows of text whereas the screen capacity of the video display 12 is limited to one-third this amount or twenty-four lines of displayed text. Thus, the memory 10 can be descriptively divided into three segments or portions, each of which contains twenty-four rows of text; the first memory segment starting at row one, the second at row twenty-five, and the last segment starting at row forty-nine. It will be appreciated that the storage to display capacity relationship described is provided by way of example and the other ratios may be utilized without departing from the scope and spirit of this invention.

The apparatus includes a command circuit 14 (FIG. 1A) which is responsive to operator initiated commands or signals supplied from an incoming cable 16. These incoming command signals are utilized to address a ready only memory (ROM) 18 which supplies instruction as well as check signals for control of the apparatus. The selection of the appropriate instruction and check signals and their order of read out from the ROM 18 is determined by a command timing unit 20. The timing unit 20 responds to the status of a memory row address circuit 22 (FIG. 1B) and in turn determines the sequencing of the ROM 18 as will be subsequently further described. The memory row address circuit 22 serves to select the row address of the memory 10 and briefly includes a scroll address counter 24 which supplies the address of the first row of the display as determined by instruction signals from the command circuit. The multilevel output of the scroll address counter 24 is loaded into a memory address row counter 26 via cable 28. The row counter 26 addresses the display memory 10 and is stepped one row upon the read out of each character row until an entire twenty-four rows of the memory have been displayed. Upon read out of an entire video raster comprised of twenty-four memory rows, the row counter 26 is loaded with the output of the scroll address counter 24 and again stepped through twenty-four successive rows.

The address of the last row of the video display 12 is determined by an end of display (EOD) address generator 30. The EOD address is fed to a cursor row address circuit 32. Either the address of the first row of the display or the address of the last row of the display is compared with the address of a cursor address row counter 34 by a comparator 36. When coincidence is obtained, the scroll address counter 24 is decremented or incremented as necessary to maintain the cursor row address within the displayed memory rows thus maintaining the cursor within the operator's view.

The command circuit 14, in response to an incoming command signal 16, checks the state of the scroll address counter 24 as well as the status of the cursor row counter 34 and in response to such a status check, directs the apparatus to perform the desired instructions. In response to an instructional command, the scroll address counter 24 is either incremented, decremented, or preset to the address of the first row of the memory. Similarly, the address of the cursor address row counter 34 is altered to provide the address of the selected cursor row and, should the selected address be such that the cursor would tend to leave the viewing area of the display, the memory address row counter 26 is appropriately incremented or decremented to maintain the cursor upon the screen.

COMMAND CIRCUIT

The various instruction and check signals for control of the apparatus are provided by the read only memory (ROM) 18. Serving to address the ROM 18 is a ROM address counter 38, the outputs of which are connected to the address inputs of the ROM via parallel lines 39. The ROM address counter 38 is loaded with the output of a two position multiplexer 40 and stepped in response to timing signals from the timing unit through clock 42 and load 44 inputs as will be subsequently described. The ROM counter 38 is addressed by the multiplexer 40 via lines 46. The multiplexer 40 in turn is controlled by a receive command signal fed to the control port 48 from an instruction decoder 50. The multiplexer 40 additionally includes two multilevel inputs. The first input fed via cable 16 is provided either by the operator in response to the depression of an appropriate key on the keyboard, or from signal levels supplied by an incoming modem (not shown). The alternate input to the multiplexer is provided along cable 52 by the enable and command outputs of the ROM 18. As illustrated, the ROM 18 provides two discrete four level outputs 54 and 56 each of which is connected to the input of the multiplexer 40. Thus, in accordance with a receive command at the port 48, the output of the multiplexer is alternately switched between the incoming commands via cable 16 or the output of the ROM via cable 52 for loading the ROM address counter 38 with a selected address as will be further described. The command outputs 54 from the ROM are fed to input ports 58 of the instruction decoder 50. The enable outputs 56 are fed to enable inputs 59 of the instruction decoder 50. After the instruction decoder 50 has processed a set of commands, a receive command signal is generated and fed to port 48 of the multiplexer 40 which switches the multiplexer to the incoming command cable 16 for receipt of the next instruction command.

Additionally, the ROM outputs 54 and 56 address a check decoder 60 including address 62 and enable 64 inputs. The check decoder 60 is selectively enabled by the enable lines from the ROM 18. In response to an enable signal, command information at the output 54 of the ROM 18 is decoded. Additionally, the check decoder 60 includes four additional inputs 66, 68, 70 and 72; three of which, designated TS-1, TS-25, and TS-49, are provided by the scroll address counter 24. The remaining input designated Coinc 72 is connected to the output of the comparator 36. The signal levels at each of the four inputs 66 through 72 are routed in response to command signals to two output ports 74 and 76, respectively designated NO and YES, which send control signals to the timing unit 20. Serving to load (jump) or clock (skip) the ROM address counter 38, the YES and NO output signals from the check decoder 60 are sent to the timing unit 20 as described in the following section.

TIMING UNIT

With reference to FIG. 1A, the timing unit 20 includes a clock 78, driving a frequency divider 80 of modulo ten. The output of the divider 80, is fed to the toggle input of a type "D" "jump" flip-flop 82. Serving to set the jump flip-flop 82, the direct input thereof is connected to the YES output 76 of the check decoder 60. In response to a YES signal, the flip-flop 82 will set and toggle in response to the negative going edge of the output of the divide by ten counter 80. The output of the flip-flop is fed to one input of a jump AND-gate 84, the output of which is connected to the load input 44 of the ROM address counter 38. In response to the occurrence of a load and a clock signal, the ROM counter 38 will load with the multiplexer 40 address whereas a clock signal alone causes the counter 38 to increment. Serving to gate the output of the jump flip-flop 82, the alternate input of the AND-gate 84 is connected to the nine count output of the divider 80 via line 86. The output of the AND-gate 84 goes high providing a load signal to the counter 38 when the divider 80 generates the count nine pulse. This count nine pulse is also coupled to the clock input of the counter through a clock OR-gate 88 and the simultaneous occurrence of the load and clock signals cause the counter 38 to load with the output address of the multiplexer 40.

The NO output 74 of the check decoder 60 is connected to the set input of an RS type "skip" flip-flop 90, the reset input of which is connected to the zero count output of the divide by ten divider 80 via line 92. The output of the skip flip-flop 90 is connected to one input of a skip AND-gate 94, the alternate input of which is fed by the count seven output of the divider 80 via line 96. The output of the skip AND-gate is connected to one input of the OR-gate 88, the remaining input, as previously mentioned, being connected to the count nine output of the divider. Thus, in response to a NO signal from the check decoder 60, the counter 38 is twice incremented for each cycle of the divide by 10 divider. During normal clocking conditions, the counter is incremented once for each divider cycle by the count 9 output pulse from the divider. For purposes of discussion, it is assumed that the check decoder 60 has not received an enable signal and therefore the YES and NO outputs are low. In this condition, the nine count output of the divider 80 is coupled via line 86 through the OR-gate 88 causing the ROM address counter 38 to step for each complete cycle of the divider 80. A NO signal from the check decoder 60 is fed to the set input of the skip flip-flop 90 causing it to set and remain set until the reset by the zero output of the divider via line 92. This set condition of the flip-flop 90 permits two clock pulses to be sent to port 42 incrementing the ROM counter 38. Thus, for each cycle of the divider 80, the presence of a NO signal from the check decoder 60 increments the counter 38 an additional step as compared with the single increment generated under normal clocking conditions.

In response to a YES output at port 76, the jump flip-flop 82 is caused to set and remains set until toggled by a negative going pulse at its clock input provided by the output of the divider 80. The output of the flip-flop 82 pulls the input of the AND-gate 87 high, allowing the count nine pulse feed via line 86 from the divider 80 to pass therethrough causing the ROM address counter 38 to load with the output of the ROM through the multiplexer 40. The command sequence which the ROM provides in response to the various clocking and loading signals from the timing unit 20 will be considered in greater detail after discussion of the remaining circuitry.

MEMORY ROW ADDRESS

As previously mentioned, for illustrative purposes, the display memory 10 is assumed to carry seventy-two lines of character text, whereas the video display 12 is capable of simultaneously displaying only twenty-four lines. Serving to address the memory 10 with respect to the particular character row to be read out therefrom, is the memory address row counter 26 the multilevel output of which is connected via a cable 98 to the row address input of the memory 10. The memory address row counter 26 is stepped after the writing of each character row by the horizontal retrace signal via a line 100 from the video display 12 which serves as a character row completion and is applied to the clock input of the address counter 26. Thus, as each character row is written on the display 12, the counter 26 is stepped once, and the memory address row counter 26 addresses the successive memory row. After twenty-four rows have been written upon the screen of the display, a vertical retrace signal is generated which is applied to a load input 102 via line 104 of the memory address row counter 26, causing it to load with the address from the scroll address counter 24. Thus, the scroll address counter 24 provides the address of the first row to be read from the memory 10. The memory address row counter 26 progressively advances row by row until the last row is written upon the display 12 at which point a vertical retrace signal is generated. In response to the vertical retrace signal, the memory address row counter 26 again loads with the scroll address counter 24 output, which corresponds to the address of the first row to be read from the memory 10.

Serving to reset the scroll address counter 24 to the first row of the memory 10 is a reset signal via a line 106 from the instruction decoder 50. The reset signal is fed through one input of a reset OR-gate 108 to a reset input 110 of the scroll address counter 24. In response to the reset signal, the counter address is that of the first row of the memory that is row one 1. Additionally, in response to an appropriate command signal, the instruction decoder 50 provides a scroll up signal (SCUP) via line 112 which is fed to an "up" input 114 of the scroll address counter 24 causing the address thereof to decrement once from its previous count. Serving to cause the counter 24 to increment, the instruction decoder 50, in response to a command signal, generates a scroll down signal (SCDN) which is fed via line 116 to the "down" input 118 of the scroll address counter 24. Thus, in response to instruction signals from the instruction decoder 50, the scroll address counter 24 is either reset, incremented or decremented as desired.

For purposes of discussion, it will be assumed that the scroll address counter 24 has been successively incremented until the address in the counter is that of memory row seventy-two which is the last character row of the memory. Serving to decode the seventy-second row address output from the counter 24 is a "72" decoder 120, the output of which is fed to one input of a reset AND-gate 122, the remaining input being enabled by the "SCUP" signal via line 112 from the instruction decoder 50. Upon coincidence between the SCUP signal, and a row 72 address, a signal passes from the AND-gate 122 to the remaining input of the reset OR-gate 108 and to the reset input 110 of the counter. Thus, when a scroll-up signal is provided by the instruction decoder 50, the counter 24 will decrement until the output of the counter 24 is the address of row 72. At this time, the scroll address counter 24 is reset to zero. This operation provides a roll-over feature allowing the operator to view the entire memory contents by scrolling in a single direction (UP in this case).

Similarly, scroll down rollover is obtained when the operator depresses the scroll down key so that the instruction decoder 50 provides consecutive scroll-down "SCDN" instructions beyond the point where the output of the scroll address counter contains the address of the first text line of the memory. Serving to decode the first row address is a row "1" decoder 124 the output of which is fed to one input of a row 1 AND-gate 126. The remaining input of the AND-gate 126 is connected to the SCDN output of the instruction decoder 50 via line 116. Upon coincidence between the SCDN signal and a row 1 address, a signal passes from the AND-gate 126 to a preset 72 input 128 of the counter 24. Thus, when a scroll-down signal is provided by the instruction decoder 50, the counter 24 will increment until the output of the counter 24 is the address of row 1. At this time, the scroll address counter 24 is reset to the address of row 72 thus providing a downward scroll roll-over feature. As described, the operator may continue to scroll the display continuously in either direction. As previously mentioned, the scroll address counter 24 provides three test signal outputs designated test scroll row one TS-1, test scroll row twenty-five TS-"25" and test scroll row forty-nine TS-"49", to the ports 66, 68, and 70 respectively. One of these test signals is generated when the scroll address counter contains the address of the first row of one of the three segments.

The output of the scroll address counter 24 is loaded into the memory address row counter in response to a vertical retrace signal from the video display 12. After each vertical retrace signal, the memory address row counter 26 is incremented by the horizontal retrace signal until twenty-four memory rows have been displayed. It will be appreciated that when the memory counter has been loaded with the address of a row in the third or last segment of the memory i.e. rows 49 through 72 inclusive, the counter 26 will provide the address of row 72 to the memory 10 before the generation of a horizontal retrace signal. Serving to roll-over the address counter 26 is a row "72" decoder which is connected to the counter 26 by the cable 98. The output of the row 72 decoder is coupled to one input of a row 72 AND-gate 132 the remaining input of which is connected to the horizontal retrace signal from the video display 10. The output of the AND-gate 132 feeds a reset input 124 of the memory counter 26 so that, in response to a coincidence between a row 72 decoding and a horizontal retrace pulse, the memory counter 26 presets to the address of row one of the memory 10 and continues to increment in response to subsequent horizontal retrace signals until a full twenty-four rows of the memory have been addressed. In this manner, the memory address rolls-over allowing the first and the last lines of the memory to be contiguously displayed.

CURSOR ROW ADDRESS

It will be appreciated that the output of the scroll address counter 24 provides the address of the first row read from the memory. Serving to provide the address of the last text row to be read from the memory is the End of Display (EOD) address generator 30. The EOD address generator 30 includes a magnitude 49 comparator 136, the input of which is connected to the output of the scroll counter via cable 28, providing the start of display (SOD) address. When the SOD address exceeds the line forty-nine (49) address, the magnitude comparator 136 supplies a signal to a binary adder 138. In response to an input signal from the comparator corresponding to an SOD address exceeding forty-nine, the adder 138 adds the address of the scroll address at input port 140 with an address sevety-two rows thereafter. In effect this is the equivalent of subtracting forth-nine rows preceding the SOD address. In the absence of a signal from the magnitude comparator indicating an SOD address in the first two segments of the memory, the binary adder 138 provides an output row address which is twenty-three rows after the SOD address.

The EOD address from the binary adder 138 is coupled via cable 142 to one input of a cursor multiplexer 144. A second input of the multiplexer receives the SOD address from the scroll counter 24. The multiplexer includes two control inputs; one designated EOD which is connected via line 146 to the EOD signal output of the instruction decoder 50 and the second input designated SOD which is connected to the SOD output of the instruction decoder 50 via line 148. In response to an SOD signal from the instruction decoder 50, the address of the scroll counter is routed to the output of the multiplexer 144 which in turn is fed via cable 150 to one input of the comparator 36 forming part of the cursor row address circuit 32. In response to an EOD signal via line 146 from the instruction decoder 50, the EOD output of the binary adder passes through the multiplexer 144 to the comparator 36. The comparator compares, upon command, the address of the first (SOD) and last (EOD) row address with the output of the cursor row address counter 34 and upon coincidence an output signal is fed to the coinc input 72 of the check decoder 60. The output of the cursor address row counter 34 is fed to a cursor generator 153 and serves to provide the address of the row position of the cursor. A suitable cursor generator is described in U.S. Pat. No. 3,609,749 entitled "Character Display System Having Negative Image Cursor" issued to W. B. McClelland on Sept. 28, 1971 and having a common assignee with this application.

In response to an incoming cursor up command via cable 16 initiated by the operator to raise the cursor on the screen, a line decrement signal (LDEC) is fed from the instruction decoder 50 via line 158 to a one input of the cursor address row counter 34 and also to an input of a preset 72 AND-gate 154. The LDEC signal causes the cursor row address row counter to count down which corresponds to an up movement of the cursor upon the display screen. As the cursor is decremented row by row, the cursor address counter 34 will eventually contain the address of the first row of the memory 10. Serving to decode this address, is a row 1 decoder 156, the output of which is fed to the remaining input of the AND-gate 154. When an LDEC signal from the instruction decoder 50 and the first row address from the counter 34 coincide, the AND-gate provides a preset 72 signal to the counter 34. This preset operation, in response to a line decrement signal LDEC when the counter address is at row one, results in a roll-over of the cursor counter in a manner similar to that discussed in connection with the operation of the scroll address counter 24. Similarly, in response to a selected command, the instruction decoder 50 provides a line incremented (LINC) signal via line 152 to an up input of the counter 34 for downwardly incrementing the cursor. After a series of LINC signals have been fed to the cursor counter 34, the counter eventually contains the address of row seventy-two of the memory. This address is decoded by a row seventy-two decoder 160, the output of which is fed into one input of a row seventy-two AND-gate 162. The alternate input of the AND-gate is connected to the LINC line 152 from the instruction decoder 50. In response to the coincidence of a LINC signal and the decoding of row seventy-two, the AND-gate 162 provides an output pulse to a reset OR-gate 164 which passes to a reset input of the cursor address row counter 34. Thus, in response to a coincidence of a row seventy-two address and a LINC command, the cursor row counter will reset to the address of the first memory row. Serving to directly reset the cursor row counter, the alternate input of the reset OR-gate 164 is connected to the reset output of the instruction decoder 50 via line 106.

OPERATION

With respect to FIGS. 3 through 7, several flow charts of selective ROM 18 command sequences are provided which serve to illustrate the operation of the apparatus of FIG. 1. A receive command is provided by the instruction decoder, upon completion of a prior program sequence, which is fed to port 48 of the multiplexer 40, routes the next incoming command signal through the multiplexer for address of the ROM 18. FIG. 2 is a signal flow chart illustrating operation of the apparatus in response to an incoming cursor and scroll home command. The command is initated for resetting the display 12 to the first line of the memory 10 and the cursor to the first display row. The "home" command signal passes through the multiplexer and is loaded into the counter for addressing the ROM. The ROM sends an enable command to the instruction decoder which generates a reset signal via line 106 for reset of the scroll counter 24 and the cursor counter 34. Reset of the scroll address counter 24 places the first memory segment upon the display and reset of the cursor address row counter 34 places the cursor on the first row of the display. After reset, the sequence stops and the ROM is ready to receive the next command.

As illustrated in FIG. 3, in response to an incoming scroll down command, the instruction decoder generates an SCDN signal via line 116 and the scroll counter 24 decrements shifting the display down one character row. The ROM is clocked to the next address and an LDEC signal is fed via line 158 from the instruction decoder to the cursor counter 34 decrementing the counter downward so as to maintain the cursor's relative position with respect to the display. If the address of the scroll counter is that of row one, the SCDN signal will cause the scroll counter to roll over in the opposite direction as previously described. As mentioned, the cursor counter 34 is decremented in response to a scroll down command. This feature maintains the cursor upon the screen as the memory is scrolled thus assuring that the cursor will not be removed from the operator's view.

With respect to FIG. 4, in response to a scroll up command, the instruction decoder generates a SCUP signal via line 112 which upwardly scrolls the counter. Subsequently, a LINC signal is generated via the line 152 incrementing the cursor row address counter 34.

FIG. 5 illustrates a flow diagram initiated in response to a segment advance command. The instruction decoder 50 provides a SCUP signal to the scroll counter 24, and the counter scrolls up one line. The ROM counter 38 is stepped and the decoder 50 sends a LINC signal to the input of the cursor counter 24 which increments. In response to the next clock pulse, the ROM commands the check decoder 60 to test its TS 1 input to determine if the scroll counter 24 contains the address of the first row of the first segment of the memory 10. For purposes of discussion, it will be assumed that the scroll row address counter does not contain the address of the first row of the first segment which is row one. Thus a NO signal is fed from the output 74 of the check decoder to the timing unit 20, causing the memory to provide two steps pulses skipping the ROM address counter 38 two positions. The check decoder in response to the new ROM output, checks the counter for the address of the twenty-fifth row which is the first row of the second memory segment. It will be assumed that the scroll address counter 24 does not contain the address of row twenty-five. The ROM address counter 38 skips two positions and again the check decoder 60 checks for the address of row forty-nine. In the absence of an affirmative check, the ROM sends a recirculate command to the check decoder 60 which forces a YES output to the jump flip-flop 82 which returns the ROM sequence to the start position. After the scroll counter 24 has been incremented and the cursor counter 34 incremented one row, the check decoder 60 again checks the scroll counter 24 for the presence of either the first, twenty-fifth, or forty-ninth row addresses. In response to the presence of the address of one of these rows, the check selector provides an output signal at the "YES" output 76, and the timing unit jumps the ROM to a stop position. The scroll address 24 then carries the first row of one of the three memory segments.

With reference to FIG. 6, the ROM, in response to a cursor down command, addresses the instruction decoder 50 which sends an EOD signal to the control input of the multiplexer 144. The EOD signal from the EOD decoder 30 is routed through the cursor multiplexer 144 to the comparator 36 whereas it is compared with the address of the cursor row address counter 34. In the event a coincidence condition is detected, a coincidence signal (COINC) is fed to the COINC input 72 of the check decoder which is routed to the YES output 76 thereof. In response to the YES signal, the timing unit 20 skips the ROM address counter 38 and the ROM in turn instructs the decoder 50 supply a SCUP signal. Responsive to the next clock timing pulse the ROM 18 directs the decoder 50 to generate an LINC signal. The incrementation of the scroll address counter 24 when the cursor is in the last line of the display, assures that the cursor will not be moved off the display screen, but rather, the display is moved up one row before the cursor is incremented. For purposes of discussion it is assumed that a coincidence did not occur between the EOD signal and the cursor address. The check decoder 60, in this instance, provides a NO signal to the timing unit. In response to this signal, the ROM 18 is "skipped" and the instruction decoder 50 sends a LINC signal to the cursor row counter 34.

With reference to the logic diagram of FIG. 7, in response to a cursor up command the instruction decoder 50 sends an SOD signal to the cursor multiplexer 144. The output of the scroll address counter 24 is fed to the comparator for comparison with the cursor address row counter 34. In response to a coincidence, the check decoder sends a YES signal to the timing unit. The ROM is "jumped" and the decoder 50 sends an LDEC signal to the cursor counter 34. Thereafter, the ROM 18 is stepped and the decoder 50 sends an LDEC signal to the cursor counter 34. In the event a coincidence does not occur when the cursor address and SOD addresses are compared, which is the case when the cursor is not on the first row of the display, the ROM "jumps" and an LEDC signal is sent from the decoder 50 to the cursor counter 34. Thus, it is assured that in response to a cursor up command, the cursor will not be moved off the screen. Rather, if the cursor is in the first row of the display, the cursor will move up one row and the display will also scroll up one row thus retaining the cursor upon the screen.

Although the invention has been particulary shown and described with reference to a preferred embodiment thereof, it will be understood that various changes in form and detail may be made without departing from the spirit and scope of the invention.

Claims

What is claimed is:

1. A method for row addressing a storage memory providing encoded information to a visual display having an instantaneous display capacity less than the memory capacity and tracking a cursor indicator therewith comprising the steps of:

providing the address of the first row of the portion of the memory being displayed;

loading said first row address into a second counter which serves to row address the memory to those memory rows being displayed;

selecting the address of a row counter determining the row address of a cursor;

comparing the address of the cursor row counter with the address of the second memory counter to determine whether the cursor address will place the cursor on the visual display; and

varying the address of said first row of the portion of the memory being displayed to an address which will place the cursor upon the visual display.

2. An apparatus for row addressing a memory providing encoded information to a visual display, the memory having a storage capacity exceeding the instantaneous display capacity of the visual display comprising:

means for providing a plurality of selected command signals;

a cursor address means for determining the row address of a cursor indicator, said cursor address means including means for varying the address thereof;

first address means containing the address of the first row to be displayed from the memory, said first address means including means for varying the address thereof in response to one of said selected command signals;

second address means selectively loaded with the address of said first address means and said second address means successively addressing said memory with respect to those memory rows being displayed;

comparison means operable in response to a cursor row relocation command from said command means for comparing said cursor address with an address related to the address of said first row address means; and

means operable in response to a comparison condition for varying the address of said first address means so as to maintain the row address of said cursor within those memory rows displayed upon the visual display.

3. An apparatus for row addressing a memory, the memory providing encoded information to a visual display, the memory having a storage capacity exceeding the instantaneouss display capacity of the visual display and being divisible into at least two non-overlapping portions comprising:

means for providing a plurality of selected command signals;

row address means providing the address of the first row to be visually displayed from said memory, said row address means including means for varying the address thereof in response to a first selected command;

cursor row address means for providing the row address of a cursor indicator on the display, said cursor address means including means for varying the address thereof in response to a second selected command so as to facilitate positioning the cursor over the visual display while displaying a fixed portion of the memory;

means responsive to a third selected command for varying the address of said row address means and said cursor address means in a predetermined relationship;

means for determining the presence of the address of the first row of each of said portions by said row address means, and means for varying the address of said row address means in response to a fourth selected command signal until the address of said row address means is that of the first row of one of said memory portions.

4. The apparatus of claim 3 which further includes means for varying the address of said cursor address means in response to a change in the address of said row address means so as to maintain the cursor upon the visual display.

5. An apparatus for row addressing a storage memory, the memory providing encoded information to a visual display, the memory having a storage capacity exceeding the instantaneous display capacity of the visual display comprising:

first address means providing the address of the first memory row of a selected portion of the memory to be displayed;

second address means selectively loaded with the address of the first memory row to be displayed as provided by said first address means, said second address means serving to row address the memory;

means for sequentially advancing said second address means to address successive rows of the selected portion of the memory;

means for providing a plurality of command signals for directing the operation of said first and second address means;

means for selectively varying the first row address of said first address means in response to a first selected command signal from said commmand signal means thereby selecting an alternate portion of the memory for display; and

means responsive to said first selected command signal and to a preselected address of said first address means for presetting said first address means to a predetermined address.

6. The apparatus of claim 5 which further includes means responsive to a second selected command signal from said command signal means and to a preselected address of said second address means for presetting said second address means to a predetermined address.

7. The apparatus of claim 5 wherein said first address means is preset in response to said first selected command signal and to the address of the last row of the memory by said first address means, to the address of the first row of the memory.

8. The apparatus of claim 5 wherein said first address means is preset in response to said first selected command signal and to the address of the first row of the memory by said first address means to the address of the last row of the memory.

9. The apparatus of claim 6 wherein said second address means is preset in response to said second selected command signal and to a preselected address of said second address means, to the address of the first row of the memory.

10. The apparatus of claim 6 which further includes means determining the row address of a cursor and a comparator which serves to compare the row address of said cursor with a selected address from said second address means and providing a control signal upon the coincidence thereto, said control signal serving to initiate a selected command from said command means.

11. The apparatus of claim 10 which further includes means responsive to a selected command signal from said command signal means and to a preselected address of said cursor row address means for presetting said cursor row address means to a predetermined address.

12. The apparatus of claim 11 wherein said cursor row address is preset in response to said selected command signal from said command signal means and to a preselected address of said cursor row address means to the address of the first row of the memory.

13. The apparatus of claim 12 wherein said cursor row address is preset in response to said selected command signal from said command signal means and to a preselected address of said cursor row address means, to the address of the last row of the memory.

14. The apparatus of claim 10 which further includes means for providing the address of the last memory row upon the visual display, said last row address being compared with said cursor row address by said comparator and in response thereto providing said control signal.

15. The apparatus of claim 10 wherein said comparator serves to compare the address of said first address means with the address of said cursor address means and provides said control signal in response thereto.