U.S. patent number 3,895,807 [Application Number 05/387,194] was granted by the patent office on 1975-07-22 for electronic selection bingo game unit.
Invention is credited to David Warren Friedman.
United States Patent |
3,895,807 |
Friedman |
July 22, 1975 |
Electronic selection bingo game unit
Abstract
The invention relates to a selection intersection selecting unit
for a bingo game. There are 75 unique selection intersections in a
bingo game, and this unit permits any one of the intersections to
be selected with equal probability. The unit consists of an
electronic circuit including a 5 .times. 15 switch matrix. The
circuit further consists of a clock circuit means with a low
frequency and a high frequency output, and a counter circuit driven
by the output. The low frequency output is much greater than 75
c.p.s. The counter circuit drives the switch matrix, and the high
frequency output is applied to the counter only during a low output
of the matrix. The counter has two sets of outputs, one set
containing 5 outputs and the other 15, and each set is connected to
a different axis of the matrix. Thus, after each count, a different
intersection of the matrix is selected and removed. The remaining
intersections will then also be selectable with equal
probability.
Inventors: |
Friedman; David Warren
(Meguro-ku, Tokyo, JA) |
Family
ID: |
11712600 |
Appl.
No.: |
05/387,194 |
Filed: |
August 9, 1973 |
Foreign Application Priority Data
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Jan 23, 1973 [JA] |
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48-9151 |
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Current U.S.
Class: |
463/22; 340/323R;
463/19; 273/237 |
Current CPC
Class: |
A63F
3/0645 (20130101) |
Current International
Class: |
A63F
3/06 (20060101); A63b 071/06 (); A63f 003/06 () |
Field of
Search: |
;273/138A,1E,139,13AB,134A,135A,135B,136A ;340/323 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Pinkham; Richard C.
Assistant Examiner: Kramer; Arnold W.
Attorney, Agent or Firm: Wenderoth, Lind & Ponack
Claims
I claim:
1. An equal probability selection electronic device for a bingo
game allowing a human operator to make, by successive operation,
the selection of any one of 75 (or fewer, if some are not
selectable) unique selection intersections, comprising:
a switch matrix comprised of 75 slide switches arranged in a 5
.times. 15 Cartesian coordinate form, each slide switch being used
to indicate a selection intersection and being individually
controllable by the operation of the human operator to define
whether or not the slide switch is selectable and lamp indicators
operatively positioned to define the intersection selected at the
time of selection;
a selector circuit coupled to said switch matrix and comprised of
counter circuit means for successively addressing the slide
switches;
clock circuit means coupled to said counter circuit means for
driving the counter circuit means and providing a clock pulse
output having one of a relatively high and relatively low
frequency, the relatively high frequency being used only to sweep
past any addresses previously selected;
feedback circuit means connected between the switch matrix and the
clock circuit means for controlling said clock pulse output such
that the clock pulse output is selected to be of low frequency when
a selectable slide switch is being addressed and is otherwise
selected to be of high frequency; and
selection start switch means arranged to provide, by successive
operator use for each desired selection, both a start signal to the
clock circuit means for initiating a selection of a slide switch
and a stop signal for initiating termination of a selection cycle,
the arrangement being such that the clock pulse output may be
stopped only when a selectable slide switch is addressed, which
occurs at equal time segments of the addressing sequence,
regardless of the number of slide switches no longer
selectable.
2. A device as recited in claim 1 wherein said clock circuit means
has clock frequencies which are asynchronous and further comprising
a misselection prevention circuit means operatively coupled and
driven by said clock circuit means with a low frequency to inhibit
a high frequency for a delay time of 1/(the high frequency output),
which eliminates erroneous advancement of the counter circuit means
due to the arbitrary phase relationship of the high frequency with
respect to the low frequency.
3. A device as recited in claim 1, wherein said clock circuit means
comprises a high frequency clock to provide said high frequency
output, and a low frequency clock to provide said low frequency
output, the low frequency in Hertz being numerically much greater
than the number of slide switches, and the high frequency in Hertz
being numerically greater than (2N') . (low frequency output),
where N' is equal to 5 .times. 16 = 80.
4. A device as recited in claim 3 wherein said clock circuit means
has clock frequencies which are asynchronous and further comprising
a misselection prevention circuit means operatively coupled and
driven by the low frequency clock to inhibit the high frequency
clock for a delay time of 1/(the high frequency output), which
eliminates erroneous advancement of the counter circuit means due
to the arbitrary phase relationship of the high frequency
asynchronous clock with respect to the low frequency asynchronous
clock.
5. A device as recited in claim 3 further comprising an acquisition
request memory operatively coupled to said clock circuit means, a
minimum time control circuit means for controlling the minimum
operation time of a selection start switch, and inhibit circuit
means, said inhibit circuit means including a nand gate for
preventing operation of the acquisition request memory until after
a currently selected selection intersection has been removed by
opening the contacts of the slide switch corresponding to the
currently selected selection intersection, one input of said nand
gate being connected through an inverter to the feedback circuit
means and another input thereof being directly connected to the
output of said minimum time control circuit means, the output of
said nand gate being connected to said acquisition request memory,
said inhibit circuit means being enabled by a change in the signal
from said feedback circuit means when the slide switch
corresponding to the selected selection intersection is opened, and
thereby causing deletion of that selection intersection from future
consideration.
6. A device as recited in claim 1 further comprising an acquisition
request memory operatively coupled to said clock circuit means, a
minimum time control circuit means for controlling the minimum
operation time of a selection start switch, and inhibit circuit
means, said inhibit circuit means including a nand gate for
preventing operation of the acquisition request memory until after
a currently selected selection intersection has been removed by
opening the contacts of the slide switch corresponding to the
currently selected selection intersection, one input of said nand
gate being connected through an inverter to the feedback circuit
means and another input thereof being directly connected to the
output of said minimum time control circuit means, the output of
said nand gate being connected to said acquisition request memory,
said inhibit circuit means being enabled by a change in the signal
from said feedback circuit means when the slide switch
corresponding to the selected selection intersection is opened and
thereby causing deletion of that selection intersection from future
consideration.
Description
BACKGROUND OF THE INVENTION
The present invention relates to a bingo game unit making possible
selection from among 75 unique selection intersections with equal
probability by utilizing electronic circuit means.
In units which have been in use heretofore for bingo, adjustment of
the unit itself is difficult because of rocking, etc. when it is
used on board a boat, etc. Furthermore, such units have defects in
that the balls used for selection have different weights, making it
difficult to obtain a set of 75 balls yielding equal probability of
selection.
The object of the present invention is to overcome the
above-mentioned defects and to provide a unit most appropriate for
the bingo game which is compact and requiring no adjustment, and is
to obtain a bingo game unit including an electronic clock circuit
including a minimum time control circuit capable of controlling the
minimum operation time of a selection start switch and two clock
circuits. A high frequency clock circuit and a low frequency clock
circuit are provided, both having frequencies sufficiently higher
than 75 c.p.s.. A counter circuit is driven by said electronic
clock circuit and forms 75 unique selection intersections, while a
switch matrix circuit is driven by said counter circuit and has 75
intersection points equipped with 75 electromechanical switches
arranged in cartesian co-ordinate form corresponding to selection
intersections numbered from 1 through 75. Visual display units
corresponding to said electromechanical switches in a one to one
ratio are provided with a board consisting of the 75 visual display
units arranged in the system of cartesian coordinates equipped with
additional switches mechanically interlocked with said
electromechanical switches, respectively, and having such a
characteristic which allows for removal of (75-M) selection
intersections already selected and memory of removed selection
intersections by means of the position of the abovementioned
electromechanical switches. A feedback circuit is driven by said
switch matrix circuit and provides a feedback control signal to the
aforesaid electronic clock circuit in order to select the output of
the abovesaid low frequency clock circuit as the output of the
abovesaid electronic clock circuit and to allow selection of one of
the selection intersections when the feedback control signal is 1,
and to select the output of the abovesaid high frequency clock
circuit as the output of the abovesaid electronic clock circuit
when the feedback control signal is 0, indicating memory of a
previously removed selection intersection, arranged such that the
probability of selecting any one selection intersection from among
M remaining selection intersections is essentially 1/M. The
selected intersection is indicated by means of the abovesaid visual
display units and after operation of the switch associated with the
selected intersection of the switch matrix circuit the visual
indication is removed and the memory of the removed selection
intersection is displayed on the board of the visual display units
mentioned above, and the system is further arranged such that the
(75-M) selection intersections already removed may not be selected
again.
DESCRIPTION OF THE DRAWINGS
Preferred embodiments of the persent invention will be described
hereunder referring to the attached drawings in which:
FIG. 1 is a perspective view which shows the external appearance of
the main part H of bingo game unit embodying the principles of the
present invention;
FIG. 2 is the main circuit diagram which shows an embodiment of the
main part H;
FIG. 3 is a timing signal diagram of the outputs of each principal
circuit which occur in the case of performing selection using the
main part H;
FIG. 4a is a circuit diagram which shows the connection between the
displaying board and electromechanical switches;
FIG. 4b is a perspective view of the displaying board;
FIG. 5 is an explanatory view which shows the audio unit connected
to the main part H;
FIG. 6 is a main circuit diagram including the audio circuit and
the initializing circuit.
DESCRIPTION OF THE EMBODIMENTS SHOWN HEREIN
FIG. 1 shows the external appearance of the main part H of the unit
which is formed in almost the shape of a rectangular parallelepiped
in which only the front surface 1 is somewhat inclined from the
bottom surface 2 towards the upper surface 3. Located on the front
surface 1 is the selection start switch 4 and a power supply switch
5. Located on the upper surface 3 are the 75 intersection points I1
through I75 arranged in cartesian coordinate form consisting of 5
columns and 15 rows where each of the five columns corresponds to
one of the five characters of the word "BINGO," and each
intersection point contains an electromechanical switch, S1 through
S75, and also a visual indicator unit 6 consisting of 5 lamps LX1
through LX5 forming a coordinate axis 7 and 15 lamps LY1 through
LY15, forming a coordinate axis 8. Thus, the visual indicator unit
6 indicates intersection points with one to one correspondence. The
visual indicator unit 6 may have such a construction where one lamp
is provided at each and every intersection point, or light emitting
diodes (LED) may be used in place of lamps. When light emitting
diodes are used at each and every intersection point I1 through
I75, diodes D1 through D75 may be omitted. (See FIG. 2 and FIG.
6.)
FIG. 4b shows a visual display board 11. Board 11 is arranged in
the system of cartesian coordinates and contains 75 numbered visual
display units DS1 through DS75, and consists of a connector 13
containing 75 actuating terminals and one common terminal in
addition to a power cord 14. Connector 13 is coupled with a mating
connector 12 which is connected to supplementary switches aS1
through aS75 which are mechanically interlocked with
electromechanical switches S1 through S75 (See FIG. 4a).
The mating connector 12 and supplementary switches aS1 through aS75
are contained in the main part H of the unit. Accordingly, when a
selection intersection is selected, one of the electromechanical
switches S1 through S75 is switched "OFF" and the corresponding
supplementary switch is switched "ON," thus lighting the
corresponding visual display unit. It is unnecessary to point out
that the switches S1 through S75 and supplementary switches aS1
through aS75 may be so constructed so as to obtain interlocking
movement so that the visual display units are turned off in the
reverse manner. One lamp is used in the present embodiment for each
of the visual display units DS1 through DS75 respectively.
On the front surface of board 11 the lamps are arranged behind a
coloured glass surface. FIG. 2 shows the principal circuit of the
main part H of the unit which is an embodiment of the present
invention and is capable of selecting from among 75 unique
selection intersections, in which E1 is the electronic clock
circuit whose output is connected to the counter circuit CO2 and
further to the switch matrix circuit M3 and the feedback circuit F4
successively, the feedback circuit F4 being connected back to the
electronic clock circuit E1. The main circuit is activated by an
input control signal 15 from the selection start switch 4 for the
purpose of automatically selecting one of the selection
intersections, and the selection operation is made possible by
means of the feedback control signal 16.
The object of the two clock circuits, A and B is to provide a unit
time signal for the electronic clock circuit E1 to drive the
counter circuit CO2, and the low frequency clock circuit A consists
of an astable multivibrator circuit where the duty cycle and
frequency F.sub.A are determined at fixed values by selection of
time constants t.sub.A1 and t.sub.A2. In this embodiment, F.sub.A
is a square wave at 1000 c.p.s.
The high frequency clock circuit B also consists of an astable
multivibrator similar to clock circuit A where duty cycle and
frequency F.sub.B are determined at fixed values by selection of
time constants t.sub.B1 and t.sub.B2. Since the output Bo of clock
circuit B is inhibited by a misselection prevention circuit ER11
during the time delay t.sub.D =1/F.sub.B, the frequency F.sub.B is
obtained as F.sub.B >2.times.(75+5).times. 1000=160,000 c.p.s.
Furthermore, both frequencies F.sub.A and F.sub.B are sufficiently
larger than 75. In other words, even if any number of selection
intersections or all 75 selection intersections are removed, it is
feasible to obtain a series of nondeleted selection intersections
during a single cycle having such a characteristic that memory is
accomplished by means of electromechanical switches S1 through S75
by setting the relationship between frequencies F.sub.A and F.sub.B
such that 80 cycles of the squarewave output of clock circuit B
fall within P (i.e. the negative pulse width of the squarewave
output of clock circuit A). (See FIG. 3). Connected to clock
circuits A and B is selection circuit 9 which has the purpose of
selecting between Ao or Bo or neither by means of input control
signal 15 and the predetermined feedback control signal 16 and
which consists of nand gates N15, N16 and N17.
When the output of the acquisition request memory circuit ME is 0,
the outputs of nand gates N15 and N17 are inhibited. That is, the
output of nand gate N17 is 1 during this period. While the output
of the acquisition request memory circuit ME is 1 and the output
across resistor R21 is 1, the output Ao of clock circuit A is
selected as the input of nand gate N15. Furthermore, when the
output Ao is 1, the output of nand gate N15 is O, and when the
output Ao is 0, the output of nand gate N15 is 1. During this
period, (when Ao = o), the output of nand gate N16 is inhibited or
1.
During times when the output of the acquisition request memory
circuit ME is 1 and the output of resistor R21 is 0 and after an
inhibit period t.sub.D =1/F.sub.B by means of the misselection
prevention circuit ER11 following the 1 to 0 transition of Ao, the
output Bo of clock circuit B is selected as the output of nand gate
N16. When the output Bo is 1, the output of nand gate N16 is 0, and
when the output Bo is 0, the output of nand gate N16 is 1. During
this period, the output of nand gate N15 is 1. As described above,
nand gate N17 responds only when the output of either nand gate N15
or N16 is 0. Furthermore, it is unnecessary to point out that the
output of nand gate N17 is in phase with the output Ao or Bo of
either clock circuit A or B respectively. It should be noted that
the outputs Ao and Bo have no particular phase relationship at any
time. That is, outputs Ao and Bo are asynchronous.
The misselection prevention circuit ER11 consists of capacitor C3
connected from the output Ao to one input of nand gate N16.
Capacitor C3 is discharged beginning when the output Ao makes a 1
to 0 transition and before the output of nand gate N16 could
potentially make a 1 to 0 transition. In other words, the object of
this circuit is to prohibit selection of output Bo of clock circuit
B as the output of nand gate N17 during the delay time of
approximately t.sub.D =1/F.sub.B.
A pulse forming circuit PS10 is connected to the output of nand
gate N15 through capacitor C2 coupled to the input of inverter 18,
the output of which is connected to the input of the acquisition
circuit AQ7. When the output Ao of clock circuit A makes a 0 to 1
transition, the output of nand gate N15 makes a 1 to 0 transition
which, coupled through capacitor C2, produces a negative pulse at
the input of inverter 18. Thus, the output of inverter 18 provides
a positive pulse to the input of the acquisition circuit AQ7 at the
time immediately following a 0 to 1 transition of Ao.
The acquisition circuit AQ7 consists of nand gate N19, having three
terminals on the input side and one terminal on the output side.
After the selection start switch 4 is operated and released, the
output of inverter 5a of the minimum time control circuit MN5 makes
a 0 to 1 transition. When and if a selection intersection is
selected at the same time or with a slight delay with respect to
the 0 to 1 transition of inverter 5a, the output Ao will make a 0
to 1 transition and the output of the pulse forming circuit PS10
will be a positive pulse and at this time the output of the
acquisition circuit AQ7 makes a 1 to 0 transition which resets the
acquisition request memory circuit ME. In other words, the
operation of this circuit AQ7 is that of a monitor circuit whose
purpose is to suspend the output 13 of the abovementioned selection
circuit 9 (i.e. the output of the electronic clock circuit E1) by
resetting the said acquisition request memory circuit ME and
thereby suspending further operation of the counter circuit CO2
when all the outputs of the inverter 5a, the resistor R21 and the
pulse forming circuit PS10 are 1.
The minimum time control circuit MN5 consists of a monostable
multivibrator circuit comprising nand gate N5b, inverter 5a and
capacitor C1. The said monostable multivibrator circuit is in a
stable condition when the selection start switch 4 is in an ON or 0
condition or ordinary OFF or 1 condition, but a pulse having a
fixed pulse width is generated as the output of said minimum time
control circuit MN5 during the time capacitor c1 is discharging.
This prevents the possible rapid operation of selection start
switch 4 from generating a very short pulse at the output of
inverter 5a such that it is almost predictable that selection of
closely following selection intersections would occur.
In other words, the minimum operation time of selection start
switch 4 can be controlled. Thus, it becomes feasible to always
acquire the aforementioned selection intersection with essentially
equal probability without any effect caused by the operating time
of the selection start switch 4. The inhibit circuit IH6 is
provided for the purpose of preventing a further selection until
the correct switch located at the intersection point in the switch
matrix circuit M3 is operated (i.e. open contacts) corresponding to
the selection intersection to be removed. The circuit consists of
nand gate N6b and inverter 6a.
When the selection start switch 4 is ON or 0 in the process of
selecting, the output of nand gate N5b in the minimum time control
circuit MN5 is 1. Even if an operator who performs selection does
not operate (i.e. open contacts) the switch, corresponding to the
already selected selection intersection, by mistake and desires to
perform selection, the lamps remain lit and the output of inverter
6a is 0 since the output of resistor R21 (i.e. the feedback control
signal 16) is 1, thus inhibiting the output of nand gate N6b (i.e.
the output is held at 1). When the operator operates the switch
corresponding to the already selected selection intersection, the
feedback control signal 16 becomes 0 and the output of inverter 6a
becomes 1. Accordingly, the output of nand gate N6b becomes 0
corresponding to the feedback control signal 16 during a time when
the selection start switch 4 is ON or 0.
The acquisition request memory circuit ME has the purpose of
providing a resettable memory of one bit until the said acquisition
request memory circuit ME is set for the purpose of allowing
operation of clock selection circuit 9, and comprises a set/reset
FLIP-FLOP consisting of nand gates N8a and N8b. It is set such that
the output of nand gate N8a becomes a 1 when the output of nand
gate N6b is momentarily 0 and is reset so as to obtain a 0 output
from nand gate N8a when the output of the acquisition circuit AQ7
is momentarily 0.
FIG. 2 shows the details of the counter circuit CO2. The counter
circuit CO2 is driven by the electronic clock circuit E1, and
consists of counter circuits X and Y constructed by using binary
counter stages and decoders DX and DY, and is operated by the
output 13 of the aforesaid electronic clock circuit E1. In FIG. 2,
the counter circuit X consists of a three stage sequential type
binary counter stages B1, B2 and B3, and the outputs of stages B1
and B3 are connected to the inputs of nand gate N20, the output of
which is feedback to reset terminals BR1, BR2 and BR3 of binary
counter stages B1, B2 and B3 respectively. Thus a scale-of-5
counter circuit is formed. In other words, five different output
combinations are possible so as to correspond to a series of unique
selections which are mutually exclusive. The logical value of nand
gate N20 is Q1.Q3, and the binary counter stages B1, B2 and B3 are
reset at that time only. Here, Q1 and Q3 are the output logical
values of the respective binary counter stages B1 and B3.
The nand gates N21 through N25 constitute a decoder DX and usually
have an output of 1, but the output being selected at any moment
has an output of 0. In FIG. 2, a counter circuit Y consists of four
stages of binary counters connected in series B4 through B7, and 16
(i.e. 2.sup.4) output combinations are possible so as to correspond
to a series of unique selections which are mutually exclusive, but
one combination is not used. Counter circuit Y is connected to the
4 input terminals of each of nand gates N26 through N41, each gate
having one output terminal. Nand gate N26 is not used, as mentioned
above. The output condition of counter circuit Y is similar to the
output condition of counter circuit X previously mentioned.
Since the counter circuits X and Y divide the squarewave of the
electronic clock selection circuit E1 by 5 and 16 respectively, and
a clock pulse is generated by means of a nand gate, they generate
one decoder pulse each in such a way that the output pulses of
decoders DX and DY are invariably in phase with each other at any
time.
The purpose of switch matrix circuit M3 is to provide memory for
selection intersections already removed through selection, and
consists of driving transistors TR1 through TR5 and TR6 through
TR20, resistors R1 through R5 and R6 through R20, 75 diodes D1
through D75 and 75 switches S1 through S75, being driven by the
aforementioned counter circuit CO2 where selection intersections
are arranged by using one decoder pulse each from decoder DX and
decoder DY corresponding to the above-mentioned 80 numbered
intersections. Here, since nand gate N26 is not used as described
above, 1 .times. 5 = 5 intersections are not formed as selection
intersections, but the feedback control signal 16 is 0 at such
times and this causes output Bo to be selected as the output of the
electronic clock circuit E1. Thus, 75 selection intersections are
produced and are arranged at each point of intersection of the
switch matrix circuit M3. Simultaneously, the switch matrix circuit
M3 displays which selection intersection is selected by means of a
visible display 6 using lamps. A light emitting diode may be
substituted for each lamp as well. Also, the switch matrix circuit
M3 displays whether previously selected selection intersections
have been removed or not by means of the position (i.e. ON or OFF)
of each switch in the matrix.
In selection generated by means of coincidence of one decoder pulse
from decoder DX at an arbitrary time together with a decoder pulse
from decoder DY corresponding to the aforesaid clock pulse, for
example, in the case of nand gate N21 and nand gate N40, the
current from the power supply B+ flows through lamp LX1, driving
transistor TR1, switch S1, diode D1, driving transistor TR19 and
lamp LY2 to resistor R21. Thus, a potential difference is produced
across resistor R21 and the feedback control signal 16 having a 1
output is feedback to the aforesaid electronic clock circuit E1,
because one end of resistor R21 is connected to ground. Diodes D1
through D75 are provided for the purpose of preventing the current
from flowing through lamps other than the selected set.
Feedback circuit F4 consists of resistor R21 driven by the
above-mentioned switch matrix circuit M3 and is capable of
transferring the memory of removed selection intersections to the
electronic clock circuit E1 by means of the feedback control signal
16 such that selection may be feasible only when the output of said
resistor R21 is 1 and the output of clock circuit A is in a
predetermined output condition having just made a 0 to 1
transition. A detailed description of the mode of selection during
a same using the Bingo Game unit of the present invention will be
made hereafter. Initially, all switches S1 through S75 of the
switch matrix circuit M3 are ON (i.e. closed contacts), the
selection start switch 4 is "OFF," the feedback control signal 16
is 1 and the output of the acquisition request memory circuit ME is
0. Thus, nand gate N17 is inhibited and the output 15 of the
electronic clock circuit E1 has a 1 output having no relationship
to outpus Ao and Bo of clock circuits A and B respectively. The
current flowing through the selected selection intersection switch
is then interrupted by operation of the appropriate switch (i.e.
one of S1 through S75) in the switch matrix circuit M3 causing the
feedback control signal 16 to become 0 which causes the output of
inverter 6a to become 1 which enables nand gate N6b. Next, when
selection start switch 4 is operated "ON" in order to begin
selection of any one of a series of selection intersections of a
single cycle consisting of M selection intersections, the
acquisition request memory circuit ME is set which causes its
output to change from 0 to 1 and the aforesaid nand gate N17 is
enabled. Furthermore, since nand gate N15 is inhibited, selection
of squarewave F.sub.A becomes impossible and such a condition
allowing selection of squarewave F.sub.B is obtained.
Squarewave F.sub.B advances the counter circuit CO2 to the point
where the next selection intersection not previously removed allows
current to flow through resistor R21 causing the feedback control
signal 16 to become 1 and thus inhibit nand gate N16 and enable
nand gate N15 thereby selecting squarewave F.sub.A as the output 13
of nand gate N17 which is 0 at that time until the end of negative
pulse P. This process is repeated many times while selection start
switch 4 is held "ON". Also, at the end of every negative pulse P
when squarewave F.sub.A and the output 13 of nand gate N17 make a 0
to 1 transition, the output of nand gate N15 makes a 1 to 0
transition which is coupled to inverter 18 through C2 causing a
positive pulse to appear at the output of inverter 18.
Next, depending on the operator, selection start switch 4 is
released or placed "OFF" enabling one input of acquisition circuit
AQ7. When by means of either F.sub.A or F.sub.B selection, the
counter is advanced to a selection intersection not yet deleted
causing feedback control signal 16 to become 1, another input of
acquisition circuit AQ7 is enabled. Finally, at the end of negative
pulse P, the output of inverter 18 provides a positive pulse fully
enabling acquisition circuit AQ7 such that during the pulse time,
the output of nand gate N19 becomes 0 resetting the acquisition
request memory circuit ME output to 0 and in turn inhibiting the
clock output 13 of clock selection circuit E1 thus completing the
single selection cycle wherein a single selection intersection is
selected. In other words, a series of selection intersections of a
single cycle consisting of M cycles of squarewave Ao of clock
circuit A is arranged in such a way that one of M unique selection
intersections and the transition from 0 to 1 of Ao correspond to
each other in every cycle.
Furthermore, since F.sub.A = 1000 c.p.s. and is sufficiently large
compared to N=75 and also due to the operation of minimum time
control circuit MN5, the probability of selecting any one of 75
selection intersections is substantially 1/75, which is equal to
the probability of selecting any other one of the 75 selection
intersections and is also essentially independent of the number of
selection intersections. Further, since switches in the switch
matrix circuit M3 corresponding to previously removed (75-M)
selection intersections are OFF (i.e. open contacts in the case
where M selection intersections have not yet been removed, the
current from the power supply B+ does not flow through the
intersection point corresponding to the aforesaid selection
intersection which has already been removed and the output across
resistor R21 (i.e. the feedback control signal 16) is 0.
Accordingly, the 1 input of nand gate N15 is changed to 0 and the 0
input of nand gate N16 is changed to 1, thus output Ao is inhibited
and output Bo is selected as output 13 of the above-mentioned
electronic clock circuit E1.
Also, since the frequency of clock circuit B is F.sub.B >160,000
c.p.s., 80 cycles of Bo can be contained within the negative pulse
portion P of the aforementioned clock circuit A and the 0 to 1
change of the output Ao is still obtained even if any number of
totally all 75 selection intersections have been removed, and it is
feasible to select selection intersections in any case. In other
words, the switch matrix circuit M3 has such a characteristic that
any number or the total number of selection intersections can be
removed and memorized by means of the switches. Furthermore, the
circuit is arranged such that selection is performed independently
of the (75-M) selection intersections already removed and the
probability of selecting any one selection intersection is 1/M
which is equal to the probability of selecting any other one, and
further, so that the (75-M) selection intersections already removed
are prevented from being selected again by means of the feedback
control signal 16. The mode of selection during a game using the
Bingo Game Unit of the present invention has been fully described
above. However, as shown in FIG. 5 and FIG. 6, as a second
embodiment, mechanical sound may be projected to the players to
enhance enjoyment of players through a speaker 21 driven by audio
unit 20 which has as its inputs the usual microphone 22 where
person 23 reads the number of the selected selection intersection
and also an input from audio circuit AU contained in the main unit
H.
Audio circuit AU consists of nand gate N42, capacitors C4 and C5
and a sound output connector 24. Output Ao of clock circuit A is
one input of nand gate N42 and output Q7 of binary counter stage B7
is coupled through capacitor C4 to a second input while the
remaining third input is the feedback control signal 16. The output
of nand gate N42 is coupled to sound output connector 24 through
capacitor C5. Further, in a third embodiment, an initializing
circuit IC is incorporated. The circuit consists of nand gate N43,
capacitor C6 and resistor R22 and the output of nand gate N43 is
connected to reset terminals BR4 through BR7 of binary counter
stages B4 through B7 respectively. One input of nand gate N43 is
the output of nand gate 8b of acquisition request memory circuit ME
while the other is from the power supply B through capacitor C6.
This initializing circuit IC changes the mode of selection slightly
only at the beginning where upon application of power supply B+
none of the N=75 selection intersections are selected to begin
with.
Thus, it is feasible, using the Bingo Game Unit of the present
invention, to perform successive selection with equal probability
from among 75 uniquely numbered selection intersections or fewer
depending upon how many have already been removed. Futhermore, no
adjustments are required, operation of the unit is almost automatic
and it is easy to see which selection intersections have already
been removed.
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