U.S. patent number 3,880,307 [Application Number 05/336,284] was granted by the patent office on 1975-04-29 for bin address memory system.
This patent grant is currently assigned to Kenway Engineering, Incorporated. Invention is credited to Robert H. Peterson.
United States Patent |
3,880,307 |
Peterson |
April 29, 1975 |
Bin address memory system
Abstract
A computer-controlled warehousing stacker bin address memory
system using clock signals, and comprising a keyboard or the like
for introducing binary bin address data into the system and for
issuing command signals and enable signals to a control circuit
comprising a priority encoder and a preset read only memory. One
set of shift registers, with digital display, is enabled to receive
input address data. Thereafter, command and enable functions cause
data from the display registers to be issued through a set of
execute shift registers to a data transmitter which controls
operation of the stacker crane and, where preservation of an
address is needed, as when the tote pan is being delivered to the
picking station, to place said data in a predetermined one of a
plurality of sets of storage shift registers, from which the data
is likewise, thereafter, transmitted to the E registers to cause
the stacker crane to return the tote pan to storage upon
command.
Inventors: |
Peterson; Robert H. (Salt Lake
City, UT) |
Assignee: |
Kenway Engineering,
Incorporated (Woods Cross, UT)
|
Family
ID: |
23315401 |
Appl.
No.: |
05/336,284 |
Filed: |
February 27, 1973 |
Current U.S.
Class: |
414/807;
414/274 |
Current CPC
Class: |
G06Q
10/08 (20130101) |
Current International
Class: |
G06Q
10/00 (20060101); G11c 007/00 (); B65g
001/00 () |
Field of
Search: |
;340/172.5
;214/11,152,11R,16.4A,16.4B,17R |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Shaw; Gareth D.
Assistant Examiner: Woods; Paul R.
Attorney, Agent or Firm: Foster; Lynn G.
Claims
What is claimed and desired to be secured by United States Letters
Patent is:
1. A method of controlling an automated warehousing system
comprising a stacker crane, storage bins and tote pans, the steps
of:
issuing binary bin address signals identifying the storage bin
location of a tote pan desired to be retrieved on either side of a
stacker crane traversing aisle;
communicating said binary address signals to gating means;
issuing enable signals to the gating means;
gating said bin address signals to a first memory;
issuing tote pan retrieve command signals from control means to
said first memory causing the bin address data to be fed back and
gated through said gating means to both a storage memory and
through an additional third memory to a data transmitter which
controls the stacker crane to retrieve the desired tote pan and
locate the same at a picking station.
2. A method of controlling an automated warehouse system comprising
a stacker crane, storage bins, tote pans and a plurality of memory
means, comprising the steps of:
providing command signals and sets of binary address data;
priority encoding said command signals;
gating said sets of binary bin address data sequentially to an
initial memory location;
selectively processing said priority encoded signals to initiate
ultimate successive retrieval of up to three tote pans from storage
bins respectively corresponding in location to said successive sets
of binary bin address data;
serially gating said successive sets of binary bin address data
from said initial memory location to both (a) another memory
location and (b) an output location by which retrieval movement of
the stacker crane is controlled;
communicating processed priority encoded command signals to said
output location commanding retrieval of said tote pans at said bin
address locations respectively to a picking location;
returning retrieved tote pans from said picking location to their
respective bin address locations by separately gating said sets of
binary bin address data from said other memory location to said
output location and from thence to the stacker crane by which
restorative movement of said stacker crane to return said tote pans
to said storage bins is controlled.
3. The method of claim 2 comprising deriving enabling signals from
said priority encoded signals to control said gating steps.
Description
BACKGROUND
1. Field of Invention
The present invention relates generally to computer-controlled
warehousing systems using stacker cranes and more particularly to a
novel bin address memory system for such warehousing systems
permitting retrieval of a tote pan from a right or left bin storage
location, placement of the tote pan center, right or left at a
picking station and restoration of the tote pan to the desired bin
location. The subject matter of U.S. Pat. Application Ser. No.
336,109, filed Feb. 26, 1973, also assigned to the present
assignee, is incorporated herein by reference. Said application is
now U.S. Pat. No. 3,809,259 granted May 7, 1974.
2. Prior Art
Warehousing systems comprising stacker cranes are used to
automatically pick up and deliver tote pans or pallets from bin
storage on either side of a warehouse aisle. The address of a
desired tote pan storage bin is sent to the stacker from a keyboard
or card reader at a picking station, following which the desired
tote pan is brought from bin storage and is deposited at the
picking station. Here order-picking personnel remove the required
parts, transistors, resistors, nuts, bolts, washers and the like
from the pan. The parts are counted or weighed, labeled and
packaged for delivery to the customer. When the operator has
completed his task, he uses the keyboard to command the stacker to
return the tote pan from the picking station to its proper bin
location.
Previously proposed warehousing systems of the type under
consideration have been limited in the following areas:
1. Tote pans retrieved from bins on the right side of the aisle
have heretofore been capable of being delivered only to a right
side location at the picking station, and vice versa. This severely
restricts the number of order-picking personnel who may function
efficiently at the picking station.
2. The bin address of the tote pan retrieved and placed at the
picking station must be re-entered by the operator prior to
restoration. This permits human error.
3. Only two bins can be accommodated at the picking station at any
one point in time, one on the left and one on the right.
4. There is either no bin address memory system or an inadequate
memory system in relevant prior art warehousing systems.
5. In some such systems, photoelectric reflective tape readers are
used to read the bin address from the tote pan as the bin is in the
process of being restored in order to prevent loss of the bin
address.
BRIEF SUMMARY AND OBJECTS OF THE PRESENT INVENTION
The present invention comprises a novel bin address memory system
for computer-controlled stacker cranes wherein a tote pan from a
storage bin on the right or left side of a warehouse aisle may be
automatically delivered to the center, left or right location at a
picking station. Time is saved and the human error alleviated in
addition to which a higher number of order-picking personnel may
function efficiently at the picking station at the same point in
time. The address of each tote pan at the picking station is
electronically preserved, eliminating the need to re-enter the
address or to externally read the same and re-introduce the reading
into the stacker electronics. Restoration of a tote pan to storage,
therefore, requires only that the operator depress a restore
button.
It is a paramount object of the present invention to provide a
novel computer-controlled warehousing stacker bin address memory
system.
It is another significant object of the present invention to
provide an improved stacker bin address memory system which
preserves each retrieved tote pan bin address while accomplishing
tote pan retrieval from its storage bin on either side of a stacker
aisle and placement of the retrieved tote pan at either side of a
picking station or in a central disposition at the picking
station.
It is another primary object to provide a novel stacker crane bin
address memory system which accommodates memory preservation of the
bin address of a retrieved tote pan and accomplishes restoration of
the tote pan from a left, center or right position at a picking
station to the correct bin location defined by the address.
These and other objects and features of the present invention will
be apparent from the following detailed description, taken with
reference to the accompanying drawing.
BRIEF DESCRIPTION OF THE DRAWING
The FIG. is a circuit diagram of the presently preferred
computer-controlled warehousing stacker bin address memory system
of the present invention.
DETAILED DESCRIPTION OF ILLUSTRATED EMBODIMENT
The preferred bin address, using the present system, is a four to
six digit number, depending on the size of the warehouse. In
situations where a four digit number is used, the thousands and
hundreds decimal digits are used to identify the horizontal bin
location. Thus, if the thousands and hundreds decimal digit is 35
the stacker crane would be commanded to proceed down the warehouse
aisle until it had reached the 35th vertical column of bins on
either side of the aisle. The tens and units digits are used to
define the vertical bin location. If the units digit is odd, the
bin location will be on the left side of the aisle, if even on the
right. This number instructs the stacker crane not only as to the
side from which retrieval is to be made but the correct vertical
elevation of the bin containing the tote pan to be retrieved.
##SPC1##
The bin address may be manually entered into system by a ten-key
keyboard or automatically from a card reader or computer. The
binary address comprises binary ones and zeros appearing at inputs
SD1, SD2, SD4 and SD8. In a manner hereinafter to be explained, the
indicated input bin address is passed by dual 4 to 1 line
multiplexers E2 and E3, upon receipt of clock pulses to a set of
display (D) registers E16-E19. Preferably, multiplexers E2 and E3
each comprises integrated circuit SN74153, manufactured by Texas
Instruments and disclosed on page 302 of the text The TTL Data Book
for Design Engineers, copyrighted 1973 by Texas Instruments, Inc.
The D registers E16-E19 communicate the binary bin address to a
seven segment light emitting diode display, in a well known
manner.
The keyboard is equipped such that if the wrong address is entered
in the display registers, it may be cleared by pressing the proper
keyboard button causing the display register reset signal DRR* to
go low, clearing display registers E16-E19, following which the
correct entry may be made by the operator.
It should be understood that signal SB* is used to send a new bin
to warehouse storage for the first time. Specifically, the address
in the D register is caused to be shifted to the E register. This
function is also used to restore bins after a power failure.
The card reader or keyboard causes the input signals identified on
the drawing to selectively reach the input terminals of priority
encoder E1. Priority encoder E1 is preferably integrated circuit
SN74147 manufactured by Texas Instruments (see page 147 of said
Texas Instruments text) and serves to convert nine bits of data
into four lines containing the same information. Normally, when the
keyboard is inactive, all of the input signals to priority encoder
E1 will be high, a state where nothing is occurring. When it is
desired to enable the primary encoder E1, the voltage signal EB
No.* is caused to go low. The other signals as identified, continue
high. It is to be appreciated that the priority encoder E1
functions such that, with respect to the site designations 1-9 on
the interior of E1, the low signal, if only one occurs, or the
rightmost low signal, if more than one low signal is presented,
constitutes the E1 input and the collective output at sites A-D at
pins 9, 7, 6 and 14 will be the complement of said E1 input.
Consequently, in the state just mentioned when signal EB No.* goes
low, the input to priority encoder E1 is a 9 and the output is the
complement of binary 9, i.e. "0 1 1 0".
It is further to be appreciated that when any input signal to E1
goes low following receipt of the EB No.* signal, the EB No.*
signal returns to its high state, allowing the low voltage signal
to control the output of priority encoder E1. The letter
designation of the input signals to E1 are defined as follows:
DBC* Deliver Bin Center DBL* Deliver Bin Left DBR* Deliver Bin
Right RCB* Restore Center Bin RLB* Restore Left Bin RRB* Restore
Right Bin SB* Store Bin EB No.* Enter Bin Number.
Reverting to the condition when signal EB No.* is low and remaining
inputs to priority encoder E1 are high, a binary 6, the complement
of 9, is passed to the read only memory (ROM) E4. Preferably, read
only memory E4 is integrated circuit IM5610 manufactured by
Intersil, Inc. of 10900 North Tantau Ave., Cupertino, Calif. 95014.
See all six pages of the Technical Bulletin entitled Intersil 256
BITOLAR READ ONLY MEMORY IM 5,600 IM 5,610. The ROM E4 is preset
(electrically programmed) in its condition to create as an output
any of the ones centrally listed in Truth Table 1, when the
adjacent corresponding input to E4 exists, as shown on the left
thereof in Table 1. Consequently, when EB No.* is low, the Q3
output is high and the remaining outputs of E4 are low. The Q3 high
signal is designated DSE (display shift enable) because it
conditions display (D) registers E16-E19 to receive the bin address
earlier keyed to the dual 4 to 1 line multiplexers E2 and the E3.
The low state of E4 terminals Q1 and Q2 (signals RTA and RTB),
which connect to terminals A and B, respectively, of E2 and E3
together form a zero state causing the inputs at the two zero
terminals to be gated to output terminals 1Y and 2Y. This circuit
is of such a nature that when the input signals RTA and RTB at
terminals A and B are both binary zeros, the 1Y and 2Y outputs are
connected to the 0 input terminals; when RTA and RTB are a binary
one and zero, respectively, the gates within integrated circuit E2
and E3 connect the 1Y and 2Y outputs to the 1 input terminal; when
signals RTA and RTB are zero and one, respectively, outputs 1Y and
2Y are connected to the 2 input terminals; and when the RTA and RTB
signals are both binary ones, the 3 input terminals are gated to
the 1Y and 2Y output terminals. By reason of the feedback
connections between the multiplexers E2 and E3 in respect to the
various sets of shift registers, proper address retention and
retrieval is accomplished as more fully described hereinafter.
Since only the flip-flop display shift registers E16-E19 are
enabled to receive the binary bin address, the address is
registered only at E16-E19. It is to be appreciated that all of the
registers shown in the drawing from E8 through E23 are preferably
integrated circuit SN74164 manufactured by Texas Instruments (see
page 334 of said Texas Instruments text), each of which comprise 8
shift register flip-flops having eight true outputs only. In the
circuit arrangement shown in the drawing, only the four of the
eight true outputs are used, although the invention is capable of
other configurations.
At this point in time, a high state exists at terminals 1 and 2 of
each display register E16-E19. A clock signal 4SC is input to
terminal 8 of each display register E16-E19 causing the binary bin
address to enter at location one and shift from left to right to
the fourth location. This binary number once placed in the display
register is visually displayed on a 7 segment LED display.
It is to be appreciated, in the illustrated embodiment, that all
registers shift data from left to right only. It is also to be
appreciated that clock signals 4DC and 4SC are preferably pulses
derived from a suitable clock issuing 4 pulses per operation.
Moreover, in respect to each illustrated register, the left column
will receive and store only a binary 1, the second column from the
left a binary 2, the third a binary 4 and the fourth a binary
8.
From the foregoing and Table 1, the manner in which the priority
encoder E1, the read only memory E4, the multiplexers E2 and E3 and
the registers in sets E8-E11, E12-E15, E16-E19 and E20-E23 function
for each input at priority encoder E1 should be apparent.
Selecting, for purposes of example only, a situation where the
keyboard operator depresses the "deliver right bin" key causing the
DBR* signal to go low, the priority encoder E1 would output the
complement of 4, i.e., a binary 11. Read only memory E4 would then
have high outputs at sites Q2, Q4, Q7 and Q8, the other outputs
being low. The Q1 and Q2 outputs (RTA and RTB, respectively) being
low and high, respectively, condition multiplexers E2 and E3 such
that the 1 input terminals are respectively gated to 1Y and 2Y
output terminals. The high signal from Q4 (ECE) enables AND gate
E7, while the high voltage signal from Q7 (RCE) enables AND gate
E6. The high signal from Q4 (ECE) is also delivered to each of the
execute (E) registers E20-E23 at the 2 input terminal thereby
enabling those registers. The positive voltage signal (RSE) from
terminal Q8 is delivered to the 2 terminal of each of the right (R)
registers E12-E15 to enable the same. Because of the described
state of multiplexers E2 and E3, the data stored previously in the
D registers E16-E19 is communicated from the 6 output of each
register to the 1 input of multiplexers E2 and E3 and from thence
to enabled R registers E12-E15. At essentially the same time, four
clock pulses (4SC) are issued, being received at AND gates E5, E6
and E7. Since the LCE input to AND gate E5 is low, the high clock
pulses do not change the state of E5 and its output remains low. To
the contrary, both inputs to AND gates E6 and E7 are now high and
the output will be high. Thus, AND gates E6 and E7 pass the four
clock pulses to the 8 input of R registers E12-E15 causing the bin
address previously in the D registers E16-E19 to be placed in the
left position and sequentially shifted to the right position in the
register. At the same time, the identified bin address previously
stored in the D registers E16-E19 is also placed in the left
location and shifted to the right location in E registers E20-E23
and parallel output by a data transmitter to the stacker crane.
Thus, the tote pan, the address of which is transmitted, is caused
to be retrieved by the stacker crane, brought to the picking
station and shifted to the right at that station for removal of
desired merchandise.
In like manner, as can be appreciated from a careful examination of
Truth Table 1, the addresses of pans being delivered left and
right, respectively, to the picking station are preserved in L
registers and R registers, respectively, and each of said stored
addresses is passed to the D and E registers when the corresponding
pan is to be returned to its storage bin location. The notation in
the right column of Table 1, C+K, means the input signal from the
card reader or keyboard, depending upon which is being used.
It is preferred that the EB No.* signal be retained high when a
tote pan is delivered by the stacker crane to the center position
of the picking station following delivery of the DBC* signal to the
priority encoder E1. This disables the priority encoder, making it
impossible for the operator to effectively signal for delivery of
an additional tote pan. Otherwise, a plurality of tote pans may be
delivered and situated in left, right and, lastly, center
positions, the electrical system illustrated in the drawing
accommodating storage and retrieval of the address of the left tote
pan in the L registers, the address of the right tote pan in the R
registers and the address of the center tote pan in the D and E
registers.
The invention may be embodied in other specific forms without
departing from the spirit or essential characteristics thereof. The
present embodiment is therefore to be considered in all respects as
illustrative and not restrictive, the scope of the invention being
indicated by the appended claims rather than by the foregoing
description, and all changes which come within the meaning and
range of equivalency of the claims are therefore intended to be
embraced therein.
* * * * *