Programmable music synthesizer

Abstract

A programmable music synthesizer which is completely electronic having no movable parts except for manually operated switches and controls wherein each note of a sequence of notes is digitally encoded in terms of a scaler value of the note, its time duration and relative octave range; the digitally encoded information being entered into an electronic memory via a keyboard comprising the manually operated switches and controls; the controls being further effective during the playback portion of the operation at which time the digitally encoded information is automatically withdrawn in accordance with the order in which the notes have been stored, a portion of the decoded information being used to selectively actuate a variable frequency generator the output of which appears as a predetermined sequence of musical notes each of which persists for a time duration in accordance with another portion of the prestored information.

Description

SUMMARY OF THE INVENTION

The present invention relates to a programmable music synthesizer and more particularly to a completely electronic implementation thereof having no moving parts except for manually operated switches and controls. An electronic memory is provided for storing digital information defining a sequence of notes including the value of each note relative to a standard musical scale, and also the octave and the time duration of each note. The digital information is entered into the electronic memory during the programming portion of an operative cycle. The stored information is recovered from memory during the playback portion of an operative cycle. The scale and octave portions of the stored information are used to generate an audio signal of desired frequency. The audio signal persists for a predetermined time in accordance with the time duration portion of the information stored with each note.

Prior art attempts to synthesize music are readily distinguishable from the present invention and as such may be generalized by classification into two categories: the first of which includes non-programmable music synthesizers an example of which is disclosed in the patent to Fredkin et al, U.S. Pat. No. 3,610,801; and secondly, devices comprising crude analogs of mechanical player pianos, which upon inspection will be found to be lacking, among other things, any ability to control the relative time relationship of the notes generated. Examples of the latter devices include the subject of the patent to D'Agata, U.S. Pat. No. 3,520,983 and a device called a "Psych-Tone" described in the Popular Electronics' Electronic Experimenter Handbook, 1973 Edition.

A programmable music synthesizer constructed in accordance with the principles of the present invention is readily adaptable for a wide variety of uses. Since a principal feature of the device is its reprogrammable nature this, coupled with the fact that the unit is totally self-contained, makes it particularly valuable as an aid in composing music. The compact nature of the preferred embodiment of the present invention facilitates its use in this latter capacity.

Other uses of the subject invention include: the teaching of music, as an electronic music box, and as a musical door bell.

According to the present invention, the device for composing, recording and playing back a sequence of musical notes comprises a keyboard the respective keys of which represent the notes capable of being generated including the octave, the time duration of each note and the control signals for stepping the apparatus through its various modes of operation. The keyboard is operatively connected to a memory portion having a plurality of storage locations each of which is adapted to store digital information defining a note in terms of its value on a scale of notes as well as the time duration and octave range of the note. An address register is connected to the memory portion to permit the storage locations of the memory to be sequentially scanned thus initially facilitating the storage of digital information pertaining to a new sequence of notes; and subsequently thereto, during the playback portion of an operative cycle, enabling the automatic and sequential scanning of the plural memory locations at a rate determined by the time durational information stored therein. For purposes of determining the time duration of each note, a time decoder is connected to the output of the memory, an output signal being generated therefrom in accordance with the time duration portion of the information stored at that particular memory location. The output of the time decoder is in turn used to step the address register such that upon the occurrence of each output signal the address register is stepped; this in turn initiates the referencing of the next storage location in memory. Also connected to the output of the memory is a tone decoder which is operative from the time a particular memory location is first referenced until such time as the time decoder generates an output signal to initiate referencing of the next successive memory location. The tone decoder generates an audio signal having a frequency determined by the balance of information contained at the memory storage location being referenced including the information defining the relative value of the note on the musical scale and its octave.

Although the preferred embodiment of the present invention has a limited memory capacity of some sixteen 8 -bit words, with each word generating a corresponding note, it is possible to increase the memory capacity without altering the operating principles of the present invention thereby enabling an entire musical score or a plurality thereof to be selectively played-back after having been programmed therein. Similarly, the preferred embodiment of the present invention is disclosed as embodying a single tone decoder. It should be immediately apparent to those having ordinary skill in the art that additional tone decoders may be conveniently added so as to program the device to simultaneously reproduce a plurality of notes. By extending the design principles to include a plurality of time decoders the notes will be available for play-back in a time overlap manner. These and other features should become more readily apparent from the following specific description.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagrammatic representation showing the principal operating portions of a programmable music synthesizer constructed in accordance with the principles of the present invention.

FIG. 2 is a detailed representation of the time decoder of FIG. 1.

FIG. 3 is a detailed representation of the tone decoder of FIG. 1.

DETAILED DESCRIPTION OF THE INVENTION

Turning now to FIG. 1, therein is illustrated a diagrammatic representation of the preferred embodiment of the subject programmable music synthesizer, the heart of which comprises a memory 10. In the prefered embodiment, memory 10 comprises sixteen 8-bit words selectively addressable on a half word basis. The first three bits of each word, corresponding to bits B.sub.1, B.sub.2, and B.sub.3, define the time duration of a note i.e. how long the note or rest is to persist. These 3 bits facilitate eight possible time lengths; from a 16th note to a whole note. The means for selecting and determining the time length of a note are discussed in further detail below in connection with the explanation of FIG. 2.

The balance of the bits comprising the 8 bit word are used to define the octave; the relative value of a note within an octave; and, a possible rest or stop condition. In the preferred embodiment bit B.sub.4 defines one of two octave ranges available; while bits B.sub.5, B.sub.6, B.sub.7, and B.sub.8 are used to define the relative value of a note within an octave as well as the stop and rest conditions.

Memory 10 is perhaps most conveniently implemented using semiconductor memory chips which may be mounted on a "mother-board" thus facilitating the ready substitution of the memory portion of the apparatus. Such semiconductor memory chips are commercially available, an example of which is presently being marketed by Fairchild Semiconductor Manufacturing Co. under part number 93403. Each chip contains 16 four bit words, thus two such chips are necessary to implement the memory in the preferred embodiment.

The design of the subject music synthesizer is such that the memory 10 may be readily enlarged. Thus, increasing the number of words in the memory 10 results directly in the increase of the number of notes which may be played back provided addressing means are available to address all word locations in memory. Likewise, increasing the number of bits in each word results in a corresponding increase in the amount and type of information available to define each note.

Alternative modes of implementation of the memory 10 include the use of static and dynamic shift registers. Another alternative concerns the use of read only memory techniques, these being particularly useful as a means for cutting the unit price of a music synthesizer to be used as a door bell or for some other application wherein there is no need to continuously update, or change, the sequence of notes. The use of a read only memory nevertheless facilitates periodic reprogramming in the sense that a different memory board may be readily substituted for the one currently in the unit. There is also the possibility of using a "reprogrammable" read only memory, such as that marketed by the Intel Corporation under number 1702A.

Addressing of the memory 10 is accomplished by means of an address register 12 which in the preferred embodiment of the present invention comprises a conventional four stage binary counter the output of which is capable of addressing any of the sixteen storage locations of memory 10. As will be noted from the explanation which follows, an output from the highest order stage of the address register 12 appears as a carry (C), the signal normally occurs after the highest order location in memory 10 has been scanned. The carry signal serves to toggle a flip flop 14; this condition signals the completion of either the programming or playback portion of an operative cycle of the music synthesizer.

The count stored in the address register 12 is advanced manually by means comprising an advance button 16, or alternatively is advanced automatically by the output of a time decoder 13. The advance button 16 is used to advance the address register 12 during the programming portion of an operative cycle during which time information is being stored in memory 10. Alternatively address register 12 is automatically stepped by the output of the time decoder 13 during the playback portion of an operation.

The sequencing of the address register 12 by means of the advance button 16 enables the memory 10 to be selectively addressed for arbitrary periods of time during which digitally encoded information may be stored in both half-words of the memory address currently being referenced by the address register. Storage on a half word basis is effected by the selective actuation of RIGHT WRITE and LEFT WRITE control keys, as is discussed in detail below. Stepping of the address register 12 by means of the output of the time decoder 13 occurs at a rate determined by the informational content of the memory address location currently being referenced by the address register 12. A detailed explanation of the time decoder 13 both from the standpoint of construction and operation is given below in conjunction with the explanation of FIG. 2.

A clock 15 is shown in FIG. 1 as being operatively connected to the time decoder 13. The clock 15 functions to supply the time decoder with a continuous stream of periodic pulses which are employed in the time decoder to generate synchronized output signals including the signal used to step the address register 12. The clock 15 utilized in the preferred embodiment of the present invention comprises a variable frequency oscillator of conventional design having a controlled output which may be varied over the range of 2 to 10 Hz. Although the clock 15 may be operated at a variety of frequencies, the output thereof is generally left unchanged during the playback of any particular sequence of notes. The facility to vary the base frequency of the signal generated by clock 15 affords an independent degree of control over the rate at which a sequence of notes may be played back from the music synthesizer.

It should be noted that the signals generated by the advance button 16 and the time decoder 13 are selectively gated into the address register 12 by means of NAND gate 30 and AND gate 42 with the output of the advance button being inhibited during the playback mode while output signals from the time decoder are inhibited during the reprogramming mode.

Information is entered into the memory 10 from a keyboard 21 via a binary encoder 22. The keyboard 21 comprises 16 selectively actuated microswitches representing the 16 notes capable of being played by the subject device over a two octave range. The information comprising the note selection is encoded in a conventional manner by means of the binary encoder 22 into a four bit code which in turn is stored as a half word in memory 10. Storage of a code representation of a selected note in memory 10 is accomplished by depressing a RIGHT WRITE key 19. Similarly a LEFT WRITE key 18 is provided to store an indication of the octave range and the time duration of a note; one bit of the left half word being used to determine the octave while the other three bits are used to determine how long a note, or rest, is to be.

On the output side of the memory 10 is an output register 23 which serves to buffer information from the memory to the time decoder 13 and to a tone decoder 24. The tone decoder comprises a variable modulo counter which cycles at a varying rate depending upon the value of a preset count entered therein. The variable modulo counter is driven by a constant frequency clocking signal from a clock 26. As will be explained below in conjunction with the explanation of FIG. 3, the clock 26 is capable of generating an output signal over a range of from 100 to 500 kHz; however, during a particular operative cycle clock 26 operates at a predetermined frequency, which in the preferred embodiment is normally set to 260.6 kHz in order to obtain an output of middle C for the lowest note. Varying this frequency allows the range of the device to be transferred up or down. The stable output signal of the clock 26 is divided into desired frequency components by the tone decoder 24 which functions to generate a signal having a frequency corresponding to the tone, or note, to be reproduced. The manner of construction and mode of operation of the tone decoder 24 should become more readily apparent from the detailed discussion thereof given below in conjunction with the explanation of FIG. 3. For now it should suffice to say that the output of the tone decoder 24 corresponds in frequency to a particular musical note; the output signal being fed to a power amplifier 25 and from thence to a speaker 27.

Consideration is now given to the execution of an operative cycle of the programmable music synthesizer of FIG. 1 commencing with the programming portion thereof. For this purpose a switch 20 when set to PROGRAMMING MODE removes the ground or zero voltage which in turn results in the partial conditioning of NAND gates 30, 32, and 34. These latter gates afford protection against the accidental "dumping" of memory during the playback mode of operation.

Also at this time a start button 17 is depressed which "sets" flip-flop 14 thus activating the synthesizer. Just prior to the setting of flip-flop 14, i.e. when the flip-flop 14 is reset, the audio output of the tone decoder 24 is muted, the address register 12 is reset, the memory 10 is disenabled, and the output of the time decoder 13 is inhibited. Thus, at such time as flip-flop 14 becomes set the address register 12 will register a count of 0. The Start signal conditions the corresponding memory location to accept information from the keyboard 21 via the binary encoder 22. The first information to be entered into the keyboard 21 comprises the relative value of a note which, in accordance with the representation of Table 1, is associated with a particular one of the 16 keys comprising the keyboard 21.

TABLE 1 __________________________________________________________________________ CONTROLS KEY 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RIGHT/ PITCH C C Sharp D D Sharp E F F Sharp G G Sharp A A Sharp B Rest Stop WRITE LEFT/ TIME/ 1/16 1/8 3/16 1/4 3/8 1/2 3/4 1 1/16 1/8 3/16 1/4 3/8 1/2 3/4 1 WRITE OCTAVE __________________________________________________________________________ LOWER OCTAVE UPPER OCTAVE

The note being selected is entered into memory by simultaneously depressing the appropriate key on the keyboard 21 and the RIGHT WRITE key 19. This automatically transfers a signal on the output line corresponding to the selected key on the keyboard 21, which output signal is converted in the binary encoder 22 into a four bit binary representation which appears as bits B.sub.5, B.sub.6, B.sub.7, and B.sub.8 at memory 10 where it is stored as the right half of word 0.

The next step is to enter "time" and "octave" information, corresponding to the note just selected, into the left half of memory word 0. This is done by simultaneously depressing the LEFT WRITE control key and one of the 16 keys of the keyboard 21 representing the desired time and octave selected in accordance with the provisions of Table 1. A corresponding four bit representation will be entered into bit locations B.sub.1, B.sub.2, B.sub.3, and B.sub.4 of memory location 0.

It will be noted that in addition to the twelve notes entered into the right half of a memory word it is possible to enter a "rest" signal or a "stop code". As will become apparent from the explanation of the synthesizer in its playback mode, the occurrence of a rest signal results in the muting of the output of the tone decoder 24 for a period of up to 1 full note. The occurrence of a stop code indicates that there are no further notes in the particular tune being played.

After both the right and left half words have been entered into memory location 0 the Advance button 16 is depressed thus permitting a pulse to appear at the output of AND gate 30 which in turn steps the address register 12 by one count thus referencing memory location 1. Information defining the second note in the tune is now ready to be entered into the right half word of memory location 1 by means of the appropriate key on the keyboard 21. This operation is effected in the manner outlined above with respect to the entry of similar information into the right half word of memory location 0. In similar manner the left half word of memory location 1 receives information defining the time and octave range of the corresponding note. Thereafter the Advance button 16 is again depressed causing the address register 12 to reference memory location 2. This process is repeated until information has been stored in all sixteen locations of memory 10. Alternatively, a stop code may be entered as desired.

This completes the explanation of the programming portion of the operation; however, it should be noted that after the sixteenth note has been stored, in memory location 15, and the advance key is thereafter depressed the resultant input to the address register 12 causes the address register to recycle generating a carry signal which is returned to the flip-flop 14 causing it to be reset. When the control flip-flop 14 is reset it mutes the audio output, it resets the memory address counter to 0, it disenables the memory, and inhibits the time decoder. Nothing else happens.

Attention is now directed to the operation of the programmable music synthesizer in its playback mode. This mode of operation is initiated by positioning switch 20 to PLAY MODE. Subsequently, depressing the Start key 17 sets the flip-flop 14 and partially conditions NAND gate 40 and AND gate 42. The tone decoder 24 will generate an output signal to the speaker 27 corresponding in frequency to the note registered in the 0 word location of memory 10, this latter information being buffered through the output register 23 of memory 10 and into the tone decoder 24 as information bits B.sub.4, B.sub.5, B.sub.6, B.sub.7, and B.sub.8 . The corresponding time duration information is buffered into the time decoder 13 as bits B.sub.1, B.sub.2, and B.sub.3. These latter bits are decoded in the time decoder which generates a timed output signal in consequence thereof which output signal completes the conditioning of AND gate 42 thus stepping the address register 12 to memory location 1. In addition to stepping the address register the output of the time decoder temporarily mutes the output of the tone decoder 24 so that there is a slight pause between notes. This latter feature permits the same note to be played successively such that they appear as distinct notes rather than as one long note. Succeeding notes are played in the same manner with play continuing until flip-flop 14 is reset by a carry from the address counter 12 or alternatively by an output from AND gate 38 and NAND gate 40 signalling the detection of a stop code.

Referring now to FIG. 2 therein is disclosed a detailed representation of the time decoder 13 of FIG. 1. As indicated above, the time decoder serves to step the address register 12 during the playback mode of operation. The separation between successive stepping signals to the address register 12 determines the time duration of a note generated in tone decoder 24. The information determining the separation between successive stepping pulses is derived from the time duration portion of the digital information stored in memory 10, i.e. the informational contents of bit locations B.sub.1, B.sub.2, and B.sub.3. This latter information is used to selectively gate a particular one of a stream of pulses being generated by the clock 15 onto the output line of the time decoder 13. In this respect clocking signals from clock 15 are used to toggle a four-stage counter 28 capable of generating, in timed sequence, a binary coded representation of from 0 through 15; these latter signals are partially decoded in logic 29 forming a corresponding number of independent signals, each of which occurs during respective successive states of counter 28. In the preferred embodiment, only 8 of the 16 signals generated by the decoding logic 29 are required since notes of only eight different time durations are provided for. The outputs of the decoder 29 condition a conventional selection gating circuit 31 such that an output signal is generated therefrom upon coincidence with the digitally encoded information stored in memory 10 as bits B.sub.1, B.sub.2, and B.sub.3.

In effect, the time decoder of FIG. 2 counts the signals generated by the clock 15 and when a count corresponding to the count stored in memory 10 is reached, the time decoder generates an output signal to the address counter 12 resulting in the stepping of the latter to the next successive memory location.

To this end the time decoder of FIG. 2 is further provided with gating circuitry including NAND gates 35 and 37 and AND gate 39. The NAND gate 35 permits the stepping of the counter 28 by clocking signals from clock 15 only when flip flop 14 is set to the start state. NAND gate 37 and AND gate 39 function collectively to transfer an output signal from the time decoder 13 to the address counter 12 and AND gate 38 of FIG. 1, only during the last half of a clock cycle during which coincidence is detected in the multiplexer 31 between the input bits B.sub.1, B.sub.2, and B.sub.3 and the count represented in counter 28. It is on the trailing edge of the output signal from AND gate 39 that the address register 12 is incremented. The trailing edge of the output signal from AND gate 39 is made to persist for a sufficient length of time to ensure stability in AND gate 38 thus avoiding premature or accidental conditioning of the latter. This may conventionally be effected by inserting a suitable time delay at the input to AND gate 38. The counter 28 is reset by the first clock pulse following the appearance of an enable signal from the output lead of the multiplexer 31. A flip flop 33 is set by the first clock pulse after the inhibit signal, generated at the output of AND gate 36 of FIG. 1, is removed. This prevents the starting of a playback operation until the beginning of a clock pulse, and insures that the first note will not have a variable length.

Turning now to FIG. 3, therein are disclosed the details of the tone generator 24 of FIG. 1. The tone generator functions as a frequency divider which uses the high frequency output signal from clock 26 as an input to a frequency dividing network which in turn selectively generates the desired frequency components corresponding to the musical notes to be generated. The heart of the tone generator 24 is the variable modulo counter 44. Counter 44 functions as a preset counter which is loaded with a predetermined count chosen such that the complement thereof when divided into the high frequency output of clock 26 results in the cycling of counter 44 at a rate equal to four times the frequency of a note to be generated. This signal is in turn stepped down to two times the desired note frequency, i.e. one octave above the desired note, by permitting the signal to toggle a complementary type flip-flop. A further reduction to the desired frequency is obtained by using the output of the aforementioned flip-flop as an input to a second complementary type flip-flop, the note of desired frequency appearing at the output thereof.

The synchronous counters 28 and 44 of FIGS. 2 and 3 respectively, are constructed from integrated circuit four bit synchronous counters marketed by Fairchild Semiconductor under catalog number 9316. Counter 28 requires one unit and counter 44 requires two.

In the preferred embodiment of the present invention counter 44 comprises an eight stage counter capable of generating an output signal every 256 input clocking pulses. Thus, if a count of seven is preset into counter 44, the first clock pulse to be inputted from clock 26 will step the counter to a count of 8 such that an output signal will be generated after some 249 clocking pulses. By dividing 249 into the base frequency of 260.6 kHz and thereafter dividing the result by 4, there is produced at the output of the tone decoder 24 a signal having a frequency of approximately 261.6 Hz corresponding to a middle C. Other notes are similarly derived by entering a predetermined count into counter 44 in accordance with the following Table of Values.

TABLE OF VALUES ______________________________________ VARIABLE OUTPUT STANDARD FREQ. PRESET MODULO FRE- (EQUAL TEMPERA- COUNT COUNT QUENCY NOTE MENT SYSTEM ______________________________________ 7 249 261.6 C 261.6 21 235 277.2 C sharp 277.2 34 222 293.4 D 293.7 46 210 310.2 D sharp 311.1 58 198 329.0 E 329.6 69 187 348.4 F 349.2 80 176 370.2 F sharp 370.0 90 166 392.5 G 392.0 99 157 415.0 G sharp 415.3 108 148 440.2 A 440.0 116 140 465.4 A sharp 466.2 124 132 493.6 B 493.9 ______________________________________

The predetermined count to be entered into the variable modulo counter 44 is established by means of a diode matrix 46. The diode matrix may be of conventional design and it together with the binary decoder 48 converts the four bits, B.sub.5, B.sub.6, B.sub.7, and B.sub.8, comprising the right half word of a memory location into the proper signal representation to establish a desired precount in the variable modulo counter 44. As indicated, the outputs from the binary matrix 46 selectively condition inputs to the variable modulo counter 44 to in turn establish any desired predetermined count in the corresponding flip-flops of the modulo counter 44. It should be noted that after the predetermined count has been entered into the flip-flops comprising modulo counter 44, the clocking signals from clock 26 step the counter along until an overflow or carry is generated in the highest order stage. An output from the highest order stage of the variable modulo counter 44 re-establishes the predetermined count in the flip-flops. The counter continues to cycle in this manner with every second output from the highest order stage being used to toggle a flip-flop 49 to its set state and correspondingly every fourth output of the highest order flip-flop of variable modulo counter 44 is used to toggle the flip-flop 50 to its set state.

Logical gating means comprising: a pair of NAND gates 52 and 54, inverters 56 and 58, and NAND gate 60, are partially conditioned by the octave information comprising the bit B.sub.4. The manner in which these logic components cooperatively function with the outputs of flip-flops 49 and 50 to deliver an output signal of desired frequency to the audio amplifier 25 of FIG. 1 and in turn to speaker 27 is explained below.

It will be noted that variable modulo counter 44 cycles at a rate determined by the complement of the preset count divided into the base clock frequency of 260.6 kHz. Also, an output signal from the flip-flop 49 partially conditions NAND gate 52 every second output pulse from the variable modulo counter 44 while an output signal from flip-flop 50 partially conditions NAND gate 54 every fourth output signal of the variable modulo counter 44. The output of the in-line, inverters 56 and 58 completes the conditioning of NAND gate 52 or NAND gate 54. Which of the NAND gates 52 and 54 is conditioned depends upon the state of the input signal corresponding to bit B.sub.4. Thus, if B.sub.4 is "low" the signal on the output side of inverter 58 will be "high" thus conditioning NAND gate 52. Under these same conditions the signal on the output side of inverter 56 will be "low" and as a consequence NAND gate 54 will not be conditioned. Conversely, if B.sub.4 is "high" the output side of inverter 58 will be "low" while the output of inverter 56 will be "high". Thus NAND gate 54 will be conditioned by NAND gate 52 will not. A "low" signal from AND gate 36 de-conditions NAND gate 60, and prevents sound from being generated during a REST, between notes, or when flip-flop 14 is reset. Alternatively, a "high" signal on the Inhibit lead to NAND gate 60, permits the audio signal being generated by NAND gates 52 and 54 to appear as an input to the audio amplifier 25 of FIG. 1.

While a preferred embodiment of the present invention has been disclosed and the operation has been described in terms thereof, it should be readily apparent that various substitutions may be readily made without departing from the spirit of the invention. As an example, the tone generator 24 may conveniently be implemented by means other than a variable modulo counter. In similar fashion the keyboard may be altered to vary the sequence of steps involved in the operation of the subject synthesizer in its PLAYBACK and PROGRAMMING modes. Accordingly, while the particular form of the device has been shown and described, it is not intended that the scope of the invention be limited to the particular form disclosed in that alternative forms of the device will immediately be evident to those skilled in the art.

Claims

What is claimed is:

1. A music synthesizer comprising means to generate a digital representation corresponding to each one of a sequence of musical notes, said last named means further comprising first means to define the frequency of each note and second means to define the time duration thereof, electronic means for separately storing each of said digital representations comprising said sequence of musical notes, and means for sequentially recovering each of said digital representations comprising said sequence of musical notes from said electronic storage means, and means for generating from said digital representations audio signals corresponding to said sequence of musical notes.

2. A music synthesizer operative to generate audio signals in the form of a sequence of musical notes from prestored digital representations thereof, each of said prestored digital representations comprising a first plurality of bit positions defining the frequency of a note and a second plurality of bit positions defining the time duration thereof, electronic storage means, said prestored digital representations being stored in said electronic storage means, and means operatively connected to said electronic storage means for sequentially recovering said prestored digital representations from said electronic storage means and for generating from said digital representations audio signals in the form of said sequence of musical notes.

3. A programmable music synthesizer operable in a first mode to store a selected sequence of signals comprising preselected notes of a musical score and in a second mode to playback said stored signals comprising said selected sequence of signals to thereby recreate said musical score therefrom, comprising means for generating a coded representation for each of said preselected notes, said coded representation comprising a plurality of digitally encoded bits a first plurality of which define the frequency of a note and a second plurality of which define the time relationship of said note with respect to other of said preselected notes, means operatively connected to said first named means for storing said coded representations of said preselected notes, and means connected to the output of said means for storing said coded representations for recovering said coded representations of said preselected notes and for generating audio signals therefrom in said selected sequence and bearing said predetermined time relationship with respect to said other of said preselected notes.

4. A programmable music synthesizer operative to store a digital representation comprising a sequence of musical notes and wherein said digital representation comprises a plurality of digitally encoded bits a first plurality of which defines the frequency of a note and a second plurality of which defines the time duration thereof, said synthesizer comprising a keyboard adapted to enable an operator to sequentially select a series of notes, digital encoding means operatively connected to said keyboard for generating a digital representation of each of said notes as said notes are selected, electronic storage means operatively connected to said digital encoding means for sequentially storing the digital representation corresponding to each of said series of notes in the order in which said notes are selected by an operator of said programmable music synthesizer, said last named means including means to automatically scan the successive memory locations of said electronic storage means at a rate determined by said second plurality of digitally encoded bits comprising said digital representation of each note, and means operatively connected to said last named means for generating audio signals from said first plurality of digitally encoded bits comprising said digital representation of each note.

5. A programmable music synthesizer comprising a keyboard comprising a plurality of selectively actuatable keys, each of said keys selectively representing the pitch and time duration of a particular musical note, a multi-location electronic storage means, means for sequentially scanning said multi-location electronic storage means, means operatively connecting said keyboard and said multi-location electronic storage means, control means operatively connected to said scanning means and to said multi-location electronic storage means for sequentially storing digital information defining the pitch and time duration of musical notes selected from said keyboard, said control means further operative to initiate the scanning of the digital information stored in said plural storage locations of said multi-location electronic storage means, said control means further comprising means for directing a first plurality of bits of said digital information comprising a first portion of the informational contents of a particular one of said multi-storage locations of said electronic storage means to a time decoder to determine the time duration of a particular note and for directing a second plurality of bits of said digital information comprising a second portion of the information stored at said particular one of said plural storage locations of said electronic storage means to a tone decoder for determining the frequency of said note.

6. An apparatus particularly operative for composing musical scores comprising a keyboard each key of said keyboard operative to generate a signal representing a particular note on a musical scale, said keys being further used to define the time duration of a particular note relative to other notes and the octave in which the selected note is to be played, storage means operatively connected to said keyboard and operative to store a coded representation of each note selected via said keyboard including information defining the value of said note on said musical scale together with the octave and the time duration of said note, addressing means operatively connected to said storage means and operative to sequentially scan the plural storage locations of said storage means, and means for stepping said addressing means, said last named means further comprising manually actuated means for stepping said addressing means thereby sequencing said storage means through said plural storage locations at a rate which facilitates entry of the coded representation of a note selected via said keyboard and a second means for automatically stepping said addressing means at a rate determined by that portion of a signal entered via said keyboard defining the time duration of a note relative to said other notes.