Electrocardiographic waveform analyzer

Abstract

There is disclosed a system for reviewing ECG signals at high speed. Successive ECG waveforms are superimposed on each other in a display, but the rate at which traces of the waveforms are formed is independent of the rate at which ECG waveforms are played back from a tape on which they are recorded. This is achieved by storing data representative of each ECG waveform in a recirculating memory whose recirculation rate is faster than the input data rate, and using the recirculated data to form the display. A similar recirculating memory is provided to form a display of each 4-second ECG signal segment which contains a premature beat, this display being formed automatically without requiring operator control.

Description

This invention relates to the analysis and display of electrocardiographic waveforms, and more particularly to such analysis and display at high speeds.

In the field of continuous ECG recording, a patient is often provided with a small, portable tape recorder; standard electrodes are attached to the patient's chest and leads are connected to the tape recorder. A continuous ECG signal, extending over as long a period as 24 hours, may thus be recorded on a standard tape cassette without in any way confining the patient. Rather than to require a physician or technician to review a 24-hour tape in "real time" (which would require 24 hours of effort), techniques have been devised for speeding up the review procedure.

In Holter et al. U.S. Pat. No. 3,215,136 issued on Nov. 2, 1965 and entitled "Electrocardiographic Means", one such technique is disclosed. The ECG signal recorded on the tape is played back at a much greater speed than that used during recording; for example, a tape may be played back 60 times as fast. The ECG signal is applied to the vertical deflection plates of an oscilloscope, and the horizontal sweep is triggered by each ECG waveform. What results in the case of a normal signal is a series of similar superimposed waveforms displayed on the screen. The waveforms "blend" into each other and what is viewed is for all intents and purposes a single ECG waveform which is smeared slightly in view of small differences from cycle to cycle. Whenever an "unusual" (e.g., premature) waveform signal is applied to the vertical deflection plates, the resulting trace is "different". This is an indication of an abnormal waveform. The reviewer may then slow down the tape, and play the signal back at slower speed while a paper trace is made of the waveforms in the sequence of interest.

A continuous bright (normal) waveform is formed on the display provided that the combination of tape speed and the persistence of the phosphor on the face of the CRT are great enough to allow one waveform to blend or merge into another. This can be understood by considering the kind of display which is formed when the tape is played back at normal speed, with the horizontal sweep being synchronized to the waveforms (that is, there being approximately 1 horizontal sweep per second, corresponding to a 60 beat-per-minute heart rate). In such a case, the electron beam sweeps across the face of the tube once each second, and the waveform which is displayed is of the well-known "bouncing ball" type. Unless the persistence of the phosphor is very long, a complete ECG waveform is not continuously visible. Only when the tape is played back at greater speed do the superimposed successive ECG complexes result in a continuous bright image.

But if the persistence of the phosphor is too high, then with a high frame rate (60 per second) there can be considerably smearing of the display. On the other hand, if the phosphor has low persistence, even a 60-per-second frame rate will result in flicker. The basic problem in the design of such a system is that the quality of the image is necessarily dependent on the tape speed.

It is an object of our invention to provide a system for analyzing ECG waveforms at high speed by forming superimposed traces of them on the screen of a CRT, but in which the quality of the image thus formed is independent of tape playback speed.

Another object of our invention is to control the automatic continuous display of a short ECG signal segment whenever an abnormal condition is detected, in order to insure that no such conditions are missed. Each segment thus displayed remains on the screen until another is detected. This allows the technician or physician reviewing the waveforms to examine a short segment "at his leisure". (The tape can even be stopped during this time period, without either trace disappearing from the face of the CRT; the last ECG waveform which was read from the tape remains at the top of the display, and the last 4-second segment containing an abnormal waveform remains at the bottom of the display.)

In accordance with the principles of our invention, each analog ECG waveform read from the tape is sampled and digital representations of the samples for a complete waveform are temporarily stored. When the samples representative of a complete waveform are available, they are quickly transferred to a recirculating shift register (recirculating memory). Successive samples at the output of this recirculating shift register are converted to analog form and used to form a single ECG waveform at the top of the CRT display. The horizontal sweep of the CRT is synchronized to the recirculation time of the shift register. The important point here is that the recirculation rate (CRT horizontal sweep time) is completely independent of the rate at which ECG waveforms are read from the tape. (In fact, even if the tape is stopped, the recirculating data continues to be used to form a display of the last waveform.)

While ECG waveforms may be read from the tape at a rate of 60 per second, the CRT frame rate, that is, the rate at which ECG waveforms are formed on the display, may be in the hundreds per second. This means that each individual waveform may be traced out on the screen several times prior to the storage of a new waveform in the recirculating shift register. Smearing of the continuous bright image can be avoided by using relatively low persistence phosphors (e.g., P-31); and with a high enough frame rate, there is no flicker.

A similar technique is used to control the formation of a 4-second segment of the ECG signal -- at the bottom of the display. Samples of the last 4 seconds (in real time) of the ECG signal are temporarily stored. When an abnormal condition is detected (automatically, by use of conventional prematurity detectors, for example), the samples representing four seconds of the ECG signal are transferred to a second recirculating shift register. Thereafter, the data stored in this second shift register are used to form a display at the bottom of the screen. The display is formed continuously until another abnormal condition is detected, at which time the samples representative of a new 4-second ECG signal segment are transferred to the second recirculating shift register. This new 4-second ECG signal segment is then continuously traced out on the CRT. In this case, too, the trace which is formed on the CRT is completely independent of the rate at which the ECG signal is analyzed by the system.

Further objects, features and advantages of the invention will become apparent upon consideration of the following detailed description in conjunction with the drawing, in which:

FIG. 1 depicts the form of the display which is achieved in accordance with the principles of my invention;

FIGS. 2, 3 and 4, placed from left to right, are a schematic representation of the illustrative embodiment of the invention;

FIG. 5 depicts the counting chain for deriving the seven clock signals required by the system of FIGS. 2-4;

FIG. 6 depicts several waveforms which will be helpful in understanding the manner in which two different displays are formed on the CRT; and

FIG. 7 depicts various timing waveforms which will be helpful in understanding the operation of the illustrative embodiment of the invention.

As shown in FIG. 1, the display which is formed on the face of the CRT consists of two parts. The upper part is the trace of an ECG waveform. In the illustrative embodiment of the invention, 225 ECG waveforms are traced out each second. Since the tape is played back at 60 times the recording speed, in the usual case there are slightly more than 60 ECG waveforms read from the tape per second. Depending on the exact rate at which ECG waveforms are read from the tape, each waveform is displayed several times. The frame rate is fast enough such that even though the persistence of the screen phosphor is so low that each individual trace persists for less than 1/225 second, there is no flicker because all of the successive waveforms blend together in the observer's eye.

Whenever a premature beat is detected, it is traced out several times in rapid succession, as in the case of all other waveforms, and although the traces are seen for only a brief interval, if the superimposed traces are different, the reviewer is immediately informed of the abnormal condition. At the bottom of the display of FIG. 1, there is shown a typical 4-second ECG signal segment which includes a premature beat. As will be described in detail below, whenever a premature beat is detected, the 4-second segment containing that beat is displayed at the bottom of the CRT. This is accomplished automatically -- even if the operator misses the momentary out-of-place premature beat in the upper display. The lower trace persists indefinitely until the next premature beat is detected, at which time a new 4-second segment is displayed. The lower trace is also formed at a 225-per-second frame rate. Since in the usual case, premature beats do not immediately follow each other, the lower 4-second segment may be traced out many, many times before it is changed.

The system of FIGS. 2-4 requires several timing signals. Various gate inputs are shown connected to respective clock waveforms; the timing of the system will be explained in detail below. Before considering the illustrative embodiment of the invention, however, it should be noted how all of the necessary clock waveforms may be derived. As shown in FIG. 5, the basic system clock is a 3.6864 MHz oscillator, depicted by the numeral 500. A conventional divider chain, consisting of dividers 502, 504, 506, 508, 510 and 512, is used to derive six other clock waveforms as is known in the art. Each divider element in the chain causes its output to change state only in response to a negative step in its input. Thus any transition in the waveform of a clock signal always occurs when all higher-frequency clock signals exhibit negative transitions.

FIG. 2 depicts symbolically a tape playback unit 200 whose output is applied to the input of a play-back amplifier 216. The amplified ECG signal, whose rate in the illustrative embodiment of the invention is 60 times the real time rate, is applied to the input of R-wave detector 244 and comparator 218. The minus input of the comparator is connected to the output of digital-to-analog converter 224. The purpose of this connection will be described below, but at this point it is sufficient to understand that the output of the comparator is positive whenever the instantaneous amplitude of the signal at the plus input is greater than that at the minus input, and that the output of the comparator is negative when the opposite condition exists. The R-wave detector 244 does not per se form a part of the present invention. It simply functions to trigger one-shot multivibrator 246 whenever an R wave in the continuous ECG signal is detected. Any conventional R-wave detector may be used; one such R-wave detector is shown in Harris U.S. Pat. No. 3,490,811, issued on July 6, 1971 and entitled "Electrocardiographic R-Wave Detector." R-wave detection is required in the system because it is the detection of each R wave that initiates transfer of a waveform to a recirculating memory for subsequent display.

The ECG signal is sampled and it is the digital representations of the samples which are temporarily stored. (The display itself is actually formed by recirculating digital samples and converting them to analog form, followed by the application of the analog signal to the vertical deflection plate of the CRT.) The technique for converting each analog sample of the ECG signal to an 8-bit binary value is a standard one involving the use of a successive approximation register 220 (e.g., chip No. AM 2502), a digital-to-analog converter 224 (e.g., Hybrid Circuits chip No. 371-8), and a standard comparator 218. The register 220, in successive clock cycles, increases or decreases the binary value at its outputs in a direction determined by the potential level at the "approximation control" input of the element. The 8-bit value is converted to analog form by converter 224, and the analog signal is applied to the minus input of comparator 218. The comparator functions to determine whether the instantaneous value of the ECG signal is greater or less than the value represented by the 8-bit output of register 200, and the polarity of the comparator output determines whether during the next clock cycle the register 220 increases or decreases its output value in an attempt to cause the output of converter 224 to match the instantaneous value of the ECG signal. It requires nine clock pulses at the clock input of converter 220 to control the 8-bit output of the register to properly represent the instantaneous value of the ECG signal which is to be sampled.

The sampling rate is 14.4 kHz. Although 14,400 samples are thus taken each second, since the tape is played back at 60 times recording speed, the effective sampling rate of the ECG signal (translated to real time) is 240 samples per second. As is known in the art, this is a high enough sampling rate so as not to lose any important information in the ECG signal.

Successive approximation register 220 is triggered when a negative step is applied to its "convert" input. Thereafter, nine clock pulses are required at its clock input until the 8 bits at the outputs B0-B7 represent the binary value of a sample. The convert input of the register is triggered at a 14.4 kHz rate. The clock pulses occur at a much higher rate -- 460.8 kHz -- so that each binary sample is fully derived long prior to the next sampling cycle.

The waveforms which characterize the operations of elements 202 and 204, as well as register 220, are shown at the top of FIG. 7. The 14.4 kHz clock signal is applied directly to the K input of J/K flip-flop 202, and through inverter 230 to the J input. The 460.8 kHz clock signal is applied to the clock input of the flip-flop, and the flip-flop changes state on a negative transition in the clock signal whenever the states of the J and K inputs have changed. Since a negative transition occurs in the 460.8 kHz clock signal prior to a transition in the 14.4 kHz clock signal (due to delays in successive dividers in the counting chain of FIG. 5), the state of flip-flop 202 changes only on the negative step in the clock signal which follows a change in the 14.4 kHz signal. This is shown by the three upper waveforms of FIG. 7. The third waveform shows the state of the Q output of the flip-flop and it is apparent that it follows the 14.4 kHz clock signal, with an opposite polarity and after a delay of one cycle of the 460.8 kHz signal. The 14.4 kHz clock signal is applied to one input of gate 204, and the Q output of the flip-flop is applied to the other input. Only when both inputs are high is the output of the gate low. Thus following each positive step in the 14.4 kHz clock signal, a short negative pulse appears at the output of gate 204. This negative pulse, applied to the convert input of register 220, triggers a successive approximation cycle. The 460.8 kHz clock pulses are applied through inverter 242 to the clock input of the register, and after nine clock cycles the 8-bit output of the register represents the binary value of the instantaneous magnitude of the ECG signal at the output of amplifier 216. In the fifth line of FIG. 7, the vertical arrows represent the completion of each conversion cycle, that is, the availability of a digital sample at the outputs of register 220.

Digital multiplexer 226 is provided with two groups of eight inputs each. Bits B0-B7 at the outputs of register 220 are extended to input set A, while input set B is grounded. The multiplexer operates to extend respective bit values in a selected one of the two input groups to its eight outputs M0-M7 in accordance with the polarity of the signal at the SELECT A input. When this input is low, the signals (ground) at the B inputs are extended to the multiplexer outputs; when the SELECT A input is high, bits B0-B7 are extended to the multiplexer outputs.

The eight multiplexer outputs are connected to the data inputs of respective 256-bit shift registers 228-0 through 228-7. The output of gate 258 is connected to the shift input of each shift register. As will be described shortly, as long as the SELECT A input of multiplexer 226 is high, successive shift pulses from gate 258 control the storage of successive 8-bit samples in the eight shift registers. Shift pulses are generated at a 14.4 kHz rate, there thus being one shift pulse for each new sample (at the multiplexer outputs) which is taken of the ECG signal.

The shift registers thus represent 256 8-bit samples of the ECG signal. As described briefly above, all of this data is rapidly transferred to a recirculating memory (another set of 8 shift registers) for subsequent display. Since incoming ECG waveform data is shifted along the shift registers 228-0 through 228-7 it is important to synchronize the rapid transfer of the data to the recirculating memory at a time which permits each ECG waveform to be properly placed on the display (FIG. 1).

The R-wave detector 244 detects the presence of each waveform. But each waveform is detected when the samples representative of the R wave are still stored at the input end of the shift registers. Rather than shifting the data out of the shift registers as soon as an R wave is detected, it is preferable to allow the data to be shifted down the registers until the R wave is centered; this, in turn, permits the overall waveform to be centered on the display. Accordingly, when the R-wave detector 244 verifies the presence of an R wave, one-shot multivibrator 246 is triggered. It is only at the trailing edge of the positive output pulse of this multivibrator that one-shot multivibrator 250 is triggered. It is when the output of this multivibrator goes high that the system rapidly transfers the data in shift registers 228-0 through 228-7 to the recirculating memory used to form the display. Potentiometer 248 is used to control the delay between the detection of an R wave and the start of the rapid transfer of data out of the shift registers. It is on the leading edge of the pulse at the output of one-shot multivibrator 250 that the transfer begins.

The entire transfer takes place in less than one period of the 14.4 kHz clock, as will be explained in connection with the timing waveforms of FIG. 7. The duration of the pulse generated by one-shot multivibrator 250 must be at least as great as one period of the 14.4 kHz clock signal, but it should not be excessively long or else data will be transferred out of the shift registers at the fast rate when it should be stored in them at the slow rate (14.4 kHz). For this reason, in the illustrative embodiment of the invention, the duration of the pulse at the output of multivibrator 250 is 1.5 periods of the 14.4 kHz clock signal.

As shown in FIG. 7, the Q output of flip-flop 252 is normally low. The Q output of the flip-flop is fed back to the K input. Since the J input (output of multivibrator 250) is normally low, the 14.4 kHz clock pulses applied to the clock input of the flip-flop have no effect since if both inputs to a J/K flip-flop are low, the flip-flop state does not change with the application of clock pulses. But as soon as the output of multivibrator 250 goes high, as shown in FIG. 7, the flip-flop changes state with its Q output going high on the next negative transition at the clock input. This occurs at a falling edge of the 14.4 kHz clock waveform. As soon as the flip-flop changes state, the K input goes high along with the J input. The next negative step in the clock input causes the flip-flop to change state once again (a J/K flip-flop changes state upon the application of a clock input whenever both of the J and K inputs are high). Thus, as shown in FIG. 7 it is at the trailing edge of the next 14.4 kHz clock pulse that the Q output of flip-flop 252 goes low once again. It remains low until another R wave is detected, that is, until after approximately another 256 samples have been taken. It is during a single period of the 14.4 kHz clock signal, while the Q output of flip-flop 252 is high, that 256 shift pulses are applied to the shift input of registers 228-0 through 228-7 at a very high rate in order to rapidly transfer all of the data to the recirculating memory.

Ordinarily, the Q output of flip-flop 252 is high, and this output is coupled to one input of gate 256. The 14.4 kHz clock signal is applied through inverter 222 to the other input of gate 256. Consequently, the output of gate 256 follows the 14.4 kHz clock signal, as indicated in FIG. 7. The output of gate 256 is connected to one input of gate 258. Ordinarily, the output of gate 254, one of whose inputs is connected to the Q output of flip-flop 252, is high. This output is connected to the second input of gate 258 and has no effect on its output. Consequently, as long as flip-flop 252 has its Q output high, it is only gate 256 that controls the application of shift pulses to the shift registers. The 14.4 kHz clock signal is extended through gate 258, but is inverted. The output of gate 258 is thus the complement of the 14.4 kHz clock signal. Each of shift registers 228-0 through 228-7 executes a shift operation when a positive step is applied to its shift input, that is, when the output of gate 256 goes low. This is depicted in FIG. 7 by the vertical arrows in the line labeled SHIFT (SLOW). It is the falling edge of each waveform in the 14.4 kHz clock cycle that controls the shifting of data in the eight shift registers.

During the time that the Q output of flip-flop 252 is low, the SELECT A input of multiplexer 226 is high, thus allowing bits B0-B7 from register 220 to be extended through the multiplexer to the shift register inputs. It is in this way that a new sample is stored in the shift registers during each of the 14.4 kHz clock cycles. It should be noted from FIG. 7 that each sample is available at a time indicated by the arrows in the line labeled "CONVERSION COMPLETE", each sample being stored in the shift registers shortly thereafter with the generation of a SHIFT (SLOW) signal.

But whenever an R wave is detected, and following the delay introduced by one-shot multivibrator 246, flip-flop 252 changes state. At this time the Q output goes low so that the inputs to the shift registers 228-0 through 228-7 represent eight 0's. With the Q output high, gate 254 transmits 3686.4 kHz clock pulses through it; these pulses pass through gate 258 to the shift register shift inputs. This operation is shown by the line labeled "GATE 254" in FIG. 7. The output of the gate is ordinarily high but as soon as flip-flop 252 changes state, the 3686.4 kHz pulses are extended through it. These pulses are extended through gate 258 to the shift inputs of the eight shift registers. Just as a shift operation is controlled by the output of gate 256 going low, so a shift operation is controlled by the output of gate 254 going low. The bottom line of FIG. 7 labeled "SHIFT (FAST)" depicts the fast shift operations. Since fast shift pulses are generated during one complete cycle of the 14.4 kHz signal, and since the fast shift pulses (which occur at a 3686.4 kHz rate) occur at a rate which is 256 times as fast as the slow shift pulses, it is apparent that all 256 bits in each shift register are shifted out on conductors 270-0 through 270-7 during one cycle of the 14.4 kHz clock signal, as indicated in FIG. 7. At the end of this cycle, there are 256 0's stored in each shift register inasmuch as the data input to each shift register represents a 0 since the SELECT A input of multiplexer 226 is low throughout the duration of the fast shift operation. Immediately following the 256 fast shift pulses, flip-flop 225 changes state once again and successive samples are stored in the shift registers at the slow rate.

It should be noted that a slow shift pulse is generated shortly after each sample conversion -- except for that sample conversion which immediately precedes the Q output of flip-flop 252 going high. Thus one sample of the ECG waveform is actually lost, that is, not stored in shift registers 228-0 through 228-7 during that cycle of the 14.4 kHz clock signal in which the previously stored samples are rapidly transferred out of the shift registers. This is of no importance, particularly since the "lost sample" occurs between successive ECG waveforms (along the base line). It should also be noted that the number of bits actually shifted out of the shift register depends upon the number of samples which are taken between successive R waves. This number can vary although it is more or less constant as long as normal in-step waveforms are present.

Another set of 256-bit shift registers 304-0 through 304-7 is provided on FIG. 3. The samples which are shifted out of registers 228-0 through 228-7 at a 3686.4 kHz rate are stored in registers 304-0 through 304-7. Thereafter, the samples are recirculated in these registers at the same time that they are used to form the upper trace on the display. The recirculating rate is much slower than the high-rate transfer.

It is when the Q output of flip-flop 252 is high that the fast transfer is to take place. Conductor 262, which is connected to the Q output of the flip-flop, is extended to the SELECT A input of digital multiplexer 302. The outputs of shift registers 228-0 through 228-7 are connected to the eight inputs in input set A of multiplexer 302. Consequently, during the fast transfer, the samples which are being transferred between registers are extended through multiplexer 302 to the inputs of shift registers 304-0 through 304-7. During this transfer, clock pulses appear on conductor 260 at a 3686.4 kHz rate. These pulses are extended through gate 308 to the shift inputs of register 304-0 through 304-7. Consequently, the 256 shift pulses which are generated during a single cycle of the 14.4 kHz waveform control the storage of all data representive of a single ECG waveform in registers 304-0 through 304-7. At the end of the fast transfer, conductor 260 remains high and has no effect on the shifting in registers 304-0 through 304-7. And conductor 262 which now goes low causes the data at the eight inputs in set B of multiplexer 302 to be extended through the multiplexer to shift registers 304-0 through 304-7. The eight output conductors D0-D7 from these registers are extended back to respective inputs of set B of multiplexer 302. Consequently, shift pulses applied to the registers simply control the recirculation of the data stored in them.

The shift pulses which control the recirculation are derived from gate 306. As long as the Q output of flip-flop 252 is high (during the slow storage of samples in shift registers 228-0 through 228-7, and during the recirculation of data in shift registers 304-0 through 304-7), conductor 266 is high in potential. This conductor is connected to one input of gate 306 and the 115.2 kHz clock signal is connected to the other input of the gate. Consequently, 115.2 kHz clock pulses are extended through the gate and through gate 308 to the shift inputs of registers 304-0 through 304-7 to control the recirculation of the data. (The data which are shifted out of the registers on conductors D0 - D7 are also extended to the circuitry on FIG. 4 which is used to form the display, as will be described below.)

The recirculation rate is controlled by the 115.2 kHz clock signal, and each waveform is represented by 256 bits in registers 304-0 through 304-7. It is thus apparent that in each second there are 115, 200/256 or 450 complete recirculations of data. As will be described below, an ECG waveform trace is developed only during alternate recirculations, and consequently an ECG waveform is traced out on the display 225 times each second. Since ECG waveforms are actually processed from the tape at the rate of approximately 60 per second, it is apparent that each ECG waveform is traced out on the CRT several times.

The circuitry described thus far functions to temporarily store each ECG waveform and to then quickly transfer it to a recirculating memory from which a trace may be developed. In a similar manner, provision is made for temporarily storing approximately 4 seconds of the ECG signal (represented by 1,024 8-bit samples), and following the detection of a premature beat to quickly transfer this data to another 1024-sample recirculating memory to control the continuous display of a 4-second (real time) ECG signal segment at the bottom of the display. (Instead of 4 seconds of storage, it is also contemplated that a signal including as few as three successive ECG waveforms be stored.)

The 8-bit samples at the output of register 220 are extended to the eight inputs in set A of multiplexer 310. The eight inputs in set B are grounded and the eight outputs of the multiplexer are extended to the inputs of the eight 1024-bit shift registers 312-0 through 312-7. Multiplexer 310 and registers 312-0 through 312-7 are analogous to multiplexer 226 and shift registers 228-0 through 228-7. Data is normally stored in registers 312-0 through 312-7 at a 14.4 kHz rate, but when a premature beat is detected and the data in the registers are to be transferred out to a recirculating memory at a fast rate, the 3686.4 kHz clock is employed.

The output of R-wave detector 244 is extended over conductor 264 to the input of prematurity detector 314. This detector, having a time constant of 6 seconds (real time), functions to average the time interval between successive pairs of R waves, and to energize its output if any R wave is premature by 10 percent. Any of many prematurity detectors can be employed, and one such prematurity detector is disclosed in Harris U.S. Pat. No. 3,616,791 entitled "ELECTROCARDIOGRAPHIC MORPHOLOGY RECOGNITION SYSTEM" dated Nov. 2, 1971. Rather than to detect only premature beats, it is also possible to detect an abnormal morphology as is disclosed in the last-mentioned patent for the purpose of triggering a new 4-second segment display whenever any abnormal beat is detected (even if it is not premature).

When a premature beat is detected, one-shot multivibrator 316 is triggered. The period of this multivibrator is controlled by potentiometer 338, the potentiometer being set so that the premature beat will be displayed approximately at the center of the display. (That is, the fast transfer out of registers 312-0 through 312-8 is delayed by approximately 2 seconds in real time, or 2/60 seconds in processing time). At the trailing edge of the pulse at the output of multivibrator 316, multivibrator 318 is triggered for controlling the fast transfer.

The Q output of flip-flop 320 is normally low and the Q output is normally high. Consequently, 14.4 kHz clock pulses are extended through inverter 342 and gate 336 to one input of gate 322 to control the storage of samples in registers 312-0 through 312-7 at the same rate as the rate at which they are taken, namely, 14.4 kHz. When one-shot multivibrator 318 is triggered, however, the J input of flip-flop 320 goes high and the flip flop changes state just as flip-flop 252 changes state when one-shot multivibrator 250 is triggered.

As soon as flip-flop 320 changes state (on a negative step in the 3.6 kHz clock signal), it is gate 334 which transmits clock pulses from the 3686.4 kHz clock through gate 322 to the shift registers, rather than gate 336 transmitting 14.4 kHz clock pulses through the same gate 322. Also, the SELECT A input of multiplexer 310 goes low so that following the fast transfer out of the shift registers, each shift register contains 1024 0's. Flip-flop 320 controls the fast transfer during four complete cycles of the 14.4 kHz clock signal since the clock input of flip-flop 320 is connected to the 3.6 kHz clock signal. While the clock signal for multivibrator 252 is 14.4 kHz, the clock signal for multivibrator 320 is 3.6 kHz. That is because there are 4 times as many bits stored in each of registers 312-0 through 312-7 than there are stored in each of registers 228-0 through 228-7. The storage of samples in the 1024-bit shift registers and the fast transfer of the samples out of the registers is analogous to the storage of samples in the 256-bit registers and the fast transfer of the bits out of the registers. (During the fast transfer, four samples from register 220 are "lost", that is, not stored in registers 312-0 through 312-7 but that is of little concern.)

In a similar manner, multiplexer 400 and shift registers 402-0 through 402-7 control the fast storage of 1024 samples in the shift registers, followed by their recirculation. During the fast transfer, conductor 326 is high and the SELECT A input of multiplexer 400 is high. At this time, the samples on conductors 330-0 through 330-7 which are shifted out at a fast rate from registers 312-0 through 312-7 are stored in shift registers 402-0 through 402-7. The shift pulses for the shift registers pass through gate 406 and are derived from conductor 324. The clock pulses used to control the storage of data in registers 402-0 through 402-7 are those used to control the transfer of data out of registers 312-0 through 312-7.

Following the fast transfer, conductor 324 remains high in potential and has no effect on the shifting of bits in registers 402-0 through 402-7. Similarly, conductor 326 switches to a low potential so that the eight inputs in set B of multiplexer 400 are selected for extension to the outputs. Consequently, data shifted out of registers 402-0 through 402-7 are recirculated in a manner comparable to the recirculation of data controlled by multiplexer 302 and shift registers 304-0 through 304-7. Since conductor 328 is high in potential at all times other than during a fast transfer of samples from one set of shift registers to the other, gate 404 functions to extend 460.8 kHz clock pulses through gate 406 to the shift inputs of registers 402-0 through 402-7. It should be noted that the rate at which data is recirculated in registers 402-0 through 402-7 is 4 times as great as the rate at which data is recirculated in registers 304-0 through 304-7. That is because there are 4 times as much data stored in the former set of registers than in the latter. By using a clock which is 4 times as fast, there is a complete recirculation of 4 seconds of data in registers 402-0 through 402-7 in the same time that there is a complete recirculation of one second of data in registers 304-0 through 304-7; in both cases, a complete CRT line of data is recirculated at a rate of 450 recirculations per second. Since the lower trace on the CRT is formed during only every other recirculation, the lower trace is formed at a rate of 225 per second. (As will be described below, the upper end and lower traces are formed during alternate horizontal sweeps.)

The samples shifted out of registers 402-0 through 402-7 are applied to the eight inputs in set A of multiplexer 418. The data which are shifted out of registers 304-0 through 304-7 are applied to the eight inputs in set B of multiplexer 418. The SELECT A input of multiplexer 418 changes polarity at a rate of 450 per second so that during alternate horizontal sweeps either 256 samples are extended through the multiplexer to control the formation of the upper CRT trace, or 1024 samples are extended through the multiplexer to control the formation of the lower CRT trace.

Since data for each of the two displays is recirculated at a rate of 450 complete recirculations per second, and each display is formed in alternate cycles, a 225 Hz clock signal is required for alternately controlling the use of the samples shifted out ot either of the two recirculating memories. Multiplexer 418 is utilized for alternately controlling the formation of a display from either 256 samples which are recirculated in one memory or from 1024 samples which are recirculated in the other. The 225 Hz clock signal is extended through inverter 412 to the SELECT A input of the multiplexer. During each half cycle that the SELECT A input of the multiplexer is high, 1024 samples from shift registers 402-0 through 402-7 are extended through the multiplexer to the inputs of 8-bit latch 422. It will be recalled that data is recirculated in shift registers 402-0 through 402-7 under control of a 460.8 kHz clock. Since there are 1024 samples stored in the shift registers, complete recirculation of the data occurs at a 450 Hz rate (460,800.div. 1,024=450). Similar remarks apply to the recirculation of data in shift registers 304-0 through 304-7, data being shifted at one-quarter the rate so that complete recirculations of data also occur at a 450 Hz rate. It is thus apparent why a 225 Hz clock signal is used to switch between the two sets of inputs in multiplexer 418; there is a complete recirculation of each set of data during each half cycle of the 225 Hz clock.

Each sample which is extended through the multiplexer is stored in 8-bit latch 422. The latch must be strobed at the same rate at which new samples are extended through the multiplexer. When the 225 Hz clock signal is high, it is the samples from shift registers 304-0 through 304-7 which are extended through the multiplexer to the latch, at a 115.2 kHz rate. For this reason, the latch must be strobed at this rate. Gate 410 is enabled when the 225 Hz clock signal is high, and 115.2 kHz clock pulses are transmitted through inverter 408, gate 410 and gate 420 to the strobe input of the latch. In a similar manner, during alternate cycles, it is gate 416 which is enabled and it is now the 460.8 kHz clock signal which is extended through inverter 414, gate 416 and gate 420 to the strobe input of the latch. In both cases, the latch is strobed on the falling edges of the 115.2 kHz and 460.8 kHz clock signals, to ensure that a sample extended through multiplexer 418 has had time to settle.

The output of the latch is extended to the input of digital-to-analog converter 424, and the output of this element is an analog representation of the signal to be traced out on the display.

The output of the digital-to-analog converter 424 is not extended directly to the vertical input of CRT 430. Instead, it is extended through a resistor 432 to a summing junction. The second input to the summing junction is a potential source 438 which is extended through a potentiometer 436. The potentiometer simply controls the vertical position of the entire display, a technique well known in the art. The third input to the summing junction is the 225 Hz clock signal which is extended through potentiometer 434. During alternate half cycles of the clock signal, the vertical deflection signal is increased so as to allow the two different displays to be formed at different levels on the face of the CRT.

FIG. 6 depicts the relevant timing waveforms for the CRT. At the top of the drawing there are shown the 450 Hz and the 225 Hz clock signals. It will be recalled that when the 225 Hz clock signal is high the SELECT A input of multiplexer 418 is low so that it is the samples required for the upper trace which are extended to latch 422. It is at this time that the vertical deflection signal is increased by the 225 Hz clock signal extended through potentiometer 434, with the output of the digital-to-analog converter 424 being positioned on the base line defined by the 225 Hz clock signal. This is shown in the bottom waveform of FIG. 6. During alternate half cycles of the 225 Hz clock signal, when the SELECT A input of multiplexer 418 is high and the lower trace is to be formed on the display, the 225 Hz input to the summing junction is low and the output of the digital-to-analog converter 424 is positioned on the lower base line. (The additional bias through vertical position control potentiometer 436 simply moves the entire display up or down on the screen; the setting of potentiometer 434 controls the space between the two separate traces.)

As described above, horizontal sweeps must occur at a 450 Hz rate, two horizontal sweeps being required during each cycle of the 225 Hz clock so that one trace may be made for each display. The 450 Hz clock signal is extended to the input of one-shot multivibrator 426. The short ("retrace") pulse output from this multivibrator, shown in FIG. 6, is used for two purposes. First, it triggers the horizontal sweep circuit 428, the output of which is extended to the horizontal deflection circuit of the CRT. Any standard horizontal sweep circuit may be utilized for this purpose, and the horizontal sweep waveform is shown in FIG. 6. Second, since the triggering of the horizontal sweep circuit first results in the retrace of the signal, followed by a sweep, it is desirable to blank the CRT during the retrace. For this reason, the output of one-shot multivibrator 426 (the retrace multivibrator) is extended to the blanking input of the CRT to shut off the electron beam during retrace.

It is thus apparent that the CRT display is completely independent of the tape speed. Once data is stored in the recirculating memories, a continuous display will be formed even if the tape is stopped altogether and no new input data is examined. The recirculation rate, since it is independent of tape speed, can be selected in any particular system, in conjunction with the particular phosphor which is used in the CRT, to provide the best possible display for the purposes of the system. The quality of the display does not change even if the tape speed is varied. Furthermore, the automatic formation of the lower display, which depicts every 4-second segment of the ECG signal which contains a premature beat, ensures that no premature beat goes undetected.

Although the invention has been described with reference to a particular embodiment, it is to be understood that this embodiment is merely illustrative of the application of the principles of the invention. Numerous modifications may be made therein and other arrangements may be devised without departing from the spirit and scope of the invention.

Claims

What I claim is:

1. A system for reviewing an ECG signal stored on a recording medium comprising means for reading the ECG signal from said recording medium at a rate substantially faster than the rate at which said ECG signal was recorded, first means for temporarily storing successive ECG waveforms read from said recording medium, first recirculating memory means, means responsive to the storage of an ECG waveform in said first temporary storage means for transferring the stored ECG waveform to said first recirculating memory means, second means for temporarily storing a segment of the ECG signal read from said recording medium which is at least long enough to include 2 normal heartbeat cycles, second recirculating memory means, means for detecting an abnormal heartbeat in the ECG signal read from said recording medium and responsive thereto for transferring the temporarily stored ECG signal segment to said second recirculating memory means, means for recirculating an ECG waveform stored in said first recirculating memory means and an ECG signal segment stored in said second recirculating memory means at rates faster than the rates at which an ECG waveform and an ECG signal segment are stored in said first and second temporary storage means, and display means synchronized to the recirculation rates of said first and second recirculating memory means for displaying all ECG waveforms stored in said first recirculating memory means superimposed on each other, whereby ECG waveform traces are formed on said display means at a rate faster than that at which they are read from said recording medium, and for displaying separately the ECG signal segment stored in said second recirculating memory means.

2. A system in accordance with claim 1 wherein ECG waveforms and ECG signal segments are stored in said first and second temporary storage means and in said first and second recirculating memory means in the form of samples.

3. A system in accordance with claim 2 wherein the ECG waveform stored in said first temporary storage means is transferred to said first recirculating memory means at a rate so fast that during the transfer time there is an insignificant change in the ECG signal read from said recording medium.

4. A system in accordance with claim 2 wherein the ECG signal segment stored in said second temporary storage means is transferred to said second recirculating memory means at a rate so fast that during the transfer time there is an insignificant change in the ECG signal read from said recording medium.

5. A system in accordance with claim 2 wherein said display means includes a CRT, means for converting the samples recirculated in said first and second recirculating memory means, during respective recirculation cycles thereof, to derive a vertical deflection signal for said CRT, means for synchronizing the horizontal sweeps of said CRT to the recirculation rates of said first and second recirculating memory means during respective recirculation cycles thereof, and means for changing the bias of said vertical deflection signal for respective ones of said recirculation cycles so that two separate displays are formed on said CRT.

6. A system in accordance with claim 2 wherein said abnormal heartbeat detecting means is a prematurity detector.

7. A system in accordance with claim 1 wherein the ECG waveform stored in said first temporary storage means is transferred to said first recirculating memory means at a rate so fast that during the transfer time there is an insignificant change in the ECG signal read from said recording medium.

8. A system in accordance with claim 1 wherein the ECG signal segment stored in said second temporary storage means is transferred to said second recirculating memory means at a rate so fast that during the transfer time there is an insignificant change in the ECG signal read from said recording medium.

9. A system in accordance with claim 1 wherein said abnormal heartbeat detecting means is a prematurity detector.