Optical Character Recognition System

Abstract

An optical character recognition system is arranged to process format conditioning documents which designate the locations of data fields on data documents to be read. Those portions of the data documents outside the data fields which are designated by the conditioning document are rendered invisible to the system, thereby permitting the system to process only data which may be located in the midst of other printed matter. A fine line adjustment capability permits the system to reposition the document as necessary to locate a data field which is not located precisely as had been indicated by the format conditioning document. The system is thus automatically adaptable to any data format without requiring specialized programming. The system samples successive vertical slices of data characters being optically scanned and reassembles the slices electronically for purposes of recognition. The position of each slice is analyzed in order to predict the position, relative to the photo-sensitive array, of the next slice. This permits reliable system adaptation to a data line which is fully or partially skewed relative to its document page. Failure to recognize one or more data characters during scan of a line results in successive automatic re-scans of that line with automatic increase of detection sensitivity during each re-scan to permit characters of relatively light print to be recognized.

Description

BACKGROUND OF THE INVENTION

The present invention relates to optical character recognition systems and more particularly to an optical character recognition system which is far less expensive than those available in the prior art and which is adaptable to read a wide variety of data formats without requiring the intercession of a specially trained programmer.

Optical character recognition machines are currently being utilized to read information from original documents directly into data processing and communication systems. Such machines eliminate the need for key-to-tape and key-to-disk equipment for purposes of data entry since the optical character recognition machine itself converts the printed data into language suitable for use by the data processor or computer.

A typical document to be read by optical character recognition machine comprises a form having specific delineated regions in which data is entered, either by a typewriter or by hand print. The lines defining the regions in which data is to be entered on the form, as well as instructions appearing on the form to facilitate use of the form, is not to be read by the machine in most cases. In order to render this material invisible to the optical character recognition of the prior art, it has been necessary to devise special programs which instruct the machine to only scan predetermined fields in which data is known to be located. There are at least two severe disadvantages associated with this specialized programming approach. For one thing, the machine must be specially programmed for each different form because the data format on different forms varies. In other words, in order to assure that the machine reads only data, a special program must be devised each time the data format is changed. This procedure requires a specially trained programmer who must be familiar with both the format to be employed and the particular operation of the processing circuitry within the machine. For another thing, these specialized programs provide relatively little leeway for recognizing data which is not located precisely in the manner expected by the program. This problem is particularly distressing in the case of printed forms in which the blank form has been shifted even a fraction of an inch from the edge of the page relative to that position which is expected by the program. Under such conditions, with the data not in position as expected by the program, the characters cannot be recognized and the document must be rejected by the machine.

In addition to the problems described above, many prior art optical character recognition machines are not capable of recognizing spaces between characters so that data which had been spaced on the source document is bunched together by the machine and rendered difficult to interpret.

Still another problem inherent in many prior art optical character recognition machines relates to their inability to accommodate data lines which are inadvertently skewed relative to the document page. For example, if the source document, when typed, was not oriented properly in the typewriter, a data line may be skewed on the page. Moreover, in the course of typing, or even hand printing, adjacent characters are often vertically mis-positioned relative to the other characters in the line. Under such circumstances the prior art optical character recognition machines have limited or no capability of recognizing the skewed or mis-aligned characters.

It is therefore an object of the present invention to provide an inexpensive optical character recognition machine which is readily adaptable to a variety of data formats without requiring the intercession of a specialized programmer having knowledge of the internal workings of the machine.

It is another object of the present invention to provide an optical character recognition machine which is capable of automatically adjusting the position of a document in the machine in order that inadvertently mis-positioned data can be sought and properly positioned so as to be read by the machine.

It is another object of the present invention to provide an optical character recognition machine which is capable of recognizing individual characters mis-aligned vertically relative to other characters in a line and which is capable of accommodating a significant degree of skew in a line of data being read.

It is still another object of the present invention to provide an optical character recognition which recognizes spaces between characters as such and provides space character codes to maintain proper orientation between data.

It is a general object of the present invention to provide an inexpensive optical character recognition machine having an extremely flexible data format capacity and which is not hampered by the aforementioned disadvantages inherent in prior art optical character recognition machines.

SUMMARY OF THE INVENTION

In accordance with the principals of the present invention an optical character recognition machine is automatically programmed to accept a particular data format by first processing a format conditioning document which instructs the machine as to the locations of data fields on data documents to be read. In this sense the machine is self programming since each run of data is preceded by a conditioning document. Two possible format modes are disclosed. In a vertical format mode the format conditioning document includes only a column of line position marks located on the left hand margin of the document, each mark designating the location of a data line on the data documents to be read. Spacing from line to line may vary and all lines designated by the conditioning document are read on each data document. In the horizontal format mode the conditioning document contains both the vertical format marks in the left hand margin and horizontal field delineators within each line designated by a vertical format mark. A predetermined character designates the beginning of each delineated data field and defines the pitch and font for that field. A second predetermined character designates the location of the end of the data field. Only those locations corresponding to the designated data fields are read on the data documents. Areas between the designated fields are invisible to the machine. Each line may have a different field length, and the number of fields may differ from line to line. With this approach specialized programming by highly skilled personnel is eliminated.

The system includes a line position analysis circuit which monitors the position of each data sample relative to the photo-sensitive detecting array. The position of each sample is utilized to predict the position of the next sample so that a data line which is skewed relative to the data document page can be tracked during successive samples by the recognition circuitry. Moreover, if a character or line is found to be off center in the array relative to the position predicted by the conditioning document, the document position is automatically stepped relative to the optical scanning equipment until the line or character is properly centered in the array.

The system includes an operation mode which requires no attention by an operator. In this mode documents which are not processed because of failure to recognize one or more characters, are placed in a reject stack or bin. At a later time the operator, at his or her convenience, can reprocess these documents and perform any required correction procedure. An automatic re-scan feature is also provided to permit re-scan over any line having an unrecognized character. If all characters are not recognized on the first scan, the document page is adjusted to place the line in the center of the photo-cell array and the line is re-scanned. If any characters are not recognized after re-scan, additional re-scans are automatically made with the detection sensitivity changed upon each re-scan. If after a predetermined number of re-scans, characters are still not recognized, the operator is alerted to make keyboard corrections. In this mode the machine automatically displays the unrecognized character to permit keyboard entry by the operator.

The document transport path is characterized by a common driving cylinder, driven by a step motor, the cylinder being arranged to drive two pairs of transversely spaced capstans from the same driving cylinder surface. By employing the common drive cylinder the possibility of inadvertent skewing of a document by the driving mechanism is significantly minimized.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and still further objects, features and advantages of the present invention will become apparent upon consideration of the following detailed description of specific embodiments thereof, especially when taken in conjunction with the accompanying drawings, wherein:

FIG. 1 is a functional block diagram of the control logic portion of the optical character recognition system of the present invention;

FIG. 2 is a functional block diagram of the recognition circuitry portion of the optical character recognition system of the present invention;

FIG. 3 is a partially diagrammatic front view in plan of the document picker mechanism employed in the present invention;

FIG. 4 is a partially diagrammatic side view in plan of the document elevator mechanism employed in the present invention;

FIG. 5 is a partially diagrammatic front view in plan of the document transport path employed in the present invention;

FIG. 6 is a broken top view in plan of the transport path of FIG. 5;

FIG. 7 is a schematic diagram of the pneumatic controls employed in the present invention;

FIG. 8 is a schematic diagram of the master timing circuit for the system of the present invention;

FIGS. 9 through 13 are schematic diagrams of the circuitry associated with the manual controls of the present invention;

FIGS. 14 and 15 are schematic diagrams of the master program counter and associated control logic employed in the system of the present invention;

FIGS. 16 through 25 are schematic diagrams of the read and format program counters and associated program control logic employed in the system of the present invention;

FIGS. 26 through 33 are schematic diagrams of the scan counter, memory data multiplexer circuitry, and associated control logic employed in the system of the present invention;

FIG. 34 is a schematic diagram of the diagnostic control panel employed in the system of the present invention;

FIG. 35 is a timing diagram illustrating the operating cycles of the system memory unit,

FIGS. 36 through 42 are schematic diagrams of additional control logic associated with the memory data multiplexer circuits employed in the present invention;

FIGS. 43 through 48 are schematic diagrams of the memory address multiplexer and associated control logic employed in the system of the present invention;

FIG. 49 is a timing diagram illustrating the time relationship between various signals generated and employed in the Recognition Circuits of the present invention;

FIGS. 50 through 53 are schematic diagrams of additional control logic associated with the memory address multiplexer of the present invention;

FIGS. 54 through 63 are schematic diagrams of the control circuits associated with the memory unit of the present invention;

FIGS. 64 and 65 are schematic diagrams of the memory unit employed in the system of the present invention;

FIGS. 66 through 72 are schematic diagrams of the line position analysis circuitry employed in the system of the present invention;

FIGS. 73 and 74 are schematic diagrams of the interface logic employed in the system of the present invention;

FIGS. 75 through 79 are schematic diagrams of the interface between a magnetic tape unit and the system of the present invention;

FIGS. 80 through 82 are schematic diagrams of the interface between the system of the present invention and keyboard and printer units;

FIG. 83 is a schematic diagram of a control panel connector board employed in the system of the present invention;

FIG. 84 is a schematic diagram of the document advance counter and associated control logic employed in the system of the present invention;

FIG. 85 is a schematic diagram of the mechanism connector board employed in the system of the present invention;

FIG. 86 is a schematic diagram of the control and indicator panel employed in the system of the present invention;

FIGS. 87a through d are schematic diagrams of the mechanism control panel employed in the system of the present invention;

FIG. 88 is a schematic diagram of the scan mirror motor employed in the system of the present invention;

FIGS. 89 through 92 are schematic diagrams of the quantizer-multiplexer circuits employed in the system of the present invention;

FIG. 93 is a schematic diagram of the 13 columns of shift registers employed in the recognition circuitry of the system of the present invention;

FIG. 94 is a schematic diagram of the details of a single shift register column employed in the circuit of FIG. 93;

FIG. 95 is a schematic diagram of an amplifier employed in shift columns of FIG. 94;

FIG. 96 is a schematic diagram of a decoder and control logic employed in the recognition circuitry of the present invention;

FIG. 97 is a schematic diagram illustrating the inter-relationship between the shift register columns and the individual character recognition masks employed in the system of the present invention;

FIGS. 98 through 103 are schematic diagrams of the best match detector circuits employed in the system of the present invention;

FIGS. 104 through 108 are schematic diagrams of the column counter and window generator circuits employed in the system of the present invention;

FIGS. 109 through 118 are schematic diagrams of the best match store circuits employed in the system of the present invention; and

FIGS. 119 through 124 are schematic diagrams of the data control circuits for the recognition circuitry of the system of the present invention.

DESCRIPTION OF PREFERRED EMBODIMENTS

I. GENERAL

The optical character recognition system described herein is part of the same system described in U.S. Pat. No. 3,812,459 et al. That patent application is concerned with the optical components employed in an optical character recognition system; the present application relates to the document handling mechanism, system control logic, and character recognition circuitry for the same optical character recognition system. Numerous references made herein to the optical components of the system relate to the components in the aforesaid patent which is incorporated herein by reference.

In order to facilitate signal tracing between the numerous schematic diagrams disclosed herein, each component bears a reference numeral in which the first digit or digits correspond to the figure number in which the element or component is found and the last two digits identify that component or element in the figure. An input signal received by an element bears a parenthesized reference numeral designating the element or component from which that signal originated. Likewise an output signal from an element or component bears the reference numeral of the component or element receiving that signal. In this manner signals and logic operations can be traced from schematic to schematic and, more particularly from element to element. The one exception to this approach relates to timing signals TPA, TPB, TPC, TPD, TPE, and TPF which originate in the circuit of FIG. 8 and are utilized throughout the system without bearing source or destination reference designation.

Particular voltage levels are not specified herein unless necessary to an understanding of the system operation. For ease in reference, however, a convention is employed in which logic one constitutes a relatively high or positive voltage whereas logic zero constitutes a relatively negative or ground voltage.

The drawings disclose the entire system for purposes of the present application, and signal tracing from drawing to drawing will provide those of ordinary skill in the art with a complete understanding of all functions capable of performance by the system. To facilitate an understanding of the inventive concepts of the present application, the approach employed herein in describing the system is to describe in detail only those portions of the system which relate to the inventive functions, whereas conventional functions and operations performed by the system are not described in detail. Consequently, while substantially all of the illustrated components bear reference numerals, only those components which relate to the inventive function are described in detail. The description itself is segmented into four major sections: General Operation (in the present section); Mechanism Operation; Control Logic Operation; and Recognition Circuit Operation. These major sections are further subdivided into sub-sections in which thhe various operations are described in detail.

It will be understood by those skilled in the field of optical character recognition systems that the present system approach can be utilized in the recognition of substantially any standardized font or print. For purposes of facilitating the present description, however, only the recognition of OCR-A font is described in detail. The system capacity to recognize other fonts, including Farrington 7B or hand written characters, is referred to in passing to the extent necessary to illustrate the flexibility of the system.

Referring specifically to FIG. 1 of the accompanying drawings, the control logic of the present system is illustrated in functional block diagrammatic form. Before proceeding with the detailed description of the FIG. 1 block diagram, it is beneficial to bear in mind that the control logic, in effect, includes circuitry for performing three distinct programs. These are: (1) the master program, which is primarily responsible for document handling in the mechanism; (2) the load format program, which is performed during specific steps of the master program and which is responsible for setting up the system in response to a format document so that data on documents to be read can be quickly located and processed; and (3) the read program, which is performed during specific master program steps and which is responsible for precessing data recognized by the system and effecting various functions required in response to the non-recognition of data.

The blocks illustrated in FIGS. 1 and 2 include parenthesized designations of the figures in which detailed circuitry for those blocks may be found.

Mechanism block 101 relates to that portion of the system which physically handles and stacks documents to be processed. Operation of this portion of the system, and its interrelation with the rest of the control logic, is best described in terms of a transport test mode which is simply a mode in which documents are transported through the mechanism to test the mechanism operation. When the start switch and transport test switch are actuated at control panel 110, the master program is initiated at the master program counter 103. Under the control of the master program the document feed shoe lowers into the document input hopper toward the top document in the stack. If the top document is below the downward reach of the feed shoe, the input hopper elevator is automatically actuated until the top document contacts the feed shoe. When such contact is made the feel shoe is automatically raised with the top document secured thereto by means of suction. Upon being raised to a predetermined height, the document is delivered forwardly toward the transport path (or document track) entrance. When the feed shoe reaches its maximum forward position a first set of transversely spaced pinch rollors is actuated to couple the document to a step motor having as its primary function the stepping of the document through the read station where it may be scanned by the optical scanning equipment. The document is released by the feed shoe approximately 30 milliseconds after the pinch rollors are activated to assure that the pinch rollors engage the document before feed shoe release. The feed shoe is then returned to its rest position.

Actuation pulses are fed to the document feed step motor to advance the document along the transport path. A document skew test station is located in the transport path prior to the read station. The skew station comprises three photocells arranged in a line transversely to the transport direction. Only two photocells are actuated, depending upon the width of the document being transported. If a wide document is employed, only the inboard and outboard photocell sensors are active; if a narrower document is employed, the inboard and intermediate photocells are active. When one of the active photocells senses the document in the transport path, subsequent steps of the step motor are counted until the second active photocell senses the document. If the count exceeds a predetermined count, for example two, the document is considered skewed relative to the transport path and is to be rejected instead of attempting to read data from that document. If the count between skew sensor actuations is below the predetermined count, there is no skew error and the document is stepped further along the transport path.

Just downstream of the read station along the transport path there is a second set of pinch rollors which is actuable to engage the document to the document advance step motor. A photo-sensor associated with this set of pinch rollors automatically actuates these pinch rollors when a leading edge of the document has reached this point of the transport path. It is this second set of pinch rollors which controls stepping of the document through the read station until the trailing edge of the document has passed through the read station.

The first and second set of pinch rollors engage respective capstans or drive cylinders which are all driven by a common main drive cylinder rotated under the control of the document advance step motor. The use of a common main drive cylinder for the capstans engaged by both sets of pinch rollors assures that all drive points for the document are controlled from a common driving source and thereby minimizes the possibility of document skewing occasioned by the driving source.

Continuing with the description of the test transport mode, the document advance motor continues to step the document along the transport path. When the trailing edge of the document passes the skew test station, the system counts further steps of the step motor until a predetermined number is reached, this number being sufficient to make sure that the trailing edge of the document passes through the read station. When this count is reached an end of document condition is determined and a reject pinch rollor is actuated which engages the document to continuously driven belts which feed the document into an appropriate stacker bin. These functions described above are controlled by the mechanism block 101, mechanism connector board 12, master program counter 103, and document advance control 107 illustrated in FIG. 1.

Lifting of the uppermost document and delivering same to the transport path proceeds in the same manner for the format load and read modes as in the test transport mode. Departure from the procedure in the test transport mode occurs in the other modes once the document leading edge reaches the skew sensor station without detection of a skew error. In the subsequent description, the load format mode is discussed first, followed by the read format mode.

In the load format mode a format conditioning document is processed by the system and indicates where data fields in subsequent documents are to be found. Characters located outside the fields designated by the format conditioning documents are invisible to the system; that is, characters located outside the designated fields are simply not processed or stored by the system. The load format mode may be a vertical format mode in which the format conditioning document simply comprises a vertical column of one or more marks or specified characters, each designating the location of a line in which data is to be found in succeeding documents. In this vertical format mode, the system reads any and all data on an entire line which has been designated by the format conditioning document. Alternatively, the load format mode may be a horizontal format mode wherein the conditioning document contains both vertical format and horizontal field designations. On the horizontal format and horizontal field designations. On the horizontal format conditioning document the column of vertical format markings is present to designate the lines in following documents on which data is to be found. In addition specific characters designating the start and termination of data fields on each data line are provided. Areas between the designated fields on a data line are invisible to the machine. Every line may have a different field specified and the number of fields may differ from line to line.

Assume operation in the vertical format load mode. Once reaching the skew sensor station without having been rejected because of a skew error, the document is stepped one step at a time, with each step being approximately 0.020 inch. After each step the optical scanning equipment scans the line located at the read station. Data, if any, received at photo-diode array 201 (FIG. 2) is quantized into sixty serial bits on the MUXSD line by quantizer and multiplexer 202. These 60 bits represent 60 elements of a vertical slice of a scanned line on a document. That is, as the optical scanning equipment scans across the line at the read station, successive vertical slices, each 60 elements or photo-diodes high, are detected by the recognition circuits (FIG. 2). If the optical equipment views a portion of a character, the one or more photo-diode elements see a black segment which is manifested as a logic one or high level in the corresponding bit of the sixty bit serial data stream supplied by the quantizer multiplexer 202. The absence of a character segment is sensed as a white detected by the particular elements in the photo-diode array, and this white is manifested as a logic zero in the serial data stream. This data stream is applied to the line position analysis circuitry 118 which, in vertical load format, looks for six blacks or logic ones in a row to signify that a format mark has been detected. As the data is fed serially to the line position analysis circuitry 118, this circuitry counts successive zeros (i.e., white spots detected at the array) preceding and immediately following the six or more consecutive black spots signifying a vertical format mark. The purpose of this is to determine when the format mark is centered vertically in the array. If the number of white spots above the format mark is greater than the number of white spots below the format mark, the mark is low in the array and the line position analysis circuits commence to advance the document one more step, after which another analysis is made. This analysis for detecting centering of the mark is continued until the mark is in fact centered. While this is occurring the document advance counter counts the number of steps which the document has been advanced from the top of the document to the centering of the first detected mark. This count in the document advance counter 107 is then connected through the memory data multiplexer 116 to the vertical format portion of the memory module 119 under the control of the memory address multiplexer 117 and the memory control circuits 115. The document is then advanced a predetermined number of steps and line position analysis is repeated until another mark is detected and centered. The number of steps between successive detected vertical format marks is stored in the memory module 119 in similar fashion to permit the system to properly position subsequent documents so that each data line may be scanned. When the trailing edge of the document passes the skew station the system recognizes an end of document condition and a special character signifying this condition is stored in the next vertical format section of memory 119 to indicate that no further lines are to be found on documents being read. The line position analysis circuitry 118 performs numerous other functions during other operating modes, but during load format operation its primary function is mark centering as described above. From the foregoing it will be seen that successive sections of the vertical format portion of memory module 119 contain the locations of successive lines on each document at which data to be read appears.

During vertical load format the document advance counter 107, as mentioned above, keeps track of the spacing between successive lines containing data fields. The document advance counter is a seven bit counter and is therefore capable of registering 128 steps. Since it is possible that two successive lines of data are separated by more than 128 steps, it is necessary to incorporate a flag into the memory along with the count of 128, each time a larger spacing occurs between data lines. This flag signifies to the system, during the read mode, that the document should be advanced 128 steps, after which the next incremental count should be retrieved from memory to control further document stepping. If the following number in the vertical format portion of the memory is zero, the system interprets this as an indication that the end of document has been reached and no further lines of data are present in the document.

When the processing of the vertical format conditioning document is completed, the vertical format conditioning document is rejected from the mechanism and placed in a stack. The next document in the stack can then be read according to the format delineation designated by the conditioning document. Actually, the master program is arranged to automatically proceed to the read program operation upon receiving the next document after the format conditioning document has been processed. During the read program operation the system pulls successive numbers from the vertical format section of the memory, advances the step motor according to these numbers, and reads the data on the appropriate lines of the document.

The memory data multiplexer unit 116 controls the entry of four data sources into memory module 119. One source is the document advance count from document advance counter 107. A second source is the recognition data received from the data control unit 208 in FIG. 2, which data corresponds to the character recognized by the recognition circuits. A third data source is the data entered from the keyboard and printer interface 104. The fourth data source is the horizontal scan position count which is generated within the memory data multiplexer circuitry and therefore does not appear as an input source in FIG. 1. The memory module 119 itself is divided into three portions: one portion receives data coming from the recognition circuits or the keyboard; another portion receives vertical format data; and the third portion receives horizontal data. For each memory address portion there is a different address counter provided. The memory address multiplexer 117 includes a data address counter, a vertical format address counter, and a horizontal format address counter. Depending upon the nature of the write cycle, the memory address multiplexer 117 and memory data multiplexer 116 control entry of information into the proper portion of memory module 119. Actual multiplexing is accomplished at the multiplexer circuits 116 and 117; however control signals for operating the multiplexer circuits originate in the memory controls circuitry 115. The memory controls circuits designate to the memory module 119 and to the multiplexer circuits the nature of the memory cycle (i,e., vertical format entry, horizontal format entry, data entry, etc.) to be performed. In the vertical format load mode, after an address is written into memory, the vertical format address counter is incremented. When the memory cycle is complete the document is advanced six steps and another line position analysis is performed to look for the next vertical format mark. When this mark is centered the document advance counter contents are entered into the memory address designated by the current count in the vertical format address counter. When the end of the document is reached, the document advance counter is reset and an additional memory write cycle is initiated wherein all zeros are entered into the next vertical format location of the memory.

There are 86 memory positions in the vertical format section of memory. As the vertical format load mode proceeds, the system continuously monitors the number of vertical format words wich have been entered into memory. If the number of vertical format entries reaches 86, the system inteprets this as a format error. Theoretically, if the longest document is 14 inches in length, and if six lines per inch is the most dense spacing permissible, only eighty four vertical format marks can possibly be detected. Thus, if 86 marks are detected, a malfunction, such as a double pulsing of the address counter, etc., has occurred and an error is registered.

In the case of the horizontal format load mode, the system looks for vertical format marks and centers such marks in the same manner as is done in the vertical format load mode. However, upon centering each vertical format mark, the line corresponding to that mark is scanned by the optical scanning system for the purpose of detecting beginning and end of field characters. Scanning is effected by energizing the clutch and brake coils of the scan motor, thereby coupling the mirror cam to the motor to permit the mirror to initiate scan. There is an aperture in the cam which controls the beginning of line (BOL) photocells. When the cam is at its home position (i.e., looking at the left hand edge of the paper), the BOL photocell detects a light through the cam aperture. After the clutch and brake are energized, the cam moves approximately 7.degree. to 10.degree. after which the aperture de-energizes the BOL photocell. This 7.degree. to 10.degree. basically defines the left hand margin reference point on the document page. When the BOL photocell is turned off, the horizontal scan position counter in the data multiplexer circuit 116 begins counting timing pulses provided at the rate at which vertical slices or samples of characters are registered at the photo-diode array during a scan. The scan motor is synchronized with the basic system clock so that the BOL photocell may serve as a reference point from which horizontal position of characters can be measured.

During a scan in the horizontal format mode the system awaits recognition by the recognition circuitry of a specific beginning of field character. Upon recognition of such character, the horizontal scan count corresponding to its horizontal scan position is written into the horizontal format portion of the memory. In addition the lower order bits of the recognized character are written into the same portion of the memory. Scanning continues until a second and subsequent characters are detected and recognized, the scan position and low order bits of these characters also being written into the memory. The first character represents the beginning of a horizontal field; the second character represents the end of that field. Subsequent characters represent beginning and end of field markers in alternation, it being possible to place substantially any number of fields in a line. If an odd number of field characters are recognized a format error is indicated, since each field must have a beginning and end of field character. After all of the fields have been registered the document is advanced until the next vertical format mark is detected and centered. Before the system actually begins looking for the next vertical format line, the document is stepped a sufficient number of steps to remove the previous vertical format mark and associated line out of the array. When this is done the document is stepped one step at a time and a line position analysis is performed at each step to look for the vertical format mark. In this manner each line, and the fields on each line, are recognized and their locations stored in the memory to permit the system to look only for these fields when reading a document.

As successive data fields are detected on the horizontal format conditioning document, their addresses are stored successively in the horizontal format portion of memory. The address of the next available section of the horizontal format portion of memory is continually maintained in a separate register so that when the horizontal format conditioning document has been completely processed, this separate register has stored therein the address of the next available section of the horizontal format portion of memory. During the read mode, as the location of each data field is retrieved from memory, the address of that section of the memory from which the data field location is retrieved is compared against the contents of the special register. In this manner the system is able to automatically determine when the last data field has been read from a document.

As mentioned above, when a character representing the beginning of a data field is detected during a scan, the lower order of bits of that character as recognized are stored in the horizontal format portion of memory. Actually there are two low order bits of the recognized character so stored. These two bits are utilized to specify the font to be utilized for characters which will be read in that field. The two bits provide a combination of four different conditions, thereby permitting for different fonts to be specified. Naturally the number of bits can be increased if desired so that the system may be programmed to recognize substantially any number of fonts. In addition, the beginning of field character utilized in the conditioning document is selected in accordance with the font to be used in the field identified by that character. Moreover two bits may be stored at the end of the field count to designate the pitch (characters per inch) of the utilized font; of course the particular beginning of field character employed would be coded to represent pitch. For example, the OCR-A font may be provided at 10 pitch or 8 pitch, so that the stored bits from the recognized character distinguish to the system which pitch is being used in the designated fields. In the vertical format load mode, the control panel format switch identifies which font is to be utilized during a reading mode.

Considering now the read mode for documents which have been preceded by a vertical format conditioning document, each document to be read is picked and delivered to the transport path as described in relation to the test transport mode. The document is stepped through the read station in accordance with the vertical format data stored in the vertical format portion of memory 119. Specifically, the first vertical format information stored in the memory represents the number of steps required to advance the document, from the top of the document, to place the first line to be read at the read station of the transport path. This is done automatically, with the characters being processed in the manner described subsequently in relation to FIG. 2. WHen the line has been completely processed the document is automatically stepped by the number of steps indicated in the next section of the vertical format portion of memory, whereupon the next line to be read on the document is automatically positioned at the read station. The actual operation carrying out this function is as follows. After the line is to be read (or when the leading edge of the document reaches the skew station), the count stored in the next section of the vertical format portion of memory is withdrawn from the memory and placed in the memory output data register in memory address multiplexer 117. The ones complement of that count is preset into the document advance counter 107. The document advance motor is then stepped, with the document advance counter contents being incremented upon each step, until the count in the document advance counter 107 is all ones. At this point the document has been advanced the required number of steps to bring the line to be read to the read station. When this line reaches the read station the clutch and brake for the scan motor are energized to move the cam and mirror to begin scanning. The recognition circuits begin operating, and upon recognizing data, supply data to the memory data multiplexer along with memory write commands.

If a character is not recognized the system generates a character substitution code, which as described herein is the code for an underline. The underline code and the read error flag are placed in the data memory position corresponding to the character location at which the unrecognized character was found. The system automatically places the horizontal scan count, corresponding to the location of the unrecognized character, immediately adjacent the error flag in the data memory.

The recognition circuits continue to recognize or not recognize characters as the line is scanned. In the system as described, there are eighty four positions for recognized characters in each line; theoretically there should be only eighty characters on an eight inch line at the maximum pitch. When the scanning mirror reaches the right hand margin of the paper the read enable mode terminates. If at this time fewer than 84 write commands have been received from the recognition circuitry, the memory controls unit 115 automatically generates memory fill characters which are stored in memory to fill the 84 positions on the memory line.

After the line has been read and the memory fill cycle has been completed, the system determines if a read error flag flip-flop has been set during the scanning of the line, indicating that an unrecognized character was found during the previous scan. If the flip-flop is not set, indicating that a line has been completely recognized, that line is automatically transferred out of the memory module to the output device (printer, tape, eyc.). While data is being transferred to the output device the control logic automatically steps the document to the next line according to the vertical format information stored in memory. Depending on the speed of the output device the scanning mirror may be back at the left hand margin of the document before the output data of the previous line has been completely transferred to the output device, in which case the system waits until the output data has been completely transferred.

If one character or more has not been recognized in a scanned line, a complete re-scan of that line is performed. If all of the characters in the line are recognized during the re-scan, operation proceeds as described above with the line of data transferred to the output device. If a character is still not recognized after the re-scan, the threshold level of the output amplifiers from the photo-diode array is adjusted to render these amplifiers more sensitive. A second re-scan is then performed and if all characters are recognized the data is transferred to the output device as with a normally recognized line. If again there is an unrecognized character in the re-scan line, the threshold level of the array amplifiers is changed again. This adjustment of the threshold level of the array amplifiers permits lightly printed characters to be more readily recognized. Specifically, gray spots on the document would tend to be recognized more as black rather than white as the threshold of the amplifiers is increased. In the system as described as many as four re-scans at adjusted threshold levels of the amplifiers may be effected. Importantly, in those re-scans in which the threshold level is adjusted, the recognized data from previous scans is not disturbed; rather, the stored unrecognized character flags are sought and their scan location determined. When the scan mirror is placed at the scan location of the unrecognized character, a read enable condition is initiated. Importantly however the read enable relates only to those characters which have not been recognized previously. If all of the characters are recognized after four or fewer re-scans the system proceeds as previously described.

If there is still at least one character that is not recognized after four re-scans at adjusted levels of the array amplifiers, there are three possible alternatives which can be pre-selected by the system operator. One alternative is the reject mode which causes the document to be automatically rejected if there is any character not recognized after a fourth re-scan. A second alternative is the error substitution mode wherein the data for the line is automatically transferred to the output device with an underline code replacing any unrecognized character. The third alternative is the error correction mode wherein the scanning apparatus automatically returns to the unrecognized character which is then projected onto a viewing screen for display to the operator. A cursor mark points to the unrecognized character on the screen. The operator can then enter directly into the system from keyboard 111 the character which has been unrecognized by the system. This data passes through data multiplexer 116 into the memory at the proper character location selected by the memory address multiplexer 117. The error flag for that character is then automatically deactivated and the system continues processing. If more than one unrecognized character is present in a line, this process is repeated to permit keyboard entry of each of the unrecognized characters. Once the last character in the line has been corrected the system automatically searches through the memory to make sure that all characters have been recognized and data is transferred to the output device.

The line position analysis circuitry 118 also comes into play during read mode operation. Specifically, this circuitry is continuously determining whether or not a line is high or low in the array and approximately how high or low it is. If a line is determined to be high or low, the document is stepped forward or backward to try to bring that line as close to being centered in the array as possible. In addition the line position analysis circuitry 118 utilizes the position in the array of a detected character slice to predict the position in the array of the next character slice.

Operation in the read mode, after a horizontal format conditioning document has been processed, is similar to processing after a vertical format conditioning document has been processed insofar as positioning the document relative to the read station is concerned. Once the first line to be read is positioned at the read station, the first scan count stored in the horizontal portion of memory is retrieved under the control of the memory address multiplexer 117. The count is stored in the horizontal format field position register in the memory data multiplexer 116. The scan mirror is then positioned in accordance with the retrieved count, after which the next stored horizontal scan count is retrieved and placed in the same register. This second retrieved scan count corresponds to the end of the field to be read. A read enable cycle is initiated and continues until the scan count corresponding to the actual mirror position is the same as the stored scan count corresponding to the end of the data field. When the read enable cycle is terminated, the next stored scan count, corresponding to the beginning of the next data field, is retrieved and stored in the register and the scanning mirror is positioned accordingly. This positioning of the scan mirror in accordance with the stored scan counts continues until all data fields in the line have been read. In the meantime the recognition circuits supply recognition data and initiate memory write cycles to store the data being recognized. As each field is stored, the data control unit 208 in the recognition circuitry generates an end of field character, which in the system as described is the tab character. This end of field character is placed in memory to serve as a field separator so that successive data fields can be automatically spaced at the output device.

Referring specifically to FIG. 2 of the accompanying drawings, the recognition circuitry of the optical character recognition system are illlustrated in functional block form. The basic timing for the recognition circuits is illustrated in the timing diagram of FIG. 49. The basic timing for the recognition circuits is controlled by the multiplexer counter located in the quantizer and multiplexer 202. The multiplexer counter defines one timing interval, designated herein as MUX interval, for each six successive master timing pulses. There are 64 MUX intervals for each recognition circuit cycle. During one MUX interval in each 64 interval cycle the 60 channels of data detected by photo-diode array 201 is sampled and stored in parallel in a register in quantizer and multiplexer unit 202. This data is then transferred in parallel to a shift register from which it is shifted out serially during the remaining 63 MUX intervals (i.e., one shift per interval) to 13 columns of shift registers in unit 203. The 13 columns of shift registers effectively serve to reconstitute the samples or vertical slices of data characters to permit recognition of these characters by mask circuitry at unit 204. The mask circuitry comprises weighted signal lines connected to the various shift register stages to provide 64 different output signals, each representing a different character mask. If the character in the thirteen shift register columns corresponds to a character for a particular mask, the output signal from that mask has a higher amplitude output signal than any other mask output signal. The determination of the highest level mask output signal is made in the best match detector 206 which in turn provides a seven bit ASCII code output signal representing the recognized character. In addition the best match detector examines the amplitude level of the highest mask output signal and provides a four bit number representative of that amplitude. At the best match store unit 207, the four bit correlation function representing the amplitude of the highest level mask output signal is quantized into sixteen levels. If the function is at the highest or next highest level, the best match store unit considers recognition to have been successful and the seven bit character code is transferred through the data control unit 208, along with the OCRW memory write command, to the control circuitry for storage in memory module 119. If the correlation function falls within the third, fourth or fifth highest possible levels, recognition is not automatic; instead, the mask output signal must coincide in time with a character window generated at the column counter and character window generator 205. The character window is synchronized to the character spacing for the particular format being read and therefore serves to identify those times when a character should be present for recognition. If no character at all is detected within the window interval, data control unit 208 generates a space character for storage in memory unit 119. If the four bit correlation function is at the third, fourth or fifth highest level and there is no time coincidence with the window interval, a non-recognition condition exists and is so indicated by setting the read error flip-flop at data control unit 208 which in turn provides the read error flag (RERF) signal. If the correlation function is at the sixth or seventh highest level, and this level is maintained at the end of the window interval, a match is detected and the character is stored in memory.

If the correlation function for the character in the mask is below the seventh highest level, but a character is in fact in the mask, a read error condition is signified by setting the read error flip-flop in data control unit 208. As described in relation to the control circuits in FIG. 1, if the read error flip-flop is set during a scan, the line is re-scanned automatically one or more times.

The individual circuits representing the blocks in FIG. 2 are described in greater detail hereinbelow at which time other functions for these circuits are further described.

II. MECHANISM

The mechanism portion of the present invention serves the following functions: automatically raising and lowering a stack of documents to place the uppermost document of the stack in position to be picked and transported to be read; automatically picking the uppermost document from the stack and delivering it to a transport path; and automatically transporting a document along the path so that it may be read and later delivered to a suitable storage location. The drawings relating to these functions are FIGS. 3, 4 and 5.

II(A). DOCUMENT PICKER

Referring specifically to FIG. 3 of the accompanying drawings, there is illustrated the essential features of the picker mechanism of the present invention. A stack 301 of individual documents is placed on a vertically adjustable elevator platform 302. The picker mechanism, generally designated by the numeral 300, is located above the document stack and is arranged to deliver the uppermost sheet of the stack to a document transport path 303. The picker mechanism includes a feed shoe 304 supported at one end of a horizontally extending hollow support rod 305. Air passages 306 are defined internally of feed shoe 304 and communicate with the interior of hollow rod 305. A plurality of longitudinally extending openings 307 are defined in the lower surface of feed shoe 304 and communicate with internal passages 306. The end of rod 305 remote from feed shoe 304 is selectively connected to a negative pressure or vacuum source which draws air in through openings 307 and passage 306 and creates a negative pressure at the lower surface of feed shoe 304.

An air motor 308 is arranged to selectively translate a horizontally extending push rod 309 along its longitudinal axis. A control arm 310 is coupled at 311 to the remote end of push rod 309. Control arm 310 depends vertically from coupling 311, the latter being a pivotal coupling which permits relative rotation between control arm 310 and push rod 309. Pivotal coupling 311 is not fixed to the mechanism frame so that it is free to translate horizontally as push rod 309 is driven by air motor 308.

The lower end of control arm 310 is pivotally engaged to one end of a crank arm 312. The other end of crank arm 312 is pivotally secured to rod 305. Control arm 310 extends somewhat below rod 305 so that control arm 310 and crank arm 312 join at a location below rod 305. Control arm 310 is pivotally secured to the mechanism frame at a location 313 intermediate its remote end. This pivotal engagement 313 permits horizontal translation of push rod 309 to be reflected as oppositely directed horizontal translation of rod 305. Specifically, if air motor 308 translates push rod 309 to the left as viewed in FIG. 3, control arm 310 is rotated counterclockwise about pivot point 313. The lower end of control rod 310 is thus driven to the right and pulls on crank arm 312 which in turn translates rod 305 to the right.

A horizontally extending support arm 314 is pivotally secured proximate one of its ends to a portion of the mechanism frame lying between pivot point 313 and pivotal engagement 311. The pivotal engagement between the frame and support arm 314 is designated by the numeral 315. At the opposite end of support arm 314 there is provided a pin 316 which extends horizontally in a direction perpendicular to support 314. Pin 316 engages a slot 317 defined through the upper end of a vertically disposed lift arm 318. The lower end of the lift arm is pivotally secured at 319 to rod 305 at a location intermediate the two ends of that rod. The intermediate portion of support arm 314 is secured to the armature of a picker solenoid 320. Solenoid 320 is arranged so that its armature may be selectively reciprocated vertically. When armature 321 is driven upward, support arm 314 is pivoted counterclockwise (as viewed in FIG. 3) about pivot 315 on control arm 310. Pin 316 thereby raises lift arm 318 by means of the engagement with slot 317 and causes feed shoe 304 to pivot upwardly about the remote end of rod 305. When armature 321 is pulled downward, pin 316 is lowered and permits lift arm 318 to drop. This lowering of lift arm 318 results in a lowering of feed shoe 304 as rod 305 pivots clockwise about its remote end.

Pin 316 on horizontal support arm 314 is also arranged to close a microswitch 322 when armature 321 of picker solenoid 320 is in its extended position. Closure of this switch thus indicates that picker shoe 304 is raised. Another pin 323 extends perpendicularly from push rod 309 and is arranged to close a microswitch 324 when push rod 309 is retracted by air motor 308. Lift arm 318 carries a switch-closing member 325 which is arranged to close a microswitch 326 when rod 305 is driven to its extreme right-most position as viewed in FIG. 3; this position corresponds to a feed complete position for feed shoe 304, in which position a document has been delivered to transport path 303.

Lift arm 318 is sufficiently long to restrict the delivery stroke for feed shoe 304 to a straight line, parallel to path 303, thereby assuring proper entry of a picked document onto the transport path 303. As illustrated in FIG. 3, the transport surface of delivery path 303 slopes slightly upwardly from the entry edge in a downstream direction. The forward edge of the lower surface of feed shoe 304 is correspondingly sloped (i.e., the height of the feed shoe decreases in a forward direction) so as to promote smooth entry of a document onto the transport path 303 between the two sloped surfaces. Specifically, the sloping portion of feed shoe 304 and the entrance of transport path 303 are contoured such that a document delivered by the feed shoe contacts the delivery path downstream of the sloping portion whereupon it is grabbed by drive rollers as described subsequently in relation to FIG. 5. A plurality of vacuum ports or apertures 330 are defined through the transport surface of transport path 303 slightly upstream of an apex 331 which defines the break between the sloped and flat portions of the transport path.

Apertures 330 are connected to a source of negative pressure or vacuum and serve to detect the presence of two documents inadvertently being delivered to the transport path by the feed shoe. More particularly, if the feed shoe delivers only a single document to the transport path, that document is delivered downstream of the location of ports 330. A second document however contacts the sloping portion of the transport path and blocks air flow being suctioned into ports 330. Its blockage is sensed in a manner described subbsequently and results in stopping of the document feed process.

Portions of the sloping leading edge of the transport path, at locations upstream of ports 330, are recessed to define flow channels 332. These flow channels communicate with a source of positive pressure, causing air to flow toward the storage bin 301. This air serves to riffle the documents being lifted by shoe 304 during delivery of a document to the transport path and thereby aids in separating two or more documents which have inadvertently been lifted by the feed shoe. In this regard it is to be noted that feed shoe 304 actually makes contact with the uppermost document in the stack at a level substantially below the leading edge of transport path 303 so that the riffle air delivered from flow path 332 does not interfere with the suction required at openings 307 to lift the uppermost document. Additional riffle air flows can be employed in relation to document stack 301 to facilitate separation of individual documents and alignment of documents relative to the stack and the transport path 303.

For purposes of understanding the operation of the mechanism illustrated in FIG. 3, it is necessary to point out that feed shoe 304 is illustrated in approximately a half stroke position such as it would assume in the midst of delivering a picked document to transport path 303. When the mechanism is at rest, feed shoe 304 is displaced substantially to the left of the position illustrated in FIG. 3. When at rest, push rod 309 is retracted, drawing pivot point 311 to the right and causing the lower end of control arm 310 to be displaced to the left. The forward or right-most end of feed shoe 304 in this position is free to drop into the bin containing document stack 301.

Assuming for the moment that the uppermost sheet in stack 301 is at a high enough level to permit it to be picked by feed shoe 304, a typical operation of the mechanism of FIG. 3 will be described. First the normally extended armature 321 of picker solenoid 320 is retracted, permitting lift arm 318 to fall and cause rod 305 to pivot clockwise about its left end until the lower surface of feed shoe 304 contacts the uppermost document in stack 301. Assuming the vacuum source to be in operation, suction at openings 307 in the lower surface of feed shoe 304 causes the uppermost sheet in stack 301 to attach to the lower surface of the feed shoe. An interlock, to be described subsequently, indicates that a document has blocked openings 307 and causes picker solenoid 320 to extend armature 321. When the armature is thus extended control arm 318 is raised to in turn raise feed shoe 304 to a height slightly above the entry point to transport path 303. Air motor 308 is then operated to extend push rod 309 and thereby pivot control arm 310 about pivot point 315. Control arm 310 thus drives rod 305 to the right so that feed shoe 304, with a document attached, is translated over transport path 303. At the end of the feed stroke, switch-actuation member 325 operates microswitch 326, resulting in the disengagement of the document from feed shoe 304 so that it may be driven along the transport path in a manner to be subsequently described. Push rod 309 is then retracted and feed shoe 304 is returned to its ready position above document stack 301.

The various interlocks and controls operated in response to actuation of switches 322, 324 and 326 are described subsequently; the present description is concerned only with the operation of the mechanism per se.

Since for practical reasons the vertical motion of feed shoe 304 must be limited, it is necessary to raise and lower elevator platform 302 to assure that the uppermost document in stack 301 can be engaged by the feed shoe. In order to determine when it is necessary to raise platform 302, there is provided a flange 327 extending from feed shoe 304 and arranged to block an air-pressurized sensing port 328 when feed shoe 304 is in its lowermost position. The back pressure resulting upstream of port 328 is used, as described subsequently, to provide a control signal for operating an elevator mechanism which raises and lowers the platform 302.

II(B). ELEVATOR MECHANISM

The elevator mechanism for raising and lowering platform 302 is illustrated diagrammatically in FIG. 4 of the accompanying drawings and is generally designated by the reference numeral 400. Platform 302 is supported horizontally by a vertically extending lift member 401 which is adapted to slide vertically along support member 402 under the control of a pair of rolling bellows type air cylinders 403. Only one such air cylinder 403 is illustrated in FIG. 4; the other air cylinder is located on the opposite side of the elevator unit, into the plane of the drawing, so that raising and lowering forces can be applied simultaneously and equally on both sides. The description of mechanism 400 which follows relates to only that side of the mechanism which is visible in FIG. 4; it being understood that corresponding parts are provided on the opposite side (into the plane of the drawing) to simultaneously effect identical purposes.

Air cylinder 403 includes a push rod 404 which is secured at its end to an intermediate location along pivot arm 406. One end of pivot arm 406 is pivotally secured to vertical support 402 and is constrained from vertical movement. The opposite end of pivot arm 406 is pivotally secured to a control arm 407 which has one end pivotally secured to lift member 401 and its other end pivotally secured to a pivot plate 408. Pivot plate 408 extends into the plane of the drawing to the other side of the elevator mechanism; plate 408 also extends in height to a fixed support member 409 where it is a pivotally secured and constrained from either horizontal or vertical motion.

A second lever arm 410 is pivotally secured to support member 402 at one end and to a second control arm 411 at its other end. Lever arm 410 is substantially identical to lever arm 406 except that it is not driven by an air cylinder and is located above lever arm 406. Control arm 411 is pivotally secured at one end to lift member 401 at a location substantially above that at which control arm 407 is pivotally secured. The other end of control arm 411 is pivotally secured to the top end of a further plate 412, the other end of which is pivotally secured to support member 409.

The double watts linkage mechanism 400 provides a mechanical advantage which magnifies the displacement of push rod 404 to provide a greater vertical displacement of lift member 401 and platform 302. Specifically, as armature 404 is extended, lever arm 406 tends to rotate in a counterclockwise direction about its end fixed to support 402. The resulting upward force exerted on control arm 407 tends to pivot that control arm in a clockwise direction about its end secured to pivot plate 408. The end of control arm secured to lift member 401 tends to raise the lift member and platform 302. Pivot plate 408 swings outwardly (i.e., counterclockwise) about its point of attachment to support member 409 as lift member 401 is raised. A similar operation ensues for lever arm 410, control arm 411 and pivot plate 412. Specifically, as lift member 401 is raised by control arm 407, control arm 411 tends to pivot in a clockwise direction about its point of securement to pivot plate 412. The pivoting action of control arm 411 however is constrained by a lever arm 410 to follow a similar pivot path to that followed by control arm 407. Pivot plate 412, in accommodating the pivoting action of control arm 411, tends to swing outwardly (i.e., clockwise) about its point of attachment to support member 409.

Lowering of the elevator mechanism proceeds in an inverse manner upon retraction of push rod 404 by air cylinder 403. Specifically, as push rod 404 is retracted, lever arm 406 tends to rotate in a clockwise direction about its end fixed to support member 402. A resultant downward force is exerted on control arm 407 which pulls lift member 401 downwardly and imparts a slight counterclockwise rotation to control arm 407. In accommodating the downward movement of the lift member, pivot plate 408 swings inwardly (i.e., counterclockwise) about its point of attachment to support member 409. The lowering of lift member 401 tends to rotate control arm 411 about its end secured to pivot plate 412, the pivoting fo control arm 411 being constrained by lever arm 410. Pivot plate 412 swings inwardly to accommodate the motion of control arm 411.

The double watts linkage arrangement for elevator mechanism 400 is a low friction device which utilizes low tolerance parts. Amplification factors depend on locations of pivot points but typically are on the order of 4 to 1.

II(C). DOCUMENT TRANSPORT PATH

The transport path 303 referred to in relation to FIG. 3 is illustrated in detail in FIGS. 5 and 6 of the accompanying drawings. The purpose of the transport path is to properly position a document in order that successive lines of text may be scanned and read, and then to eject the document into either of two storage bins. The transport path is essentially flat throughout most of its length; however, the document entrance section slopes upwardly toward the downstream end of the track until reaching apex 331. As described previously, feed shoe 304 functions to deliver a document to the transport path such that the document first contacts the transport path in the region of the apex 331 and downstream of double document sensing ports 330. To continue the transporting motion of the document along the transport path from the point of delivery by the feed shoe, a pair of transversely spaced capstans or drive rollers 501 is provided. These drive rollers are positioned such that their peripheries are oriented substantially tangentially to the plane of the transport path at a location substantially at apex 331. Both the drive rollers 501 are frictionally driven by the same cylinder 503 which is driven by step motor 500 to advance the document in small increments on the order of 0.02 inches per step. Cylinder 503 has a constant diameter throughout its length (i.e., - into the plane of the drawing in FIG. 5) so that both drive wheels 501 are driven at the same speed. The use of a common drive for both transversely spaced drive wheels 501 significantly minimizes the possibility of a document becoming skewed while being transported along the transport path. A second set of drive wheels 504 are transversely spaced in a manner identical to drive wheels 501 and communicate tangentially with the transport path surface at a location somewhat downstream of drive wheels 501. Drive wheels 504 are also both driven by master drive cylinder 503 so that all drive wheels 501 and 504 are driven at the same speed.

Drive wheels 501 can only drive a document along the transport path when respective pinch rollers 505 are positioned in peripheral engagement with the drive wheels. Pinch rollers 505 are selectively translatable into engagement and out of engagement with drive wheels 501 under the control of solenoid 506. Likewise, pinch rollers 507, under the control of solenoid 508, are positionable to render drive wheels 504 capable of imparting forward motion to a document along the transport path.

Three pairs of drive wheels 509, 510 and 511 are successively spaced longitudinally along the transport path. These drive wheels are rendered operative by respective pinch roller pairs 512, 513 and 514, respectively, which are in turn controlled by respective solenoids 515, 516 and 517. The function of drive wheel pairs 509, 510 and 511 is to rapidly eject a document from the transport path after the document has been scanned and read by the system. To this end, drive wheels 509, 510 and 511 are driven relatively rapidly at the same speed by means of a common motor 518.

A location along the transport path between drive wheels 501 and 504 is designated as the read station 520. A line of text material appearing at this location is scanned by the optical equipment and processed by the recognition circuitry. Scanning is in a direction into the plane of the drawing of FIG. 5.

Slightly downstream of drive wheels 501 there are located three transversely spaced skew detector stations. Each skew detector station includes an assembly 521 in which is located a light-emitting diode and a photocell. Light emitted by each light-emitting diode (LED) is directed downwardly toward a respective prism 522 located in a plane of the transport path. The transversely spaced prisms 522 serve to reflect light from the light-emitting diode back toward the photocell in assembly 521 unless the light path between assembly 521 and its corresponding prism 522 is blocked by a document in the transport path.

Depending on the width of a document being read, two of the three light-operated skew detectors are rendered operative. Although the logic involved in the actual skew detection is described in greater detail in relation to the control logic portion of the systems, it should be mentioned here that the philosophy behind the skew detection is based on the fact that a straight or unskewed document should block all of the operative skew detectors simultaneously. If only one of the skew detectors is blocked it is an indication that the document is skewed in the transport path and the transport procedure is automatically stopped. As a practical matter the system permits step motor 500 to step once between blocking of first one and then another of the skew detectors; however if two steps of motor 500 occur between blocking of one skew detector and another, transport is automatically stopped.

The skew detector thus serves to prevent jam-ups which might otherwise occur if a skewed document were transported along the transport path. Of course skewing of a document is significantly minimized, as described below, by virtue of the fact that drive rollers 501 are driven at precisely the same speed so that no net turning moment is applied to the document during transport.

The system is arranged so that drive rollers 501 never drive a document at the same time as drive rollers 504. To this purpose solenoid 506 is actuated (to thereby engage drive wheels 501 and pinch rollers 505) when the document is delivered to the transport path by the feed shoe 304 of FIG. 3; solenoid 508 remains unactuated at this time. The document is stepped by drive wheels 501 through the read station 520 and upon reaching drive wheel 504 actuates a second feed capstan sensor comprising assembly 523 and prism 524. Assembly 523 is similar to assemblies 521 in that it contains a light-emitting diode and a photocell; prism 524 is similar to prisms 522 in that it is located in the transport path plane in alignment with the assembly 523. When the document blocks the second feed drive sensor (as is more clearly described in relation to the electronics portion of the system), solenoid 508 is deactuated resulting in disengagement of pinch rollers 505 from drive wheels 501 and a termination of the driving capability of drive wheels 501. After a short delay, on the order of 30 ms, solenoid 508 is actuated to bring pinch rollers 507 into engagement with drive rollers 504 so that stepping of the document is continued under the control of the drive rollers 504.

A further optical sensing unit is located in the transport path proximate the first ejection drive wheels 509. This sensor includes assembly 525 and the prism 526 and provides an indication to the system that the document has entered the ejection region of the transport path. This indication is stored in the system to acknowledge the fact that the document can be rapidly ejected from the transport path when necessary by actuating solenoids 515, 516 and 517. Such ejection normally takes place when reading of the document has been completed; however ejection of the document may also be effected under other conditions.

After being ejected from the transport path the document may be automatically delivered to either a normal stacker bin 530 or a reject stacker bin 531. The entrance to the stacker bin section is monitored by a stacker entry detector comprising assembly 527 (LED and photocell) and prism 528. The stacker entry detector functions to turn off the transport mechanism in the event of a document jam in the process of document entry into one of the stacker bins. Specifically, the time during which a transported document blocks the stacker entry detector is monitored in the electronics portion of the system. If this time exceeds a predetermined time interval, a document jam is assumed and document transport is terminated. Likewise a photo-sensitive jam detector (including LED and photocell assembly 534 and prism 531) is located at the entry to normal stacker bin 530 to monitor the time required for a document to enter the normal stacker bin; and a detector (including LED and photocell assembly 536 and prism 537) is located at the entrance of the reject stacker bin 531 to monitor the time required for document to enter the reject bin. If the time required for a document to completely enter either bin exceeds a predetermined time, transport is terminated since a jam is assumed.

A document upon being ejected by drive wheels 509, 510 and 511, is driven into the stacker region by first stacker drive wheel 532. Drive wheel 532 is also driven by motor 518. Downstream of the stacker region entry detector (assembly 527) and prism 528) there is located a pivotable bifurcated document steering member 538, which, during normal ejection, is positioned in radially spaced relation from drive wheel 532 so as to guide a document driven by drive wheel 532 into the normal stacker bin 530. Member 538 is pivotably controlled by solenoid 539. When the latter is actuated, steering member 538 is pivoted counterclockwise (as viewed in FIG. 5) so that the upstream end of bifurcated steering member 538 pivots into suitably provided recesses in the periphery of drive wheel 532 (as indicated in dashed lines in FIG. 5). In this position steering member 538 blocks entry of the document into the normal stacker bin 530 and instead steers the document further along the transport path towards drive wheel 533 which directs the document into the reject stacker bin 531. Control of solenoid 538 is determined by the document reject logic described herein in relation to the electronics portion of the system.

II(D). PNEUMATIC CONTROL SYSTEM

The pneumatic controls employed in the system are illustrated schematically in FIG. 7 of the accompanying drawings. A source of pressurized air (P+) is applied to a pressure regulator 701 from which it is delivered to the various controls. One flow path includes a valve 702 which is opened and closed by the solenoid (to be described subsequently) which is actuated when it is desired to operate air cylinder 308 to initiate a feed stroke for feed shoe 304. Specifically, when a feed stroke is to be initiated, valve 702 is opened and pressurized air flows through flow restriction 703 to actuate air cylinder 308.

Another path for the outflow from regulator 701 includes a pressure isolating flow restrictor 704 connected in series with a check valve 705 and an actuable valve 706. Outflow from the actuable valve 706 is divided into two flow paths which supply respective air cylinders 403 to actuate the elevator mechanism illustrated in FIG. 4. A pressure tap is connected between flow restrictors 704 and check valve 705 to supply air under pressure to orifice 328 which as described in relation to FIG. 3, is employed as part of a height sensing arrangement for feed shoe 304. Specifically, flange arm 327 secured to the feed shoe is lowered with the feed shoe and blocks outflow from orifice 328 when the shoe has reached its lower limit position. When orifice 328 is unblocked, a portion of the air flow through restrictor 704 is bled off via orifice 328. This creates a relatively low pressure at the upstream side of check valve 705, which pressure is insufficient to actuate air cylinders 403. In this condition, therefore, the air cylinders 403 remain unactuated and the elevator mechanism of FIG. 4 remains stationary. When orifice 328 is blocked by flange member 327, the pressure upstream of check valve 705 is increased sufficiently to provide a significant air flow to air cylinders 403 and the elevator mechanism is raised. Valve 706 acts to selectively inhibit elevator operation under the control of circuitry to be described subsequently.

From the foregoing description it is seen that lowering of the feed shoe 304 into the document bin continues until such time as the feed shoe encounters the uppermost sheet of the stack, or flange 327 blocks bleed flow through orifice 328, whichever, occurs first. If the uppermost document in the stack is encountered before orifice 328 is blocked, the elevator mechanism remains stationary. The uppermost document is picked and delivered to the transport path in the manner to be described subsequently. If on the other hand the bleed orifice 328 is blocked by flange member 327 before feed shoe 304 encounters the uppermost sheet in the stack, air cylinders 403 are actuated to raise the elevator until such time as the documents in the stack raise the feed shoe sufficiently to unblock orifice 328. At this time the feed shoe is in contact with the uppermost document in the stack and this document is picked and delivered to the transport path.

Still another parallel path for outflow from pressure regulator 701 terminates in a nozzle 707 located in a vacuum chamber 708. Specifically, nozzle 707 is directed to to issue air flow into the funnel-like upstream end of a venturi tube 709. The region surrounding nozzle 707 and the entrance to venturi tube 709 is enclosed to define vacuum chamber 708. The relatively high velocity air issued from nozzle 707 aspirates air from vacuum chamber 708 to provide a relatively low pressure condition therein. The downstream end of venturi 709 is connected to supply riffle air to riffle channel 332 located at the entrance to the transport path.

Vacuum chamber 708 serves as the vacuum of low pressure source for the system. A flow passage 710 supplies flow to chamber 708 from either of flow passages 711 or 712, depending on the position of valve 713. When valve 713 is in the position illustrated in FIG. 7, suction is applied to channel 307 in the feed shoe 304 via tube 305 to permit the feed shoe to lift the uppermost document from the stack. A vacuum-actuated switch 8724 is actuated when suction applied to the feed shoe is blocked by a picked document. This switch actuation enables the feed shoe to be raised so that the document may be fed to the transport path.

Valve 713, which is solenoid-controlled in the manner to be described in relation to the system electronics, may also be positioned to bring flow passage 712 into flow communication with vacuum chamber 708. Under such circumstances suction is applied to document level detectors in each of the normal and reject stacker bins 530 and 531 via respective flow restrictors 714 and 715; in addition suction is applied via flow restrictor 716 to the double document sensing port 330 located proximate the entry portion of the transport path.

A vacum switch is associated with double document sensing port 330. This vacuum operates when suction is applied to sensing port 330 and the latter is blocked. Acuation of the vacuum switch is reflected in the electronics of the system to stop the feed process. Likewise, vacuum switches are associated with each of the stacker bin and document level detectors so that a full stacker bin results in stopping the v system and prevention of jamming.

III. SYSTEM ELECTRONICS

To facililtate understanding, the description of the electronics portion of the system is subdivided into two major sections: the Control Logic Circuitry and the Character Recognition Circuitry. The Control Logic Circuitry relates to system timing, storage and utilization of recognized characters. The Character Recognition Circuitry, as the name implies, receives data resulting from the optical scanning of a document, recognizes such data, and provide electronic signals representative of the recognized data for use by the Control Logic Circuitry. In the following description the Control Logic Circuitry is described first, followed by the Character Recognition Circuitry. For ease in understanding, the following description is not structural such that each section refers to one specific drawing figure; rather, the description is structured in relation to different system functions such that each section of the description involves a number of different drawing figures.

III(A). CONTROL LOGIC CIRCUITRY

III(A.1). TIMING CIRCUITRY

A timing circuit, which generates all timing pulses for the system, is illustrated schematically in FIG. 8 of the accompanying drawings. The primary timing source is a crystal-controlled oscillator 801 which provides a series of pulses at a frequency of 5.898 MHz. The train of master timing pulses is applied to an eight bit counter 802 which is wired to a preset logic circuit 803 so as to provide output pulses at a frequency of 159 KHz with a pulse width of 2.04 .mu.s. Specifically, counter 802 is preset to a count of 104 and counts to a count of 140 before being preset. This results in a divide-by-37 operation with the last stage of the counter remaining high or binary one between the counts 128 and 140. This signal is applied to gate 7801 in the magnetic tape interface unit of FIG. 78.

The pulses from oscillator 801 are also applied to flip-flop 804, acting as a divide-by-2 circuit, which applies pulses at a 2.949 MHz frequency to flip flop 805. During normal operation flip flop 805 is maintained in the clear condition by the output signal from the inverter 806 so that output pulses appear at the Q output terminal of flip flop 805 at the same frequency as the input pulses applied to flip flop 805. Inverter 806 receives the HALF SPEED signal from flip-flop 2531, 2532 during the Error Halt mode. That is, the half speed operation is initiated during a manual entry of characters which have not been recognized automatically by the system. At such time the output signal of inverter 806 removes the clear signal from flip flop 805 which then acts as a divide by 2 circuit. Under these conditions the Q output signal from flip flop 805 is a train of pulses at a frequency of 1.475 MHz.

The Q output signal from flip flop 804 and the Q signal from flip flop 805 are applied to NAND gate 807. During normal operation the CLOCK output pulses from NAND gate 807 appear at a frequency of 2.949 MHz. During half speed operation the output pulse frequency is 1.475 MHz.

Flip flops 808, 809 and 810, and AND gates 811, 812 and 813 are interconnected to provide a divide-by-6 counter circuit. The counter circuit is preset to start its count at 2 and continues until count 7 before auatomatically presetting, thereby skipping counts zero and 1. This counter circuit operates on the pulses provided by NAND gate 807 and provides pulses which are utilized by a decoder circuit which includes NAND gates 814, 815, 816, 817, 818 and 819. These six NAND gates decode the six respective states of the counting circuit and provide six corresponding timing pulses TPA, TPB, TPC, TPD, TPE and TPF. Each of these timing pulses is also connected to a respective inverter buffer 821 through 826 which provides the TPA through TPF pulses. These six-phase master timing pulses serve to subdivide consecutive master timing intervals into six discrete subintervals, the master timing intervals being repetitive at a frequency of approximately 492 KHz in normal operation and 246 KHz during the half speed operation mode. The TPA through TPF timing pulses are 170 nanoseconds in duration with a spacing of 170 nanoseconds off time between phases. In other words, the time between the leading edge of the TPA pulse and the leading edge of the TPB pulse is 340 nanoseconds.

Four-bit counters 827, 828, 829 and 832 are driven by timing pulse TPF and operate as free running countdown circuits for various timing purposes. The various reference designations associated with each of counters 827 through 832 relate to Model 74161 manufactured by Texas Instruments; it is to be understood however that other counters can be connected to perform the same function described herein.

NAND gate 833 is driven by timing signals from counters 827 and 828 and in turn drives inverter 834. The output signal from inverter 834 in turn is applied to AND gate 835 along with the TPF timing pulse to provide a VSCP pulse on every 64th TPF timing pulse. This VSCP pulse is connected to the circuits of FIG. 81 and is utilized in the timing for interface with demonstration printers.

The flip flop 836 is connected to counter 829 and receives the TPA timing pulses to provide a pulse once during every 2048 TPA pulses. Since the TPA pulse repetition rate is approximately 492 KHz, the Q output signal pulse rate from flip flop 836 is approximately 240 Hz. This signal is applied to the drive circuits for the scan synchronous motor in FIG. 85 where it is divided by four to generate a 60 Hz scan control signal synchronized with the basic master timing oscillator 801. The scan motor utilized in the system optics is 387 a 900 rpm synchronous hysteresis motor and is geared down at a 125 to 40 ratio to provide a 4.8 rps rate at the drive shaft to the scan mirror. A single lobe cam is utilized to drive the scan mirror which therefore also has a rate of 4.8 scan cycles per second. This is to be compared to the fact that the photocell array in the Character Recognition circuits is sampled once every 64th TPF pulse. For this scan rate and for the timing described, the recognition system is able to take 1600 samples per scan cycle. The maximum distance between center lines of OCR-A characters is 0.055 inch. If, as assumed here, this distance is divided into eight sample periods, each sample element which is 0.006875 inch. The cam causes the mirror to scan a line 8 1/4 inches long. With 0.006875 inch per sample, this requires 1200 samples and therefore 1200/1600 .times. 360.degree., or 270.degree. of the cam revolution is required for reading a line. The remaining 90.degree. are used for transition at the end of a scan, returning the mirror to the left hand margin of a document page, and providing a 12.degree. dwell at the left hand margin of the clutch/brake start/stop operation.

Counters 830 and 831 provide resettable timing pulses for the master and read program counters. The signal ATCL is a pulse which is generated each time either of the master or read program counters is advanced, and has the purpose of resetting counters 830 and 831, as well as flip-flops 1001 through 1006 in FIG. 10. Counters 830 and 831 count the 240 Hz pulses provided by the counter 829. The Qc output terminal of counter 830 is designated TC30 and goes high on four counts and low on eight counts. This signal is applied to flip-flop 1004 in FIG. 10, causing signal DL 30 to go high after eight counts, or approximately 32 ms after the ATCL goes high. The TC3.7 signal from the Q.sub.B output terminal of counter 831 goes high at 16 counts and low at 32 counts and sets flip-flop 1006 in FIG. 10. The TRC signal provided at the Q.sub.D output terminal of counter 831 goes high at 128 counts and low at 256 counts to set flip-flop 1005 in FIG. 10 after one second. In addition flip-flops 1001, 1002 and 1003 in FIG. 10 count four TRC pulses so that flip-flop 1003 is set after 4.0 seconds. These three flip-flops, once set, remain set until they are cleared by the next ATCL.

III(A.2) CONTROL PANEL AND MANUAL CONTROLS

The control panel illustrated in FIGS. 86a and 86b, contains various switches for control of the system and various display lights for indicating system status. The control panel contains the following rotary switches which affect the indicated functions, modes and operations:

Operate Mode Switch 8601 -- 3-position, two pole. 1. Error Halt Mode 2. Reject Mode 3. Error substitute Mode Document Width Switch 8602 -- 3-position, two pole. 1. Wide 2. Medium 3. Narrow Font Style (Format) switch 8603 -- 4-position, two pole. 1. Handwriting ) ) 2. OCR-A ) Vertical format only 3. NarrowFarrington 7B ) 4. Mixed -- Horizontal format Lines per inch switch 8604 -- 2-position, two pole. 1. 6 lines per inch 2. 3 lines per inch The following momentary switches are also on the control panel: Lower Hopper 8605 Reject Document 8610 Format Load 8606 Start 8607 Stop 8608 Repeat Line 8609 Clear 8614

The system status indicator lamps are illustrated in FIG. 86b and are lit under conditions corresponding to the nomenclature for the respective driving signals in that Figure. Each lamp is also actuable by the LAMP TEST signal which permits the operator to light all lamps to determine if any are burned out. The driving signals for the lamps are derived from circuitry in FIG. 83.

The connector board for the control and indicator panel is illustrated in FIGS. 83a and 83b. To insure correct operation, signals from the rotary switches in FIG. 86a are stored in latches 8301-8308 during MPSP time of the master program. MPSP is high when the system is in stop condition and the master program counter (FIG. 15) is at MPSO. Should the operator change a switch setting while the system is running, the unchanged latch output maintains the previously set operating condition. If any switch is changed when MPSP is low, comparison circuits 8311 through 8318, which compare the switch settings and latch conditions, operate via gate 8319 to set an Operator Error flip-flop comprising NOR gates 8309 and 8310. This operates circuitry in FIG. 9 to generate a stop signal which stops the system. The Operator Error indicator lamp is actuated to indicate to the operator that the desired switch setting should be made and the start switch re-actuated. The Error indicator light is reset by the start switch and the storage latches 8301-8308 are restored to the proper switch settings.

The rotary switches 8601-8604 are wired to provide a binary code output. This binary code is stored in the latches 8301-8308 and is then decoded to provide the desired control signal. This use of latch circuitry permits a reduction in the number of wires required at the control panel.

All signals from the switches are terminated with pull-up resistors to +5 volts.

The circuit of FIG. 83b receives input signals which represent the various conditions of the system and which serve to actuate the various system status lamps. These signals go through a set of gates and/or inverters and are then applied to the lamp circuits in FIG. 86b. The various input signals are discussed as they are generated in relation to the master program counter description.

Most of the manual control functions are implemented by circuits in FIG. 9. The start-stop circuitry includes gates 901 and 902, which form a stop flip-flop; flip-flop 903 is the start flip-flop. Signal RP is a "power on; clear" signal which initially puts the system in the stop condition.

Operation of the start switch 8607 causes STSW to go high and STSW to go low, resetting the stop flip-flop 901, 902. Start flip-flop 903 remains in the reset condition so that STR is high. AND gate 905, with high MPSO and STR inputs, provides a high MPSP signal for setting latches 8301-8308. NAND gate 906, with MPSP and the output of the stop flip-flop high, provides a low SCLR, which is the start clear signal. Gate 907 effectively "or's" the PWR ON CLR and CLSW (clear switch 8614) signals to provide PR. PR is "or'ed" with SCLR at gate 908 to provide signal MCLR which is the master clear signal for the system. Therefore each time the start switch is operated and the unit is in the stop condition (STR being high) the system is set to a clear condition. When the start switch 8607 is released, STSW goes low and STSW goes high. Gate 904, with STSW low and a low from the stop flip-flop 901, 902, enables the setting of the start flip-flop 903 at the next TPF clock pulse. With flip-flop 903 set, STR is high and STR is low, thereby inhibiting MPSP and SCLR.

Various stop signals are "or'ed" by Gate 902 to return the system to the stop condition. These are

Spsw -- stop switch 8608 signal through Gate 1301

Label -- generation of a tape label prevents the system from being put into the start condition (signal from tape interface, FIG. 76, via inverter 1302, gate 1301)

Fmersp -- format error; stop (signal from read and format program counter, gate 2101.

Oprer -- operator Error signal from FIG. 83a.

He -- detected Document Supply Hopper Empty Signal (from 1401, 1402).

Dcerr -- document error indication, which includes Pick Fail, Document Jam and Skew Error (from 1403).

The primary function of the start flip-flop 903 is to enable the Master Program counter (FIGS. 14, 15) to advance from the MPSO to the MPS1 state. Once the counter has advanced, the system follows its normal sequence of operations even though the start flip-flop may be reset.

Gates 909 and 910 form a flip-flop to control the elevator valve 706 with signal HRVS HLD via inverter 911 and driver 8709. When this line is low, elevator valve 706 is energized and allows the elevator 400 to raise the stack of documents to be picked. A Hopper Empty (HE), Document Error (DCERR) or a signal from the lower hopper switch (LWHPSW) during MPSP time, sets the flip-flop 909, 910 and the HRVS HLD signal goes high. With the elevator valve de-energized the air holding up the elevator is allowed to bleed off and the input hopper returns to its lowest position. When the start switch is operated the MCLR signal from inverter 912 resets flip-flop 910, 911 and seals off the bleed valve.

Gates 913, 914 form a flip-flop for format entry control. Operating the format enter switch 8606 to provide signal LFSW during MPSP sets this flip-flop via NAND gate 915. It is reset by the PR signal (CLEAR) and by the master program signal MPS6, which occurs after the conditioning document has been completely processed.

III(A.3) TRANSPORT PATH CONTROLS

Control over the mechanism protion of the system is effected at the mechanism panel which is illustrated schematically in FIGS. 87a through 87d of the accompanying drawings. Equipment at the mechanism panel permits control over the following: the document picking mechanism; read station document transport; document eject and output stackers; scan motor and clutch/brake; photocell sensor stations; switch sensor station; solenoid control; display mechanism for manual entry of data; and pneumatic assembly for air pressure/vacuum system.

The mechanism panel assembly includes a plurality of solenoid drivers 8701 through 8709 which are illustrated in FIG. 87a of the accompanying drawings. These drivers are used to control various system solenoids and valves illustrated in FIGS. 87b and 87d of the accompanying drawings and described in the following paragraphs:

Driver 8701 operates the picker solenoid 320 illustrated in FIG. 87d. This is the solenoid which selectively lowers feed shoe 304 to reach for the next document in document stack 301.

Driver 8702 controls the shoe vacuum valve 713 illustrated in FIG. 87d. Valve 713 is a solenoid valve which gates vacuum from vacuum chamber 708 to the feed shoe 304 via tube 305. Suction channels 307 in the bottom surface of feed shoe 304 allow the vacuum to grab the uppermost document in stack 301.

Driver 8703 controls the picker feed valve 702 illustrated in FIG. 87d. When picker feed shoe 304 has lifted a document and has returned to its highest position, solenoid valve 702 is energized automatically by virtue of the fact that microswitch is actuated. This permits air pressure from the air assembly to actuate air cylinder 308 and cause the feed shoe and the document to move forward toward the transport path. The de-energizing valve 702 permits air pressure to escape from air cylinder 308 and a spring returns the feed mechanism to its initial position.

Driver 8704 controls the first feed solenoid 506 illustrated in FIG. 87b. When feed shoe 304 has moved to its extreme feed position (to the right in FIG. 3), microswitch 326 is actuated by member 325. At this time the FFS solenoid 506 is automatically energized to engage the leading edge of the document between pinch rollers 505 and drive rollers 501, the latter being driven by the document step motor 500. Solenoid 506 remains energized until the leading edge of the document is sensed by photocell assembly 523 located at the second set of pinch rollers 507.

Driver 8705 controls the second feed solenoid 508 illustrated in FIG. 87b. The second set of solenoid operated pinch rollers 507 is located just downstream of read station 520. When the leading edge of the document passes this set of pinch rollers, photocell assembly 523 automatically energizes solenoid 508 and de-energizes solenoid 506. Rollers 507 engage the document to the drive rollers 504 and document stepping continues, under control of the master, read and format programs.

Driver 8706 controls the eject solenoids 516, 517 and 515 illustrated in FIG. 87b. After a document has been read, solenoid driver 8706 actuates the three eject solenoids which are evenly spaced along the transport path. These solenoids operate pinch rollers 512, 513 and 514, respectively, which engage the document to spaced belts which are continually driven by rollers 509, 510 and 511. This moves the document to the stacking mechanism at which a second set of continually moving belts is located. These belts are always in contact with the respective drive rollers. Solenoid 508 is turned off 30 milliseconds after the eject solenoids are deactuated.

Driver 8707 controls the stacker select solenoid 539 illustrated in FIG. 87b. Solenoid 539 controls document steering member 538 which is used to steer the documents to either the normal stacker bin 530 or the reject stacker bin 531. When solenoid 539 is de-energized, the document is steered into normal bin 530. When solenoid 539 is energized the document is steered into reject bin 531. Appropriate timing interlocks are provided in order that the steering member 538 cannot be moved while a document is progressing through the stacking mechanism. The steering condition is set before the document is ejected.

Driver 8708 controls the track motor relay 8710 which in turn controls the track motor 518, as illustrated in the FIG. 87b. The eject and stacker drive belts are moving continuously, driven by an electric motor 518. If a document jam is detected, relay 8710 is energized by driver 8708 to remove the primary power from motor 518. After the operator has investigated the cause of the jam and cleared any jammed document, the next operation starts, which de-energizes relay 8710 and permits motor 518 to run continuously again.

Driver 8709 controls the elevator valve 706 illustrated in the FIG. 87d. Document stack 301 is raised or lowered by the elevator mechanism of FIG. 4 which is controlled by two air pistons 403. Valve 706 is an air escape valve which is closed to prevent bleeding. When valve 706 is closed, the elevator may be raised by controlled air pressure from the air assembly as illustrated in FIG. 7. This air pressure is supplied when the feed shoe 304 is lowered to reach for a document. If the uppermost document of the stack is too low, the feed shoe extends far enough down to cause member 327 to block outlet 328. The resulting back pressure actuates air pistons 403 until the top of the stack of documents raises the feed shoe and outlet 328 becomes unblocked. A check valve 705 and solenoid valve 706 prevent air from escaping air pistons 403. The elevator can only be lowered by de-energizing valve 706 and permitting air to be bled from pistons 403. This is accomplished automatically under certain conditions, such as the hopper empty condition. A manual switch is also provided to permit operator-controlled lowering of the elevator. The solenoid valve is automatically re-energized when the start switch is operated.

Control over the document step motor 500 is illustrated in FIG. 87b and 87c. The document step motor, which controls document advance through read station 520, is a bifar wound 4-pole step motor. It includes 200 steps per revolution (i.e., 1.8.degree. per step), and the diameter of the drive capstan is chosen so that each step of the motor advances the document 0.0208 inches. The motor is bidirectional and can be selectively reversed to perform a fine line adjustment when it is necessary to center a line of data at the read station. The primary step control is the signal DCMT which is generated as described in relation to FIG. 84. A reverse direction control signal (DOWN-COUNT) is generated during fine line adjustment as described in relation to FIG. 72. These two signals are utilized in the circuit of FIG. 85 to provide the signals DCSM1, DCSM2, DCSM3, and DCSM4. These four signals actuate respective drivers 8711, 8712, 8713 and 8714 in FIG. 87c which in turn drive the four poles of step motor 500 as illustrated in FIG. 87b.

The scan clutch 8715 and brake 8716 are illustrated schematically in the FIG. 87d. The mechanical portion of the scan mechanism comprises a 900 rpm synchronous hysteresis scan cam motor 8717. The motor is controlled by a permanent magnet-type clutch/brake assembly, and operates mirror and lens cams for controlling the positions of the scan mirror and focusing lens in the optical path. The mirror and lens cams form one assembly which is coupled to the motor 8717 when both the clutch and brake solenoids 8715 and 8716 are energized, or is coupled to the main casting through the brake plate when the clutch and brake solenoid are de-energized. When the clutch and brake solenoids are de-energized permanent magnets insure engagement of the brake plates to the stationary portion of the assembly and disengagement of the clutch plate from the moving scan motor 8717. The clutch/brake has an approximate electrical energization time of 15 ms and a de-energization time of 2 ms. The scan printer speed is reduced by a ratio of 40/125 to obtain the desired angular speed for the shaft of the clutch/brake assembly. Two separate solenoid drivers 8718 and 8719 are employed for the clutch solenoid 8715 and brake solenoid 8716 respectively, but both drivers are actuated by a common clutch/brake input signal derived as described in relation to FIG. 85.

Solenoid driver 8720 in FIG. 87c is employed to actuate the display mirror solenoid 8721 in FIG. 87b. During an error halt mode (i.e., a manual entry mode) it is desirable to display any unrecognizable character directly from the document being read. When an unrecognized character is detected (as described subsequently), the system positions the scan mirror in the optical path to pick up the image of the unrecognizable character as well as the images of the two adjacent characters. Solenoid 8721 is then engaged to move a second mirror (reference U.S. Pat. application Ser. No. 367,880, filed on concurrent date herewith by John H. MacNeill, entitled "Visual Display of Unrecognizable Characters In Optical Character Recognition Machines," and assigned to the same assignee as the present application), located proximate the photo-sensitive array for the characters being read, to cause the three character images to be displayed on the screen for the operator. The operator determines what the unrecognizable character should be and enters same through the manually actuated keyboard. The signal which actuates driver 8720 is designated the CURSOR SHUTTER signal and is generated in the circuit of FIG. 85.

Referring to FIG. 87d, the system includes nine light-sensitive detector assemblies, each including a light-emitting diode (LED-1 through LED-9) and nine photo-transistors (Q-1 through Q-9). Eight of these (2 through 9) are identical in construction, the light-emitting diode and photo-transistor being mounted in the same assembly and pointing in the same direction along parallel paths. These assemblies are then mounted along the document mechanism, pointed at a prism assembly on the opposite of the document path. When no document is in the path, light is emitted by the light-emitting diode and reflected by the prism to the photo-transistor. Therefore, light crosses the document path twice when no document blocks a sensing station. When a document does block a sensing station, the single document effectively blocks the light twice; that is, the document blocks light emitted from the light-emitting diode toward the prism, and blocks light reflected by the prism toward the photo-transistor. This arrangement is very advantageous from an assembly and wiring consideration and provides a relative large light-to-dark ratio in the photo-transistor output signal.

The photocell assembly which includes LED-1 and photo-transistor Q-1 is employed to sense a window in the driving cam for the scan mirror. In this case the light-emitting diode LED-1 and photo-transistor Q-1 are on opposite sides of the cam.

As illustrated in FIG. 87d, light-emitting diodes LED-1 through LED-9 are connected in series between a source of positive dc voltage and ground. Each of photo-transistors Q-2 through Q-9 are connected to provide appropriate logic signals to the circuitry in FIG. 85 to operate various circuits illustrated in that Figure. The logic functions effected by these photo-transistors are described briefly in the following paragraph for ease of reference.

Light-emitting diodes LED-6, LED-7 and LED-8 and photo-transistors Q-6, Q-7 and Q-8 correspond to the three photocell assemblies 521 proximate the first feed rollers 501 in the transport path. These three assemblies are arranged in a line parallel to the leading or top edge of the document entering the transport path. They are positioned between the first feed rollers 501 and read station 520 and are responsible for detecting skew in a document being entered into the feed path. Specifically, after the document is picked it is then advanced by step motor 500 until it reaches the skew detection station as determined by assemblies 521. The document width switch S3 at the control panel (FIG. 86) permits selection of which skew station photo sensors are in operation. For very narrow documents only LED-6 and Q-6 are operative; the other two assemblies being disabled. For medium width documents LED-7 and LED-6 and Q-7 and Q-6 are operative. Wide documents utilize Q-6, Q-8, LED-6 and LED-8.

The skew station photocells perform three essential functions: detection of the leading edge of the document to determine the occurrence of picking failures; testing the leading edge of the document for excessive skew; and detection of the trailing edge of the document in order to generate the "read complete" signals.

Light-emitting diode LED-9 and photo transistor Q-9 are part of assembly 523 located proximate the second set of drive rollers 504 in the transport path. The function of this assembly is to detect the leading edge of the document so that solenoid 508 may be actuated and solenoid 506 may be deactuated. The signal provided by photo transistor Q-9 is designated FCBDPC.

Light-emitting diode LED-5 and photo transistor Q-5 correspond to assembly 525 located just downstream of the first eject pinch roller 512. When document processing is completed, the document must be advanced by step motor 500 until the leading edge of the document reaches assembly 525. When the leading edge is detected by photo transistor Q-5, the eject solenoids 515, 516 and 517 are energized and solenoid 508 is de-energized.

Photo transistor Q-2 and light-emitting diode LED-2 correspond to assembly 534 at the entrance to the normal stacker bin 530. Photo transistor Q-3 and light-emitting diode LED-3 correspond to assembly 536 at the entrance to the reject stacker bin 531. The signals from these detectors actuate logic circuitry in FIG. 85 which in turn effects the following functions: reset the "document in track" flip flop 923, 924 (FIG. 9); inhibit changing of the stacker selector; and provide an input signal to the "document in reader" lamp.

The mechanism assembly contains a number of switches which are automatically actuable during mechanism operation to monitor and control various functions. These switches are illustrated in FIG. 87d and are described in the following paragraphs.

The shoe vacuum switch 8724 is a single-pole single-throw vacuum switch which closes when a document closes the channels 307 along the underside of feed shoe 304 to prevent further aspiration of air by the evacuated shoe. Naturally valve 713 in FIG. 7 must be properly positioned so that vacuum is, in fact, applied to the feed shoe before switch 8724 can respond to blockage of the feed shoe channels by a document. Closure of switch 8724 actuates the circuitry in FIG. 85 to be described subsequently.

The feed solenoid switch 322 is a single-pole double-throw switch which is held actuated (as illustrated in the FIG. 3) when support arm 318 for the feed shoe is at its normal or raised rest position. When the picker solenoid 320 is energized to lower arm 318 to reach for a document, switch 322 is released. The switch is actuated again when the arm is raised after a document has been picked. Switch 322 must then be actuated before the picker feed valve 308 can be actuated to move the feed shoe 304 and document toward the transport path. Logic for accomplishing these functions in response to closure of switch 322 is illustrated in FIGS. 85, 14 and 15 of the accompanying drawings.

The picker arm forward switch 326 is a single-pole double-throw switch which is actuated when the picker arm and feed shoe 304 is in its extreme feed position. Such position is indicative that the leading edge of the document should be engaged by the first set of the pinch rollers in the transport path; consequently operation of switch 326 is effected through the circuitry of FIG. 85 to operate the first feed solenoid 506.

The double document switch 8725 is a single-pole single-throw vacuum switch (referred to in FIG. 7) which is closed when the feed shoe has delivered two or more documents simultaneously to the transport path. Specifically, switch 8725 is actuated when sensing port 330 near the leading edge of the transport path is blocked, as would occur when the bottom of two simultaneously picked documents falls from the feed shoe as a result of the suction applied to the port 330. Logic effected by the actuation of switch 8725 is illustrated in FIG. 85.

III(A.4) MECHANISM CONNECTOR BOARD

The mechanism connector board schematic is illustrated in FIG. 85 which is subdivided into FIGS. 85a, 85b, 85c and 85d. The circuits in these Figures provide direct interface between the mechanism itself and the controls and logic for operating the mechanism.

Referring specifically to FIG. 85a, NAND gates 8501 through 8509 are provided to operate in accordance with he state of photo transistors Q-1 through Q-9 respectively, of FIG. 87d. Each NAND gate is arranged to provide a binary or relatively positive output signal when its corresponding photo transistor is rendered conductive. NAND gates 8507 and 8508 also respond to the ND and the MD signals. In this regard the MD signal is applied to inverter 8510 before being applied to NAND gate 8507.

The output signal from NAND gate 8501 is designated BOL and is utilized in the circuit of FIG. 16. This BOL signal is also inverted by inverter 8511 before being utilized in other circuits as indicated in the drawing.

The output signals from NAND gates 8502 and 8503 are combined in an AND function by applying them together to NAND gate 8512 and then inverting the output signal from gate 8512 be means of inverter 8513. The resulting output signal STG is a combined indication of the presence or absence of a document located at the entry to the normal and reject stacker bins 530 and 531. The status of the picker arm swith 326 is reflected by the state of the picker arm flip flop defined by NAND gates 8514 and 8515. The state of the double document switch 8725 is reflected by the state of inverter 8560. The shoe vacuum switch 8724 and the feed solenoid switch 322 are connected to components of the circuit in FIG. 85d which will be described subsequently.

III(A.5) MECHANISM CONTROL LOGIC

Most of the control logic for the mechanism appears in FIGS. 9 through 15 of the accompanying drawings and is functionally interrelated to the manual controls and the master program counter. The following description is merely a brief resume of the functioning of the logic circuitry, a more detailed description being presented in the section outlining the master program steps MPS0 through MPS7.

When the system is in the start condition and a RDLN (read line) command signal is received from flip flop 7301, 7302, the master program counter in FIG. 15 advances from MPSO to MPS1. The PAS signal is provided by gate 1304 during the MPS1 interval; this signal remains on during the first 30 ms of the MPS2 interval due to the interaction of the gates 1303 and 1304. The PAS signal is applied to driver 8702 for the shoe vacuum valve 713, as well as to circuitry in FIG. 85d which generates the PICKER SOL signal to operate picker solenoid 320. This energization of the picker solenoid permits the picker to lower and reach for the document in the input hopper.

As illustrated in FIG. 85d the input to inverter 8517 is connected to vacuum switch 8724 for the feed shoe. In addition switch 8724 is connected to NAND gate 8518 which drives a one-shot multivibrator 8519. Gates 1404 and 1405 serve to test for closure of vacuum switch 8724 within four seconds of feed shoe energization. If the switch does not close within this time the hopper empty flip flop 1401, 1402 is set.

As mentioned the circuits in FIG. 85d control the picker mechanism during the MPS1 interval. Vacuum switch 8724 for the feed shoe must operate and the solenoid switch 322 must release to provide proper picker operation. This triggers the 40 ms monostable multivibrator 8519 to delay the release of the picker solenoid 320 and insure that the vacuum in the feed shoe has had time to build up and obtain a good grip on the document being fed. At the end of the 40 ms period of one-shot 8519 the picker solenoid is de-energized. When the feed shoe rises, solenoid switch 322 is reset, allowing the picker feed valve 702 to be energized. The feed shoe moves forward until the picker arm forward switch 326 is actuated to provide the PAFSW signal which actuates flip-flop 8514, 8515 in FIG. 85a and permits the master program counter to advance to the MPS2 state.

During the MPS2 interval the flip flop defined by gates 917 and 918 is set to provide the FFS signal to energize the first feed solenoid 506 via driver 8707. Thirty milliseconds after the start of the MPS2 interval the PAS becomes de-energized, thereby deactuating shoe vacuum solenoid 713. This also triggers one-shot 8519 so that the picker feed valve 702 is turned off after 40 ms. This 40 ms interval insures that the vacuum in the feed shoe has been released so that a document will not be pulled when the picker arm returns to its rest position. When the picker arm begins back toward its rest position it releases the picker arm forward switch 326, making signal PAF high at the output of gate 8515. This is the signal which permits the master program counter to advance to the MPS3 state.

During the MPS3 interval the document is advanced to the skew sensing station. Gates 8401, 8402, 8403, 8404, and 8405 cooperate to generate the document motor advance pulses (DCMT) until either the SKWB or SKER signals go low. The SKWA and SKWB signals are generated in the circuit of FIG. 12 in response to operation of the skew sensor station photocells. SKWA goes high whenever a document blocks any of the enabled skew photocells. SKWB goes low whenever the document blocks Q-6 for narrow documents or all enabled photo transistors for medium and wide documents. The number of steps of motor 518 required from the point at which SKWA goes high and SKWB goes low is a measure of the amount of skew of the top edge of the document. Gate 8402, and the following circuitry, permits application of the DCMT pulses to motor 500 during the MPS3 interval until signal SKWB goes low or until the counter 8406, 8407 detects a skew error. Gate 8401 enables the counter 8406, 8407 to count steps from the time SKWA goes high until either SKWB or SKER goes low. If either SKWB or SKER go low, gates 1406 and 1407 operate to permit the master program counter (FIG. 15) to advance from the MPS3 state to the MPS4 state.

During the MPS4 interval, tests are made to determine if a document is left in the track from a previous operation and if the scan mirror has returned to its BOL (beginning of line) position. A test is also made to determine if the document advance counter 8406, 8407 has detected a skew error. The tests are performed in the circuit of FIG. 14. Specifically, NAND gate 1408 responds to a detected skew error by setting the flip flop defined by gates 1409 and 1410. In most operations, setting of the flip flop 1409, 1410 actuates NAND gate 1411 which in turn operates circuitry in FIG. 21 to provide the reject command (REJCM) signal. The system is in the MPS4 state for only a few microseconds to make these tests and then advances to the MPS5 state. If, in the MPS5 state, the reject command and the read complete signals are not present, the system proceeds to perform a load format or read operation by enabling the respective load format or read program counter.

If either the read complete or reject command signals are present during an MPS5 interval, the system automatically advances to the MPS6 state. The document must be advanced to the eject enter station during MPS6 if it has not already been advanced that far during the MPS5 interval. NAND gate 1305 generates the signal to effect this operation, this signal being applied to gate 8403. Gate 8403 responds by generating advance pulses DCMT for motor 500 until the stop edge of the document blocks the eject photo transistor Q-5. Gate 1411 enables the advance of the master program counter from MPS6 to MPS7 when the ejected document enters a stacker throat. Gate 1411 requires that the EJEN signal be high, that any data output sequence be complete (as indicated by the OUT-IN-PRO signal) and that there be no documents in the stacker throat (as indicated by the STG signal).

At MPS7 the flip flop defined by gates 919 and 920 is reset. This flip flop controls the second feed solenoid 508. When flip-flop 919, 920 was set, signal SFS was low and set flip-flop 1101, 1102 in FIG. 11. When flip-flop 1101, 1102 is set and signal SFS becomes high gate 1103 generates the EJS signal to actuate the eject solenoids 516, 517 and 518. When a document blocks the entrance to the stacker section of the mechanism, thereby blocking photo transistor Q-4, the STEN signal goes low to reset flip flop 1101, 1102 and deactuate the eject solenoids 516, 517 and 518.

Return of the master program counter from the MPS7 state to the MPS0 state is effected by the gate 1412 after the trailing edge of the document has passed the skew sensing station.

III(A.6) MASTER PROGRAM COUNTER

The master program counter circuit is illustrated in FIG. 15. The circuits which implement the logic necessary to increment the master program counter are illustrated in FIG. 14. Detailed description of the master program counter is provided in the form of an outline wherein each step in the program sequence and the implementing circuits are identified. The following two paragraphs serve as introduction to the outline by describing certain general operation.

A program advance or step is initiated by a low signal on one of the inputs to gate 1413. The output of this gate is applied to NAND gate 1414. Two inputs to gate 1414 from gates 1415 and 1416 are single-cycle control signals used during debugging operations; these are always high during normal operation. Gate 1414 samples the advance signal at TPE time to set flip-flop 1417, 1418. With this flip-flop set, its output is sampled at TPF time by gate 1419 and inverter 1420 to generate MPCT and MPCT pulses. The MPCT (Master Program Counter Toggle) pulses go to the three-bit master program counter formed by flip-flops 1501, 1502 and 1503. The outputs of this counter go through gates 1504, 1505, and 1506 to a three-bit to eight-output decoder 1507. Gates 1504, 1505, and 1506 are used during a read test mode to force a count of 5 into the decoder. Flip-flop 1417, 1418 is reset by TPA.

The MPCT signal sets flip-flop 1508, 1509 which is also reset by TPA. The output of gate 1508 goes to the D input of the decoder 1407 which has the effect of disabling the decoder from the beginning of MPCT (TPF) to the beginning of the next TPA. The counter advances at the trailing edge of MPCT. With the decoder disabled during this short period, it cannot generate any spurious pulse while the counter advances. When the decoder is thusly disabled, all inputs to gate 1413 are high. When the decoder is enabled it proceeds to the next step, enabling another input gate for 1413. Another low signal input to gate 1413 cannot occur until the appropriate conditions are present as set forth in the master program outline. A hopper empty (HE) or document error (DCERR) condition cause the counter to immediately return to state MPS0 through gates 1510 and 1511. The remaining circuits in FIG. 14 are used to detect various fault conditions such as Hopper Empty, Pick Fail, Document Jam, Double Document, and Skew Error.

In the outline for the master program which is presented in the following section, the referenced program steps occur during the master program counts indicated in the following list:

MP Count Program Steps ______________________________________ MPSO A1 - A3 MPS1 A4 - A15 MPS2 A16 - A25 MPS3 A26 - A29 MPS4 A30 - A35 MPS5 A36 - A44 MPS6 AA5 - A51 MPS7 A52 - A53 ______________________________________

III(A.7) MASTER PROGRAM OPERATIONAL OUTLINE

A1. detect for read line or transport test commands (gate 1421). If present, proceed to A2; if not, remain in standby.

A2. detect if mechanism is in start position (gate 1422). If yes, proceed to A3; if not, return to A1.

A3. check for document in skew sensor station (no document if SKWA is high; gate 1422). If no document, proceed to A4; if document present, return to A1.

A4. energize picker arm solenoid 320 (gates 1303, 1304) and shoe vacuum solenoid (gates 8520, 8521, 8522, and 8523). Proceed to A5.

A5. detect if shoe vacuum switch 8724 is closed (gate 1405). If not, proceed to A6; if yes, proceed to A8.

A6. detect if 4.0 second timer expired (counter 1001, 1002, 1003; gate 1404). If not, return to A5; if yes, proceed to A7.

A7. set the hopper empty flip flop (1401, 1402), reset the start flip flop 903 (gate 902), and return to A1.

A8. detect if picker arm solenoid switch 322 is released (is arm down?) (gates 8524, 8525, 8526). If yes, proceed to A9; if not, proceed to A14.

A9. de-energize picker arm solenoid 320 (gates 8521, 8522, and 8523). Proceed to A10.

A10. detect if picker arm solenoid switch 322 is actuated (is arm up?) (gates 8524, 8525). If not, proceed to A14; if yes, proceed to A11.

A11. energize picker feed valve 702 (inverter 8527, flip flop 8528 and NAND gate 8529). Proceed to A12.

A12. after picker arm start switch is released, energize valve 713 to permit detection of double document feed. Proceed to A13.

A13. detect if the picker arm forward switch 326 is actuated; if not, proceed to A14; if yes, proceed to A16.

A14. detect if the 4.0 second timer expired (counter 1001, 1002, 1003; inverter 1423, gate 1424). If yes, proceed to A15; if not, return to A4.

A15. set pick failure flip flop 1425, 1426 and reset start flip flop 903 (gates 1403, 901). Proceed to A1.

A16. energize first feed solenoid (gates 917, 918), start 30 ms delay (counters 830, 831; flip flop 1004), and deactuate shoe vacuum valve 713 (gates 1303, 1304). During 30 ms delay proceed to A17 to detect double document feed; after delay, if no double document feed is detected, proceed to A21.

A17. detect for closure of double document vacuum switch 8725 (gates 1427, 1409, 1410). If closed, proceed to A18; if not, proceed to A24.

A18. detect if system is in transport test, load format, or not reject modes (gates 1428, 1429). If so, proceed to A19; if not, proceed to A20.

A19. actuate document error signal (gate 1403) and reset start flip flop 903 (gate 902). Proceed to A1.

A20. set the document to reject signal (gates 1428, 1430, 1431, 2102, 2103). Proceed to A26.

A21. detect if shoe vacuum switch 8724 is deactuated (gate 8518). If not, proceed to A24; if de-actuated, proceed to A22.

A22. start 40 ms delay (gate 8530, one-shot 8519). At end of delay deactuate picker feed valve 702 (flip flop 8528, gate 8529). Proceed to A23.

A23. detect if the picker arm forward switch 326 is released (gate 1432). If released, proceed to A26; if not, proceed to A24.

A24. detect if 1.0 second timer has expired (flip flop 1005; gates 1433, 1434). If not, return to A16; if so, proceed to A25.

A25. set the pick failure flip flop 1425, 1426 (gate 1434) and reset start flip flop 903 (gates 1403, 902). Return to A1.

A26. with the first feed solenoid 506 still energized, actuate document advance motor 500 a sufficient number of steps until either SKWB or SKER goes low; count motor steps between SKWA and SKWB signals (flip flop 917, 918; gates 8401, 8408, 8409, 8410, 8403, 8404, 8405; counters 8406, 8407). Proceed to A27.

A27. is either SKWB or SKER low? (Gates 1406, 1407) If so, proceed to A30; if not, proceed to A28.

A28. detect if 250 ms timer has expired (flip flop 1006; gate 1435). If not, return to A26; if so, proceed to A29.

A29. set document error signal (gates 1435, 1425, 1426) and reset start flip flop 903 (gates 1403, 902). Return to A1.

A30. detect if SKER is low, indicating a skew error (gates 1408, 1409, 1410). If so, proceed to A31; if not, proceed to A33.

A31. detect if unit is in either of the transport test, load format or not reject modes (gates 1428, 1430). If so, proceed to A35; if not, proceed to A32.

A32. set document reject signal (gate 1431). Proceed to A33.

A33. determine if the previous document is in the track, or if a transport test mode exists, or if the BOL signal is high (gates 1436, 1437). If so, proceed to A34; if not, proceed to A36.

A34. determine if the 1.0 second timer has expired (gates 1433, 1438). If not, return to A30; if so, proceed to A35.

A35. set document error signal (gates 1438, 1439, 1440, 1429) and reset start flip flop 903 (gates 1403, 902). Return to A1.

A36. detect if unit is in transport mode and signal SKWA is high (gate 1441). If so, proceed to A44; if not, proceed to A37.

A37. detect if document reject condition exists (gate 1442). If so, proceed to A44; if not, proceed to A38.

A38. detect if load format mode is in effect (decoders 2301, 2401, input signals LDFT and LDFT). If so, proceed to A40; if not, proceed to A39.

A39. read document in accordance with steps in the read program (refer to description of read program steps). Proceed to A43.

A40. process conditioning document in accordance with format program steps (refer to description of format steps). Proceed to A41.

A41. determine if a format error occurred (gates 2001, 2002, 4301, 4501, 5101, 5102, 5103). If not, proceed to A43; if so, proceed to A42.

A42. set the format error flip flop 2104, 2105 and reset the start flip flop 903 (gates 2101, 902). Proceed to A44.

A43. determine if the read operation or format entry operation has been completed (decoder 2401; flip flop 2106, 2107; gates 1442, 1443). If not, return to A36; if so, proceed to A44.

A44. determine if all the read data has been transferred out of the system and if the read and format program counters are at zero (gates 1444, 1443, 2501). If not, return to A36; if so, proceed to A45.

A45. end of document sequence; advance document until leading edge covers eject entrance photocell assembly 525 (gate 7303; flip flop 7304, 7305; gate 7306; flip flop 7307, 7308; gate 7309; inverter 7310; gates 1305, 8403, 8404, 8405). Proceed to A46.

A46. determine if document has reached the eject entrance photocell 525 (gate 1411, signal EJEN). If not, proceed to A49; if so, proceed to A47.

A47. determine if previous document is jamming entrance to stacker section as determined by photocell assembly 527 (gate 1411, signal STG). If so, proceed to A49; if not, proceed to A48.

A48. determine if all data has been transferred out and the end of document sequence is complete (gate 1411, signals OUT-IN-PRO and MPS6). If not, return to A45; if so, proceed to A51.

A49. determine if the 1.0 second timer has expired (gates 1433, 1445). If not, return to A45; if so, proceed to A50.

A50. set document jam flip flop 1439, 1440 (gate 1445) and reset start flip flop 903 (gates 1403, 902). Return to A1

A51. deactivate second feed solenoid 508 (gate 921; flip flop 919, 920) and activate eject solenoids 515, 516, and 517 (flip flop 1101, 1102; gate 1103). Proceed to A52.

A52. determine if signal SKWA is low, indicating that the document is out of the skew sensor station (gate 1412). If so, return to A1; if not, proceed to A53.

A53. determine if the 1.0 second timer has expired (gates 1433, 1446). If not, return to A51; if so, return to A50.

III(A.8) READ AND FORMAT PROGRAM COUNTER

The read and format program counter and related circuits are illustrated primarily in FIGS. 17 through 25 of the accompanying drawings, however circuits in other figures are of course related insofar as they may provide or receive signals related to the read and format program counter operation. Complete description of read and format program counter operation is provided in the format program counter outline and read program counter outline included hereinbelow. The following general comments are included to facilitate an understanding of these outlines.

The read and format programs have their individual control gates but share the same 4-bit counter and its control. These controls operate similarly to those associated with the master program counter with one exception: the master program counter only advances in sequence or is reset to zero; the read and format programs not only advance in sequence under some conditions but are also steered or jumped to other counts according to conditions detected by the control circuits.

Gates 1601 through 1606 and 1608 through 1619 are the gates which control the read program counter to step in sequence from one count to the next. The signals are OR'd together by the 8 input gate 1607. Gates 2003 through 2019 are the gates which control the format program counter to step in sequence from one count to the next. The signals from these gates are OR'd by gate 2020 which, when actuated, provides a low FTCA signal. This signal is also OR'd at gate 1607. Gates 2502 through 2518 are the gates which control the steering or jump conditions for the read and format programs. Any condition which calls for a jump in the program will generate a low input signal to gate 2519 which enables flip flop 2520 to become set on the positive-going edge of the next TPD pulse. The Q output signal from the flip flop 2520 is designated JPCT and is applied as one input signal to gate 1607. Since gate 1607 thus receives input signals for controlling read program stepping, format program stepping, and all program jumps, this gate controls all advances of the program counter whether sequentially or not.

Gates 2521 through 2524 are utilized to generate the step number to which a program jump is to be made and receive appropriate signals from gates 2514, 2516, 2517 and 2518. The jump control signals which are not connected to gates 2521 through 2524 are utilized to jump the program counter to zero (RPSO or FPSO). When signal JPCT is high and TPD is high, gate 2525 strobes the jump count into the 4-bit memory circuit 2526. The output signals from memory circuits 2526 are applied to the preset inputs of the 4 bit binary counter 2527. The JPCT signal is also applied to the load signal of counter 2527.

Counter advance pulse RPCT is generated at gate 1626. If signal JPCT is high, counter 2527 advances once for each RPCT pulse. If JPCT is low, counter 2527 is preset to the jump count stored in memory circuit 2526. It will be noted that the RPCT signal is generated in a manner similar to the MPCT.

The read program decoder 2301 and associated output inverters are illustrated in FIG. 23; the format program decoder and associated output inverters are illustrated in FIG. 24. These are four-bit to sixteen-output decoders. Decoder 2301 is enabled when signal LDFT is low, as is the case during read mode operation. Decoder 2401 is enabled when signal LDFT is low, as is the case in the load format mode. Signal DCIN, applied to both decoders, is high during the short time interval when the program counter is changing state. This inhibits any spurious pulses from being generated by the decoder when the counter is changing state.

III(A.9) FORMAT PROGRAM

The format program has sixteen discrete steps corresponding to the sixteen counts in counter 2527 and as decoded by decoder 2401. These steps are listed below with a brief notation as to the function performed when each step is active.

Fps1 -- move scan to vertical format mark position.

Fps2 -- advance document one step and count.

Fps3 -- test for end of document or if number of lines exceeds maximum.

Fps4 -- perform line position analysis.

Fps5 -- test results of line position analysis.

Fps6 -- memory write cycle for document advance counter.

Fps7 -- reset document advance counter and initiate horizontal format mode.

Fps8 -- scan for horizontal format and store horizontal format data.

Fps9 -- advance document twelve steps and count.

Fps10 -- test for signal DAT177 (advance document 128 steps).

Fps11 -- memory write cycle for DAT177.

Fps12 -- reset document advance counter to zero.

Fps13 -- reset document advance counter to zero; memory write cycle; end of document.

Fps14 -- set read complete flip flop.

Fps15 -- reset format advance counter

III(A.10) FORMAT PROGRAM OUTLINE

B1(fpso)--determine if proper conditions exist to initiate format program (gates 1704, 2005, 2020, 1607). Reset document advance counter 8406, 8407 (gates 2501, 2526, 2527, 8414). Proceed to B3 (gates 1607, 1625, 1627, 1628, 1626 and counter 2527).

B2(fps1)--determine if the scan mirror is directed toward the left edge of the document by sensing whether or not photo transistor Q-1 has been activated (gate 2006). Proceed to B3 (gates 2010, 2020, 1607, 1625, 1627, 1626, and counter 2527).

B3(fps2)--advance document one step and add one count to document advance counter 8406, 8407 (gates 8415, 8408, 8409, 8410, 8403, 8404, 8405). Proceed to B4 (gates 2007, 2010, 2020, 1607, 1625, 1627, 1626, counter 2527).

B4(fps3)--determine if the end of the document has passed the skew sensor station or if 86 vertical format words have been placed into memory (gates 2018, 2001). If the end of document has not passed the skew station and 86 vertical format words have not been placed into memory, set the format error flip-flop and the read complete flip-flop and reset the start flip-flop and proceed to B5 (gates 2018, 2019, 2020, 1607, etc.). If the end of document has not passed the skew station by 86 vertical format words have been placed into memory return to B1 (gates 2001, 2104, 2105, 2109, 2110, 2102, 2103, 2506, 2509, 2519). If the end of document has passed the skew sensor station proceed to B14 (gates 2025, 2517, 2519; flip-flop 2510; and gates 2521, 2523, and 2524). Clear the line position analysis circuits 6623 through 6608 (gate 6602).

B5(fps4)--perform line position analysis (refer to line position analysis section). Upon completion of line position analysis proceed to B6 (gates 2009, 2010, 2020, 1607, etc.).

B6(fps5)--examine results of line position analysis. If mark is centered proceed to B7 (gates 2012, 2014, 2020, 1607, etc.). If no mark is detected proceed to B11 (gates 2024, 2518, 2519, 2522, 2524; flip flop 2520). If a non-centered mark is detected, set the format error flip flop and the read complete flip flop, reset the start flip flop, and return to B1 (gates 2002, 2104, 2105, 2109, 2110, 2102, 2103, 2506, 2509, and 2519).

B7(fps6)--store the document advance count, if not equal to zero, with flag DAC8 (DAT177) = 1 (gates 2003, 2004, 6306, 6307; multiplexers 2601 through 2605; gates 6003, 6004, 6311, 6312; multiplexers 4801 through 4804) by selecting DAC1 through DAC7 as the data input and the vertical format address count as the memory address. Increment the vertical format address counter 5201, 5202 (gates 6018, 6019). Upon completion of the memory cycle proceed to B8.

B8(fps7)--reset document advance counter 8406, 8407 (gates 2527, 8414). Reset scan advance counter 2801-2803 (gates 3601, 3602). When scan mirror returns to beginning of line, proceed to B9 (gates 2013, 2014, 2020, 1607, etc.).

B9(fps8)--determine that a vertical format mode with no horizontal format exists and that there is no reject command and the scan mirror is at the beginning of the line. If these conditions obtain proceed to B10 (gates 2017, 2016, 2015, 2014, 2020, 1607, etc.). If horizontal format mode exists, scan the line to detect field definition marks; for each mark detected store the scan count and the lowest order bits of the character recognized in the horizontal format memory; advance the horizontal format memory address counter (multiplexers 2601-2605; gates 3001-3003; multiplexers 4801-4804; and memory controls section in general). Test for excess number of horizontal field and set format error (counters 5104, 5105; gates 5101, 5103, 2104, 2105, 2109, 2110, 2102); test for unrecognized field characters and set format error (gates 5102, 5103, 2104, 2105, 2109, 2110, 2102); enter the horizontal format data into the memory (refer to memory section for description); if format error is detected return to B1 (gates 2506, 2509, 2519). At the end of the line scan proceed to B10 (gates 2017, 2016, 2015, 2014, 2020, 1607, etc.).

B10(fps9)--advance document six steps for six-lines-per-inch pitch or twelve steps for three-lines-per-inch pitch (gates 8416, 8415, 8403, 8404, 8405); increment the document advance counter 8406, 8407 (gates 8416, 8415, 8408, 8409, 8410); return to B2 after appropriate number of steps have been implemented (gates 2021, 2023, and 2519). Test for even number of horizontal format words stored; if number of words is not correct set reject command and return to B1 (gates 4501, 5103, 2104, 2105, 2109, 2110, 2102, 2506, 2509, and 2519).

B11(fps10)--determine if count in document advance counter 8406, 8407 has reached 127 steps (gate 8411); If not, return to B2 (gates 2022, 2023, 2519); if so, proceed to B12 (gates 2008, 2010, 2020, 1607, etc.).

B12(fps11)--identical to B7 except that exit is to B13 instead of B8.

B13(fps12)--reset document advance counter 8406, 8407, to zero (gates 2527, 8414). Return to B2 (gates 2023, 2519).

B14(fps13)--reset document advance counter to zero (as in B13). Proceed as in step B6 except to exit to B15.

B15(fps14--set read complete flip flop 2106, 2107. Proceed to B16 (gates 2019, 2020, 1607, etc.).

B16(fps15)--no functions. Proceed to B1

III(A.11) READ PROGRAM OUTLINE

C1(rpso)--determine if proper conditions exist to initiate read program (gates 1704, 1601, 1607). Reset document advance counter 8406, 8407, (gates 2501, 2526, 2527, 8414). Proceed to C2 (gates 1607, 1625, 1627, 1628, 1626, and counter 2527).

C2(rps1)--fetch vertical format document advance number from memory (gates 4307, 4308, 4309, 6001, and associated memory cycle controls). Gate the ones complement of the fetched number into the document advance counter 8406, 8407 (inverter 8420; gates 8419, 8410, 8421-8427). Increment vertical format address counter 5201, 5202 (gates 6018, 6019). Store contents of horizontal format address counter 5104, 5105 in memory latches 5106, 5107 (inverter 5112). Store bit 8 of the addressed memory word in flip flop 1702, 1703 (gates 4701, 1701). At the end of the memory cycle proceed to step C3 (gates 4307, 4308, 4309, 1602, 1606, 1607, 1625, 1627, 1628, 1626).

C3(rps2)--examine contents of document advance counter 8406, 8407 (gate 8411). If original number was all zeros (i.e., DAT177 is low), set read complete flip flop 2106, 2107, (gate 2502) and return to C1 (gates 2505, 2519; flip flop 2520); if original number was not all zeros (i.e., DAT177 is high), proceed to C4 (gates 1603, 1606, 1607, etc.).

C4(rps3)--advance document until signal DAT177 goes low (gates 8428, 8415, 8408, 8409, 8410, 8403, 8404, 8405). Examine condition of flip flop 1702, 1703. If signal DAF8 is high when DAT177 is high, there is no line to read; obtain advance increment from memory and return to C1 (gates 2508, 2509, 2519, etc.). If signal DAF8 is high and DAT177 is high, read the line by proceeding to C5 (gates 1614, 1619, 1607, etc.).

C5(rps4)--when the read complete flip flop 2106, 2107 has been set, return to C1 (gates 2503, 2505, 2519, etc.). If the reading of a line has not been completed, and if there is no output of data in process, but the command to read is still present, preset counter 1713, 1714 (gate 1712) and proceed to C6 (gates 1615, 1619, 1607, etc.).

C6(rps5)--gate the horizontal format address from latches 5106, 5107 to the horizontal address counter 5104, 5105 (gates 5108, 5109, 5110; inverter 5111). Reset the scan counter 2801, 2802, 2803 (gates 3601, 3602). Proceed to C7 when the beginning of a line photocell assembly (photo-transistor Q1) is actuated (gates 1608, 1605, 1606, 1607, etc.).

C7(rps6)--read the line at the read station by performing the following functions:

a. at the beginning of the RPS6 step, preset the data address counter 5001, 5002, to a count of 44 (to be converted to a count of 88 by the memory address multiplexer) (gate 1901, inverter 1902, gate 5003, inverter 5006, flip flop 5007, gates 5008, 5009, inverter 5010, gates 5011, 5012).

b. enable scan mirror clutch/brake 8715, 8716 (gates 3802, 3803, 3703, 3704, 3705).

c. count scan slices at counter 2801, 2802, 2803 (gates 3703, 3701) and generate the scan duration signal SCDR (3807).

d. write the data and the scan count into the memory data section (gates 5601, 5602, 5603; flip flop 5604; and memory control circuitry).

e. detect and remember location of unrecognized characters (gate 5701; flip flop 5702, 5703).

f. perform line position analysis (reference description of line position analysis circuits).

g. if operating in vertical format mode, gate signal SCDR to provide the read enable signal RDEN for each character slice (gates 4317, 4316).

h. Generate the LINE COMP signal at the data address counter 5001, 5002 when the counter is full.

i. Proceed to C8 when the entire line has been read (gates 1616, 1619, 1607, etc.).

C8(rps7)--the line position analysis results in the generation of signals indicating that the character sensing array is filled, as well as pulses (FNAT) for initiating movement of the document during fine line adjust, and pulses (FNAC) to indicate that the fine line adjustment operation has been completed. Generation of these signals is described in the section dealing with line position analysis. If the array has been filled and a reject mode established, set the reject command and return to C1 (gates 1707, 2111, 2109, 2110, 2102 and inverter 2103; gates 2506, 2509, 2519, etc.). If the array has been filled and no reject mode has been established, proceed to C15 (gates 1707, 2516, 2517, 2519, 2521 through 2524, etc.). Determine if the fine line adjust procedure has been completed without the array having been filled (gate 1706): if there is no read error set the buffer full flip flop 5505 and return to Cl (gates 2529, 2530, 2504, 2505, 2519, etc.); if there is a read error after one attempt to recognize the previously unrecognized character (LTRY = 1), return to C6 (gates 2513, 2514, 2519, 2521 through 2524); if there has been a read error and the second try at recognition has been completed (LTRY = 1), proceed to C9 (gates 1617, 1607, etc.). Increment counter 1713, 1714, at the end of the RPS7 interval.

C9(rps8)--reset the horizontal scan counter 2801 through 2803 (gates 3602, 3602). When the scan returns to the beginning of the line proceed to C10 (gates 1608, 1605, 1606, 1607, etc.).

C10(rps9)--scan the line as many as four times if all characters are not recognized. Re-read only those characters not recognized during the RPS6 step.

a. Indicate the number of the current scan (gate 1715; counter 1713, 1714; gate 1716; inverter 1717).

b. Adjust photocell detection level in accordance with the number of re-scans (gates 1718-1721). If all the characters have been recognized or the ERR FLD signal is high, set the buffer full flip flop 5505 (gates 5704, 5702, 5703, 5502, 5503) and return to C1 (gates 1801, 1802, 2510, 2512, 2519, etc.).

d. If the ERR FLD signal is stilll high, and it is not the fourth scan of the line, return to C9 (gates 2515, 2517, 2519, etc.).

e. If the ERR FLD signal is still high, and the last re-scan attempt has been made, and a reject mode exists, set the reject flip flop 2109, 2110 and return to C1 (gates 1705, 2112, 2506, 2509, 2519, etc.).

f. If the ERR FLD signal is high, and the last re-scan has been attempted, and an error halt mode exists, proceed to C11 (gates 1705, 1604, 1606, 1607, etc.).

g. If the ERR FLD signal is still 1, and the last re-scan has been attempted, and an error substitute mode has been intiated, set the buffer full flip flop (gates 5501, 5503) and return to Cl (gates 2507, 2509, 2519, etc.).

C11(rsp10)--reduce scan motor drive to half speed in preparation for pointing to unrecognized character (gates 2531, 2532, 806; flip flop 805; counter 829; flip flop 836). When the scan mirror returns to the beginning of the line, proceed to C12 (gates 1608, 1605, 1606, 1607, etc.).

C12(rps11)--search for first unrecognized character in memory and place horizontal count of that character in the EPR register 2704-2706 (reference description in section on memory controls). Reset the horizontal scan counter 2801, 2802, (gate 3602). If all characters in the line are recognized, reset flip flop 5702, 5703 to drive the ERR FLD signal high (gate 5705). When the ERR FLD signal goes high, return to C1 (gates 2511, 2512, 2519, etc.). If the ERR FLD signal remains low, proceed to C13 (gates 1618, 1607, etc.).

C13(rps12)--enable the scan mirror clutch/brake 8715, 8716 (gates 3702, 3703, 3704, 3705). Advance mirror to cursor position (CRPS); allow for clutch/brake stop time by modifying the scan count to cause deacutation of the clutch/brake prior to reaching the cursor position (gate 3701; counter 2801-2803; adders 4001-4003; data registers 2704-2706; gates 3315 through 3828, 3302; inverter 3329). Upon reaching the cursor position proceed to C14 (gates 1609, 1613, 1607, etc.).

C14(rps13)--system in pause condition to permit manual entry of unrecognized character from keyboard; repeat reading of line; reject document; clear keyboard to enter complete line.

a. Enter character via the keyboard and return to C11 (flip flops 6202, 6204; gates 6203, 6205; flip flop 4502, 4503; gate 4504; gates 2518, 2519, 2521-2524, etc.).

b. Repeat reading of line and return to C6 (gates 8325-8329, inverter 8330; gates 2514, 2519, 2521 through 2524, etc.).

c. Enter complete line, clear the keyboard and proceed to C15 (inverter 8010; gates 1610, 1613, 1607, etc.).

d. Manual reject of document by operator and return to C1 (inverter 8331; inverter 2113; gates 2114, 2115, 2109, 2110, 2102, 2506, 2509, 2519, etc.).

C15(rps14)--return mirror and cam to beginning of line (gates 3706, 3705). Upon reaching beginning of line proceed to C16 (gates 1608, 1605, 1606, 1607, etc.).

C16(rps15)--system is paused for operator intervention in the form of entry of a complete line, repeat of a line, or manual reject:

a. Enter unrecognized character through keyboard (flip flops 6202, 6204; gates 6203, 6205; flip flip 4502, 4503; gate 4505).

b. Enter characters to fill memory, set buffer full flip flop, and return to C1 (gates 6320-6323, 1610, 1613, 1607, etc.).

c. Repeat line and return to C6 (gates 8325 through 8329; inverter 8330; gates 2514, 2519, 2521-2524, etc.).

d. Manual document reject and return to C1 (inverter 8331; gates 2116, 2113, 2114, 2115, 2109, 2110, 2102, 2506, 2509, 2519, etc.).

IIIA.11) MEMORY

III(A.II.2) GENERAL

The memory consists of 512 12-bit words and is constructed using 256 .times. 1 semiconductor static random access chips with 8-bit address decoders; chip-select (C/S) and read-write command (R/W) input signals are utilized.

FIG. 64 illustrates a memory module containing 24 each INTEL Model 1101 memory chips. There are 12 data input lines (MDI-1 through 12) and 24 data output lines (MDO-1 through 12, and MDO-1 through 12). Eight memory address lines MAD-1 through 8) select the 256 word positions of each chip. C/S-1 selects memory addresses 0 - 255; and C/S-2 selects memory addresses 256-511. When the write line R/W is high, the data on the data input lines MDI-1 through 12 is written into the memory position specified by address MAD-1 through 8 and C/S-1, C/S-2. Data output appears on lines MDO-1 through 12 corresponding to the contents of the position specified by address MAD-1 through 8 and C/S-1 and C/S-2. Driver circuits for the data output signals are illustrated in FIG. 65.

III(A.11.b) READ-WRITE

There are memory cycles which are referred to as Read Only and Wrtie/Read. The latter are controlled primarily by making the R/W line high at the correct time in relation to the data and address inputs. A read only cycle requires only the correct addressing of the memory.

III(A.11.c) SINGLE-DOUBLE CYCLE

There are also memory sequences which are referred to as single-cycle and double-cycle. In the single-cycle sequence a single data word is writtn into or read out of a specified address. In the double-cycle sequence two data words are written into or read out of two successive addresses.

III(A.11.d) MEMORY PARTITION

The memory is partitioned into three basic data areas.

Area one consists of 256 words selected by C/S-1 being low. This is the area allocated to the horizontal format information. Each field to be specified requires a beginning and end point, which are specified by the corresponding scan count stored in this portion of the memory. The 256 words are sufficient to specify a total of 128 fields on a document.

Area two consists of 86 (0-85) words selected by C/S-2 being low. This is the area allocated to the vertical format information. Therefore the maximum number of incremental advances from the top edge of the document to the first line to be read and to each succeeding line is 86. The maximum length document is 14 inches and the maximum number of lines per inch is 6; therefore 84 or 85 is the maximum number of memory words required for vertical format.

Area three consists of 168 (88-255) words selected by C/S-2 being low. This is the area allocated to hold the ASCII codes of eighty-four recognized characters and the corresponding scan count at the time at which the write command for that character was given. The writing and reading of data in this area is usually a double-cycle sequence. When data is read out to the output device, only single-cycle commands are used to extract the character codes since the scan position is no longer of interest.

III-A.11.e) MEMORY COMMANDS

There are ten distinct memory cycle commands which can be generated during the operation of the system. These are outlined as follows:

a. MCMA - (RPS1-INH) -- This is the command which obtains the vertical format data from the memory during a document read cycle.

b. MCMB - (ODRQ) -- This is the command which requests character codes from the memory for transmission to the output interface.

c. MCMC - (Read HORZ Format) -- This is the command which requests horizontal format data from the memory during a document read cycle.

d. MCMD - (Read Search) -- This is a command which is generated during RPS9 and RPS11 of the read program to search through the data portion of the memory to find the first character with a "character unrecognized" flag.

e. MCME - (Write Vertical Format) -- This is a command which is generated during FPS6, 11 and 13 of the format program to write vertical format data into the memory.

f. MCMF - (Write Horizontal Format) -- If the unit is in the horizontal format mode, during FPS8 of the format program, this command is generated to write the scan count and control bits into the memory for the control of horizontal format.

g. MCMG - (Write data during RPS9 rescan) -- During RPS9 rescan on the read program, only those characters which were not recognized during RPS6 are reread. Upon rereading, the recognized character codes or the substitute code for unrecognized characters is written into the memory. ##SPC1##

h. MCMH - (Keyboard WRITE) -- This is a memory write command generated by a keyboard entry during RPS13 or RPS15 of the read program.

i. MDMI - (MEM FILL) -- This is a memory write command which can be generated during RPS6, 9, 13 and 15 of the read program. It is used to fill the data portion of the memory with blank character codes following the last data character entered.

j. MDMJ - (Write data during RPS6) -- This is a double memory write cycle. The unit scans a line during RPS6 of the read program to attempt to read all characters in specified areas. Write commands from the recognition circuit cause the code and horizontal scan position of the character to be written into memory.

III(A.11.f) TIMING

Timing for the memory cycles is illustrated in the timing diagram of FIG. 35. Memory controls and timing circuits are illustrated primarily in FIGS. 54-63. The following description relates primarily to these figures.

The four read cycle commands MCMA, MCMB, MCMC and MCMD are OR'D, together by gate 6001 and inverter 6002 to initiate a read memory cycle. The six write cycle commands MCMF, MCME, MCMG, MCMH, MCMI, and MCMJ are OR'D together by gate 6003, which is part of a flip-flop with gate 6004, and inverter 6005 to initiate write memory cycles. Two memory commands MCMD and MCMJ are OR'D together by gates 6006 and 6007 to generate double-cycle commands; the other eight memory commands are single-cycle.

When a memory cycle command is initiated, the output of gate 6001 goes high and the output of 6002 goes low. If gate 6001 is high when MCYC (memory cycle complete) is high, gate 6008 enables the J input of flip flop 6009. At TPE time, gates 6010 and 6011 generate a clock pulse to change flip flop 6009 to the one state. This initiates the MCC1 portion of the memory cycle. On the following TPE pulse the same circuits generate another clock pulse to set flip flop 6012 to the one state. This initiates the MCC2 portion of the memory cycle operation. If this is a double-cycle memory operation, gates 6006 and 6007 would inhibit the K input to 6009, maintaining MCC1 and MCC2 until the next TPE pulse. If it is a single-cycle operation MCC1 would be reset when MCC2 goes on.

During a double-cycle operation MCC1 and MCC2 are on until the next TPE pulse when the MCC2 signal at gate 6007 allows flip flop 6009 to return to the zero state and terminate MCC1.

MCC1 on the MCC2 off defines the read/write portion of a single-cycle operation, or the first cycle of a double-cycle operation. Both MCC1 and MCC2 on defines the second read/write part of a double-cycle operation. MCC1 off and MCC2 on indicates that the memory cycle is complete (MCYC). For timing purposes a memory cycle complete delayed (MCYCDL) signal is generated by flip flop 6101.

The MCYS signal (Memory cycle start) is generated by gate 6021, when either MCC1 or MCC2 are on to indicate that a memory cycle is in process.

The write command R/W is generated at the required times by gates 6003, 6004, 6015; inverter 6016; flip flop 6017. The various timing pulses during the memory cycles are generated by gates 6102 through 6106 in FIG. 61. The RDST1 signal from gate 6102 is used to gate memory output data into registers at the end of the first memory cycle. The DAST1 signal from gate 6104 is used for various testing or gating of data previously stored in the registers. Signal RDST2 from gate 6103 gates memory output data into the output register at the end of the second part of a double memory cycle.

Signal MCYCPF from gate 6106 and signal MCYCPB from gate 6105 are used for various functions at the end of the memory cycle.

Memory cycle complete (MCYC or MCYCDL) are used to indicate the end of a memory cycle and signal the removal of the memory cycle command. The initiating command must be deactuated if the control logic is to cycle and turn off MCC1, MCC2, MCYS and MCYC.

Six of the memory cycle commands (MCMA, MCMB, MCME, MCMF, MCMH, and MCMI) cannot occur simultaneously with each other or any of the other four cycle commands. Memoryy cycle commands MCMC, MCMD, MCMG and MCMJ cannot occur simultaneously with the other six but could possibly occur simultaneously with each other. Therefore a priority circuit has been provided in FIG. 56.

III(A.11.g) MEMORY CHIP SELECT

Refer to Table M1 and gates 6301-6304 for the requirement anc circuits to generate chip select C/S-1 and C/S-2 signals.

III(A.11.h) DATA MULTIPLEXER SELECT

Refer to Table M1 and gates 6305, 6306, 6307 for the requirements and circuits to generate the data select control bits DSA and DSB. The actual data multiplexer is illustrated in FIG. 26. Data sources are discussed in more detail in another section.

III(A.11.i) ADDRESS MULTIPLEXER SELECT

Refer to Table M1 and gates 6308-6312 for the requirements and circuits to generate the address select control bits ASA and ASB. The actual address multiplexer is illustrated in FIG. 48. Address sources are discussed in greater detail in another section.

III(A.11,j) REGISTERS AND PULSES

There are three memory data output registers. The MDR register in FIG. 44 is a 10-bit register which holds data codes and vertical format data. The HCR register in FIG. 27 is a 12-bit register which holds horizontal count data for horizontal format control. The EPR register in FIG. 27 is an 11-bit register to hold horizontal count for unrecognized character RPS9 rescan during the read program.

Refer to Table M1 and gates 6308, 6310, 6313, 6314, 6315 for the requirements and circuits for generating the MDRST signal which is used to gate data into the MDR register.

Refer to Table M1 and gates 6316, 6317 for the requirements and circuits for generating the HCRST signal which is used to gate data into the HCR register.

Refer to Table M1 and gates 6318, 6319 for the requirements and circuits for the EPRST signal which is used to gate data into the EPR register.

III(A.12) DATA MULTIPLEXER

DATA SOURCE

The data multiplexer is illustrated in FIG. 26. Logic associated with the data multiplexer is illustrated in FIG. 30.

Table M2 shows which data sources are selected by the six memory write commands MCME, MCMF, MCMG, MCMIM and MCMJ to be placed on the 12 memory data input lines MDI-1 through MDI-12.

There are four primary data sources:

a. Recognition circuit data codes RDC1-RDC8

b. Scan counter output SCC1-SCC11

c. Document advance step counter DAC1 through DAC7 and DAT177

d. Keyboard input Code KDC1-KDC8.

These are generated as follows:

a. Recognition Circuit Data Codes

The 8 -bit ASCII (odd parity) data codes are generated by the Recognition Circuitry and are transmitted to the circuit of FIG. 26, upon request, during RPS6 and RPS9 of the read program. The 8 bits RDC1-8 are so transmitted with a write command OCRW, which is received at the circuit of FIG. 56 where it initiates memory cycles MCMG and MCMJ.

b. Scan Counter

The scan counter (FIG. 28) consists of three counter sections 2801, 2802, 2803. The clear signal (SCCLR) and the count pulses (SCCT) for the counter are generated in the circuits of FIGS. 36 and 37, respectively. Scan Counter

TABLE M2 __________________________________________________________________________ MEMORY DATA MULTIPLEXER MCMF MCMF MCMG MCMH MCMI MCMJ WRITE WRITE RPS9 RPS13, 15 RPS6,9,13,15 RPS6 RPS6 VERT. HORT. DATA KEYBOARD MEMORY WRITE WRITE SCAN FORMAT FORMAT WRITE ENTRY FILL DATA COUNT __________________________________________________________________________ DSA 1 0 1 0 1 1 0 DSB 1 0 0 1 0 0 0 MDI-1 DAC1 SCC3 RDC1 RDC1 0 RDC1 SCC3 2 DAC2 SCC4 RDC2 RDC2 0 RDC2 SCC4 3 DAC3 SCC5 RDC3 RDC3 0 RDC3 SCC5 4 DAC4 SCC6 RDC4 RDC4 0 RDC4 SCC6 5 DAC5 SCC7 RDC5 RDC5 0 RDC5 SCC7 6 DAC6 SCC8 RDC6 RDC6 0 RDC6 SCC8 7 DAC7 SCC9 RDC7 RDC7 0 RDC7 SCC9 8 DAT177 SCC10 RDC8 RDC8 1 RDC8 SCC10 9 0 SCC11 RERF 1 1 RERF SCC11 10 0 FIRST FIELD RERF 0 1 RERF SCC1 11 0 RDC1 0 0 0 0 0 SCC2 12 0 RDC2 0 0 0 0 0 __________________________________________________________________________ Notes: (1) First Field - "1" for first word of horizontal format of each line. "0" for all other horizontal format words. (2) MDI9/10 - RERF/RERF. MDI9=1, MDI10=0 for recognized clar. MDI-9=0 -- MDI-10=1 for unrecognized clar. Clear (SCCLR) is generated by gates 3601, 3602, during format program step FPS7 and read program steps RPS5, RPS8, and RPS11, all of which occur previous to enabling of the scan counter. MPS5 keeps the scan counter reset until the format and read program counters are enabled.

Scan counter count pulses (SCCT) are generated by gates 3701, 3702 and 3703. MUX 63 us a pulse which occurs every 64th TPF pulse; this is the horizontal scan sample frequency. The SCSP (scan stop) signal is normally high until the scan counter reaches a predetermined count selected by the document width selector. BOL (beginning of line) is a signal from a mechanism photocell (phototransistor Q1) which senses a window in the cam which operates the scan mirror. BOL is low when the cam positions the mirror at a dwell when the scan is at the left hand margin of the page. When the clutch and brake are engaged the cam is coupled to the synchronous scan motor 8717. BOL goes high just before the cam follower comes off the dwell and the mirror begins its scan. This provides a consistent reference point at which to begin the scan count during each scan.

Gates 3801-3803 generate the SCAN CONTINUE signal during read program steps RSP6, RPS9 and format program step FPS8 to initiate the energization of the clutch/brake 8715, 8716. SCAN CONTINUE goes to gate 3703, which actuates gates 3704 and 3705 to provide the clutch/brake energize signal. Gate 3706 insures that the clutch/brake stays energized until the cam window returns to BOL except during read program steps RPS12 and RPS13. These are the two program count steps which control the mirror to point to an unrecognized character in the Error Halt mode to allow for keyboard entry.

Gates 3802 and 3804 set a flip-flop 3805, 3806 at an early scan count to enable the SCDR (scan duration) signal from gate 3807. SCDR in turn provides a RDEN (read enable) signal, via the circuit of FIG. 43, to the Recognition Circuits. Gates 3808-3811 set flip-flop 3812, 3813 at different counts and conditions to provide the SCSP (scan stop) signal and turn off the SCDR signal. During format program step FPS8 scan counts are stored in the memory to provide begin and end of field positions. During read program step RPS6, each data write command (OCRW) from the Recognition Circuitry causes the character code and character scan position count to be stored in memory (reference gates 5601-5603; flip 5604; and FIG. 28).

c. Document Advance Counter

The document advance counter is illustrated in FIG. 84 and consists of a series of gates to control the 7-bit counter 8406 and 8407 and to generate the DCMT (Document Motor Toggle) pulses. This counter circuit serves two purposes. During format load it counts the steps of motor 500 required to advance the document at the read station from the top edge to the first line mark, and the number of steps to advance to each succeeding line mark. During read mode the counter controls the number of steps required to advance the document from line to line. During format load the seven output bits DAC1 through DAC7, and the "all ones" condition DAT177, are used. In general the format program counter advances the conditioning document until it centers the line mark in the read array or the counter reaches all ones; i.e., DAT177 goes low. When a line mark is centered in the array, a memory write cycle (MCME) is initiated which writes a number into the vertical format portion of the memory. The number represented by DAC1-7 is neither all ones nor all zeros. and DAT177 is high and therefore is written into the memory as a one. If the counter reaches all ones before finding the next line mark, the document advance command must be written into memory, but is accompanied by a flag to command the advancing of the document without a command to read a line. In this case signals DAC1-7 are all ones and DAT177 is low at gate 8411, which results in a zero being entered for this bit. With continued advance of the format document, the end of the document eventually appears, and a command must be written into the vertical format memory position to indicate this. When the end of document appears the format program counter causes the document advance counter to be reset to zero and a MCME memory write command is initiated. Signals DAC1-7 all become zero and DAT177 becomes high.

During read program mode step RPS1, read vertical format memory cycles (MCMA) are initiated. The 7-bit count (DAC1-7) is obtained from the memory and its ones compliment is used to preset the document advance counter 8406, 8407. The bit corresponding to DAT177 is designated MDAF8 and is gated by gate 1701 and stored in flip-flop 1702, 1703. Three operations can result from this vertical format data. If DAC1-7 is not all zeros or not all ones and DAT177 (DAF8 at gate 1702 output) is high, this is an indication that the document should be advanced to read a line. The control circuits advance the document motor 500 the number of steps required to make the counter output (DAC1-7) all ones, forcing DAT177 low. When such conditions exist the document has been advanced the number of counts originally determined by the conditioning document. If the original count DAC1-7 had been all ones, forcing DAT177 low, presetting the counter to the ones complement from the memory places zeros into the counter. DAT177 being low or zero results in DAF8 at flip-flop 1702, 1703 being low. This then causes the document to advance the number of steps to again make DAC1-7 all ones and DAT177 low. With DAF8 having been set to zero there is no command to read a line. When the end of the document is reached DAC1-7 is set to all zeros. When this is read out of memory and its ones complement is preset into the count, the counter becomes all ones. DAT177 had been high during the write command so DAF8 becomes high. As described in reference to read program counter operation, RPS1 obtains the vertical format count from memory and places the ones complement into the counter. RPS2 examines the DAT177 output gate of the counter. If DAT177 is low the present contents of the counter is all ones, and the count read out of memory is all zeros. This sets the Read Complete flag. If DAT177 is high, the read program counter continues for further processing.

The document advance counter is also used during the document pick process to count the number of steps required to cover the skew station photocells. The count after one of the photocells is covered and stops when two are covered. At three lines per inch operation, two steps are allowed and three steps are considered a skew error (SKER goes low at gates 8401, 8402). At six lines per inch, one step is allowed and two steps is a skew error.

During load format, when a line mark is found and the step count is written into memory, the document is advanced a fixed number of steps before the system looks for the next line mark. At three lines per inch the document is advanced twelve steps and at six lines per inch it is advanced six steps. The line called DAT12 from gate 8412 and inverter 8413 indicates that the counter has reached the count of 6 or 12 as required.

d. Keyboard Input Code KDC1-KDC8

The keyboard data input is used primarily during RPS13 in the read program for the manual entry of unrecognized characters. The keyboard code comes through inverters as illustrated in FIG. 80 and from there go to the data multiplexer in FIG. 26. During RPS13 and RPS15 the keyboard entries generate memory write commands MCMH.

III(A.13) ADDRESS MULTIPLEXER

The memory is partitioned into vertical format, data, and horizontal format sections which are discussed elsewhere herein. These three sections have independent address controls for which appropriate counters are provided.

The vertical format address counter is illustrated in FIG. 52 and consists of 7-bit counter 5201, 5202 and output gate 5203. The counter is held in the reset condition except during step MPS5 of the master program operation when either a load format or read operation is progressing. Signal VFADT is the count pulse which is generated by gates 6018, 6019. During format load, a memory write cycle signal MCME causes a VFADT pulse to be provided at the end of the write cycle. During document read a memory read cycle signal MCMA causes a VFADT pulse to be provided at the end of the memory cycle. Gate 5203 generates a signal VFAT86 when the vertical format address counter 5201, 5202 has reached a count of 86 and exceeded the allotted count. The data address counter is illustrated in FIG. 50 and includes counter elements 5001, 5002 and associated gates. At various times, as controlled by the signal ADSO into gate 5003 and the KBCLR signal at read program step RPS15 at gate 5004, the data address counter is preset to a count of 44. The low order bit of the counter DAD1 is gated in FIG. 48 as the second least significant bit of the memory address MAD-2; similarly the other counter bits are displaced. This has the significant effect of multiplying the starting address by two. The data address represented by DAD1-DAD7 thus starts at memory position 88. Certain of the data memory cycles are double cycle operation where data codes are written into or read out of the memory on the first part of the cycle, and the scan count position of the character is written into or read out of the memory on the second part of the memory. That is, addresses 88, 90, 92, etc. contain character codes whereas addresses 89, 91, 93, etc. contain scan counts SCC1-SCC11. A signal MCC2 is generated by the memory controls to go high during the second part of a double cycle memory operation. This signal goes to the address multiplexer (FIG. 48) to act as the low order bit (MAD-1) of the data address. A line complete signal is generated after 84 data write or read commands. That is, the counter starts at 88 and adds 2 x 84 memory cycles for a final count of 256. The counter is advanced by the DADT signal (data address toggle) which is generated by gates 5401-5404 in the memory control circuitry. The horizontal address counter consists of counter elements 5104, 5105 and associated circuits in FIG. 51. The horizontal format has been allocated 256 words of the data memory; therefore it requires a full 8-bit address count. The counter is normally held in the clear state except during step MPS5 of the master program. During load format mode, at the end of document, FPS14 of the format program acts through inverter 5303 to store the last horizontal format address used in storage units 5301, 5302. During document read operation this last used format address is compared with the address counter by gates 5304 through 5312. When the last address is reached during read operation, this circuit, with inverter 5313, signals that the horizontal field is complete and, eventually, that read operation is complete (via gate 2106).

Due to the rescan feature it is necessary to be able to restore the horizontal format address for the beginning field of each line. Therefore, at RPS1 time in the read program, the horizontal format address is stored in memory units 5106, 5107. At RPS5 and RPS8, just before read cycles RPS6 and RPS9, respectively, this stored count is preset into the counter 5104, 5105 via gates 5108-5111. During a normal read operation the read program counter goes in sequence. RPS0, RPS1, RPS2, RPS3, RPS4, RPS5, RPS6, RPS7 and back to RPS0. The address count is stored in the memory units 5106, 5107 at RPS1, the counter is preset during RPS5, the counter is advanced during RPS6 and the new count is set in the latches at RPS1, etc. With a rescan, the sequence goes from RPS7 back to RPS5 and then to RPS6. This bypasses RPS1, and at RPS5 the previous initial count is restored to the address counter 5104, 5105. This also occurs during RPS9 rescan, returning to RPS7 and then RPS8.

The horizontal address counter is advanced by the HFADT signal (horizontal format address toggle) via gate 5110. This signal is generated by gates 4302, 4303, 4304 and 4305. Gate 4302 advances the counter at the end of a memory write cycle during step FPS8 of the format program; i.e., during format load. Gates 4303 and 4304 generate the advance pulses at the end of memory read cycles for horizontal format. The HCR10 signal is derived from the memory bit which indicates that horizontal format data is the beginning of the first field of a line; this must occur with the first field of line flip-flop 4306. As the reading of a line progresses and the horizontal format control is read out of memory, eventually the data for the first field of the next line is read out with signal HCR10 high. This inhibits the horizontal format memory address counter so that the counter is at the correct address for the beginning of the next line.

III(A.14) VERTICAL FORMAT

Write and Read Operation

Referring to the outline for the Format Program Counter, steps FPS6, FPS11 and FPS13 are memory write cycles for vertical format. These three signals are "or'd" together at gate 2003 to generate a memory cycle signal MCME via inverter 2004. This signal in turn goes to gate 6003 in the memory controls to initiate a single cycle memory wrtie operation. The Data Multiplexer selects the Document Advance Counter as the data source and the Address Multiplexer selects the Vertical Format Address as the memory address. The memory cycle complete (MCYCDL) signal from flip-flop 6101 enables the format program counter to advance, and the vertical format address counter is advanced. The three different possible data contents and their meaning, as obtained from the document advance counter, are described hereinabove.

Referring to the outline for the Read Program Counter, step RPS1 requires a memory read cycle for vertical format. Gates 4307, 4308, 4309 generate the RPS1-INH (MCMA) signal which is the Read Vertical format memory command. When RPS1 goes high, gate 4309 provides a negative MCMA signal which initiates the memory cycle at gate 6001 in the memory controls and inhibits the advancement of the Read Program Counter at gate 1602. At the memory cycle complete time, signal MCYCPB resets flip-flop 4307, 4308 and turns off MCMA, allowing the Read Program counter to advance. The use of the memory output to preset the document advance counter to the ones complement has been described hereinabove.

III(A.15) RECOGNITION DATA

Write and Read Cycles

There are four different memory commands associated with the data from the Recognition Circuits. They are as follows:

a. RPS6 - Original scan and read of complete line

b. RPS9 - Rescan of previously unrecognized characters

c. RPS11 & RPS13 - Keyboard entry to replace unrecognized characters.

d. ODRQ - Output data request from peripheral interface. a. Memory cycle signal MCMJ is generated in the circuit of FIG. 56 during each RPS6 read enable period by OCRW commands from the recognition circuits. MCMJ is a double cycle write memory operation. During the first half cycle the ASCII code generated at the Recognition Circuits is written into memory. On the second half cycle the scan count (SCC1-SCC11) associated with the position of the recognized character is written into the next memory word position. Refer to Table M1 (memory cycle summary) for the data and address multiplexer operations. Memory cycle signal MCMJ is generated by gates 5601-5603 and flip-flop 5604. b. Memory cycle signal MCMG is generated during each RPS9 on rescan of previously unrecognized characters. MCMG is a single cycle write memory operation. Memory cycle signal MCMG is generated by gates 5605, 5606, 5607 and flip-flop 5608. Data and address sources and multiplexer operation are similar to MCMJ during RPS6 and are described hereinabove. c. In the Error Halt mode, if there are still unrecognized characters after four RPS9 rescans, the system projects the unrecognized character onto a screen for operator viewing. The data address counter has been advanced to the address of the unrecognized character. The unit system pauses at RPS11 to enable the keyboard for operator entry of a character from the keyboard. The keyboard data comes through the circuit of FIG. 80 to the data multiplexer. The keyboard data strobe signal (KBST) goes to gate 6201 to generate a write command KBDW. This signal goes to memory cycle flip-flop 4502, 4503 to generate the memory cycle signal MCMH. d. When a line of recognized data is ready to be transferred out of the system, the buffer full (BUFFL) signal from gate 5507 goes to flip-flop 7307, 7308 and, via gate 7311, initiates data output sequences. BUFFL enables the line data available (LNDAV) signal to the output unit. Data Request signals from the output unit generate the output data request signal (ODRQ) at gate 7312 and inverter 7313. These signals initiate memory read cycles for data to be placed on the output interface. ODRQ commands generate MCMB memory cycles. Table M1 shows some of the requirements for this operation.

III(A.16) HORIZONTAL FORMAT

Write and Read Operation

The horizontal format memory operations consist of write cycles during load format program count FPS8 and read cycles during read program counts RPS6 and RPS9.

a. FPS8 -Write Operation or Load Format

During format load with horizontal format control the system positions the conditioning document at each vertical format line mark. At each line the unit then scans across the line to read the field-identifying character. For each field there are begin and end of field characters. The position of the characters, as defined by the scan count (SCC1-SCC11) at the position the character is recognized, defines the begin and end positions of the field. The characters printed on the conditioning document are used to define various parameters for each field. Referring to Table M2 "Memory Data Multiplexer" and the column for memory cycle MCMF, it is noted that only the nine high order bits of the scan count (SCC3-SCC11) are stored in memory to define the field position. The horizontal scan counter is counting at a rate of 145 character slices per inch. For OCR-A font characters at ten pitch, each character is equivalent to 14.5 slice counts. By dropping the two low order bits, the variation of field position may vary a maximum count of three out of 14.5, or approximately 1/5 of a character space. This was done to conserve memory. It is possible to expand the memory word length from 12 to 16 bits; in doing so, the ten high order bits of the scan count (SCC2-SCC11) can be stored and only the low order bit SCC1 would be dropped. This would provide better precision in defining the begin and end positions of the field.

Referring again to the same columns of Table M2, it is noted that memory input bits 11 and 12 are the two low order bits (RDC1, RDC2) of the ASCII code for the character which has been read. This means that the begin of field character can specify four conditions or parameters, and the end of field character can specify 4 more. The system as disclosed is set up for the following control by the begin of field character:

Character RDC2 RDC1 ______________________________________ 0 0 0 Handwriting 1 0 1 Not assigned 2 1 0 Farrington 7B Font 3 1 1 OCR-A Font ______________________________________

The two low order bits of the end of field character are presently used to control the pitch (characters per inch) parameter and the mark sense control. Each of the fonts has the two following pitches:

OCR-A 10 and 8 characters per inch Farrington 7 and 6 characters per inch Handwriting 5 and 4.3 (4.0) characters per inch

The low order bit RDC1 controls the pitch. If RDC1=0, the higher density pitch is selected; if RDC1=1, the low densith pitch is selected.

The second end of field bit (RDC2) is used to control the mark sense. If RDC2=0, any extraneous marks or other conditions which result in an unrecognized character cause the system to operate in the normal rescan mode, with the results determined by Operate Mode Switch. If RDC2=1, it is anticipated that this is a mark sense field wherein a mark results in an unrecognized character, or the OCR-A symbol for overstrike. The substitute code for an unrecognized character (underline) or the code for the overstrike is placed in memory. In this case the read error flag is inhibited for this field, and no rescans are requested.

If the memory-word size is expanded, the four low order bits RDC1, 2, 3, and 4 of both the begin and end of field characters can be stored. Table M3 shows a possible assignment of the functions and parameters to be controlled by the begin of field character. The end of field character bits are left unassigned, and are available for any function to be added in the future.

One bit of the horizontal format memory word is used to identify the first character of the first field of each line. This is required to separate the groups of horizontal format words of each line. It is possible to provide a memory parity bit to make the 16-bit word odd parity. The system as disclosed has a parity bit for the ASCII data codes only. This can be retained if the additional parity bit is used but the added parity bit enhances the integrity of the vertical and horizontal format control. The FPS8 memory cycles (MCMF) are initiated at gate 4302 by the OCRW write commands from the Recognition Circuit.

b. RPS6/RSP9 - Read Operation of Horizontal Format

The circuits for controlling the memory read operations for horizontal format are illustrated in FIG. 43. The operation consists essentially of obtaining the format word for the beginning of the first field and storing the scan count bits from the memory in the HCR register of FIG. 27. The output of this register is compared with a modified scan count

TABLE M3 __________________________________________________________________________ HORIZONTAL FORMAT BEGINNING OF FIELD CONTROL CHARACTERS __________________________________________________________________________ HEX Code Usable Control CONTROLLED FUNCTIONS of 4 LSB Characters Font Pitch LPI Mark Sense __________________________________________________________________________ 0 0 P OCR-A 10 3 No 1 1 A Q OCR-A 10 6 No 2 2 B R 7B 7 3 No 3 3 C S HAND 5 3 No 4 4 D T OCR-A 8 3 No 5 5 E U OCR-A 8 6 No 6 6 F V 7B 6 3 No 7 7 G W HAND 4.3(4.0) 3 No 8 8 H X OCR-A 10 3 Yes 9 9 1 Y OCR-A 10 6 Yes 10 J Z -- 11 K -- 12 L OCR-A 8 3 Yes 13 M OCR-A 8 6 Yes 14 N -- 15 -- __________________________________________________________________________ SCC3 and SCC4M through SCC11M by the exclusive-OR circuits at the top of FIG. 33. When the modified scan count equals the count in the HCR Register, the signal "HZ SCAN COMPARE" is obtained from output gate 3301. This signal goes to gate 4310 to operate flip-flop 4311. With the flip-flop toggled to the one state, the Read Enable (RDEN) to the Recognition Circuits is turned on and a request is made to the controls to provide the next horizontal format word from memory. Again this word is stored in the HCR register, replacing the previous count. When the modified scan count equals the count in the HCR register, the "HZ Scan Compare" signal toggles flip-flop 4311 back to the zero state, turning off the RDEN signal, and thereby requesting the readout of the next horizontal format word from the memory. Each time a new horizontal format word is obtained from memory, memory bit number 10, which is stored as HCR-10 in FIG. 27, is examined. If HCR-10 is a one (high), this indicates that the current format word is the first horizontal format word for a line. When initially going into RPS6, RPS9 and FPS8, flip-flop 4306 is reset to a zero condition. This flip-flop (First Field of Line) is used to force the acceptance of the first horizontal format word from the memory and enables the generation of a horizontal format address count pulse (HFADT) at gate 4305. Flip-flop 4306 is toggled to the opposite state by the first HFADT and stays there until the system goes out of steps RPS6, RPS9, or FPS8. With this flip-flop in the toggled position, HFADT is generated for only those horizontal format words in which HCR10 is zero (low). If HCR10 is high, flip-flop 4312, 4313 is set and prevents generation of further read enable signals for the remainder of the scan in operation. HFADT is also inhibited so that the horizontal format address counter stays at the last address. When the next line is scanned, the address for the horizontal format word is the correct one.

Previously it was noted that the contents of the HCR register (FIG. 27) were compared with a modified scan count. Since the conditioning document requires a printed character for begin and end of field, it may appear that the end of one field and the beginning of the next must be at least one character (or 0.1 inch) apart. The effective end of the field is stretched by the following method. In FIG. 39, gate 3901 and 4-bit adders 3902 and 3903 subtract a count of 8 from scan count SCC4-SCC11 to provide a modified count of SCC4M-SCC11M. This is only performed when HFAD1 is low; that is, when the state of the low order bit of the horizontal address counter is low while waiting for the end of field. By substracting eight from the scan count, the counter must go an extra eight counts before the end of field horizontal scan compare signal is obtained. Therefore, the end of field is stretched eight counts. At the highest density of ten characters per inch, each character position is equivalent to 14.5 horizontal scan counts.

Memory read cycles for horizontal format are initiated by the signal "EN RD HZ FT" generated by flip-flop 4314, 4315. This signal goes to the memory priority circuits 5609-5611 to generate memory cycle signal MCMC. Refer to Table M1 memory cycle summary for various functions for this memory cycle.

For horizontal memory read cycles, memory output bits MDO-1 through MDO-10 are gated into registers 2701, 2702 and two of the four bits of register 2703 by the signal HCRST. Memory output bits MDO-11 and 12 are gated into the other two bits of 2703 by the HCRST signal gated with signal HZAD1 being low at gate 3202. This provides storage in HCR-11 and HCR-12 of the two low order bits of the format character designating the beginning of field. The two bits of the character for end of field are stored in register 2901 via gate 2902 at HCRST time when HZAD1 is high. As a result of the timing of the operation these control bits are always available during any Read Enable times.

III(A.17) RESCAN (RPS9)

The previous paragraphs described the horizontal format operations during the full line read cycle of RPS6 and the unrecognized rescan cycle of RPS9. The same horizontal field position and control information is needed during RPS9 as RPS6. The essential difference during RPS9 is that a search is made through the memory to look for the unrecognized character flags. When such a flag is found the associated scan count position of that character is also read from memory and placed in the EPR register 2704, 2705, 2706. This count corresponds to a position just to the right of the unrecognized character and it is required to actuate Read Enable at gate 4316 at a position just to the left of the character. This is accomplished by three 4-bit adders illustrated in FIG. 40, which add variable counts to the scan count depending on the pitch of the characters. This modified count (SCC1P-SCC11P) goes to exclusive-OR circuits in FIG. 33 and is compared with the count in the EPR register 2704-2706. When the counts compare, a signal "ERR SCAN COMPARE" is generated by gate 3302.

The read search process for unrecognized character is performed by circuits illustrated in FIG. 54. RPS9 going high enables the output signal RD SEARCH from gate 5405. This signal goes to gates 5612, 5613 at the memory priority circuits to generate the memory cycle signal MCMD (see Table M1 for summary of operation). At memory cycle complete delay time (MCYCDL), gate 5406 inhibits gate 5405 and turns off the RD SEARCH signal. MCYCDL resets and allows another RD SEARCH signal. This continues until flip-flop 5407, 5408 is turned on by either gate 5409 (which senses the unrecognized character flag) or the line complete signal. If flip-flop 5407, 5408 is turned on by the unrecognized character flag, the data address counter is not advanced (DADT inhibited at 5404), any further RD SEARCH signals are temporarily inhibited, and gate 5410 is enabled. At Error Scan compare time gate 5410 turns on flip-flop 5411, 5412, which is the Read Enable flip-flop for error characters. Within a character time the Recognition Circuits provide a write command (OCRW) for either a recognized or unrecognized character. This write command during RPS9 initiates memory cycle MCMG from flip-flop 5608. The OCRW signal resets the Search Complete flip-flop 5407, 5408 and inhibits the RD Search gate 5405. As soon as the MCMG memory cycle is completed the OCRW signal is removed and gate 5405, generating the RD Search signal, is again enabled. This continues through the data memory until the 84th character is tested at which time the Line Complete Signal stops this process.

III(A.18) LINE POSITION ANALYSIS

a. General

The line position analysis circuits are illustrated in FIGS. 66 through 72 and perform three primary functions. The first function is operative format load when the circuits perform an analysis of the format conditioning document. This function involves the sensing of vertical format marks in the left hand margin of the document page, and also involves providing an indication both when a mark is detected and when it is centered in the array. This indication signals the format program counter to take the document advance count and store it in the vertical format portion of the memory. The second function of the line position analysis circuits occurs during the read mode. As the system reads a line it determines the vertical position of the complete line of characters on the document with respect to the array. If the line is not perfectly centered in the array the circuits determine how far, and in which direction, the line is off center. The system then initiates a fine line procedure to reposition the line as close to the center of the array as possible. If there is an unrecognized character during a scan, the fine line adjust procedure positions the line closer to the center of the array for the rescan. In any event the line is repositioned with respect to the center of the array before the next line is read.

The third major function of the line position analysis circuits occurs when the system is reading at six lines per inch. Under these conditions a shorter scan region, consisting of a restricted number of the sixty photo-diodes, is utilized. When reading at six lines per inch the system controls a vertical window which enables only fifty of the signals from the photo-diode array. The line position analysis, during six lines per inch operation, determines the vertical position of each sample of a line and provides a "line following" control. That is, if the line is skewed either up or down with respect to the array, the recognition circuitry is instructed to move the vertical window. The fifty enabled bits then proceed up or down to follow the line. This function significantly increases the reliability of automatic reading at six lines per inch, which is the spacing for single space typing.

The line position analysis circuitry performs its function by accumulating data from the MUXSD (MUX serial data) line. In the quantizer-multiplexer circuit in the recognition circuitry, the 60 bits of data from the photo-diode amplifiers are compared with an adjustable threshold level and the sixty bits are then quantized into either black (ones) level or white (zeros) level. These sixty bits are gated into a 64-bit shift register, and the two upper bits and two lower bits of the shift register are forced into a white (zero) condition. Therefore, the sixty bits of the photo-diode array occupy the middle 60 bits of the 64-bit shift register. The quanti-multiplexer circuit also contains a six-bit counter which counts from zero through 63. While at the count of 63, the counter generates a signal designated MUX63. This is a signal which coincides in time with the trailing edge of TPF. Another signal used in the circuitry is called MUX63G (gated). This is generated by gating the MUX63 signal with the TPF timing signal.

The 60 signals from the photo-diode array are gated into a 60-bit parallel holding register. These 60 signals then are gated into the 64-bit parallel to serial shift register. The output of the shift register is shifted continuously at the leading edge of TPA. The MUX63 signal indicates when the last (or the 63) bit of the 64-bit shift register is being shifted out. The quantizermultiplexer circuit then provides a serial string of data, consisting of 64 bits, which scans 60 photo-diode array from the top to the bottom of a line to be read. This is the data which is gated and circulated into a 64 bit shift register 6816 in the line position analysis circuits. The recirculating portion of shift register 6816 consists of two 32-bit MOS registers, the output of the first 32 bit register shifted into four eight-bit serial to parallel shift registers 6818-6821. Gates 6822-6828 sense the parallel output from the shift registers to detect certain numbers of adjacent black (one) and white (zero) bits. The output of gates 6824-6826 set and reset the SRQ flip-flop 6830. Within the line position analysis circuits this flip-flop output signal is called SRQ (serial register Q output). For the purpose of the analysis described herein the SRQ output signal is also identified as a mark. In load format a mark is defined as seven adjacent black (or one) bits. In the read mode, a mark is considered to be seventeen adjacent black (or one) bits.

During step FPS4 of the load format program, a line position analysis is performed. Step FPS4 causes one vertical scan period of MUX serial data to be gated (via gates 6806, 6807, 6808, 6814) into shift register 6816. During the next period from one MUX63 to the next MUX63, the output of shift register 6816 is analyzed to determine if there is a mark (or seven continuous black bits) in the register. The circuitry also determines the position of this mark with respect to the center of the shift register. This analysis thus determines whether or not there is a mark in the array and the relative position of that mark. The results of this analysis are used by the format load circuitry in a manner previously described to control the progression of the format load program counter.

During steps RPS6 and RPS10 of the read program, the MUXSD (data) is gated into the shift register 6816. The gating may remain open for many cycles of MUX63. This has the effect of superimposing many scans of the MUXSD data on one another. As it is being scanned across the shift register, the line is divided into segments. These segments may consist of 0.8 inch character portions of the line, or may consist of shorter segments associated with fields in horizontal format. The effect of accumulating multiple scans of MUXSD into the shift register of the line position analysis circuits is to effectively take a segment of data and squeeze it sideways to render it the equivalent of one continuous vertical line. Normally the tallest character of OCR-A font is approximately 18-20 photo-diode elements high. If within any one segment the characters are vertically misaligned or the line is skewed, the horizontal projection of that section of line may result in a set of black elements in the serial data which could be much higher than the 18 to 20 elements of a character. This effectively provides the system with a horizontal projection of the black bits occurring over the entire segment. The line position analysis program counter consists of a three-bit synchronous binary counter 6609. This provides eight steps, or LPSO through LPS7, decoded by decoder 6628, for the line position analysis program. LPSO is a holding position in which shift register 6816 is disabled or erased. The unit is enabled to advance from LPSO to LPS1 during the FPS4 step of the format program, and during the scan duration steps RPS6 and RPS10 of the read program. During LPS1 gates 6809, 6814, 6806, 6807, 6808 allow the accumulation of MUXSD into the shift register.

Appropriate conditions, discussed below, command the system to advance from LPS1; the succeeding program steps perform the analysis. One of the analyses involves counting (via counters 6719, 6720), the number of zeros or white spots in the MUXSD, starting at the top of the array and stopping when the unit sees a mark or reaches a maximum number of zeros. The white or zero count at the top of the array is transferred to the A registers 7001, 7002. When a mark is detected, the zero counter 6719, 6720 is reset, and after the mark passes out of the end of the shift registers, the zero counter is used to count the number of zeros or white spots following the mark up to the end of the MUXSD data stream. Another register, designated the B registers 7003, 7004 is utilized to store the minimum count of the number of zeros detected below the mark. MUX63 is used to synchronize the beginning and end of the MUXSD data stream.

The line position analysis circuits also contain another counter called the mark center counter 6706, 6707. This counter is used to determine the center of any mark in a segment with respect to the top of the array or the beginning of the MUXSD. This is accomplished by counting all the zeros or white spots above the mark and half of the black or one bits of the mark. After the mark is shifted out of the shift register 6816, the system no longer counts zeros entering the mark center counter 6706, 6707. After processing one cycle of the accumulated data in shift register 6816, the mark center counter contains a count which indicates the center of the mark with respect to the top of the array. This count is utilized in the "line-following" procedures of reading at six lines per inch. Counter 6706, 6707 is also utilized during steps RPS6 and RPS10 of the read program and determines the center point of each segment as the unit scans across a line. The center count of each segment is utilized to control the vertical window position of the succeeding segment, thereby providing a predictive position for the next segment.

For purposes of load format, the line position analysis circuitry provides two signals. The first signal is designated MARKCD (mark centered). The second signal is LPER (line position error). At the end of the line position analysis during format program step FPS4, the MARKCD signal is high if the system has detected a mark of at least seven black elements in height and located within the center range as determined by the circuits. Signal LPER indicates one of the following error conditions:

1. Array filled. An array filled condition occurs if all 38 bits of the blacks enable window (which is used during load format) are black; that is, the mark that has been detected is at least 38 elements high.

2. Double mark. This condition occurs if two marks at least seven black elements high are detected within the blacks enable window of 38 elements.

3. Mark high. If the unit detects a mark at least seven elements in height, but the mark has gone past or above the centered position, it is considered a mark high error condition.

During load format a line position analysis is performed during format program step FPS4. When a mark center condition is detected, the system progresses to store the document advance count in the vertical format data portion of the memory. The unit then advances the document twelve steps (or 0.120 inch). This should advance the mark just detected out of the array so that it is not detected as a mark high condition and does not erroneously actuate the LPER signal.

During read program step RPS6, a line position analysis is performed to determine where a line of data is with respect to the center of the array. During the analysis the A register 7001, 7002 remembers the least number of white or zero bits between the top of the array and the mark. The B register 7003, 7004 remembers the least number of whites or zero bits between the mark and the bottom of the array. The two adders 7021, 7025 perform the difference of A - B and B - A. The fine line adjust circuit 7201, 7202, 7209-7213 takes the positive difference of A - B or B - A and decodes this difference. The circuit of FIG. 72d then recodes this difference to determine the amount of fine line adjust, or the required number of motor steps, to bring the line close to the center of the array.

When the read program counter advances to step RPS7 the system performs the required fine line adjust. The fine line adjust is controlled by three signals from the line position analysis circuits. One signal, designated DOWN COUNT, is used to determine whether the document is to be moved forward or reverse. When DOWN COUNT is low, the system is commanded to back up the document. This is done if B - A is positive; that is, the number of white spots below the mark is greater than the number of white spots above the mark.

A second signal, designated FNAT, generates pulses at the 960 cycle per second step rate to increment the document step motor 500. The number of pulses generated is in accordance with that indicated by the fine line adjust circuitry in FIG. 72d. When the required number of steps have been effected, the system turns on a third signal, designated FNAC (fine line adjust complete). This is the enabling signal for the read program counter to advance from step RPS7.

In case where the fine line adjust moves the document forward, the FNAC signal is turned on immediately after the last required FNAT advance pulse. In the case where the document has to be moved backward to perform the fine line adjust, then a 6 millisecond settling time is initiated between the last FNAT advance pulse and the FNAC indication. This time is necessary to allow the motor to settle down; that is, it is required to allow a backward to forward reversal of the document advance motor 500.

During read program steps RPS6 and RPS10, for six lines per inch operation, the line position analysis circuitry performs a "line-following" function. As the system reads during the RPS6 and RPS10 steps, and as soon as a mark enters shift register 6818 through 6821, a first segment condition is indicated at flip-flop 6837. This triggers a line position analysis function which determines the position of that segment with respect to the top of the array. The center of this first segment is stored in both the first and moving segment registers (6901, 6902) to indicate to the recognition circuits the desired position of the center of the vertical window for the fifty bits of enabled photo-diode array and the position of the 20 bits for the recognition enable window. As the reading progresses across the document page, the system triggers an additional "mark centered" analysis for each 0.8 inch segment, or at the end of each field. The result of each one of these analyses is stored in moving segment register 6902. As each segment is analyzed, its center position with respect to the top of the array replaces the previous moving segment count held in the register.

The four signals that are sent from the line position analysis circuitry to the recognition circuit window generator are FMCK 4, FMCK 8, FMCK 16, FMCK 32. These four bits, derived from multiplexer 6904, are utilized to provide the count which represents the center of the segment with respect to the top of the array.

Assuming that an unrecognized character is detected during one RPS6 scan and repeat cycle, the amount of fine line adjustment must be utilized to modify the output of the first segment register 6901. This is done to indicate to the vertical window generator (at the recognition circuits) approximately where the first segment resides as a result of the fine line adjust. Upon rescan, a new vertical position of the first segment is generated, replacing the previous first segment register count. This is utilized to predict where the center will be for the next segment. System operation progresses to determine the vertical position of each succeeding segment and to put the center position count into the moving segment register 6902. As the system starts a line, multiplex circuit 6904 first gates out the count of the first segment register 6901 on the FMCK 4 through FMCK 32 lines. After the first segment position is detected and analyzed, the multiplexer 6904 gates the moving segment register count onto the FMCK lines to the vertical window generator at the recognition circuits.

b. Load Format (FPS4)

As previously described, the page reader circuitry generates an LPSR (line position reset) signal which goes low during format program step FPS3 and read program steps RPS5 and RPS9. This signal serves as a reset for the line position analysis circuits in preparation for its operation during the FPS4, RPS6 and RPS10 steps. The LPSR signal resets the various counters and flip-flops and also presets both of the A zero count registers 7001, 7002 and B zero count registers 7003, 7004 to a count of 48. During load format the system is forced into a six line per inch operating condition and the vertical blacks enable window is 38 bits high; that is, in the photo-diode array, bits 13 through 50 of the 64 bits are available. During load format: there is also no "line-following" procedure followed; the blacks enable window is always at the bits numbered 13 through 50; there is no fine line adjustment made so that if the unit is in horizontal format mode the load format program counter advances the document until there is an indication that the line is centered. Then, during step FPS8, the system scans with the 38-element blacks enable window. Presumably the characters associated with the horizontal format fields are centered within the array; if not, they still should be within the blacks enable window as generated. If for any reason the characters of the horizontal format fall outside the 38-bit blacks enable window, the system generates a read error flag and effects at least one rescan. There is no fine line adjustment between the first scan and the rescan. If the horizontal field characters are still not recognizable, the system generates a format error, rejects the format conditioning document, and halts operation.

The line position analysis program counter generates an LPAC (line position analysis complete) signal which goes high after an analysis is completed. Initially the LPAC signal is forced low when counter 6609 is reset by the LPSR signal; therefore, in advancing from FPS3 to FPS4 in the load format program, the line position analysis complete signal is low.

C. Load Format - No Mark Detected

In this description it is assumed that there is no mark in the array and no mark to be detected by the line position analysis circuits.

C.1 (LPSO). LPSO is the start or home position of the line position analysis program counter 6609. During this step it is first determined whether the line position analysis is complete by detecting at gate 6614 whether signal LPAC is high. Initially this should not be the case because counter 6609 is reset to all zeros. The system then determines whether the format program counter is at step FPS4, as detected at gates 6613, 6614. When the format program counter reaches FPS4 the system waits for MUX 63 signal to go high at gate 6614. This signal synchronizes the line position analysis circuitry with the MUXSD serial data coming from the recognition circuit quantizer-multiplexer. When synchronization is obtained, gate 6614 actuates multiplexer 6627 to switch flip-flops 6625. This in turn actuates gate 6626 to provide the LPCT signal which advances the line position analysis program counter 6609 to step LPS1.

c.2 (LPSI). The main operation during step LPSI is the gating of the MUXSD data into the 64-bit shift register 6816, 6818-6821, and the enabling of the recirculating gate 6808 to continue accumulating data into the shift register as long as the various functions require. During load format the input gate 6814 to the shift register is also gated (gates 6807, 6808) by the 38-bit high blacks enable window. That is, only bits 13 through 50 of the MUXSD are gated into the shift register; the other 26 bits are forced into a zero or white condition. LPSI also resets the zero counter 6719, 6720. The system then determines whether the format program count is at FPS4, via gates 6615, 6616. If not, the system remains at LPS1. The system is assumed to be at FPS4 and therefore proceeds to determine whether the MUX63 signal is present at gate 6616. This signal represents the MUX63 time following that which initially enabled the system to advance from LPS0 to LPS1. The result of this timing is that the system remains at LPS1 for one full cycle during which 64 bits of multiplexer serial data are gated into the registers. At MUX63 time, counter 6609 advances to LPS2 by the action of gate 6616, multiplexer 6627, flip-flop 6625 and gate 6626.

c.3 (LPS2). The first function performed during step LPS2 is counting (at counter 6719, 6720) the zeros (white bits) being shifted out of shift register 6816. This counts the number of white bits starting at the top of the array. Normally the count of whites or zeros continues until the counter reaches a maximum allowable count of 32, or a mark is detected. Having assumed there is no mark in the array, the system continues counting zeros until it reaches the maximum allowable count of 32 which is signified by signal ZR32 going low at counter 6720.

During LPS2 the system looks for six zeros in sequence during the blacks enable window time (bits 13 through 50) to set flip-flop 6834, which is called a white group or blacks enable flip-flop. This requires that a white group of six consecutive bits must be detected at the top of the blacks enable time before the system is enabled to detect a mark. The purpose for this relates to the fact that a previous mark centered condition in load format mode would have triggered the format load program counter to have advanced the document 12 steps (or 0.12 inch) before looking for the next mark. An extremely high mark on the conditioning document, even though it had been advanced twelve steps, could still extend down into the blacks enable portion during the search for the next mark. By requiring a white group of six consecutive zeros within the blacks enable window, the lower part of the previous mark is ignored. White groups flip-flop 6834 is also referred to herein as the black mark enable flip-flop, although its Q output signal is designated WHGP throughout the drawings for purposes of consistency. With the blacks enable flip-flop 6834 set, the system then looks for seven ones (or blacks) in sequence. When seven ones in sequence are detected at the end of the shift register 6821 by gates 6825, 6826, SRQ flip-flop 6830 is set. In this analysis it is assumed that there are not seven ones in the shift registers; therefore, SRQ flip-flop 6830 is not set.

During LPS2 the first determination is whether the zero counter 6719, 6720 has reached the 32 count maximum, as determined by gates 6721, 6722, 6723. If not, the system remains at LPS2. It is assumed that the system finally counts 32 zeros without having the SRQ flip-flop set; therefore gate 6620 is actuated by the ZR32/44 signal and the program proceeds to step LPS3.

c.4 (LPS3). During step LSP0 the enable flip-flop 6624 (ENFF) was set. The ENFF signal is utilized to enable the zero counter 6719, 6720 and mark centered counter 6706, 6707. Flip-flop 6624 is reset at the next MUX63 time to stop any further counting and processing of data in the shift register. The determination made during LPS3 is whether the SRQ flip-flop 6830 has been set. This determination is made at gate 6621. Since it is assumed that there is no mark in the array, flip-flop 6830 is not set. Gate 6621 then determines whether it is MUX63 time. At the next MUX63 time flip-flop 6624 is reset via gate 6623. The line position analysis program counter 6609 derives the LPAC (line position analysis complete) signal high and returns the system to program step LPS0.

When signal LPAC is high, the format program counter can advance, and commands the document to be advanced one step and then return to FPS4 for another analysis to determine whether there is a mark in the array. In this manner the format program and line position analysis program interrelate to properly position the document.

d. Load Format - Mark Detected but Low in the Array

Assume now that there is a mark to be detected in the array within the blacks enable window time, but the mark is below center. At the next FPS4 step the system is enabled to permit advance from LPS0 to LPS1 and MUX63 time.

d.1 (LPS1). LPS1 is maintained for a period from one MUX63 time to the next, accumulating another 64 bits of data from the MUXSD line. At MUX63 time the system advances to LPS2.

d.2 (LPS2). During LPS2 counter 6719, 6720 counts the number of zeros or white spots starting at the top of the array. It has been assumed that there is a mark in the array and that it is below center; also assume that during LPS2 counter 6719, 6720 counts 32 zeros before SRQ flip-flop 6830 is set. Therefore, when zero counter 6719, 6720 reaches a count of 32, gate 6620 is enabled and the program advances to LPS3.

d.3 (LPS3). The ENFF flip-flop is still set; therefore, the system continues to count zeros while looking for a mark at gate 6824. The SRQ flip-flop 6830 is set when seven or more bits of black, which constitute the mark, are positioned at the end of the shift register 6821. When the SRQ flip-flop 6830 is set, gate 6621 is activated and the system advances to LPS4.

d.4 (LPS4). The line position analysis program counter 6609, by having advanced to LPS4, indicates that a mark has been detected within the blacks enable window at the array. Therefore the counter sets flip-flop 6611, which is the mark sensed flip-flop. Also during LPS4 the contents of the A zero register 7001, 7002, are compared with the count in the zero counter 6719, 6720 at comparator 7011. During LPSR time the A register 7001, 7002, and B register 7003, 7004 had both been present to a count of 48. During LPS 3 the zero counter 6719, 6720 was stopped when it reached a count of 32; therefore, the zero counter count is less than the count in the A register. The A > B output signal from comparator 7011 actuates gate 7017 and flip-flop 7018 which in turn triggers gate 6716 to provide the ZRAT signal. This signal clocks the new zero count into A register 7001, 7002. After the new count has been transferred to the A register, counter 6719, 6720 is reset at timing pulse TPD and the counter is enabled to count zeros below the mark. If MUX63 time occurs during LPS4 it resets ENFF flip-flop 6624 via gate 6623. If MUX63 has not occurred yet, the system remains at LPS4 for only a two microsecond duration, corresponding to one phase of the six phase clock master timer circuit. The unit is then advanced to LPS5 at timing pulse TPE.

d.5 (LPS5). The SRQ flip-flop 6830 is reset when four zeros or white bits are detected at the last four positions of the shift register by gates 6825, 6826. When the four zeros occur and reset the SRQ flip-flop, gates 6710, 6713 permit counter 6719, 6720 to count the zeros below the mark in the array. The zero counter again is prevented from counting past 32 by gates 6721-6723 and 6713. If MUX63 occurs during LPS5, flip-flop 6624 is reset. The determination made during LPS5 is whether flip-flop 6624 is reset. It is in fact reset at MUX63 time, after which the system has completed analyzing the 64 bits in the shift register. Counter 6609 is then advanced to step LPS6.

d.6 (LPS6). During step LPS6 the contents of B zero register 7003, 7004 are compared with the count in zero counter 6719, 6720. If the zero counter contents are less than the B register contents, the new count is transferred from counter 6719, 6720 to B registers 7003, 7004 by signal ZRBT via gate 7016, 7017, flip-flop 7018 and gate 6017. During LPS6 the input and recirculating gates 6814, 6808 of the shift register are enabled to start accumulating the MUXSD data for the next analysis. The unit remains at LPS6 for only a two microsecond period associated with one phase of the six phase master timing clock. The unit then advances to LPS7.

d.7 (LPS7). During LPS7 the input and recirculation gates 6814, 6808 of the shift register are enabled to permit accumulation of data for the next analysis. The LPS7 count at counter 6609 also actuates the LPAC (line position analysis complete) signal and advances to return the counter to LPS0 after a two microsecond period.

e. A and B Zero Register - Mark Position Indicator

The zero counter 6719, 6720 is a six bit synchronous counter. The A and B registers 7001, 7002 and 7003, 7004 are five-bit registers so that the A and B registers hold only the five high order bits of the zero count, the lowest order bit of the zero counter being dropped. The line position analysis circuitry includes two adders 7021, 7025. Adder 7021 provides the difference of the A register contents minus the B register contents. Adder 7025 provides the difference of the B register contents minus the A register contents. The outputs of these two adders are analyzed in the circuits of FIG. 71a to determine whether a mark is near the center of the array, is high in the array, or is low in the array. A mark centered condition is indicated if a mark is detected when no array-filled condition is determined and the output of the two adders is such that A minus B and B minus A are equal to or less than three. A mark low condition is indicated if A minus B is equal to or greater than four. A mark high condition is indicated if B minus A is equal to or greater than four. For the present analysis it is assumed that a mark is detected but is low in the array. This is indicated by adder 7205 showing that B minus A is equal to or greater than four.

Each document motor advance step moves the document 0.0104 inch. Each array photocell element equivalent height at the document is 0.005875 inch. Therefore, each motor step advances the document to approximately two elements. After a document advances one step, or two elements, on the next position analysis, A register 7001, 7002 has a count of two less and the B register 7003, 7004 has a count of two more than in the previous analysis. Therefore, moving the document one step changes the result of A minus B and B minus A by a total count difference of four. If then, A minus B is equal to or greater than four, the document should be moved one more step. If A minus B is less than four, one more step moves the mark past the center of the array.

f. Load Format - Mark Detected and Centered

During load format, the line position analysis circuits eventually detect a mark which is near the center of the array. A mark centered is defined as a condition where a mark is detected and A minus B is less than four, and B minus A is less than 4. The operation of the line position analysis circuits is the same regardless of the detected mark having been centered or low. The contents of the A and B registers effect the load format program counter only. That is, after performing a line position analysis in step FPS4, the format program advances to FPS5 and determines whether the mark is centered. If not, the determination is made whether the mark was high or the array was filled. If the answer is still no the format program advances to FPS11 and advances the document one more step. If the mark were in fact centered, then the format program counter is advanced from FPS5 to FPS6 to generate a memory write cycle, whereby the document advance count is stored in vertical format portion of the memory.

g. Line Position Error

After performing the line position analysis during step FPS4 of the format program, the format program counter advances to step FPS5. During FPS5 the system tests to see if there is a line position error. If there is a line position error the mark centered condition is inhibited at gates 7101 through 7107 and 7109, and a format error is indicated in the format control circuits which return the format program counter to step FPS0. The following conditions are defined as a line position error (LPER) during load format:

1. Array filled. An array filled condition occurs if all 38 bits of the blacks enable window are black; that is, the detected black mark is at least 38 elements high.

2. Double mark. This condition occurs if two marks, each at least seven black elements high, are detected within the black enable window of 38 elements.

3. Mark high. If the unit detects a mark of at least seven elements in height, but the mark has gone past (above) the center position, a mark high condition exists. A mark high condition is considered an error. This is indicated by the output of the B minus A adder 7025 being equal to or greater than four.

h. Read Mode - Line Position Analysis During RPS6 and RPS10

Signal LPSR (line position reset) is generated during read program steps RPS5 and RPS9, the steps preceding RPS6 and RPS10. One of the functions of LPSR is to preset each of the A and B zero registers 7001, 7002 and 7003, 7004 to a count of 48. The A and B registers are the registers which hold the minimum zero count above and below the mark as the system scans across the line. During operation at six lines per inch, the "line-following" function is performed for the vertical blacks enable window. For this purpose an additional preset is furnished during steps RPS3 and RPS13 of the read program to preset the first and moving segment center count registers 6901, 6902 to 32. That is, these reset times are utilized to preset the count of 32 which is used as a center count of 64 bit MUX serial data.

For the present analysis assume that the system is in vertical format only (i.e., not operating with horizontal format) and it is operating at three rather than six lines per inch. The analysis commences at LPS0.

h.1 (LPS0). The first determination during LPSO is whether the line position analysis is complete (signal LPAC, gate 6614). The answer under the assumed conditions is no. The next determination is whether the system is in read program steps RPS6 or RPS10 and whether the scan duration signal has been turned on (gate 6612). Assuming that this is the case, the determination is next made as to whether it is MUX63 time (gate 6614). That is, are the line position analysis circuits synchronized with the MUX serial data (MUXSD) counter at the recognition centers? When MUX63 time occurs, the system advances to LPS1 by actuating gate 6614.

h.2 (LPS1). The main function during LPS1 is to accumulate MUXSD (data) in the shift register 6816, 6818-6821. Therefore, LPS1 is one of the enabling signals to the input and recirculating gates (6809, 6814) of the shift register. MUXSD is gated to the 64 bit shift register during LPS1 when the BLACK EN signal is high. For three lines per inch operation the blacks enable window is on for the full 64 bit data. LPS1 also resets the zero counter 6719, 6720 and sets the ENFF flip-flop 6624. The first determination during LPS1 is whether the system is in horizontal format (gates 6617). The answer under the assumed conditions is no. The next determination is whether the system is operating at six lines per inch (6836, flip-flop 6837, gates 6838, 6618). The answer is again no under the assumed conditions. Therefore the system loops around and determines whether the system has scanned a segment of 128 counts (gate 6618). The meaning of this is described in the following paragraph.

The scan counter counts at a rate of 145 counts per inch as the unit scans across the page; that is, one count for every MUX63 signal. A count of 128 counts is a scan of approximately 0.8 inch. Therefore, a line position analysis is effected after accumulating MUXSD for a segment of approximately 0.8 inch (128 cycles of MUXSD). When the scan counter has generated a signal SC128, the LPS1 advance flip-flop 6619 is set. The determination is then made whether it is MUX63 time (gate 6616). When the next MUX63 signal appears the line position analysis program advances to LPS2.

h.3 (LPS3). The LPS2 step is utilized to count zeros or whites into the mark centered counter 6706, 6707. The determination of the center of the mark with respect to the top of the array is performed during LPS2, LPS3, LPS4 and LPS5, regardless of whether the system is in three or six lines per inch operation. The results of the determination are only utilized if the system is actually operating in six lines per inch mode. For the purpose of the mark centered counter 6706, 6707, the system counts zeros (whites) during LPS2 and LPS3 and half the number of ones (blacks) of a mark during LPS2, LPS3, LPS4 and LPS5. This operation yields the center position of the mark with respect to the top of the array. Therefore, LPS2 is one of the enabling signals to the counting of the zeros and half of the ones into the mark centered counter.

During LPS2 counter 6719, 6720 counts zeros (white bits) out of the shift register, starting at the top of the array and continuing until reaching a maximum count of 44. That is, if no mark is detected, zero counter 6719, 6720 counts until it reaches a count of 44, after which gates 6723 and 6713 are actuated to inhibit further countings. If the system were operating in the six line per inch mode, zero counter 6719, 6720 would stop counting at a count of 32. Starting with LPS2 the system looks for a mark of at least 17 ones (or black bits) in sequence in the shift registers. The last 32 bits of the shift register have parallel outputs which feed decoding gates 6822, 6823, 6824. When the last 17 bits of the shift register are all ones, indicating a black mark at least 17 ones in length at the end of the shift register, SRQ flip-flop 6830 is set. If there is a mark in the shift register it may be sensed either during LPS2 or LPS3. The SRQ flip-flop is reset when gates 6825, 6826 detect four zeros (or whites) appearing at the last four stages of the shift register. The question is then asked (during LPS2): Has the unit counted maximum number of zeros? (gate 6620). For three lines per inch operation this number is 44. Assuming that the answer is yes, the system advances to LPS3.

h.4 (LPS3). During LPS3, gate 6623 is enabled to permit reset of the ENFF flip-flop 6624 at MUX63 time. The system also continues to count any ones into the mark centered counter 6706, 6707. Note that the number of ones entering counter 6706, 6707 is divided by two, by means of flip-flop 6703, before entering the counter. The determination is then made whether the SRQ flip-flop 6830 is set (gate 6621). Assume for the present that no mark has been accumulated in the shift register; therefore, the answer is no. If it is not MUX63 time, (gate 6621) the system stays at step LPS3 until MUX63 time resets the enable flip-flop 6624. The system then determines if the scan duration has terminated (gate 6601) or if a black field has been detected by flip-flop 6839 (gate 6602). If not, the system returns to LPS0.

The foregoing description has illustrated the accumulation of 128 cycles of MUXSD into the shift register, followed by an analysis of the contents of the shift register with the result that no mark was found. Upon returning to LSPO the system defects that signal LPAC is high (at gate 6614) indicating that a line position analysis has not been completed. The read program is still in step RPS6 or 10, and the scan duration is still active. At the next MUX63 time, the system advances to LPS1 in the line position analysis program.

h.5 (LPS1). Assume the same sequence of operation during step LPS1 as described in section h.2 above. The system is not in horizontal format and is not operating at six lines per inch. Consequently, the system awaits a scan count of 128 (at gate 6618) or the end of a scan duration (at gates 6601 and 6612). Assume that the system is now in the midst of a second segment of 128 scan counts proceeding across the line. When the SC128 signal is received at gate 6618, it sets the LPS1 advance flip-flop 6619. At the next MUX63 time the system advances to LPS2.

h.6 (LPS2). Assume the same conditions considered in h.3 above except that in this case assume there is a mark which occupies a portion of shift registers 6618-6821 close to the center of the array. Under these circumstances, the mark is detected and the SRQ flip-flop 6830 is set before zero counter 6719, 6720 reaches a count of 44. Gate 6620 detects this situation and advances the line position analysis program to LPS3.

h.7 (LPS3). If MUX63 time occurs during LPS3, enable flip-flop 6624 is reset. Assuming that MUX63 has not yet occurred, the system continues to count ones, divided by two, into the mark centered counter 6706, 6707. Gate 6621 then determines whether the SRQ flip-flop 6830 has been set; since it has, the line position analysis program is advanced to LPS4. In this situation the time duration of the LPS3 step is two microseconds; that is, one cycle of the six phase master timing clock.

h.8 (LPS4). During LPS4 the mark centered counter 6706, 6707 continues to count half the number of ones in the detected mark. Having detected a mark as indicated by the SRQ flip-flop 6830 being set, the system now sets the mark flip-flop 6611 by advancing to step LPS4. SRQ flip-flop 6830 is reset when four consecutive zeros (or whites) are detected in sequence at the last four stages of shift register 6821. During LPS4 the system compares the contents of A zero register 7001, 7002 with the count in the zero counter 6719, 6720 at comparator 7011. If the count in the zero counter is less than the contents of the A register, the new zero count is placed in the A register by the ZRAT signal derived at gate 6716 by the action of gate 7017 and flip-flop 7018. Zero counter 6719, 6720 is then reset at the next TPD pulse so that it may count the number of zeros below the detected mark. If MUX63 time occurs during LPS4, ENFF flip-flop 6624 is reset. LPS4 duration is two microseconds, the time for one phase of the master clock. The system then advances to step LPS5.

h.9 (LPS5). During LPS5 the mark centered counter 6706, 6707 continues to count half of the ones in the detected mark if the mark is still at the end of the shift register. Once again the SQR flip-flop 6830 is reset if four zeros in sequence appear at the end of shift register 6821. During LPS5 the system counts the number of zeros below the mark, but not to exceed a count of 44 during three lines per inch operation or a count of 32 during six lines per inch operation. When MUX63 time occurs it resets ENFF flip-flop 6624 and advances the line position analysis program to step LPS6.

h.10 (LPS6). During LPS6 the B zero register 7003, 7004 has its contents compared with the count in zero counter 6719, 6720 at comparator 7011. If the zero counter count is less than the B register contents, the new count is placed in the B register by means of signal ZRBT derived at the gate 6717 by the action of gate 7017 and flip-flop 7018. Step LPS6 also enables the input and recirculation gate 6814 of the shift register. The count in mark centered counter 6706, 6707 is placed in the moving segment register 6921 during LPS6 by the M SEG GT signal generated by gate 6929. If this detected mark is the first mark detected on the line being scanned, the contents of counter 6706, 6707 is also placed in the first segment register 6901 by the F SEG GT signal generated at gate 6928. The function of the moving segment register relates to the "line-following" operation which is discussed in greater detail subsequently. Step LPS6 remains in force for a duration of two microseconds after which the program advances to LPS7.

h.11 (LPS7). During step LPS7 the input and recirculation gate 6814 for the shift register remains enabled to permit accumulation of data for the next analysis. The determination is made whether the scan duration has terminated (gate 6601) or a black field has been detected (gate 6602). Assuming the answer to be no, the system returns to LPS0 where it determines whether or not a line position analysis has been completed. If the answer is no, and the system is in either the RPS6 or RPS10 steps of the read program, and the scan duration is still in force, gates 6612, 6613 and 6614 cooperate to advance the program to step LPS1 at the next MUX63 time.

h.12 (LPS1). Assume that the previously described analysis has been repeated for a number of SC128 count pulses and that the system is approaching the end of the scan line during which it has accumulated a smaller number of MUXSD into the shift register. The determination is then made whether or not the unit has reached the end of the scan duration during steps RPS6 or RPS10. If so, flip-flop 6619 is set, activating gate 6615 to prime gate 6616 so that at the next MUX63 time the program advances to step LPS2.

h.13 (LPS2). As described previously in relation to step LPS2, the program advances to LPS3 if the maximum number of zeros have been counted or the SRQ flip-flop 6830 has been set. Assume that the unit does in fact advance to LPS3.

h.14 (LPS3). Now assume that the SRQ flip-flop 6830 has not been set. At the next MUX63 time, the ENFF flip-flop 6624 is reset. The determination is then made, at gates 6601, 6602, if the scan duration is completed or a black field has been detected. Since it has been assumed that it is the end of a scan duration, gate 6602 activates gate 6604 which in turn activates gate 6606 to set the highest order stage of counter 6609. As a consequence the LPAC signal goes high and the LPAC signal goes low to return the counter to LPS0. With LPAC low, gate 6614 maintains the program at LPS0 until there is further operation of the read program.

Now assume, during the LPS3 step, that the SRQ flip-flop was set. The system then automatically advances from LPS3 to LPS4 by the action of gate 6621.

h.15 (LPS4). The operation during step LPS4 progresses as described above in h.8. The unit remains in LPS4 for a two microsecond duration and then advances to LPS5.

h.16 (LPS5). The system remains in LPS5 until the next MUX63 time and performs the operations described in paragraph h.9. When flip-flop 6624 is reset, the program advances to LPS6.

h.17 (LPS6). During LPS6 the system performs the functions described in paragraph h.10. The program remains at LPS6 for a period of two microseconds and then advances to LPS7.

h.18 (LPS7). The determination made during LPS7 is whether the end of scan duration has occurred or a black field has been detected (gates 6601, 6602). It has been assumed that the scan duration has terminated; therefore gate 6602 actuates gate 6604 to in turn actuate gate 6608. The latter gate provides the ADJCSL signal which is applied to the load terminal of the step counter 7221 to permit entry of the fine line count (i.e., the required line position correction step number) into counter 7221. In addition the line position analysis complete signal is actuated at this time and the line position analysis program returns to step LPS0.

The foregoing description has illustrated the process of scanning across a line of data during the RPS6 and RPS10 read program steps. There are also two counts of zeros (whites) stored in the A and B registers. Register A contains the minimum number of zeros or white spots from the top of the array to the top of the mark. The B register contains the minimum number of zeros from the bottom of the mark to the bottom of the array. The contents of the A and B registers are maintained until the next LPSR signal is received by the line position analysis circuitry. The contents of the A and B registers are now utilized for any required fine line adjustment. If the previous reading and analysis had been effected during step RPS6 of the read program, the next step of the read program counter is RPS7. RPS7 is the read program step during which any required fine line adjustment is performed.

i. Fine Line Adjust - Read Mode (RPS7)

No line adjustment is performed after a read and scan operation during an RPS10 step. However, the "line-following" function data, utilized during six lines per inch operation, is utilized during RPS10.

The contents of the A register 7001, 7002 and the B register 7003, 7004 are applied to adders 7021 and 7025. The carry signal from the B minus A adders 7025 is designated B .gtoreq. A. This signal is high if B minus A results in a positive number, and the signal is utilized to control the selector input of multiplexer 7201. If the signal B .gtoreq. A is low, the output of the A minus B adders 7021 is selected at multiplexer 7201 as the input to the four bit to 16 line decoder 7202. If the signal B .gtoreq. A is high, the output of adder 7025 is selected as the input to decoder 7202. Table L1, in the first column, indicates the possible results of A minus B operation. This column should also be read as B minus A for the case where the B minus A result is positive.

The sixteen line output from decoder 7202 is identified as A minus B in the second column of table L1. The column identified as "A.sub.2 " minus "B.sub.2 " is actually the A minus B count divided by two. As previously explained, when a document is moved in a forward direction, the number of steps moved is subtracted from the A count and added to the B count. Therefore, the effect of moving the document is to change the difference of A minus B by twice the amount. Therefore, in calculating the required amount of movement for a document, take A minus B and divide by two; then place in the first column of table L1 to obtain the desired result. For example, in the A.sub.2 minus B.sub.2 column, consider the row designated 12-13. The actual difference in the A and B count is 24 to 26. The 12-13 is the actual difference divided by two. In the second column, designated DIF, the numeral 6 indicates that the decoder 7202 has decoded this difference (12-13) as 6. The third column then indicates that the number of motor steps required for adjustment is 7. The calculations for verifying this operation are as follows: (9) each motor step moves the document 0.0104 inch; (b) seven steps of the motor advances a document 0.0728 inch. Each vertical element viewed by the array is 0.005875 inch. Therefore, dividing the 0.0728 by 0.005875 provides a result of 12.4 elements. The required movement, as indicated by the first column, was 12-13 elements. Therefore, this is the closest approximation that can be made to bring the line close to the center of the array.

The output signals from decoder 7202 are designated DIFO through DIF12, and are applied to four decoder gates 7210-7213. These gates generate a TWOS complement to preset the motor step counter 7221. Continuing with the previously considered example of A minus B at 12-13, it is noted that the counter is preset to the binary equivalent of 9. When the read program advances to RPS7 to enable the fine line adjust function, document advance step pulses (FNAT) are generated to activate step motor 500 and advance the document. Referring to Table L1 again, it is noted that seven motor steps are required to advance the document advance counter to a count of zero which indicates that the fine line adjustment is completed (FNAC). When a count of zero is reached at counter 7221, further FNAT pulses are inhibited at gate 7228. If the fine line adjustment involves a backward movement of the document, the signal B .gtoreq. A actuates gate 7218 to provide the DOWN COUNT signal which instructs step motor 500 to step backward. After the motor step counter 7221 reaches a zero count further generation of the FNAT pulses are inhibited at gate 7228. In addition the continuing advance of counter 7221 is permitted until a count of six is reached, at which time the FNAC signal is generated with the aid of gates 7225, 7226, 7229, 7215. These additional six counts introduce an approximately 6 millisecond delay before the motor can be reversed or changed from a reverse to forward direction.

j. Line-Follower Function

During six lines per inch operation the blacks enable vertical window, which gates data into the shift register, is 50 bits high. In the recognition circuitry a second vertical window, 20 elements in height, is generated to enable the recognition circuits. The "line-following" circuitry of the line position analysis circuits moves these two windows up and down in synchronism to follow any detected skew or vertical mis-registration of the line. This function is performed both during the RPS6 and RPS10 steps of the read program. During LPS1 gate 6701 detects the very first mark indication in the shift register. When such a mark, of 17 bits or greater length, is detected, the system performs its first analysis. As a result of this analysis the mark centered counter 6706, 6707 contains a count representing the center position of the mark with respect to the top of the array. This mark centered counter is placed into the first segment register 6901 and into moving segment register 6921. Multiplexer 6904 selects the output of the moving segment register and gates this to the recognition circuits window generator. As the system progresses across the document in reading a line, and a line position analysis is made of each 0.8 inch segment or horizontal field segment, the new mark centered count is placed into moving segment register 6921. In this manner the center position of each segment is utilized to control the position of the black enable windows for the next segment.

After completing the first RPS6 scan and proceeding to step RPS7 to perform a fine line adjustment, the amount of fine line adjustment is stored in another register 6902. When starting to read during a second RPS6 step, if a rescan is required at the same line, the amount of fine line adjustment is utilized to modify the count stored for the first segment. The modified count is now gated by multiplexer 6904 to the recognition circuitry where the first segment should be within the array as a result of a fine line adjustment. On rescan then, the first segment is detected again, resulting in a new count stored in the mark centered counter 6706, 6707. This new count, on the rescan for the first segment, is now stored in the first segment register 6901 and moving segment register 6921; the selection is then set at multiplexer 6904 so that the output of the new count in the moving segment register is transferred to the recognition circuits vertical window generator. The scanning and modification of the moving segment register continues as the system continues reading across the line. If during the first RPS6 rescan there is still another unrecognized character in the line, the system proceeds to perform another fine line adjustment during the next RPS7. This might require a movement of the paper and storing of the required fine line adjustment count in register 6902. This stored count provides the predictive position for the first segment of the first RPS10 rescan. During the RPS10 rescan a first segment is detected, its mark centered position is determined, and this new count is now placed into the first segment register 6901 and moving segment register 6921. As the system continues to read in the RPS10 step of the read program, the vertical position of each segment is determined and the contents of moving segment register 6921 are modified and gated to the recognition circuit window generator.

TABLE L1 __________________________________________________________________________ FINE LINE ADJUST ADJUST MOTOR STEP COUNTER (FNAT) __________________________________________________________________________ No. OF COUNTER PRESET & OUTPUT A.sub.2 -B.sub.2 DIF MOTOR D.sub.D /Q.sub.D D.sub.C /Q.sub.C D.sub.B /Q.sub.B D.sub.A /Q.sub.A 24-25 12 11 0 1 0 1 22-23 11 11 0 1 0 1 20-21 10 11 0 1 0 1 18-19 9 10 0 1 1 0 16-17 8 9 0 1 1 1 14-15 7 8 1 0 0 0 12-13 6 7 1 0 0 1 10-11 5 6 1 0 1 0 8-9 4 5 1 0 1 1 6-7 3 4 1 1 0 0 4-5 2 3 1 1 0 1 2 1 1 1 0 2-3 1 1 1 1 1 1 FOR B>A MOTOR STEPS 0 0 0 0 IN REVERSE DIRECTION 0 0 0 1 MUST ALLOW MOTOR 0 0 1 0 SETTLINE TIME BEFORE 0 0 1 1 TRYING TO GO FORWARD 0 1 0 0 ON NEXT LINE 0 1 0 1 0 1 1 0 0 0 0 0 1 1 0 __________________________________________________________________________ FNAT -- FINE LINE ADJUST PULSES TO MOTOR FNAC -- LINE LINE ADJUST COMPLETE (A.gtoreq.B).sup.. (B.gtoreq.A) = (A = B) LINE CENTERED, NO ADJ.

After the first RPS10 rescan, if any additional rescans are required there is no fine line adjustment performed. Therefore, the contents of the fine line adjust register 6902 are reset to zero so that the first segment vertical count is no longer modified at adder 6903 during subsequent RPS10 rescans. As each RPS10 rescan commences, and a first segment is detected, its vertical center count is placed into the first segment register 6901 and the moving segment register 6921. Thereafter the contents of the first segment register and moving segment register are multiplexed by multiplexer 6904 to the vertical window generators to move the blacks enable window and recognition windows accordingly.

This "line-following" function, during six lines per inch operation, provides for a gross amount of skew of the line on the document. The line could in fact extend for the full sixty elements of the array. There is a requirement, however, that this be a progressive skew of the line across the document and not a zig-zag or jump skew. That is, it is still necessary that the vertical misregistration of adjacent characters, or characters within the segment, be restricted as compared to the wide latitude allowed the three lines per inch operation.

III(B) RECOGNITION CIRCUITRY

The Recognition Circuitry is illustrated in FIGS. 89-124 and serves mainly to receive and identify character signals from the photodiode array. In addition, these circuits provide various control and timing signals required to facilitate recognition of characters and the processing of characters in the Control Logic circuits.

III(B.1) QUANTIZER MULTIPLEXER CIRCUITS

The quantizer multiplexer circuits are illustrated in FIGS. 89-91 of the accompanying drawings. The 60 signals (channels 1-60) from the photo-diode array are applied to respective preamplifiers 8901-8960. Each amplified channel signal is then stored in a respective bit in registers 8961-8975. The amplifiers 8901-8960 are illustrated in detail in FIG. 91 by representative amplifiers 8901 and 8960. Each channel signal is fed through a potentiometer which serves as a gain adjustment which assures that the signal applied to the registers is at approximately the same amplitude all across the array. The output signal from the potentiometer is fed through a low pass RC filter to the non-inverting input terminal (+) of a voltage comparator operational amplifier. The inverting input terminal (-) of the voltage comparator is fed from a threshold adjust voltage bus derived from amplifiers 9101, 9102, and which is common to all 60 amplifiers. The output signals from the photo-diode array are phased such that a character segment or black detected at the array provides a negative signal. Since these negative signals are fed to the non-inverting input terminals of the channel amplifiers, a detected black appears as a low or close to zero voltage (logic zero) at registers 8961-8975.

Registers 8961-8975 simply constitute RS latches whose enable input terminals are maintained at ground. The sample signal, derived from amplifier 9010, is fed to the reset input terminals of all of the latches. When this sample signal is raised to binary 1, the latches are able to receive and store the channel signals. At any time during the sample period, the low on the respective channel signal line produces a high level signal at the Q output terminal of the latch. This Q signal remains high until the sample signal once again goes low. At load time the signals from the latches are transferred into parallel-load shift registers 8976-8983. The two uppermost input signal terminals at shift register 8976 and the two lowermost input signal terminals at shift register 8983 are continuously maintained at low signal level (ground) in order to provide two blank bits at the beginning and end of each received data slice. This is done merely for convenience because it was found simpler to utilize a 64 pulse shift cycle rather than a 60 pulse shift cycle, yet only sixty channels of data are received. Thus the data received on the channel 1 signal line is actually placed in the third bit from the start of the data slice which is to be shifted serially out of the interconnected chain of shift registers 8976-8983.

Referring for a moment to FIG. 90, flip-flops 9003 and 9004 are JK flip-flops interconnected as a divide-by-four counter utilizing timing pulse TPF as a clock input signal. The carry output signals of these flip-flops are connected through NAND gate 9006 and inverter 9007 to the ENT input terminal of counter 9008. Counter 9008 is a divide-by-16 counter, which when combined with the divide-by-four counter (flip-flops 9003, 9004) provides an overall division factor of 64. The carry output signal from counter 9008 is designated MUX63. The timing of this signal is illustrated in FIG. 49 relative to the master six phase timing sequence. The sixteen and 32 weight output signals from counter 9008 are coupled through NAND gate 9009 and inverter 9010 to provide the sample signal utilized to enter data into shift registers 8961-8975. The sample signal is high during counts 48 through 63 of the counter in FIG. 90 and is utilized to permit any black detected by a photo-diode at the array during this interval to be stored as a corresponding binary 1 signal at the appropriate shift register bit. As mentioned previously, this binary 1 or high output signal from the shift register remains so stored until the end of the sample interval (MUX count 63) whether or not a black is still being detected at the corresponding photo-diode in the array. Upon occurrence of timing pulse TPD during the MUX63 interval, the LOAD signal goes low (as illustrated in timing diagram FIG. 49) causing the data stored in registers 8961-8975 to be transferred into shift registers 8976-8983. The detected vertical character slice is thus located in the serially inter-connected shift registers where it awaits serial shifting so that it may be integrated with additional detected slices for purposes of recognition.

The MUX CLK signal, generated at gate 9202, coincides with timing pulse TPA during all but the 64th count interval for the counter in FIG. 90 (reference timing diagram FIG. 49). The MUX CLK pulses act through inverter 8984 to serially shift data through shift register chain 8976-8983 by one step during all but the 64th count interval for the counter of FIG. 90; it is during this interval that the LOAD pulse permits entry of data into the shift registers. Actual shifting in the shift register chain occurs at the leading edge of the MUX CLK pulses.

All of the binary outputs of the 64 bit counter of FIG. 90 are brought out for use in other portions of the recognition circuitry to perform various timing functions during the MUX or vertical scan interval. These output signals are labeled MUX A through MUX F and MUX A.

Amplifiers 9101 and 9102 are two halves of dual operation amplifier utilized for purposes of threshold control at the individual channel amplifiers 8901-8960. Amplifier 9101 is utilized as a summing amplifier to which the various output signals from threshold adjustment potentiometers are fed. The output voltage from amplifier stage 9101 is proportional to the sum of the currents flowing through the summation resistors connected to the inverting input terminal of that amplifier. Each of the summing resistors receives its current through appropriate transistor switches 9103 through 9110. If the switch for a particular summing resistor is off the current through that resistor is zero and therefore the effect of that particular summing resistor is nil. Amplifier stage 9102 is an inverting amplifier which drives the reference input terminals to all of the channel amplifiers 8901 through 8960 via a common bus. In the handwritten mode the signal HWGC signal, derived from inverter 12005, is low and transistor switch 9103 is rendered conductive. The collector of this transistor rises to the positive supply voltage level and conducts current through the adjustment pot connected to the HWG line. Control of this pot determines the effect of the HWG line at summing amplifier 9101. Operation of the other adjustment controls is similar with the exception that the THD1 and THD2 lines are connected to a negative supply voltage and cause a negative current to flow through their associated summing resistors, thereby serving to reduce the threshold voltage at summing amplifier 9101. The 07B line is utilized in conjunction with the 7B mode whereas the THD1 through THD4 lines are utilized in conjunction with re-scan and permit the threshold to be changed accordingly if re-scan of a line is required due to lack of recognition of a character during the first or subsequent scans.

The quantized serial data, designated by signal MUX SD, is shifted out of the shift register chain 8976-8983 from register 8983, in the same order as the channel numbers from which the data was originated. The MUX SD signal is applied to gate 9201 where it is gated with the BLKS EN 1 signal, before being applied to the mask shift registers of FIG. 93 as the MUX COL 13 signal. This gating, before being applied to the mask shift registers, insures that during six lines per inch operation only the image of the desired line enters the mask. That is, only the image of the desired line, with possibly a little overflow from the lines immediately above and below that line, enter the mask; however none of the desired line is gated out. The data from gate 9201 is fed to the column 13 shift register 9313, and then serially in turn to the column 12, column 11, etc. shift registers to the column 1 shift register 9301. The data enters each shift register 9301-9313 at terminal A and exits to the next shift register stage from terminal B. Each of the 13 shift register columns are identical and a typical column is illustrated in FIG. 94.

Referring specifically to FIG. 94, data entering the shift register at terminal A is gated at NAND gate 9404 by the RDEN signal. Gates 9403, 9404 and 9408 serve as a data stream selective switch which enters the data from terminal A into the shift register when the RDEN signal (read enable) is high. When RDEN is low, and the recirculate signal is low, the output from the shift register column is fed back into the input via terminal B. When the recirculate signal is high and the RDEN signal is low, data is prevented from entering the register.

The shift register itself, designated 9405, is a 64 bit MOS shift register, the 64 bits corresponding to a full column length. It is the purpose of the 13 individual shift register columns to juxtapose thirteen successive detected slices of a character to provide a reassembled character which can be recognized according to logic to be described below. In this regard, each column is 64 bits in length to accommodate the 64 photo-diodes in the optical detecting array. However, the maximum height of any character slice will be significantly less than 60 elements high; in fact, for OCR-A font the maximum character slice height is 18 elements of the photo-diode array. For purposes of actual character detection, therefore, a 24 bit DTL shift register, comprising 24 JK flip-flops, are associated with and included in each column. The selected data stream, designated as signal COL (or COL) is applied both to the 64-bit shift register 9405 and to the 24-bit DTL shift register utilized for actual character sensing. Shift register 9405, therefore, is utilized to maintain proper column orientation from column to column; the 24-bits in the DTL shift register serve to provide the signals utilized to detect the character.

The S/R clock signal, which is actually timing pulse TPA, is utilized to clock the dual JK flip-flops in the 24-bit DTL shift register. The signal is illustrated in timing diagram FIG. 49. The output signals in the individual 24 flip-flops change states at the trailing edge of timing pulse TPA. The clock signal for the 64-bit shift register 9405 is designated MOS CLK and is derived from inverter 9205. The MOS CLK signal is high from the beginning of timing pulse TPB to the beginning of timing pulse TPD. It is inverted by invertor 9401 to clock shift register 9405 once during each count interval of the counter in FIG. 90. After 64 MOS CLK pulses a data bit is shifted through shift register 9405, inverted by inverter 9406 and applied to the A input terminal of the next shift register column.

As illustrated, both the true and false output signals from each of the 24-bit DTL shift register stages are connected to 48 respective matrix amplifiers to provide the output signals 1-24 and 1-24. A typical matrix amplifier is illustrated in detail in FIG. 95.

Referring specifically to FIG. 95, when the input signal to the amplifier is at logic 1 level, the resistor diode combination clamps the output signal to the matrix to the level of the collector supply phototransistor 9501. The base-emitter drop in transistor 9501 cancels out the drop in the diode so that during the binary 1 condition the output signal rises fully to the collector supply level. During the zero condition the matrix driver line drops to a level corresponding to the low voltage provided by the JK flip-flop feeding the amplifier. The output signals from the amplifiers are connected to various character lines through resistor or resistor diode combinations of the different mask figures. The true outputs are connected through resistors to respective character lines to denote those areas where a character image is expected. The false output signals are connected through resistors, or resistor diode combinations to the respective character lines to denote those areas where character image should not exist. This operation is described more fully in the next section.

III(B.2) CHARACTER MASKS

Referring to FIG. 97 of the accompanying drawings, it is seen that the 64 character masks are actually 64 individual 13 .times. 24 matrices. The thirteen columns in each mask correspond to individual column shift registers 9301 through 9313. The 24 rows in each mask correspond to the 24 DTL bits (FIG. 94) in each shift register column. For ease in reference only one mask has been illustrated in detail, namely the mask for the character H. The plus signs at matrix grid locations represent locations where the presence of an image is expected for the character H; minus signs represent those locations where no portions of the H should appear. For example, a plus sign appears in column 2, row 5; this corresponds to a true output signal for bit 5 of shift register 9302. Likewise, a minus sign appears in column 5, row 6; this corresponds to a false state for bit 6 in shift register 9615. The outlines around the image H represent the boundaries of that image of 3 elements in width. Thus, imagining the boundary lines to represent a character superimposed on the mask, the character can be shifted over one column in either direction and still be recognized as an H. In effect then, as the data is being shifted through the various columns, the H can be recognized during any one of three individual vertical scans.

It is also noted that various grid locations in the matrix have multiple plus or minus signs; these indicate various weightings attributed to the presence or absence of character portions at these locations. A single plus sign or a minus sign has a weight of one, a double plus or minus sign has a weight of two, a triple plus or minus sign has a weight of four, and a quadruple plus or minus sign has a weight of eight. As mentioned above the plus corresponds to the true state of the bit in the appropriate shift register whereas the minus sign represents the false state. The pluses and minuses are summed through various resistors, with the resistors weighted as necessary, to provide a cumulative signal level. An identical character match (i.e., an H position within the shift register stages as illustrated in FIG. 97) provides the signal of greatest magnitude for the mask bus corresponding to that character. As described in subsequent sections, the mask plus having the highest amplitude above a predetermined minimum amplitude has its character recognized.

In addition to the plus and minus signs in individual grid locations, certain minus signs in adjacent locations are grouped, as illustrated by their common encirclement in the H matrix of FIG. 97. These negations are connected to the mask bus for that character through diodes in order that the absence of an image at those locations does not increase the degree of match (i.e., increase the amplitude of the bus signal) but the presence of an image decreases the degree of match since the diode is rendered conductive in such case and lowers the amplitude of the bus. The reason for this grouping is to permit differentiation between certain characters occupying a small portion of the grid area. For example, the difference between a period and a space is quite small; the grouping permits relatively sharp distinction between these two characters. The 64 individual character mask buses are applied to the best match detector as described in the next section.

III(B.3) BEST MATCH DETECTOR

The best match detector circuitry is illustrated in FIGS. 98 through 103. Each of the individual character mask buses, derived as described in relation to FIG. 97, is applied to a respective line amplifier 9801 through 9864. The amplifiers are grouped in four groups of 16 amplifiers, each group corresponding to a particular bus, namely: the SPL (special) bus, which primarily contains special symbols; the NUM (numeric) bus, which contains the ten numerals plus additional special symbols; the .alpha..sub.1 (alpha 1) bus, which accommodates the low end of the alphabet; and the .alpha..sub.2 (alpha 2) bus, which represents the high end of the alphabet. Amplifiers 9801 through 9816 are associated with the SPL bus; amplifiers 9817 through 1932 are associated with the NUM bus; amplifiers 9833 through 9848 are associated with the .alpha..sub.1 bus; and amplifiers 9849 through 9864 are associated with the .alpha..sub.2 bus. For example, the mask bus for the character H is connected to amplifier 9841 which is associated with the .alpha..sub.1 bus. The arrangement of character lines and bus columns is represented in Table R1 wherein the buses correspond to the vertical columns and the horizontal lines correspond to vertical rows of amplifiers in FIG. 98. Thus, the H amplifier 9841 is in line 8 along ##SPC2## with amplifiers 9809, 9825 and 9857. Amplifier 9841 is also in the third column along with amplifiers 9833 through 9848.

Each of the SPL, NUM, .alpha..sub.1 and .alpha..sub.2 buses feed respective amplifiers 9865, 9866, 9867 and 9868. All of amplifiers 9801 through 9868 take the configuration illustrated typically in FIG. 99. The base of transistor 9901 receives the mask bus signals in the case of amplifiers 9801-9864 or the four master bus signals in the case of amplifiers 9865-9868. The emitter of transistor 9901 for each of amplifiers 9801-9864 are tied to the respective buses with which those amplifiers are associated. Thus, the emitter of transistor 9901 in amplifier 9841 is tied to the .alpha..sub.1 bus. On the other hand, the emitter of transistor 9901 and each of amplifiers 9865-9868 is tied to a .SIGMA. bus. Considering first the 64 line amplifiers 9801-9864, the one amplifier of the 16 on each bus having the highest or most positive potential at the base of transistor 9901 causes the emitter of that transistor to rise toward the base potential. In so rising, the emitter causes the entire bus and all other emitters connected to that bus to rise to that potential. Since the base potential of all other transistors 9901 on that bus is lower than the base potential at the amplifier causing the bus to rise, all fifteen other transistors 9901 on the bus are back-biased. It is only the single activated line amplifier on any of the four buses, therefore, which supplies current to the load resistor at the input of the driver amplifier 9865-9868 for that bus. Likewise, only the single transistor 9901 for each bus conducts collector-emitter current. This conduction through transistor 9901 cuts off the otherwise conductive transistor 9902, thereby switching the collector of that transistor from logic zero to logic one. The output signal from the collector of transistor 9902 is utilized in the circuits of FIGS. 101A and 101B as described subsequently. With relation to the buses however it is seen that transistor 9901 for the one active amplifier on each bus provides a voltage which approximates the voltage on the most positive character mask bus. The amplifier of FIG. 99 thus provides both the voltage level of the most positive character line (at the emitter of transistor 9901) and the identification of the character line having the most positive voltage (at the collector of transistor 9902).

Similarly the bus (SPL, NUM, .alpha..sub.1, .alpha..sub.2, ) carrying the highest level signal causes its associated amplifier (9865-9868) to dominate the .SIGMA. bus and also provide an indication as to which bus is carrying the highest signal level. Specifically, if the highest recognition level is derived from the H mask, the base of transistor 9901 in amplifier 9841 receives a higher voltage than does the base of transistor 9901 in any of the other amplifiers 9801 through 9864. This voltage is applied to the .alpha..sub.1 bus whereupon it biases off amplifiers 9833 through 9840 and 9842 through 9848. It also activates amplifier 9867 which biases off amplifiers 9865, 9866 and 9868. The resulting level on the .SIGMA. bus corresponds to the voltage applied to amplifier 9841, less certain circuit losses. The collector of transistor 9902 and amplifier 9841 designates line 8 as the active line or row in table R1; the collector of transistor 9902 and amplifier 9867 designates the .alpha..sub.1 bus as the active column in table R1.

The .SIGMA. bus is applied to the amplifier illustrated in FIG. 100. The resulting amplified signal is designated MASK ANALOG and is applied to the circuit of FIG. 103.

Referring to FIG. 102 of the accompanying drawings, the output signals from amplifiers 9865 through 9868 are applied to a group of OR, gates 10205 through 10207. Specifically, the SPL bus is applied to gate 10205; the NUM bus is applied to gates 10205 and 10206; the .alpha..sub.2 bus is applied to gates 10206 and 10207; and the .alpha..sub.1 bus is applied to gate 10207. These gates effectively serve as a four line to three bit encoder, the three bits representing the coded states of the four vertical columns in table R1. The three bits, designated D5, D6 and D7 thus identify the bus which has been activated by a detected character. In addition signals D5 and D7 are utilized to address the individual multiplexer circuits 10101 through 10108 and 10116 through 10123 in FIGS. 101a and 101b. Thus, if the special bus contains the most positive character line, only the outputs from the special bus are passed through the multiplexers in FIGS. 101a and 101b. Whichever output bus signal is selected at the multiplexers, its level is inverted by inverters 10109 through 10115 and 10124 through 10131 to provide the line 1 through line 15 signals. These signals are applied in combinations to gates 10201 through 10204 serving as code converters to encode the selected line signal into four low order bits corresponding to the horizontal columns in table R1. These bits are designated D1 through D4 and combine with bits D5 through D7 in FIG. 113 to identify the character which has been recognized.

The MASK ANALOG signal, derived from the .SIGMA. bus as illustrated in FIG. 100, is applied to amplifier 10301 in FIG. 103. Amplifier 10301 is a high speed comparator which is utilized with flip-flops 10304, 10307, 10312 and 10316, and four switches 10308, 10309, 10313 and 10317, to provide an analog to digital conversion of the voltage level of the MASK ANALOG signal. Specifically, the circuit provides a four bit successive approximation to convert the analog signal into a four bit code represented by the signals WA1 through WA4. This code is the binary representation of the analog signal level from the mask analog amplifier. The four bit binary representation of the analog voltage, plus the seven bit character identification code as generated in FIG. 113, are fed to the best match store circuits in FIGS. 109 through 118. Negative NOR gate 10320 provides a WREN (write enable) signal whenever any one of the flip-flops 10304, 10307, 10312, 10316 are set to the one state at the termination of the analog to digital conversion process, or any time the mask analog voltage rises above zero. Since the mask analog voltage rises above zero only when the character line with the highest signal voltage rises above a predetermined threshold, the WREN signal occurs only when a character line rises above that threshold. The analog to digital conversion by successive approximation is a standardized technique and need not be described in detail herein.

III(B.4) BEST MATCH STORE

The logic circuits constituting the best match store circuitry are illustrated in FIGS. 109 through 118 of the accompanying drawings. In FIG. 113 there is illustrated a sixteen by eight bit memory comprising memory units 11303 and 11304. These receive, for purposes of storage, the seven signal lines D1 through D7 encoded in FIG. 102. The address lines for this memory unit are signals MA1 through MA4 derived from multiplexer 10902 in FIG. 109. The signals MA1 through MA4, in the write mode, correspond to the WA1 through WA4 signals generated in FIG. 103 as an approximation of the mask analog signal level. If any of the WA1 through WA4 signals is low, the WREN (write enable) signal at gate 11302 is high and, if other conditions are met, provides a write pulse for the memory unit 11303, 11304. This pulse enters the data appearing on the seven lines D1 through D7 into the memory at the addresses selected by signal lines MA1 through MA4. At the same time, the lines WA1 through WA4 are fed through multiplexer 10903 and are decoded by the four to twelve line decoder 10903 to provide a signal on one of the twelve bin lines depending upon the states of the four address lines WA1 through WA4. The selected bin line output signal at decoder 10903 is then written into the appropriate bit in register 11001 through 11003. The write command for these registers is designated WRITE and is derived from gate 11302 at the same time data is written into memory units 11303, 11304. At the trailing edge of the WRITE pulse the BIN CK signal (bin check) goes high at flip-flop 11609 to switch multiplexer 10902 from the write to the read mode. In this mode the level bins containing data are fed to the priority encoder 11101. This encoder encodes the highest order bin containing data into a four bit read address signal RA1 through RA4. This address is fed through the four bit adder 10901 to the read side of the multiplexer 10902. If the ADD BIT 1 and ADD BIT 2 signals are both zero at this time, the address provided by adder 10901 through multiplexer 10902 corresponds to the address of the character which is written into the highest location in the memory. The data which has been stored in the highest location in the memory is immediately transferred into register 11401 on leading edge of the next TPB pulse.

The ADD BIT 1 signal and ADD BIT 2 signal are generated in the circuitry of FIG. 118. This generator is set to zero by timing pulse TPF and is advanced sequentially upon the trailing edges of TPB, TPC, TPD and TPE. Therefore, initially both ADD BIT 1 and ADD BIT 2 are zero and so remain until the trailing edge of pulse TPB. Immediately after the trailing edge of TPB the ADD BIT 1 signal goes high and effects the addition of one bit at adder 10901. The address bits RA1 through RA4 are negative so that the addition of one bit to the minus number effectively decreases the address by one. Adder 10901 thus generates a new memory address for the bin immediately below the highest level bin in which data was written. This produces an output signal from decoder 10903 on the bin line which is one below the highest level stored. This is compared, in the circuitry of FIG. 112, against the output signals from register 11001, 11002, 11003 to determine whether or not data has been stored in that next lower order bin. At the same time the memory data bits 1 through 7 at memory unit 11303, 11304 are compared with the bits stored in register 11401 at comparator 11501, 11502. If the data stored in memory unit 11303, 11304 immediately below the highest order bit is the same as in the higher order bit, the COMP OUTPUT signal from comparator 11502 goes high. This COMP signal is invertd by invertor 11606 to enable gate 11602. If the low bin were occupied and the COMPARE signal were low (in other words the date in the bin immediately below the highest level stored were not compared), gate 11602 is actuated which sets the recognition inhibit flip-flop 11603, 11604 at timing pulse TPC. On the trailing edge of TPC the add bit counter 11808, 11809 advances to the count of two. This subtracts two from the address of the highest stored location and again, at the TPD pulse, the contents of memory unit 11303, 11304 are compared against the stored outputs to determine whether or not the recognition inhibit flip-flop should be set. On the trailing edge of TPD the add bit counter advances a third step, subtracting three from the address of the highest stored at TPE. Again a check is made to determine whether this bin has data in it, and if the data agrees with the data in the top most stored bin. At the end of TPE, counter 11808, 11809 advances back to zero count.

If during any of the previous steps the recognition inhibit flip-flop 11603, 11604 had been set, gate 11711 would be inhibited to prevent generation of a character recognition signal (CHAR REC) at flip-flop 11712, 11713. While the bin checks are in progress, the read address signals (RA1 through RA4) are fed to the circuit of FIG. 117 where it is determined whether or not the signal with the highest stored level is of sufficient level to justify generation of a CHAR REC (character recognized) signal. If RA4, RA3 and either RA2 or RA1 are enabled, gate 11709 is enabled to cause gate 11710 to apply a high signal to gate 11711. If the recognition inhibit flip-flop is not set (REC INH is high) and the RDEN (read enable) signal is high gate 11711 goes low at the next TPF pulse to set the character recognized flip-flop 11712, 11713. If the recognition inhibit blip-flop 11603, 11604 has not been set (REC INH is high), and if the read enable signal (RDEN) is high at TPF time, gate 11711 goes low to set the character recognition flip-flop 11712, 11713. Similarly if signal RA4 is low and either RA2 or RA3 is low (a read address corresponding to 10, 11 or 12) and the window signal is high, gates 11708, 11710, 11711 are actuated to set the recognition flip-flop again.

When the CHAR REC signal is high gate 11714 is enabled. At TPD gate 11714 generates the G REC signal which is connected to flip-flop 11719, 11720. The resulting MPRW signal from the flip-flop is the MACHINE PRINT WRITE signal utilized in FIG. 121. The machine print write flip-flop 11719, 11720 is also triggered by a SPACE signal. The TPD pulse following initiation of a SPACE signal enables gate 11718 providing a low output signal from that gate. This signal, or a low ERROR signal can also set the MPRW flip-flop. Thus the MPRW flip-flop may be set by a character recognition, a space character detection, or a read error condition. The CHAR REC signal goes high at the leading edge of TPF; the G REC (gated recognition) signal goes low at TPD. The reason for the delay is to permit the window delay flip-flop 11715 to remain high long enough to set the character recognized flip-flop 11712, 11713 before the window delay flip-flop has been reset. The DELRST (delayed reset) signal, the G REC (gated recognized) signal and the ERROR (read error) signal, all active low signals, are fed to gate 11716. Any of these signals going low resets the window delay flip-flop 11715. This flip-flop remains reset, with the WIND DELAY signal low, until the beginning of the next window time when the window signal is received to clock flip-flop 11705. The purpose of the window delay is to inhibit generation of additional recognitions until the following window time, so that multiple recognitions cannot occur.

The MCD (mask centered delay) signal is utilized during step RPS9 of the read program. When step RPS10 is not active, signal RPS10 is high producing a low level at one input of gate 11802. When the DELRST signal goes high the MCD signal goes high. During step RPS9 however signal RPS9 is low and gate 11802 does not go low until the beginning of the first window time when the signal WINDOW goes low. This causes the MCD signal to remain low keeping the RESET 4 signal low until the beginning of the first window time during RPS9.

III(B.5) LOW DENSITY SCALER

The low density scaler circuits are illustrated in FIGS. 92 and 96. This unit serves three major functions: (1) generation of various shift clocks; (2) generation of the mask centered signals; and (3) gating of MUXSD (serial data) signals.

A two-input AND gate 9201 gates the MUXSD signal from shift register 8983 with the BLKS EN 1 signal to provide the multiplexed data (MUX COL 13) which is sent to shift register 9313. The BLKS EN 1 pulse reduces to 38 columns in width for six lines per inch operation during load format time, and widens to fifty columns at six lines per inch operation during read time.

As mentioned in relation to the quantizer multiplexer description, the MUX CLK signal comprises the timing pulse train TPA with the first pulse after MUX63 time deleted. This signal is generated at gate 9202 with the aid of flip-flop 9203. MUX63 is fed to the D input of flip-flop 9203; timing pulse TPC is fed as a clock input; thus, at TPC during the MUX63 count interval, the high MUX63 state is transferred as a low to the Q output of flip-flop 9203, thereby inhibiting gate 9202. The flip-flop 9203 is not reset until the next TPB pulse; thus the TPA immediately following MUX63 is disabled during the one count interval after MUX63.

Flip-flop 9024 is utilized in the generation of the MOS CLK signal. The D input of flip-flop 9204 is continuously held high; thus at TPB time the positive-going clock for flip-flop 9204 transfers the high D input to a low Q output which causes inverter 9205 to go high. This high remains until flip-flop 9203 is reset by timing pulse TPD so that the MOS CLK signal, which rises at the leading edge of TPB, falls at the leading edge of TPD.

The mask centered determination is performed by registers 9601-9603 in conjunction with AND gates 9604-9607 and 9609. Enter pulses for registers 9601-9603 are produced for each shift of the image through the thirteen shift register columns (i.e., each vertical shift of the image through the mask) by the DEW pulses derived at gate 9209. The BLKS EN 2 pulse, which is approximately 24 shift elements in width for six lines per inch and full height at three lines per inch operation, is applied to gate 9209. The output for this gate goes low for each TPF pulse during the blacks enable 2 interval. The resulting DEW signal therefore enters into registers 9601-9603, an indication as to whether a black or logic 1 is entering each of shift registers 9301-9312 at that time. If a black is entering the particular shift register at that time, the COL signal for that register is low. This low is entered into the appropriate bit of registers 9601-9603 where it remains until the clear W time (signal CLR W), which occurs after the following MUX63 interval. Therefore, any black or logic one entering a shift register column causes an indication at registers 9601-9603 no matter what position that black or logic one occupies in the mask, as long as that black or logic one coincides with a blacks enable 2 time frame. The thirteenth shift register column 9313 is handled similarly except that it is applied to flip-flop 9611 via AND gate 9610 which is also gated by the DEW pulse. If a black appears in column 13 during any TPF pulse, AND gate 9610 provides a logic one which sets flip-flop 9611. This flip-flop remains set until the CLR W pulse resets the flip-flop. It is to be noted that a low applied to the input of a stage in register 9601-9603 is reflected as a high at the corresponding output terminal for that stage.

A mask centered condition, represented by the MASK CENT signal, occurs if there is data or a blacks indication in any of columns 2 through 6 (i.e., shift registers 9302-9306) but no data in shift register column 9301. If there is no data in column 1, the W1 signal, derived from register 9601 and inverter 9608, is high. If there is data in column 2 the W2 signal derived from register 9601 is high. If there is data in columns 3 through 6, the W3456 signal derived from gate 9605 is also high. These three signals are all applied to AND gate 9206, and when all are high they enable gate 9207. If there is data in the mask, the mask full signal is high so that at MUX63 time gate 9207 is actuated to provide the MASK CENT signal.

Gates 9604, 9606 and 9607 are utilized to determine if all 13 channels ever have data entered therein simultaneously. If this condition occurs a straight line has been detected causing NAND gate 9609 to go low resulting in a low SL signal. This signal indicates that a line wider than any character width has been detected and therefore, insofar as resynchronization of the column counter window generator is concerned, a MASK CENT signal cannot be expected to occur within the normal one character spacing.

The CLR W signal (clear window) which occurs slightly after the MUX63 interval, is generated at gate 9617. The TPD pulse occurring during MUX63 interval causes gate 9612 to provide a low output signal and thereby set flip-flop 9614. At N/2 time, which occurs two counts after the MUX63 interval (reference timing diagram FIG. 49), one input to NAND gate 9617 is high. At the next TPB pulse gate 9617 is actuated to provide the binary 0 CLR W pulse. In the interim, the MUX63 signal has gone low causing inverter 9613 to go high. Therefore at the next TPD pulse during the N/2 time after MUX63 occurs, flip-flop 9614 is reset. Consequently, only one CLR W pulse is generated during the scan cycle, and that pulse is coincident with the TPB timing pulse occurring approximately two counts after MUX63.

III(B.6) COLUMN COUNTER AND WINDOW GENERATOR

The logic circuitry for the column counter and window generator is illustrated in FIGS. 104 through 108 of the accompanying drawings. The column counter may be considered as a fly wheel which is synchronized to the character spacing for the particular format being read. The purposes of such fly wheel are: (1) to identify those times when a second character should be present; (2) to identify the times when a space character should be generated; and (3) if a character is not recognized, to determine the time at which a "character non-recognized" signal should be generated. The basic counting circuitry is composed of two divide-by-16 counters 10401, 10402. These are connected together in a normally divide-by-256 configuration; however, the counter is recycled for different operating modes as follows: at count 17 during OCR-A 8 pitch operation; at count 28 during OCR-A 10 pitch operation; at count 23 during front 7B 6 pitch operation; at count 20 during font 7B 7 pitch operation; at count 33 during hand written 4.3 pitch operation; and at count 28 during hand written 5 pitch operation. Since recycling occurs at the end of one of these counts, the counter division ratio varies. For example, during OCR-A 10 pitch operation, the counter becomes a divide by 29 counter. That is, a count of 28 is fed into data selector multiplexer 10412. When the count of 28 is reached at counter 10401, 10402, the RECYCLE signal goes low at the load inputs of the counters. At the following clock time (i.e., the trailing edge of MUX63 G when the clock inputs to the counters go high), the information on the parallel data inputs is transferred into the counters. Since the parallel data inputs are all grounded, the counters recycle to a count of 0.

The six output bits A.sub.0 through F.sub.0 of counters 10401, 10402, are decoded in the circuitry of FIG. 105 to provide the various count signals utilized at multiplexer 10412 to provide the RECYCLE signal under the specified operating formats. For example, decoding of the 28 signal applied to multiplexer 10412 is effected at NAND gate 10510 which receives the C.sub.0 D.sub.0 and E.sub.0 bits from counters 10401, 10402. These bits all become high at the start of count 28, at which time the 28 signal goes low.

The two eight-input data selector multiplexers 10405, 10406 are employed to select the proper counts at which to begin and terminate the window for the various fonts and font spacings. For example, for OCR-A operation, the window is started at the count of 10 and then again at the count of 24. The signal 10 + 24 goes low at counts 10 and 24 and appears at this low level during those counts of OCR-A operation is in effect. If OCR-A 10 pitch operation is in effect, the MUX63 G signal, which is actually timing pulse TPF during the MUX63 interval, then drives gate 10407 low to provide a high WINDOW signal at the output of flip-flop 10409, 10410. This WINDOW signal thus goes high during counts 10 and 20 at counters 10401, 10402. At count 3 or 18 multiplexer 10406 provides a low signal to prime gate 10408. This gate is enabled by signal MUX63 G to reset flip-flop 10409, 10410 at counts 3 and 18. From the foregoing it is seen that the WINDOW signal, for OCR-A 10 pitch operation, goes high at the count of 10 and low at the count of 18, and then goes high again at count 24, remaining high as the counter recycles at count 28, until the count of 3 is reached at which time the WINDOW signal goes low. Gates 10407 and 10408 are clocked by the inverted MUX63 G pulse which defines the normal time for turning the WINDOW signal on and off; however, an additional signal may be utilized to actuate the WINDOW signal. This signal is called MCRG which is derived at gate 10806 and described in detail subsequently. The RDEN signal is utilized to inhibit generation of the WINDOW signal during the time RDEN is low (i.e., no read enable).

Data selector 10411 is utilized to generate the M WIND (mid window) signal. The mid window condition occurs at various counts of counters 10401, 10402 during different operating modes, as follows: At counts 14 or 28 during OCR-A 10 pitch operation; at count 17 during OCR-A 8 pitch operation; at count 20 during 7B font 7 pitch operation; during count 23 in 7B font 6 pitch operation; at count 28 during hand written mode 5 pitch operation; and at count 33, during hand written mode 4.3 pitch operation. The M WIND signal is utilized in conjunction with the blacks counter 10702 to determine whether or not a SPACE CHARACTER signal (SPACE) should be generated.

The circuity for determining the proper pitch is illustrated in FIG. 105. Primary pitch control is effected by the font switches at the control panel connector board. When font A is selected, the Font A SW signal is low and actuates gate 10525 to provide a high 10 pitch signal. Since the font switch is a rotary switch, only one font at a time may be selected. When font B is selected, gate 10520 is actuated to provide a high 7 pitch signal. When the font selection switch is moved to the mixed position, the MIXED signal goes low and drives inverter 10525 high. If the load format mode (LDFT) is not in effect, gate 10524 provides a low DECEN (decode enable) signal which is fed as an enable input to three-bit to eight-line decoder 10517. This decoder converts signals HCR11, PITCH 1 and PITCH 2 to an indication of the proper font as follows: If these signals represent octal 0 or octal 1, handwritten 10 pitch is selected. For octal 2, 7 pitch font B is selected; for octal 3, 5 pitch is selected, for octal 4 or octal 5 OCR-A 8 pitch is selected, for octal 7 handwritten 4.3 pitch is selected. During load format, the decoder is disabled and since the LDFT (load format) signal is low, gate 10523 is actuated to force 10 pitch opeation. Thus, in load format mode, the system automatically switches to OCR-A 10 pitch operation.

The pitch selected as a result of the font switch position, the load format condition, and/or the HCR11, PITCH 1,2 conditions from main memory, and re-encoded into a three bit signal is designated CTR BIT 1, CRT BIT 2, and CTR BIT 3 (counter bits 1-3). CTR BIT 1, the output of gate 10512, is high unless hand written 4.3 pitch or hand written 5 pitch are selected. CTR BIT 2, the output of gate 10513, is high if OCR 10 pitch or OCR 8 pitch are selected. CTR BIT 3, the output of gate 10516, is high if OCR-A 8 pitch, 7B font 6 pitch, or handwritten 4.3 pitch are selected. these counter bit signals are utilized as the address input signals for the data multiplexers 10405, 10406, 10411, 10412 to provide proper window timing and spacing.

FIGS. 106 through 108 illustrate the basic circuitry utilized to maintain the window counter synchronized with the data and to determine if a space, error, or "delete line" is detected. Serial data (MUXSD) from the quantizer multiplexer enters the blacks counter 10702 as serial data when the system is in OCR-A operation. The SHIFT CLOCK pulses clock the data into counter 10702 so that output data from the quantizer multiplexer is fed to the counter as it is shifted into column 13 shift register 9313. For each black (logic 1) shifted into the 9313 shift register, one count is added to counter 10702. During OCR-A operation, CTR BIT 2 is high so that AND gate 10703 is primed. When outputs C and D of counter 10702 are both high (i.e., a blacks count of 12 has been reached), gate 10703 is enabled and applies a logic 1 signal to the J input of flip-flop 10707 via OR gate 10706. At the end of the next TPA pulse this logic 1 is transferred to the output of flip-flop 10707 to provide the MASK FULL signal. Mask full goes high, therefore, on the first shift pulse,(TPA) after twelve blacks have been counted at counter 10702. If either hand written or 7B font is selected, CTR BIT 2 goes low, disabling gate 10703. Counter 10702 then must count to 15, at which time the carry output of the counter clocks flip-flop 10704 to drive its output high and prime gate 10705. Counter 10702 again counts up to fifteen and enables gate 10705 to apply logic 1 to the J input of flip-flop 10707. Thus, for handwritten or 7B font, 31 blacks must be counted before a MASK FULL signal is generated. The blacks counter 10702 and MASK FULL detector 10703-10707 are cleared each time a character is recognized, a space is detected, or an error signal is generated as discussed subsequently in relation to the generation of the RESET 2 signal.

Assume that no new blacks have entered the blacks counter 10702 since the last character recognized signal was generated. In such case the MASK EMPTY signal from flip-flop 107 is high and is applied to gate 10710. If the system is in the read mode rather than in load format, the LDFT signal also primes gate 10710. At mid window time, the M WIND signal is high so that when MUX63 and TPE actuate gate 10709 during mid window time, NAND gate 10710 is enabled and provides a low signal at flip-flop 10712, 10713. This sets the flip-flop and generates a high SPACE signal. If, however, at least 12 blacks have been counted by blacks counter 10702 before mid window time is reached, the mask full flip-flop 10707 is set, causing gate 10710 to be inhibited and preventing generation of the SPACE signal.

If the assemblage of detected blacks entering the array is unrecognizable, the error detection circuitry in FIG. 106 provides an error indication. The end of window detector includes two-bit counter 10606, 10607 which changes state on positive-going edges of clock input TPA. When the window signal is high, the Q output of flip-flop 10606 is low and the Q output of flip-flop 10607 is high. Immediately after the window signal goes low, the following TPA pulse causes the Q output of flip-flop 10606 to go low, enabling the negative AND gate 10605 and providing a high input signal to gate 10604. Since the MASK FULL signal has already been generated, another input to gate 10604 is high. Assume that the WINDOW DELAY signal, the READ ERROR INHIBIT signal (REI), and the ERROR RESET INHIBIT (ERI) signal are high. Therefore at TPD time gate 10604 is enabled, setting the read error flip-flop 10602, 10603, and causing the ERROR signal to go low as an indication of error. The second shift pulse (TPA) after the window signal goes low causes the Q output of flip-flop 10607 to go high, disabling gate 10605 to remove the set signal to the Read Error flip-flop 10602, 10603. The ERROR signal is fed through gate 10601 as a high RERF (read error flip-flop) signal, which is sent to the main memory as a reader reset flag.

The read error flip-flop 10602, 10603 and the space flip-flop 10712, 10713 are both reset by the RESET 4 signal. RESET 4 is generated by the circuit in FIG. 108 and is provided by either the DELRST signal going low or the ACK (acknowledge) going high. The ACK signal results from completion of a write cycle at the main memory. The DELRST signal is discussed subsequently. When the main memory has acted upon the ERROR or SPACE signals, a memory cycle complete indication is provided and inverted to the ACK signal in the circuit of FIG. 120. The ACK signal is then passed by gate 10816 as a low signal to provide the RESET 4 signal which resets the space and read error flip-flops.

The delayed reset generator includes inverter 10825, flip-flop 10823, and NAND gate 10824. A low RDEN signal is inverted by inverter 10825 and fed to the data input terminal of flip-flop 10823. This flip-flop is clocked by the MUX63 G signal (TPF during MUX63). The low RDEN signal is also applied to NAND gate 10824. When the read enable condition is not active, signal RDEN is high and the Q output of flip-flop 10823 is high. Gate 10824, having both inputs high, provides a low DELRST signal. During a read enable condition, the RDEN signal is low causing gate 10824 to provide a high DELRST signal. Sometime after the read enable condition has been activated, flip-flop 10823 is clocked by the MUX63 G signal to drive the Q output signal from that flip-flop low to further disable gate 10824. When the read enable condition is deactivated, signal RDEN goes high but flip-flop 10823 maintains gate 10824 in its disabled condition so that the DELRST signal remains high. This condition subsists until flip-flop 10823 is next clocked by the MUX63 G signal at which time gate 10824 is enabled to provide a low DELRST signal. Thus, DELRST goes high in time coincidence with activation of the read enable condition but stays high for a time duration after the read enable condition has been deactivated. This time duration is approximately 120 microseconds; that is, the time duration is sufficient to permit completion of any signalling between the recognition circuits and the master memory after the read enable condition has deactivated.

The RESET 1 signal is generated by gate 10814 and inverter 10815. The input signals to negative OR gate 10814 are the DELRST signal, the GMCR signal, and the CHAR REC signal. The GMCR (gated mask center reset) signal is discussed subsequently. When any of these signals goes low, the output signals from gate 10814 goes high to provide a low RESET 1 signal at the output of inverter 10815. This signal is utilized to reset the end of window detector in FIG. 106.

The RESET 2 signal is generated by gate 10809 and inverter 10811. RESET 2 goes low if either a SPACE, ERROR, CHARACTER RECOGNIZE, or DELAYED RESET signal is received. RESET 2 is utilized to reset the blacks counters 10702 and the MASK FULL flip-flop 10707.

The RESET 3 condition is similar to the RESET 1 condition in that a mask center reset, a character recognized or delayed reset condition produce a high RESET 3 signal as long as signal ERI remains high. The ERI signal is fed to gate 10813 and permits that gate to provide the RESET 3 signal when any of the aforementioned conditions are met. RESET 3 is utilized to reset the window counters 10401, 10402.

The gated mask centered reset condition occurs only for the first character after a space or after the read enable flip-flop is set; that is, the first character is being read in a line or a field. The GMCR signal is generated by circuitry in FIG. 8. As previously stated, the SPACE signal is inhibited in load format mode by the LDST signal at gate 10710. This is necessary because the main memory, in load format mode, stores only the locations of active characters and not of space characters. In order to accommodate both the regular read mode and load format mode, an auxiliary pseudo (P SPACE) signal is generated at gate 10708. The signal goes low at mid window time whenever a MASK EMPTY signal is detected, whether or not the system is in load format mode. The P SPACE signal is fed to gate 10803 which is cross coupled to gate 10802 to define the read error inhibit flip-flop. The other input to the set side of this flip-flop is DELRST (delayed reset) so that after DELRST or P SPACE go high, the flip-flop output remains high and generates a low REI (read error inhibit) signal at inverter 10810. The REI signal, as previously mentioned, is fed to gate 10604 in the read error detector. Thus, when the read error inhibit flip-flop 10802, 10803 is set, the READ ERROR signals are inhibited. The read error inhibit flip-flop remains set until the CHAR REC signal goes low or an REIRST (read error inhibit reset) signal goes high and is gated by TPE. When the read error inhibit flip-flop 10802, 10803 is set, its high output is fed to gate 10805 as a high level. If a high MCD signal is received at gate 10804, the output of that gate goes high during each TPD interval thereafter, priming gate 10805 at each TPD time. When a MASK CENT signal is received at TPD thereafter, the output of gate 10805 goes low. This low signal is the GMCR signal (gated mask centered reset). This is one of the RESET signals used to reset window counter 10401, 10402. The window counter being reset at mask center time allows for additional time to obtain a character recognition before an ERROR signal is produced. A mask centered condition occurring at read error inhibit time causes gate 10805 to also actuate gate 10806 when RPS9 is high (in other words during step RPS6). When RPS9 is high gate 10806 is enabled producing a low MCRG signal. This gate is fed to the window generator circuit of FIG. 104 and serves to turn the window on as soon as a mask centered condition occurs during RPS6, after either spaces have been received or the read enable has just been set. Thus, not only is the window counter 10401 reset to zero by MCRG, but the window is turned on at MCRG time (at mask center time in this case during read error inhibit).

During RPS9, due to the fact that the read enable is turned on just as the new character is entering the mask matrix, the previous character is in the mask matrix. Thus if read enable is turned on slightly early, a premature mask centered condition could be produced. For this reason the MASK CENT signal does not turn the window on during RPS9. During RPS9 gate 10413 is raised to a high level by the MWIND (mid window) signal to provide a GMWIND (gated mid window) signal. This signal is fed to gate 10818 and, if mid window is reached during MUX63 G time, gate 10818 resets flip-flop 10820. This flip-flop had been turned on by the WINDOW signal going low. When the WINDOW signal goes high the flip-flop remains on until the GMWIND signal is received. The BLKS EN 2 signal is only high from the time the WINDOW signal is high during RPS9 until the mid window condition is reached or a mask center is reached. The blacks counter 10702 is only enabled these two times. The circuit is required during operation at six lines per inch to reduce the possibility that the trailing edge of letters in the line above or line below will produce erroneous mask full condition if a space were actually being scanned in a desired line. Further, if these blacks from adjacent lines are toward the right hand edges of their respective characters, they could delay the window generated by the MASK CENTERED signal such that during successive RPS9 rescans, when the left hand edge of the character following the space is coming into the array, by the time the end of window is reached this again could produce erroneous mask full conditions. For this reason, the absence of a MASK FULL signal at gate 9207 inhibits the MASK CENT signal and thus random blacks or blacks from the right hand portions of characters above or below the line during six lines per inch operation, cannot produce an erroneous mask centered condition. In other words, as has been previously stated, the mask center condition can cause the reset of the window counter immediately after a space or immediately after the read enable flip-flop has been set.

DATA CONTROL

The data control circuits are illustrated in FIGS. 119 through 124 of the accompanying drawings. The main functions of the data control circuits are: (1) generation of the end of field character; (2) generation of the space character; (3) encoding errors; and (4) correlating these functions with the output signals from the best match store circuits. The data control circuits also generate the vertical window utilized in six lines per inch operation.

The four-line to two-line multiplexers 11902, 11903, 11904, are illustrated in FIG. 119. If the address inputs to these multiplexers are 00, the machine printing bits MPB1-MPB6 are connected through to the RDCl-RDC6 data outputs. The signals that modify the addresses at the multiplexers are the SPACE signal, the HWMASK signal, the ERROR signal, and the EOF (end of field) signal. When the system is in the hand written mode or in the 7B font mode the MASK signal is high causing a high input at gate 11915. If a character is recognized and a space is not generated, the other input to gate 11915 is also high and this causes the gate output to go high. If an error is not present one input of gate 11911 is high, causing the OUTPUT signal from that gate to go low and therefore drive gate 11912 high. Since the ERROR signal is high and the EOF signal is also high (no end of field), gate 11913 remains low. Thus the address code to the multiplexers is 01, causing hand written bits (not used) to be transferred through the multiplexers to the RDC1 through RDC4 data outputs. Hand written data bits 5 and 6 are connected to positive voltage to produce a high on RDC5 and RDC6. If RDC6 is high, gate 11914 provides a low for RDC7. If an error is detected, gate 11911 is disabled. In this case the level from gate 11912 drops to zero; however the ERROR signal fed to gate 11913 causes the output of that gate to go high. Therefore the address code is 10, in which case RDC1 through RDC5 are high, RDC6 is low, and RDC7 is high. This is the character code for an underline, which is utilized in the system to denote an error character. When a space is detected during hand written operation, the positive-going space signal inhibits gate 11915. This disconnects the multiplexer data lines from the hand written decoder and reconnects the data lines to the machine print bits MPB1-MPB6. This is done because the space code is generated in the best match store circuits fed by MPB1 through MPB6.

An end of field code produces a low EOF signal at inputs to gates 11912, 11913, causing the outputs of both gates to go high. The address input to the multiplexers is then 11. Under this condition RDC1 and RDC4 are connected to B+, RDC2, RDC3, RDC5, and RDC6 are connected to ground. Gate 11912 produces a low at RDC7 which generates the TAB signal, (i.e., the HORIZONTAL TAB signal which is utilized as a field separator). RDC1 through RDC6 are fed to the main memory.

Gate 11916 is utilized to decode the over-strike character when MPB1 and MPB2 are high, and MPB3 through MPB6 are low. The resulting low provided by gate 11916 is inverted by inverter 11917 to high level and sent as an over-strike flag to main memory.

In FIG. 124 data bits RDC1 through RDC7 are fed to exclusive OR gates 12401-12407. These gates provide RDC8 which is the odd parity bit for data bits RDC1 through RDC7. RDC8 is also fed to the main memory.

The EOF signal is generated in circuit of FIG. 121. During read enable, the RDEN signal is low. If the system is in read program step RPS6 and in mixed font operation, gate 12101 is low and combines with the low RDEN signal at gate 12103 to drive that gate high. This provides a high at the data input of flip-flop 12105. Normally the MCYC and MPRW signals are high and prime gate 12102 so that the normal condition is to allow the TPE pulses to be passed to clock flip-flops 12105 and 12106. Thus, during the read mode, the Q outputs of flip-flops 12105 and 12106 are normally high. The data input to flip-flop 12107 is held high while the clock is held low. When RDEN goes high (i.e., no read enable) gate 12103 goes low. If this happens during MCYC cycle or during an MPRW period, gate 12102 goes low. As soon as these signals go high again the following TPE pulse is fed through gate 12102 as a high signal which transfers the low data input at flip-flop 12105 to the Q output of that flip-flop, causing the Q output to go high. This causes the Q output of flip-flop 12107 to go low and provide a high OCRW write command from negative NOR gate 12107. At the same time the low EOF signal (end of field) is provided. When the main memory has acted upon the OCRW write command, the RESET 4 signal goes high, resetting flip-flop 12107. In the meantime the following TPE pulse transfers the low data input at flip-flop 12106 to the Q output of that flip-flop, disabling the data input to flip-flop 12107. Thus the outputs of flip-flops 12105, 12106 are so arranged that flip-flop 12107 is set only at the negative going transition or shortly thereafter of read enable. The normal machine print write command MPRW from the best match store is fed to gate 12108 where it is combined in an OR function with the EOF signal to produce the OCRW commands.

The data control circuits also contain three vertical window generators (FIGS. 122, 123) required for six line per inch operation. These vertical windows comprise the following signals: BLKS EN 1 (blacks enable 1), which is required for enabling the mask and the line position analysis circuitry; BLKS EN 2 (blacks enable 2), which is utilized for enabling the blacks counter 10702; and WRINH (write inhibit) which inhibits the write enable command except in those vertical periods when a valid character recognition should occur. The positions of these windows in time vary with respect to the MUX63 interval, depending upon the determination by the line position analysis circuits as to where the centerpoint of the next line should be. The main control signals for the starting and stopping of the various windows are provided by the output counts of the multiplex count of FIG. 90. These are MUXA, MUXB, MUXC, MUXD, MUXE, MUXF. Adders 12201, 12205 are four bit adders which are combined as a six bit adder and serve to add the count from the multiplex counter (FIG. 90) to the derived count from the line position analysis circuits (bits FMCK4, 8, 16, 32). The two least significant FMCK bits are not transmitted from the line position analysis circuit. Bit FMCK4 is fed to inverter 12202, FMCK8 is fed to inverter 12203 and FMCK16 is fed to inverter 12204. In the line-centered condition, FMCK32 is high, FMCK4, 8 and 16 are low. By inverting FMCK4, 8, and 16, an effective count of 31 is added to the output of line position analysis circuit. With the carry input to adder 12201 held high, an additional one bit is added. This therefore adds a count of 32 to the output of the line position analysis circuit, which produces a total addition of 64. In other words, the .SIGMA.A through .sigma.F outputs from adders 12201 and 12205 rise in coincidence with the respective MUXA through MUXF inputs. However, if the line position is found to be four counts high, the signal sent from the line position analysis circuits is the count 28. That is, FMCK32 is low whereas FMCK16, 8, and 4 are high. This count however, through the use of inverters 12202, 12204 and due to the fact that the carry input to the lowest bit is held high, is transformed to the count of 2. In other words, the outputs .SIGMA.A - .SIGMA.F rise and fall two counts in advance of the MUXA through MUXF signals. Similarly if the line position were four counts or one step low, FMCK4 would be high, FMCK8 would be low, FMCK16 would be low and FMCK32 would be high, producing a total count of 36. However, since FMCK16, 8 and 4 are inverted, it is evident that the count to be added is 58. Since the count of 58 in six less than the count of 64, it is apparent that .SIGMA.A through .SIGMA.F rises six counts later than the respective MUXA through MUXF driving signals. Likewise as the FMCK4 through 16 bits vary between counts of 12 and 52, the output .SIGMA.A through .SIGMA.F varies from leading by 18 counts to lagging by 22 counts. The lead or lag is effected in four count increments; therefore, a lead would be by 2, 6, 10, 14, 18 or 20 counts, and a lag would be by 6, 10, 14, 18 and 22 counts. The two count bias in the downward direction is needed to compensate for the bias put into the line position analysis count; that is, the average bias for the line position analysis circuitry is two counts high.

The BLKS EN 2 signal goes high at the beginning of summation count (i.e., counter 9003, 9004 plus the FMCK bits) of 20 and low at the beginning of summation count 44. Thus, during six lines per inch operation, the set signal at flip-flop 12314 is high and permits the flip-flop to toggle. The first time .SIGMA.C, .SIGMA.E and .SIGMA.F are all high, which time coincides with the beginning of summation count 20, gate 12312 goes high at TPA. This sets flip-flop 12314, causing the BlKS EN 2 signal to go high. It remains high until the TPA of the first count where .SIGMA.C, .SIGMA.D, and .SIGMA.F are all high, which occurs at the beginning of summation count 44. (During three lines per inch operation the 6 LPI signal is low, causing flip-flop 12314 to remain set). BLKS EN 2 thus remains high for approximately 24 counts, beginning with summation count 20 and ending with summation count 44. If the line position analysis circuit indicates a center condition, this means that the BLKS EN 2 signal is centered in time about the vertical scan.

During six lines per inch operation flip-flop 12317 is also permitted to toggle. At the first count in which .SIGMA.C, .SIGMA.E and .SIGMA.F are high (that is, summation count 36), gate 12315 sets flip-flop 12317. Since all input signals to gate 12319 are high at this time, the WRINH output signal from that gate goes high. WRINH stays high until .SIGMA.A, .SIGMA.E, and .SIGMA.F all go high at gate 12316. The first time this happens is at the beginning of summation count 56. Gate 12316 resets flip-flop 12317 and causes signal WRINH to go low. During three lines per inch operation the 6LPI signal is low, keeping WRINH high, provided none of the other inputs to gate 12319 go low.

There are two other conditions which cause WRINH to go low. The first situation occurs if for any reason the amplitudes on two of the SPL NUM .alpha..sub.1, .alpha..sub.2 buses are the same. Under such conditions, all of the bus lines SPL, NUM, .alpha..sub.1 and .alpha..sub.2 are high, causing WRINH to go low. The second situation occurs if the hand written or 7B font is chosen. In this case the CTR BIT 2 signal is low, inhibiting the WRINH signal.

It is to be noted that the BLKS EN 2 signal is of sufficiently short duration that it can be advanced or retarded the full 20 counts in each direction without extending into the adjacent column scan period. The write enable or WRINH may extend into the following vertical scan interval if a lag of 20 counts is generated or detected in other words if the image were up to 20 counts low. This however is acceptable since by the time the image is centered in the mask, the beginning of the following scan interval is in effect.

In order to maintain proper operation of the vertical position analysis circuit or the line position analysis circuit, the BLKS EN 1 signal must be turned on no earlier than MUX count 2 and turned off no later than MUX count 62. Therefore, if more than a four count advance is generated, BLKS EN 1 must go high at MUX count 2 rather than under the control of the summation count. The circuit for effecting this includes gates 12303-12306. If FMCK8, 4, or 16 are low, gate 12304 goes high. If FMCK32 is also high, gate 12305 is enabled, disabling gate 12306 but enabling gate 12303. This primes gate 12301. When MUXD and MUXF are high, gate 12301 is driven low and flip-flop 12307 is set. With the assumed conditions of FMCK32 high and either FMCK8, 14 or 16 low, a summation count of less than 28 is generated. Under these conditions the BLKS EN 1 signal is prevented from turning on before MUX count 2.

If FMCK32 is high or FMCK32 is low and all of FMCK8, 14, or 16 are high, gate 12306 is low. Gate 12301 is disabled while gate 12306 is enabled, allowing the .SIGMA.A, ENSTP, .SIGMA.C, and .SIGMA.F signals to proceed through gate 12309 and cause gate 12306 to go high. This high-going transition clocks the high at the data input of flip-flop 12307 to set that flip-flop.

The ENST (enable start) and ENSTP (enable stop) signals are generated at multiplexer 12206. In the read mode (LDFT high), ENST corresponds to .SIGMA.B and ENSTP corresponding to .SIGMA.D. Thus, at summation count 7, gate 12308 is enabled, setting flip-flop 12307 and causing BLKS EN 1 to go high. Gate 12309 is enabled when .SIGMA.A, .SIGMA.D, .SIGMA.E and .SIGMA.F are high, which correspond to summation count 57, at which time blacks enable 1 flip-flop 12307 is reset by a low signal. Since the summation count is generated from the summation of the MUX counter (FIG. 90) and the line position adjust circuits (FMCK bits), the tail end of the BLKS EN 1 signal could extend beyond MUX count 61 if it were retarded by eight counts or more. In this case, at MUX61 time, gate 12311 is enabled, producing a low output which is fed out through again to reset flip-flop 12307.

In the read mode, BLKS EN 1 is on for 50 counts of the MUX counter; however, during load format time BLKS EN 1 is high for only 38 counts, coming on at count 13 and going off at count 51. The change from 50 to 38 counts is performed at multiplexer 12206. During load format the LDFT signal goes low causing the .SIGMA.D signal to be fed through as the ENST signal and the .SIGMA.B signal to be fed as the ENSTP signal.

CONCLUSION

The system as described is extremely flexible with respect to its ability to read data presented in a variety of formats and in its ability to re-position a document so as to properly center data in the photo-diode array. The system as disclosed is capable of reading a field eight inches wide starting one quarter of an inch from the left hand edge of a document page. A machine printing pitch of 10 characters per inch can be accommodated, with lesser pitches being easily read. Line spacing of six lines per inch or greater can also be accommodated. Documents are read line by line with the full height of the document capable of receiving data.

A variety of paper stock thicknesses and weights can be accommodated as can a variety in the reflectivity of the stock and ink.

While we have described and illustrated specific embodiments of our invention, it will be clear that variations of the details of construction which are specifically illustrated and described may be resorted to without departing from the true spirit and scope of the invention as defined in the appended claims.

Claims

1. In an optical character recognition system of the type in which optical images of data characters to be read from data documents are converted to electronic signals for automatic processing and recognition, and wherein said system in capable of ignoring all characters on a data document other than those located in prescribed data fields, a method characterized in that data field marks are not required on said data documents to designate said prescribed data fields, said method being further characterized by a format load mode wherein a format conditioning document, which is separate and apart from data documents to be read and which contains format marks which designate the locations of said prescribed data fields, is processed to identify said prescribed data fields in each of a series of data documents to be read during a read mode, said method including the steps of:

in said format load mode, detecting the locations of said format marks on said format conditioning document;

in said format load mode, storing the locations of data fields designated by the format marks detected on said format conditioning document; and

in said read mode, automatically and successively reading each data document in said series, said reading including the steps of:

during the reading of each data document, retrieving the stored data field locations; and

processing only those data characters on each data document which are located in data fields which correspond to the retrieved data field

2. An optical character recognition system of the type in which optical images of data characters to be read from data documents are converted to electronic signals for automatic processing and recognition, and wherein said system is capable of ignoring all characters on a data document other than those located in prescribed data fields, said system being characterized in that data field marks are not required on said data documents to designate said prescribed data fields, said system being further characterized by a format load mode wherein a format conditioning document, which is separate and apart from data documents to be read and which contains format marks which designate the locations of said prescribed data fields, is processed to identify said prescribed data fields in each of a series of data documents to be read during a read mode, said system comprising:

means operative in said format load mode for detecting the locations of said format marks on said format conditioning document;

memory means;

means operative in said format load mode for storing in said memory means the locations of data fields designated by the format marks detected on said format conditioning document; and

reading means operative in said read mode for automatically and successively reading each data document in said series, said reading means including:

means operative during the reading of each data document for retrieving the stored data field locations from said memory means; and

means for processing only those data characters of each data document which are located in data fields which correspond to the retrieved data field

3. The system according to claim 2 further characterized in that said format marks are arranged in a vertical column on said format conditioning document, each format mark designating a corresponding line on said data

4. The system according to claim 2 further characterized in that additional format marks are provided on each of said designated lines, said additional format marks including a beginning of field of mark indicating the location on the designated line at which each data field begins, and an end of field mark indicating the location on the designated line at

5. The system according to claim 2 further including: a transport path for said data documents; actuable stepping means for transporting said documents in discrete steps along said transport path; and a read station located in said transport path;

wherein said reading means includes:

optical scanner means actuable to scan across portions of documents located at said read station;

an array of photosensitive elements; and

an optical path for projecting scanned portions of documents at said read station onto said photosensitive elements;

said system further comprising a line position analysis circuit including:

means for monitoring the position of character images in said array;

means for detecting when an image is not centered in said array; and

means responsive to the detection of a non-centered image in said array for actuating said actuable stepping means to re-position said document until

6. The system according to claim 5 wherein said line position analysis circuit further includes:

predicting means responsive to the position of each character image in said array for predicting the position of the next character image to be received by said array; and

means responsive to the predicted position of the next character image to be received for establishing a time interval which is time coincident with the time during which the next character image will be positioned within pre-selected stages of said shift register means if that character image

7. The system according to claim 6 further characterized by:

means operable at regular intervals for quantizing images received at said array into respective binary signals indicating the reception and non-reception of character images at each of the array elements;

multi-stage shift register means, operative between quantizing intervals, for serially shifting said binary signals in turn to accumulate signals corresponding to a plurality of successive images received at said array; and

mask means for examining pre-selected stages of said shift register means to identify specific characters accumulated in said shift register means.

8. An optical character recognition system of the type wherein a document is transported in discrete steps of equal length along a transport path containing a read station, wherein an optical scanner is actuable to scan transversely of the transport direction across a line of said document located at said read station, wherein a photo-sensitive detector receives images of characters viewed by said optical scanner and converts said images into electronic signals, and wherein recognition circuitry processes signals for the purpose of identifying characters viewed by said optical scanner, said system being characterized by a format load mode wherein it it processes a format conditioning document containing format marks which designate the location of data fields on data documents to be read by the system during a read mode, at least some of said format marks comprising vertical format marks arranged in a predetermined vertical column on said format conditioning document and located on those horizontal lines which correspond to lines on which data appears in said data documents, said system comprising:

sensor means located in said transport path for determining when the leading edge of a transported document enters said read station;

counter means for counting each transport step of a document after the leading edge of the document has entered said read station;

scan control means operative in said format load mode for actuating said optical scanner to scan lines of said format conditioning document presented at said read station for the purpose of identifying vertical format marks at said recognition circuitry;

a memory unit;

means responsive to identification of a vertical format mark during scan of a line of said format conditioning documents for storing the count from said counter means in said memory unit;

means operative in said read mode for successively retrieving said counts from said memory unit;

means operative in said read mode for stepping data documents, one at a time, along said transport path and through said read station such that stepping temporarily terminates only when lines on said document corresponding to said successive retrieved counts are positioned at said read station; and

wherein said scan control means is operative in said read mode, in response to positioning of a line to be read at said read station, for actuating

9. The system according to claim 8 further characterized in that additional format marks are provided on each of said designated lines, said additional format marks including a beginning of field mark indicating the location on the designated line at which each data field begins, and an end of field mark indicating the location on the designated line at which each data field terminates, said system further comprising:

a source of timing pulses;

further counter means operative during a scan by said optical scanner for counting timing pulses, such that the count total in said further counting means corresponds to a specific location on a document line being viewed by said optical scanners;

means for storing in said memory unit the line location count of each beginning of field and end of field mark identified by said recognition circuitry during said format load mode;

means operative during said read mode for successively retrieving said line location counts from said memory unit; and

means operative in said read mode for inhibiting character identification at said recognition circuitry except during intervals when the count at said further counter corresponds to counts between the successively

10. The system according to claim 8 wherein said photo-sensitive detector comprises an array of photo-sensitive elements onto which the image viewed by said optical scanner is projected; said system further comprising a line position analysis circuit including means operatively connected to said recognition circuitry for determining if an image from a document being scanned is vertically centered in said array, and means responsive to a determination that an image is not so centered for stepping said

11. The system according to claim 10 wherein said line position analysis circuitry includes means operative in said format load mode for inhibiting storage of a step count corresponding to an identified vertical format mark location until said identified vertical format mark is vertically

12. The system according to claim 8 further characterized in that stepping of said documents along said transport path is effected by:

a step motor;

a common drive cylinder having uniform circumference along its length and arranged to be rotatably stepped about its longitudinal axis by said step motor, said common drive cylinder being disposed with its longitudinal axis oriented transversely of said transport path;

at least one pair of transport rollors spaced transversely across said transport path, each rollor positioned in circumferential engagement with said common drive cylinder so as to be simultaneously rotated at the same speed by said common drive cylinder; and

at least one pair of spaced pinch rollors which are simultaneously actuable to engage respective transport rollors such that a document in said

13. The system according to claim 12 further characterized by:

a vertically positionable stacker bin for holding a stack of documents to be processed by said system;

a feed member arranged to be selectively lowered into said stacker bin toward the uppermost document in said stack for the purpose of engaging said uppermost document and delivering same to said transport path, the distance over which said feed member is lowerable being limited; and

means responsive to lowering of said feed member to its limit position and the absence of engagement between said feed member and said uppermost document for automatically lifting said stacker bin until said uppermost

14. The system according to claim 8 further characterized by a reject mode in which said system is operative to automatically reject any document in which one or more characters have not been recognized, said system further comprising:

a normal stacker bin and a reject stacker bin, each positioned at the end of said transport path to alternatively receive documents from said transport path; and

path control means operative in said reject mode and responsive to said recognition circuitry for automatically directing documents in which all characters have been recognized to said normal stacker bin and directing documents in which at least one character has not been recognized to said

15. The system according to claim 8 further characterized by:

means responsive to failure of said recognition circuitry to recognize a data character in a scanned line for automatically initiating a re-scan of the entire line by said optical scanner; and

means responsive to failure of said recognition circuitry to recognize a data character during a first re-scan of a line for automatically increasing the detection sensitivity of said photo-sensitive detector and

16. The system according to claim 8:

wherein said photo-sensitive detector comprises an array of photo-sensitive elements arranged in a straight line to receive vertical slice images of characters being scanned by said optical scanner;

wherein said recognition circuitry includes:

means operative at regular intervals for quantizing slice images received at said array into respective binary signals indicating the reception and non-reception of character images at individual array elements;

a plurality of shift register means, operative between quantizing intervals, for serially shifting said binary signals through all of said shift register means in turn to accumulate signals corresponding to a plurality of successive slice images received at said array; and

a plurality of mask means for examining preselected stages of said plurality of shift register means, each mask means identifying a specific

17. The system according to claim 16 further comprising a line position analysis circuit arranged to receive said serially shifted binary signals in order to determine the position of individual received character slices relative to the center of said array, said line position analysis circuit further comprising means responsive to the position of each received character slice in said array for predicting the position of the next

18. The system according to claim 17 further comprising means responsive to the predicted position of the next received character slice for generating a signal having a time interval which is time coincident with the time during which the next character slice is positioned within said preselected stages of said shift register means if that character slice is positioned in said array as predicted by said line position analysis

19. An optical character recognition system of the type wherein a document is transported along a transport path containing a read station, wherein an optical scanner is actuable to scan transversely of the transport direction across a line of said document located at said read station, wherein a photo-sensitive detector receives images of characters viewed by said optical scanner and converts said images into electronic signals, said photo-sensitive detector comprising an array of photo-sensitive elements arranged in a straight line to receive vertical slice images of characters viewed by said optical scanner, and wherein recognition circuitry processes said signals for the purpose of identifying characters viewed by said optical scanner, said system being characterized in that the vertical position of successive character slices in said array is automatically predicted on the basis of the vertical position of an immediately preceding slice in said array, wherein said recognition circuitry includes:

means operative at regular intervals for quantizing slice images received at said array into respective binary signals indicating the reception and non-reception of character images at the individual array elements;

a plurality of shift registers, operative between quantizing intervals, for serially shifting said binary signals through all of said shift registers in turn to accumulate signals corresponding to a plurality of successive slice images received at said array; and

a plurality of mask means for examining pre-selected stages of said plurality of shift registers, each mask means identifying a specific character accumulated in said shift register means;

said system further comprising a line position analysis circuit arranged to receive said serially shifted binary signals in order to determine the position of individual received character slices relative to the center of said array, said line position analysis circuit further comprising means responsive to the position of each received character slice relative to said array for predicting the position of the next received character

20. The system according to claim 19 further comprising means responsive to the predicted position of the next received character slice for generating a signal having a time interval which is time coincident with the time during which the next character slice is positioned within said preselected stages of said shift register means if that character slice is positioned in said array as predicted by said line position analysis

21. In an optical character recognition system of the type wherein a document is transported in discrete steps of equal length along a transport path containing a read station, wherein an optical scanner is actuable to scan transversely of the transport direction across a line of said document located at said read station, wherein a photo-sensitive detector receives images of characters viewed by said optical scanner and converts said images into electronic signals, and wherein recognition circuitry processes said signals for the purpose of identifying characters viewed by said optical scanner, a method of controlling said system to read data located only in predetermined data fields on data documents, said method being characterized by a format load mode for said system wherein the system processes a format conditioning document containing format marks which designate the location of data fields on data documents to be read by the system during a read mode, at least some of said format marks comprising vertical format marks arranged in a predetermined vertical column and located on those horizontal lines which correspond to lines on which data appears on said data documents, said method comprising the steps of:

detecting when the leading edge of a transported document enters said read station;

counting each transport step of a document after the leading edge of the document has entered said read station; actuating said optical scanner to scan lines of said format conditioning document presented at said read station for the purpose of identifying vertical format marks at said recognition circuitry;

storing the transport step count corresponding to the line in which a vertical format mark is identified;

during the read mode, successively retrieving said transport step counts from said memory unit;

during said read mode, stepping data documents along said transport path and through said read station such that stepping temporarily terminates only when lines on said document corresponding to said successive retrieved counts are at said read station; and

actuating said optical scanner to scan across said read station in response

22. The method according to claim 21 further characterized in that additional format marks are provided on each of said designated lines, said additional format marks including a beginning of field mark indicating the location of the designated line at which each designated field begins, and an end of field mark indicating the location on the designated line at which each data field terminates, said method comprising the additional steps of:

generating a series of timing pulses;

counting timing pulses during a scan by said optical scanner such that the timing pulse count corresponds to a specific location on a document being viewed by said optical scanner; 242

storing the timing pulse count corresponding to the line location of each beginning of field and end of field mark identified by said recognition circuitry during said format load mode;

during said read mode, successively retrieving the timing pulse count corresponding to said line locations of said beginning and end of field marks; and

inhibiting character identification by said recognition circuitry during said read mode except during intervals when the current timing pulse count corresponds to a line location being viewed by said optical scanner which is part of a data field designated by the retrieved beginning and end of field line locations.