U.S. patent number 3,870,137 [Application Number 05/405,881] was granted by the patent office on 1975-03-11 for method and apparatus for coin selection utilizing inductive sensors.
This patent grant is currently assigned to Arthur D. Little, Inc.. Invention is credited to Guy L. Fougere.
United States Patent |
3,870,137 |
Fougere |
March 11, 1975 |
**Please see images for:
( Certificate of Correction ) ** |
Method and apparatus for coin selection utilizing inductive
sensors
Abstract
The method and apparatus of this invention examine properties of
coins by subjecting them to electromagnetic fields of at least two
substantially different frequencies. An indication that a coin is
acceptable is produced only after the coin has satisfied the
examination requirements at at least two substantially different
frequencies.
Inventors: |
Fougere; Guy L. (Lincoln,
MA) |
Assignee: |
Arthur D. Little, Inc.
(Cambridge, MA)
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Family
ID: |
27255196 |
Appl.
No.: |
05/405,881 |
Filed: |
October 12, 1973 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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255814 |
May 22, 1972 |
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Foreign Application Priority Data
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Feb 25, 1972 [GB] |
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8385/72 |
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Current U.S.
Class: |
194/317 |
Current CPC
Class: |
G07D
5/08 (20130101); G07D 5/02 (20130101) |
Current International
Class: |
G07f 003/02 () |
Field of
Search: |
;194/100,1A,99,101,102 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Tollberg; Stanley H.
Attorney, Agent or Firm: Davis, Hoxie, Faithfull &
Hapgood
Parent Case Text
This application is a continuation of application Ser. No. 225,814,
filed May 22, 1972 now abandoned.
Claims
What I claim is:
1. A method for examining conductive coins with respect to both
their authenticity and their denomination within a set of
acceptable coins of various denominations comprising the steps of
generating a first electromagnetic field of a low frequency range,
subjecting the coin to the first field, generating a second
electromagnetic field of a substantially higher frequency range
than that of the first field, subjecting the coin to the second
field, producing signals indicative of the degree of interaction of
the coin with each field, and producing a signal indicative of the
acceptability of the coin and selective of its denomination within
the set only if the degree of each interaction is within
predetermined tolerances of those of acceptable coins of one of the
denominations of the set.
2. The method of claim 1 wherein the coin is in one location when
subjected to the first electromagnetic field and in a second
location when subjected to the second electromagnetic field.
3. The method of claim 1 including the steps of causing the coin to
move along a predetermined path with respect to the fields.
4. The method of claim 1 including the steps of subjecting the coin
to a third electromagnetic field of a substantially higher
frequency range than that of the first field and examining the
degree of interaction of the coin with the third field wherein the
acceptability signal is produced only if the degree of each
interaction is within predetermined tolerances of those of
acceptable coins of a given denomination.
5. The method of claim 4 wherein the second field is directed
toward one face of the coin and the third field is directed toward
the other face of the coin.
6. The method of claim 1 wherein the low frequency range is below
approximately 75 kHz.
7. The method of claim 1 wherein the higher frequency range is
above approximately 75 kHz.
8. The method of claim 1 wherein the degree of at least one
interaction is indicated by a shift in the frequency of an
oscillator.
9. The method of claim 1 wherein the degree of at least one
interaction is indicated by the degree of balance of a bridge
circuit.
10. The method of claim 1 wherein a field of low frequency range
and a field of a higher frequency range are concurrently applied to
the coin.
11. The method of claim 1 including the steps of mechanically
segregating acceptable coins from inacceptable coins in response to
the acceptability indicative signal, producing a signal indicative
of the completion of segregation of an acceptable coin, and
recording the value of the coin's denomination in response to the
segregation signal.
12. A method for examining conductive coins with respect to
authenticity and denomination comprising the steps of subjecting a
coin to a first electromagnetic field of a low frequency range
below 75 kHz., subjecting the coin to a second electromagnetic
field of a substantially higher frequency range than that of the
first field and higher than 75 kHz., producing first and second
signals indicative of the degree of interaction of the first and
second fields respectively with the coin, and separately examining
the degree of interaction of the coin with each field and producing
a signal indicative of the acceptability of the coin only if the
degree of each interaction is within predetermined tolerances of
those of acceptable coins of a given denomination.
13. The method of claim 12 wherein the upper limit of the higher
frequency range is 1MHz.
14. The method of claim 13 wherein the lower limit of the lower
frequency range is 3kHz.
15. The method of claim 12 wherein the only change in frequency of
an electromagnetic field, when the coin passes through it, is coin
dependent.
16. The method of claim 12 wherein the change of frequency of an
electromagnetic field is detected and employed as an indicia of
coin authenticity and denomination.
17. The method of claim 12 including the steps of causing the coin
to move along a predetermined path with respect to the fields,
subjecting the coin to a third electromagnetic field of a
substantially higher frequency range than that of the first field,
examining the degree of interaction of the coin with the third
field wherein the acceptability signal is produced only if the
degree of each interaction is within predetermined tolerances of
those of acceptable coins of a given denomination, and identifying
the denomination of the coin.
18. The method of claim 17 wherein the second field is directed
toward one face of the coin and the third field is directed toward
the other face of the coin.
19. The method of claim 18 wherein the third field's frequency
range is above 75kHz, the first and third fields are concurrently
applied to the coin, and the coin acceptability signal is produced
only if the interaction indicative signals with respect to the
first and third fields are obtained concurrently.
20. The method of claim 1 wherein the first and second fields are
concurrently applied to the coin, and the coin acceptability signal
is produced only if the interaction indicative signals with respect
to the fields are obtained concurrently.
21. Apparatus for examining conductive coins of a plurality of
denominations with respect to authenticity and denomination within
a set of acceptable coins of various denominations comprising means
for subjecting a coin to a first electromagnetic field of a low
frequency range, means for producing a signal indicative of the
degree of interaction of the coin with the first field, separate
means for subjecting the coin to a second electromagnetic field of
a substantially higher frequency range than that of the first
field, means for producing a signal indicative of the degree of
interaction of the coin with the second field, and means for
producing a signal indicative of acceptability and denomination of
the coin only if both interaction indications are within
predetermined tolerances of those of acceptable coins of one of the
denominations of the set. l
22. The apparatus of claim 21 wherein the means for subjecting the
coin to the first field comprise a first inductor and the means for
subjecting the coin to the second field comprise a second
inductor.
23. The apparatus of claim 22 wherein the means for indicating the
degree of interaction of the coin with the first field comprises a
bridge circuit and the means for indicating the degree of
interaction of the coin with the second field comprises frequency
shift detection means.
24. The apparatus of claim 21 wherein the low frequency range is
below approximately 75 kHz.
25. The apparatus of claim 21 wherein the higher frequency range is
above approximately 75 kHz.
26. The apparatus of claim 21 further comprising means for
subjecting the coin to a third electromagnetic field of a
substantially higher frequency range than that of the first field
and means for indicating the degree of interaction of the coin with
the third field, wherein the acceptability signal producing means
produces the acceptability signal only if all three interaction
indications are within tolerances of those of acceptable coins of a
given denomination.
27. The apparatus of claim 26 wherein the second field is directed
toward one face of the coin and the third field is directed toward
the other face of the coin.
28. The apparatus of claim 21 comprising at least one inductor
operating in a higher frequency range than that of the first field
for each denomination of coin to be accepted by the apparatus.
29. The apparatus of claim 21 wherein the means for producing an
acceptability signal comprise digital logic circuitry having inputs
connected to the outputs of at least one low frequency interaction
indicating means and one high frequency interaction indicating
means.
30. The apparatus of claim 21 further comprising mechanical gate
means for separating acceptable coins from unacceptable coins, a
coin presence sensor located in a position where it will sense
accepted coins which have passed the gate and produce a signal in
response thereto, and accumulator means arranged to record the
value of an accepted coin in reponse to the gate passed signal.
31. Apparatus for examining conductive coins with respect to
authenticity and denomination comprising a coin passageway, means
for subjecting a coin in the passageway to a first electromagnetic
field of a low frequency range below 75 kHz., separate means for
subjecting the coin to a second and a third electromagnetic field
each of a frequency range above 75 kHz. and substantially higher
than that of the first field, separate means for examining the
degree of interaction of each of the fields with the coin, and
means for producing a signal indicative of acceptability of the
coin only if each of the three interaction indications is within
predetermined tolerances of those of acceptable coins of a single
denomination.
32. The apparatus of claim 31 wherein the upper limit of the higher
frequency range is 1MHz.
33. The apparatus of claim 32 wherein the lower limit of the lower
frequency range is 3kHz.
34. The apparatus of claim 31 wherein the degree of at least one
interaction of the coin with a higher frequency field is indicated
by a shift in the frequency of an oscillator and the degree of
interaction of the coin with the first field is indicated by the
degree of balance of a bridge circuit.
35. The apparatus of claim 31 further comprising means for causing
relative motion of the coin through the fields along a
predetermined path defined by a coin supporting track wherein each
of the fields is produced by an inductor driven by an alternating
current, and wherein the second field is directed toward one face
of the coin and the third field is directed toward the other face
of the coin.
36. The apparatus of claim 35 wherein a first inductor operating in
a higher frequency range than that of the first field and a second
inductor operating in a low frequency range are at substantially
the same longitudinal location along the coin path, and further
comprising combinatorial means connected so that a signal
indicative of coin acceptability is produced only if both the
interaction indications with respect to said first and second
inductors occur concurrently.
37. The apparatus of claim 35 further comprising at least one
oscillator to produce the alternating current, wherein at least one
oscillator is connected with its associated inductor so that the
presence of conductive material in the field produced by that
inductor causes the frequency of the oscillator to shift from an
idling frequency.
38. The apparatus of claim 37 wherein at least one interaction
examining means is a narrow band detector circuit responsive to the
output signal of that oscillator for detecting a predetermined
frequency shifted from the oscillator's idling frequency and
producing a signal indicative of the occurrence of the shifted
frequency, and the detector circuit produces an output pulse for
each transition of the frequency of its associated oscillator into
the bandpass of the detector.
39. The apparatus of claim 35 wherein at least one of the inductors
is an element of a bridge circuit, the bridge is driven by an
oscillator and at least one interaction indicative means is a
bridge condition detector arranged to monitor the output of the
bridge.
40. The apparatus of claim 39 wherein the detector circuit produces
a single pulse each time the output of the bridge passes into and
out of a range of signal values within a predetermined tolerance of
a predetermined value.
41. The apparatus of claim 39 wherein the bridge is a multileg
bridge having a plurality of parallel branches in parallel with an
inductor branch comprising an inductor and a resistor, and wherein
each of a plurality of bridge condition detectors is connected to
monitor the output of a bridge circuit comprising the inductor
branch and one of the other branches.
42. The apparatus of claim 39 wherein at least one inductor having
at least one pole piece is located adjacent the coin track with at
least a portion of a pole piece below the level of the track and at
least a portion of a pole piece above the level of the track.
43. The apparatus of claim 35 wherein an inductor is an element of
a multileg bridge circuit having a plurality of parallel branches
in parallel with an inductor branch comprising said inductor and a
resistor, and wherein each of a plurality of bridge condition
detectors is connected to monitor the output of a bridge circuit
comprising the inductor branch and one of the other branches.
44. The apparatus of claim 43 wherein the inductor of the inductor
branch comprises a series connected pair of low frequency field
producing inductors, one of which is located on each side of the
coin path.
45. The apparatus of claim 43 further comprising mechanical gate
means for separating acceptable coins from unacceptable coins, a
coin presence sensor located in a position where it will sense
accepted coins which have passed the gate and produce a signal in
response thereto, an accumulator means arranged to record the value
of an accepted coin in response to the gate passed signal.
46. Apparatus for examining conductive coins with respect to
authenticity and denomination comprising first inductor means
arranged to subject a face of a coin to a first electromagnetic
field which would penetrate through an authentic coin of an
acceptable denomination, second inductor means arranged to subject
a face of the coin to a second electromagnetic field having a
frequency high enough that it would not penetrate through an
authentic coin of said acceptable denomination, separate means for
indicating the degree of interaction of the coin with each of the
fields, and means for producing a signal indicative of
acceptability of the coin as a coin of said acceptable denomination
only if both interaction indications are within predetermined
tolerances for acceptable coins of said denomination.
47. The apparatus of claim 46 wherein one inductor of a series
connected pair of low frequency field producing inductors is
located adjacent each side of the coin path.
48. The apparatus of claim 46 wherein a first inductor operating in
a higher frequency range than that of the first field and a second
inductor operating in a low frequency range are at substantially
the same longitudinal location along the coin path.
49. The apparatus of claim 48 further comprising combinatorial
means connected so that a signal indicative of coin acceptability
is produced only if both the interaction indications with respect
to said first and second inductors occur concurrently.
50. The apparatus of claim 46 wherein at least one inductor having
at least one pole piece is located adjacent the coin track with at
least a portion of a pole piece below the level of the track and at
least a portion of a pole piece above the level of the track.
51. The apparatus of claim 46 further comprising at least one
oscillator to produce the alternating current, wherein at least one
oscillator is connected with its associated inductor so that the
presence of conductive material in the field produced by that
inductor causes the frequency of the oscillator to shift from an
idling frequency and at least one interaction indicating means is a
narrow band detector circuit responsive to the output signal of
that oscillator for detecting a predetermined frequency shifted
from the oscillator's idling frequency and producing a signal
indicative of the occurrence of the shifted frequency.
52. The apparatus of claim 51 wherein the detector circuit produces
an output pulse for each transition of the frequency of its
associated oscillator into the bandpass of the detector.
53. The apparatus of claim 51 wherein the detector circuit means
comprises means for periodically sampling the output signal of an
associated oscillator for a predetermined sampling interval and
means for producing the shifted frequency indicative signal when
the number of cycles in the output signal of the oscillator circuit
during each of a predetermined number of sampling intervals is
substantially equal within a predetermined tolerance to a number of
signal cycles predetermined for genuine coins of a
denomination.
54. The apparatus of claim 53 wherein the sampling means
periodically and sequentially samples the output signals of each of
a plurality of oscillator circuits.
55. The apparatus of claim 53 wherein the means for producing an
interaction indicating signal comprises a counter for counting the
number of cycles in the output signal of said associated oscillator
circuit during each sampling interval, a decoder signal pulse when
the number of cycles counted by said first counter in any sampling
interval is substantially equal to said predetermined number of
signal cycles; and a second counter responsive to said decoder for
producing said frequency detector output signal when the number of
decoder signal pulses is substantially equal to said predetermined
number of sampling intervals.
56. The apparatus of claim 53 wherein the means for producing
interaction indicating signals comprises at least one signal cycle
counter responsive to said sampled oscillator output signals for
producing an output signal proportional to the number of cycles in
each oscillator output signal sample; and wherein the means for
producing a coin acceptability indicative signal comprises at least
a first and second decoder each responsive to an output signal of
said signal cycle counter, each producing an output signal pulse
when the number of signal cycles represented by the output signal
of said signal cycle counter is substantially equal to said
predetermined number of signal cycles for its associated low
frequency or high frequency oscillator circuit, respectively, first
and second pulse counters for counting the output signal pulses
produced by said first and second decoders, respectively, and logic
means responsive to said first and second counters for producing a
coin acceptability indicative signal when the number of output
signal pulses counted by each of said pulse counters is
substantially equal to said predetermined number of sampling
intervals.
57. The apparatus of claim 46 wherein at least one of the inductors
if an element of a bridge circuit, the bridge is driven by the
oscillator and at least one interaction indicative means is a
bridge condition detector arranged to monitor the output of the
bridge.
58. The apparatus of claim 57 wherein the detector circuit produces
a single pulse each time the output of the bridge passes into and
out of a range of signal values within a predetermined tolerance of
a predetermined value.
59. The apparatus of claim 57 wherein the bridge is a multileg
bridge having a plurality of parallel branches in parallel with an
inductor branch comprising an inductor and a resistor, and wherein
each of a plurality of bridge condition detectors is connected to
monitor the output of a bridge circuit comprising the inductor
branch and one of the other branches.
60. The apparatus of claim 46 further comprising means for
indicating the denomination of acceptable coins.
Description
The method and apparatus of this invention examine the material
properties of coins by subjecting them to electromagnetic fields of
at least two substantially different frequencies. A determination
is made for each of the examination frequencies whether or not the
interaction between the coin being tested and the electromagnetic
field of that frequency produces the interaction effect within
predetermined tolerances which is anticipated for acceptable
electrically conductive coins. Certain of the examinations can be
made in such a manner that the resulting signal is also indicative
of whether the coin is within certain ranges of coin diameter and
thickness. The coin selector produces an indication that a coin is
acceptable only after the coin has satisfied the examination
requirements at at least two substantially different
frequencies.
No moving parts are required in this coin selector, except a device
to separate acceptable coins from non-acceptable coins in
accordance with the indication of acceptability and except as
mechanical energy absorbing elements may be characterized as moving
parts.
Throughout this specification the term "coin" is intended to mean
genuine coins, tokens, counterfeit coins, slugs, washers, and any
other item which may be used by persons in an attempt to use
coin-operated devices. Furthermore, throughout this specification,
for simplicity, coin movement is described as rotational motion;
however, except where otherwise indicated, translational motion
also is contemplated.
In the drawings:
FIG. 1 is a front elevational drawing of the coin track and
inductors of a coin selector formed in accordance with this
invention.
FIG. 2 is an end view of the coin selector of FIG. 1 at section
AA.
FIG. 3 is a simplified front elevational drawing of details of an
alternative arrangement of a coin track and inductors for a coin
selector formed in accordance with this invention.
FIG. 4 is a schematic block diagram of the electronic circuit for a
coin selector formed in accordance with this invention.
FIG. 5 is the top view of a typical pot core inductor.
FIG. 6 is a cross-sectional view along line A--A of the pot core
inductor of FIG. 5.
FIG. 7 is a schematic block diagram of an alternative low frequency
sub-circuit for a coin selector formed in accordance with this
invention.
FIG. 8 is a schematic block diagram of a digital electronic circuit
for a coin selector formed in accordance with this invention.
FIG. 9 is a schematic block diagram of a coin selector in
accordance with this invention.
FIG. 10 is a schematic diagram of a high frequency oscillator and
detectors for the coin selector of FIG. 9.
FIG. 11 is a schematic diagram of a low frequency oscillator,
bridge and detector for the coin selector of FIG. 9.
FIG. 12 is a schematic block diagram of a further coin selector
formed in accordance with this invention.
FIG. 13 is a schematic block diagram of a portion of another coin
selector in accordance with this invention.
The figures are intended to be representational and are not
necessarily drawn to scale.
According to the method of this invention, a coin being examined is
subjected to electromagnetic fields of at least two substantially
different frequencies which have been selected as appropriate for
the examination of the set of coin denominations which are to be
accepted by the apparatus employing the method. The lower frequency
(LF) is one which, when applied to an appropriate electromagnetic
radiator or inductor, will penetrate deeply into or through the
coins of acceptable denominations.
The higher frequency (HF) is one which will penetrate not more than
halfway through the thickness of the most worn coin to be accepted
of all acceptable denominations. In most instances the system is
designed so the HF penetrates into a small percentage of the coin's
thickness. In the case where laminated coins, such as the present
10-cent, 25-cent and 50-cent denomination coins of the United
States of America, are to be examined; an appropriate high
frequency would be one which will penetrate to approximately the
thickness of the outer layer or cladding of coins of the
denomination having the thinnest outer layer.
For the purpose of this discussion, the depth of penetration or
skin depth d in centimeters is defined as:
d = k/.sqroot.f.sigma..mu.
k is a constant having a value dependent upon the system of
measurement, where, f is the frequency, .sigma. is the DC
conductivity and .mu. is magnetic permeability of the material. At
this depth, the current density is 36.8 percent of the current
density at the surface of the material. For copper, for example,
this formula indicates that the skin depth is 6.62/.sqroot.f, or
0.00662 cm. at 1 MHz, 0.0208 cm. at 100 kHz, 0.0662 cm at 10 kHz
and 0.208 cm. at 1 kHz. For an alloy of 75 percent cooper - 25
percent nickel, which is used for the outer lamina of the U.S. 10
cent and 25 cent coins and has a substantially lower conductivity
than copper, the skin depth is 0.029 cm. at 1 MHz, 0.091 cm. at 100
kHz, 0.29 cm. at 10 kHz and 0.91 cm. at 1 kHz.
When a ferromagnetic coin shunts an inductor, such as the pot core
inductor 200 shown in FIGS. 5 and 6, in an alternating current
cirucit; the direction of change of inductance of the inductor
depends on both the skin effect and the effect of shunting by the
magnetic material. Thus, if the magnetic permeability of a coin is
high and the conductivity is low, the inductance of the inductor
will increase. If the permeability is low and the conductivity is
high, the inductance will decrease. Both types of inductance change
can be utilized in the method and apparatus of this invention.
When a nonmagnetic coin shunts the inductor, the magnetic flux
flowing through the coin material induces currents which produce an
opposing field. This tends to prevent the flux from penetrating far
into a coin of high conductivity; for coins of lower conductivity
the flux can penetrate further as discussed above. The inductance
of the inductor coil will be altered, but for discs of different
metals of the same diameters and equal thicknesses as measured in
skin depths the inductance change will be different. Naturally when
the thickness of the discs becomes small relative to one skin
depth, the difference tends to disappear. The method of the
invention provides a powerful means of coin discrimination by
examining each coin in this fashion at two substantially different
frequencies, a lower frequency at which the coin thickness is
relatively small in terms of penetration of the flux and a higher
frequency at which only shallow penetration occurs, and accepting
the coin only if it satisfies the criteria for a genuine coin of
the same denomination on both tests.
Depending upon the set of coin denominations to be accepted by a
coin selector, a selection of the lower and higher frequencies to
be employed can be made; taking into consideration the relative
positions of the inductors and the coins when the coins are being
examined. A final selection of inductor positions and frequencies
can then be made following tests of a prototype unit. Generally,
there is a large ratio between the low frequency and the high
frequency, for example, LF between 5 and 25 kHz and HF between 200
and 800 kHz are the approximate preferred ranges for a coin set
consisting of the U.S. 5-cent, 10-cent and 25-cent denomination
coins. When all of the coins in a set are of a low conductivity
material, a maximum LF of approximately 60 kHz and a minimum HF of
approximately 100 kHz could be used; a frequency ratio of
approximately 1.6 to 1. As a general proposition, while there may
be exceptions in some cases, the LF will be in the vicinity of 60
kHz or less and the HF will be in the vicinity of 100 kHz or more,
the dividing line being approximately 75 kHz.
Practical consideration suggest that frequencies between
approximately 3 kHz and 1MHz be used in most cases. At frequencies
lower than about 3 kHz, the flux fully penetrates all but the
thickest coins of the highest conductivity and it becomes
increasingly difficult to subject a rapidly moving coin to the
electromagnetic field for a sufficient period to accurately and
economically detect the interaction between coin and field. At
frequencies in the vicinity of 1 MHz and above for coins of higher
conductivity material, where the peaks of the surface of the coin
being tested are at a very short fixed distance from the inductor,
the method will be sensitive to the embossing on the surface of the
coin. This may be objectionable in some cases, however, such
frequencies may be employed to distinguish between the sides (heads
or tails) of genuine coins, to distinguish between genuine coins
which are embossed and unembossed slugs of the same material, or
even to distinguish between otherwise similar coins of different
nations which are differently embossed. At somewhat greater
distances from the coin to inductor, these frequencies tend to
produce results indicative primarily of the distance of spacing of
the coin from the inductor.
FIRST EMBODIMENT
A coin selector 10 formed in accordance with the present invention
is shown in the drawings. A coin may be introduced into the coin
selector 10 through the coin entry 20. The coin then falls under
the influence of gravity onto the coin track 30. The main portion
31 of the coin track 30 is sloped downwards in a direction away
from the coin entry 20. The portion of the coin track 30 onto which
the coin initially falls may be merely an upward extension at the
same angle of slope as the main portion 31, as indicated in FIG. 1;
but preferably the initial portion 32 is at a steeper angle than
the main portion 31. One advantageous form of the initial portion
32, which is shown in FIG. 3, is for the initial portion 32 of the
coin track 30 to be curved upwards from the main portion 31 beneath
the coin entry 20, so that the vertical motion of a coin entering
the coin selector 10' through the coin entry 20 under the influence
of gravity will be transformed into motion along the main portion
31 of the coin track 30 with a minimum of coin bouncing. Coin
tracks 30 having slopes at an angle from the horizontal of from
10.degree. to 25.degree. have been found to be satisfactory.
Adjacent and contiguous to the coin track 30 is a sidewall 40 which
is canted at a sufficient angle from the vertical to cause the face
of a coin to bear against the wall 40, when the edge of the coin is
resting on the coin track 30. An angle of 20.degree. from the
vertical has been found to be a satisfactory angle for the sidewall
40. The coin track 30 is ordinarily arranged at a right angle to
the sidewall 40 and spaced away from sidewall 40 by a distance
greater than the thickness of the thickest coin which is to be
selected by the coin selector 10. The coin track 30 and the
sidewalls 40 and 50 form a coin passageway 60. The sidewall 40 and
the coin track 30 may conveniently be molded from the same piece of
material.
In a coin selector 10, which is designed to examine and accept
genuine coins of three different denominations, a set 70 of four
inductors 72, 74, 76 and 78, are located along one side of the coin
passageway 60. Each of the inductors 72, 74, 76 and 78 is similar
to the typical inductor 200 shown in FIGS. 5 and 6. Inductor 200
comprises a coil 201 wound on a bobbin 202, which is placed around
the center pole 204 of a ferrite pot core 203. One of the set of
inductors 70, inductor 72 in the coin selector 10, is designed for
operation in an oscillator circuit at a relatively low frequency.
The remaining inductors in the set 70, inductors 74, 76 and 78 of
the coin selector 10, are designed for operation in oscillator
circuits at substantially higher frequencies than that of inductor
72.
Each of the inductors of set 70 is placed in the sidewall 40 with
their pole faces toward the coin passageway 60, and with gap
corresponding to gap 205 of the typical inductor 200, running in a
direction perpendicular to the coin track 30. The pole faces of
each inductor, corresponding to the faces of poles 204, 206 and 207
of the typical inductor 200, are separated from the coin passageway
by an approximately ten-thousandths of an inch of epoxy impregnated
fiberglass which forms the inner surface 42 of sidewall 40. The
smooth inner surface 42 of the sidewall 40 promotes rapid travel of
coins through the coin selector 10.
Inductors 72 and 74 are located at a distance from the coin track
30 such that the smallest coin which the coin selector is to
accept, the 10-cent piece in the case of coin selector 10, will be
concentric with the inductor when placed adjacent the inductor on
the coin track 30. Similarly, the inductors 76 and 78 are placed at
a distance from the coin track 30 such that the successively larger
coins to be examined by the coin selector, the 5-cent and 25-cent
pieces in the case of coin selector 10, are concentric with the
respective inductors when they are adjacent the inductor and on the
coin track 30.
The inductor 72 is part of the resonant circuit of an electronic
oscillator 80. One such oscillator has been constructed which has
an idling frequency of 9.3 kHz. when there is no electrically
conductive material in the vicinity of the pole faces of the
inductor 72. When non-magnetic electrically conductive material is
placed in the vicinity of the pole faces corresponding to the faces
of poles 204, 206 and 207 of the typical inductor 200, however, the
oscillation frequency is increased. In the case of the 5-cent,
10-cent and 25-cent pieces, respectively, the peak frequency
reached as the coin rolls past inductor 72 on the coin track 30
were approximately 10.67 kHz., 11.87 kHz. and 12.18 kHz. The peak
frequency is dependent upon the conductivity of the coin, as well
as the permeability and thickness of the coin (in some cases) and
percentage of magnetic flux from the inductor 72 which is shunted
by the coin -- a function primarily of the sizes and relative
locations of the coin and the inductor 72.
A narrow-band detector circuit 81 having a center frequency of
10.67 kHz. is arranged to monitor the oscillator frequency. When a
coin is rolled past inductor 72, the detector will produce a single
output signal when the frequency reaches approximately 10.67 kHz;
however, when a 10-cent or 25-cent piece rolls past the inductor
the oscillator frequency will go through 10.67 kHz to a higher
frequency and through again when the frequency decreases as the
coin approaches inductor 72 and then goes away from inductor 72. As
a result, the narrow-band detector 81 will produce two output
signals in the case of the 10-cent and 25-cent pieces passing
inductor 72. A second narrow-detector 82, arranged to indicate the
presence of signals of the frequencies in the range from 11.87
through 12.18 kHz., would produce no useful output signal when a
5-cent piece passed inductor 72, as the oscillator frequency would
never reach 11.87 kHz., but would produce a single output signal
when a 10-cent or 25-cent piece passed that inductor.
Many kinds of slugs and non-acceptable coinage differ substantially
in low frequency conductivity from genuine 5, 10 and 25-cent
pieces. When such pieces pass inductor 72 either two signals or no
signal will be produced at the output of each of these detectors 81
and 82. The coin selector 10 can distinguish a genuine 5-cent piece
from genuine 10 and 25-cent pieces and from many kinds of slugs and
non-acceptable coinage by accepting only coins which produce a
single output from one of the detectors 81 and 82 and rejecting
coins which produce either no output or two outputs from each
detector 81 and 82.
Each of inductors 74, 76 and 78 is connected in the resonant
circuit of an oscillator circuit 84, 86 and 88 respectively, which
is designed to reach a maximum frequency of 455 kHz. when a
10-cent, 5-cent or 25-cent piece passes its associated inductor 74,
76 or 78 respectively. Each of the oscillator circuits 84, 86 and
88 may have a different idling frequency in the absence of coins,
usually somewhere in the range of 300-400 kHz. For example, the
idling frequencies of oscillator circuits 84, 86 and 88 in an
experimental coin selector were 349, 345 and 344 kHz.
respectively.
The frequencies generated by each of the oscillators 84, 86 and 88,
associated with inductor 74, 76 and 78 are monitored by three
narrow-band detector circuits 85, 87 and 89 respectively. Each of
the detector circuits has a 455 kHz. ceramic filter, for example
Murata type SF-455-D distributed by The Murata Corp. of America,
New York, New York. Such filters, which are now commonly used in
radio receivers, are readily available and inexpensive. As in the
case of inductor 72, a determination can be made of whether a
genuine coin has passed one of inductors 74, 76 or 78, by
determining whether the associated detector, 85, 87 or 89 has
produced one output pulse, two output pulses or none. A single
output pulse from one of the detectors would indicate that a
conductive object which has passed the associated inductor has
caused the oscillator frequency to shift from the idling frequency
to 455 kHz. and then return toward the idling frequency, denoting
the possibility of a genuine coin of the denomination associated
with that inductor. No output pulse from a given detector would
indicate that either no conductive object has passed the associated
inductor, or that the conductivity and permeability of an object
that has passed the inductor, and location of the object with
respect to the inductor (a function of object diameter, and
inductor diameter and height above the track) was such that the
frequency was not shifted from the idling frequency to 455 kHz. Two
output pulses from the detector would indicate that the frequency
was shifted beyond 455 kHz., beyond the narrow bandwidth of the
detector, and then returned to the idling frequency; which is also
an indication that the object passing the inductor is not a genuine
coin of the associated denomination.
Three AND-gates 101, 102 and 103 are arranged to provide a signal
indicative of whether a coin being examined has produced an
indication of potential acceptability at both a low frequency and a
high frequency. The first AND gate 101 is connected to the output
of flip-flop 91. A signal on this output indicates that a coin is
potentially a 10-cent or 25-cent piece. The other input of gate 101
is connected to flip-flop 94 which provides an indication of
whether the coin being examined has satisfied the high frequency
test for a 10-cent piece. The second AND gate 102 is connected to
the output of flip-flop 91 and to flip-flop 98, each of which
provides indications of whether a coin is potentially a 25-cent
piece. The third AND gate 103 is connected to the output of
flip-flop 92 and to the output of flip-flop 96, which each provide
an indication of whether a coin is potentially a 5-cent piece. When
both of the inputs of one of the AND gates 101, 102 or 103 receive
a positive indication, that AND gate produces an output signal
which by means of OR gate 104 activates solenoid 110 moving barrier
111 from its normal position obstructing the entrance to the
acceptable coin passageway 120 for a sufficient period for the coin
being examined to fall into the acceptable coin passageway 120. The
outputs of AND gates 101, 102 and 103 are also connected by leads
131, 132, 133 to the accumulator 140, so that the output signal
from each of those AND gates is transmitted to the accumulator to
indicate the denomination of the coin which has been accepted.
In order to discuss the operation of coin selector 10', we take for
example the examination of a genuine 5-cent piece. The coin is
dropped into coin entrance 20 and falls onto coin track 30. The
curved initial section 32 of coin track 30 converts the energy of
the coin's vertical motion into horizontal motion along coin track
30. The coin first approaches and passes inductor 72, causing the
oscillator 80 to shift in frequency from 9.3 kHz. to approximately
10.67 kHz. As a result of this frequency shift, detector 81
produces a single output pulse which sets flip-flop 91 thereby
providing a positive output indication from flip-flop 91. Detector
82 does not produce an output signal when the 5-cent piece passes
inductor 72, as the frequency of oscillator 80 is not shifted to
the range of detector 82, which is approximately from 11.87 to
12.18 kHz. Flip-flop 92 is therefore not set and the absence of a
positive indication on its output which is applied to AND gates 101
and 102 will prevent the coin selector for identifying the coin
being examined as being a genuine 10-cent or 25-cent piece.
The 5-cent coin being examined next rolls towards and past inductor
74, which is associated with the high frequency examination of
10-cent pieces. The presence of the 5-cent piece in the vicinity of
inductor 74 causes the associated oscillator 84 frequency to
approach 455 kHz., increases above 455 kHz. and then falls past and
below 455 kHz. as the 5-cent piece approaches, moves past and away
from the inductor 74. As a result the output of detector 85
produces a first pulse as the coin approaches inductor 74, setting
flip-flop 94 and a second pulse as the coin proceeds away from
inductor 74, which resets flip-flop 94; leaving flip-flop 94
without a positive output indication of the presence of an object
which might be a 10-cent piece. The 5-cent piece then approaches
inductor 76 which is associated with 5-cent pieces. As the 5-cent
piece passes by inductor 76, the oscillator 86 frequency is caused
to approach, reach and then fall below 455 kHz.; causing a single
output pulse from the detector 87, which sets flip-flop 96
producing a positive indication at the output of that flip-flop.
Finally the coin approaches and passes inductor 78. As in the case
with inductor 74, the frequency of oscillator 88 which is
associated with inductor 78 increases to, exceeds and then falls
below 455 kHz. as the 5-cent piece passes the inductor. This causes
two output pulses to be produced by detector 89, setting and then
resetting flip-flop 98; so that at the conclusion of the
examination the output of flip-flop 98 is not a positive
indication.
After the coin being examined has passed the entire set of
inductors 70 a pulse is applied to the input of each of the AND
gates 101, 102 and 103 on lead 105 from the strobe pulse generator
106, to interrogate the AND gates regarding the examination just
completed. Since in this case the only positive indications from
the flip-flops are on the inputs of AND gate 103, only that gate
produces an output signal which passes through OR gate 104 to
activate solenoid 110 and also passes directly by lead 133 to
accumulator 140 where the acceptance of a 5-cent piece is recorded.
A suitable circuit for this purpose is shown and described below
with respect to gates 934, 935 and 936 in FIG. 9.
An alternative low frequency circuit 500 is shown in FIG. 7. An
oscillator 510 produces a low frequency signal, e.g.,: 5,000 kHz.,
which is coupled to the transformer 512. The output of the
transformer 512 is approximately 3 to 4 volts rms. That output is
applied to terminals 521 and 522 of a multiple leg bridge 520. The
two legs of the bridge on the left side of FIG. 7, comprising the
common or inductor branch, are the inductor 525 between terminals
522 and 523, and a resistor 526 between terminals 523 and 521. The
inductor 525 may be similar to the typical inductor 200 which has
already been described.
On the right side of the bridge shown in FIG. 7 there are three
branch circuits in parallel between terminals 521 and 522, coupled
at terminals 530, 540 and 550 respectively to differential
amplifiers 537, 547 and 557. In one leg of each of these circuits
is a resistor 531, 541 or 551, connected from terminal 522 to
terminals 530, 540 or 550 respectively. The other leg of each of
the branch circuits contains a resistor-capacitor combination
having the capacitative reactance sufficient to balance the
inductive reactance of inductor 525 when a genuine coin of a
particular denomination is adjacent the inductor 525. Each such leg
has a fixed capacitor 532, 542 or 552 in parallel with a small
trimmer capacitor 533, 543 or 553. In parallel with the capacitors
in each circuit is a resistance sufficient to balance the
inductor's resistance, which for convenient range limitation
comprises the series combination of variable resistor 534, 544 or
554 and fixed resistor 535, 545 or 555.
The inputs of each of the differential amplifiers 537, 547 and 557
is in effect across a bridge which can be adjusted to be in balance
when a single denomination coin is adjacent inductor 525. Thus, for
example, the capacitative reactance could be adjusted so that
amplifier 537 would detect a balanced condition when a 5-cent piece
is adjacent the inductor 525, and by similar adjustments amplifier
547 would for a 10-cent piece and amplifier 557 would for a 25-cent
piece. The output of each of the differential amplifiers 537, 547
and 557 is fed to the input of a corresponding diode rectifier 538,
548 or 558, the outputs of each of which are fed to the
corresponding limiting amplifiers 539, 549 and 559. The limiting
amplifiers are cut off at zero signal input but saturate at very
low input signal levels, and thereby convert the analog signal from
their corresponding differential amplifier 537, 547 or 557 into a
digital signal which is at one level when the differential
amplifier inputs are very close to balanced or are balanced, and at
another level at all other times (amplifier saturated). The digital
outputs of limiting amplifiers 539, 549 and 559 are fed to logic
circuitry 560 which may be of a type similar to that described with
respect to FIG. 4. The low frequency circuit 500 is used in
combination with a high frequency circuit, such as that shown in
FIG. 4.
Typical values for a circuit according to FIG. 7 would be: Resistor
526 2,000 ohms Resistors 531, 541, 551 2,000 ohms Variable
Resistors 534, 544, 554 25,000 ohms max. Resistors 535, 545, 555
5,000 ohms Capacitors 532, 542, 552 .01.mu. F Variable Capacitors
533, 543, 553 300 pf max.
Inductor 525 may be 1,100 turns of No. 39 wire on a 22 mm pot core.
Differential amplifiers 537, 547 and 557 may be Fairchild type 741
or the equivalent.
SECOND EMBODIMENT
A coin selector 600 formed in accordance with the present invention
in which all inductors are employed to examine for all
denominations of coins in the acceptable set, is shown in FIGS. 9
through 11. The mechanical arrangement of principal components is
indicated by numeral 610. A coin may be introduced into the coin
selector 600 through the coin entry 620. The coin then falls under
the influence of gravity onto the deflector 630, which is sloped
downwards in a direction away from the coin entry 620. The first
coin track 631 onto which the coin entering the coin selector 600
through the coin entry 620 under the influence of gravity first
falls is arranged so that the coin's vertical motion will be
transformed into motion along the first coin track 631 with a
minimum of coin bouncing.
Adjacent and contiguous to the deflector 630 and the first coin
track 631 and the second coin track 632 is a sidewall 640 which is
canted at a sufficient angle from the vertical to cause the face of
a coin to bear against the wall 640, when the edge of a coin is
resting on one of the coin tracks 631 or 632. An angle from the
vertical greater than 5.degree. and less than 25.degree. is
acceptable for the sidewall 640; an angle of 9.degree. having been
found particularly satisfactory for a system having two tracks such
as tracks 631 and 632. The coin tracks 631 and 632 are ordinarily
arranged at a right angle to the sidewall 640. A second sidewall
650 is arranged generally parallel to the sidewall 640 and is
spaced away from sidewall 640 by a distance slightly greater than
the thickness of the thickest coin which is to be selected by the
coin selector 600. In FIG. 9, the lower portion of the sidewall 650
is not shown. The deflector 630 and the coin tracks 631 and 632 and
the sidewalls 640 and 650 form a coin passageway 660. The sidewall
640, the deflector 630 and the coin tracks 631 and 632 may
conveniently be molded from the same piece of material. The accept
gate (block 943 in the electrical portion of the diagram) is
located approximately as indicated at 670. Further information
concerning the mechanical details of an apparatus such as coin
selector 600 is contained in British Provisional Specification Nos.
8386/72 and 8387/72, filed by the assignee of this application on
Feb. 23, 1972.
In a coin selector 600, having a mechanical arrangement 610 of
components, which is designed to examine and accept genuine coins
of three different denominations, a set 710 of six inductors 711,
712, 713, 714, 715 and 716 is located along the coin passageway
660. Each of the inductors 711-716 is similar to the typical pot
core inductor 200, shown in and described with respect to FIGS. 5
and 6. Alternatively, one or more of the inductors may be of a
different type; for example, E-core inductors of the conventional
type arranged with the three pole pieces in a line generally
parallel to the coin track. A greater or lesser number of inductors
can also be utilized without departing from the present invention;
for example, by utilizing a single inductor or pair of inductors
for more than one function, as described below.
In one coin selector constructed in accordance with this invention
for use with U.S. coins of the 5-cent, 10-cent and 25-cent
denominations, the first or arrival inductor 711 which is
encountered by a coin moving through the coin selector 600 is a
coil wound on an 11 mm diameter pot core and is designed for
operation in an oscillator circuit at frequencies in the vicinity
of 455 kHz. It is located in a sidewall, e.g.; the sidewall 650
against which the coins are caused to bear by gravity and the angle
off vertical of the sidewalls 640 and 650, at a position where it
will be passed by all acceptable coins entering the coin selector
when they fall onto the first coin track 631. The lower edge of the
inductor 711 is located approximately 1/2 mm above the first coin
track 631, to minimize the effects of coin bounce.
The second and third inductors are low frequency inductors, 712 and
713, which are two series connected coils each wound on 14 mm pot
cores located opposite each other on either side of the passageway
660 in sidewalls 640 and 650 respectively. The series connected
inductors 712 and 713 are designed for use in a low frequency
bridge circuit operating at a frequency under 25 kHz, and typically
at a frequency in the vicinity of 5 to 7 kHz. These low frequency
(LF) inductors 712 and 713 are located at the lower end of the
first coin track 631 to permit the coin being tested to become
stabilized on the track before entering their field. The lower edge
of the pot core of each of the inductors 712 and 713 is located
slightly below the first coin track 631. The use of a pair of
inductors 712 and 713 at opposite sides of the passageway 660 at
the same position, makes the conductance examination at that
position particularly sensitive to the thickness of coins being
examined and therefore provides greater protection against attempts
to defraud the coin selector with slugs or the like comprising a
conductive body with a nonconductive coating which serves to adjust
the spacing of the conductive body from the sidewall against which
the slug bears; while reducing erroneous rejection of acceptable
coins which move from side to side of the passageway 660 as they
pass through the coin selector 600.
Located along the second coin track 632, reading from right to left
in the direction of movement of a coin under the influence of
gravity are inductors 714, 715 and 716, each of which is a coil
wound on an 18 mm diameter pot core which is located in the
sidewall opposite that in which the arrival inductor 711 is
mounted, sidewall 640, and each of which is designed for operation
in an oscillator circuit in the vicinity of 455 kHz. Each such
inductor 714-716 is located with the upper edge of its pot core at
a distance orthagonal to second coin track 632, which distance is
1/2 to 1 mm greater than the diameter of the coin denomination with
which it is associated, i.e.: inductor 714 being the 5-cent high
frequency (HF) inductor, inductor 715 being the 25-cent HF inductor
and inductor 716 being the 10-cent HF inductor.
Each of the HF inductors 711, 714, 715 and 716 is connected in an
oscillator circuit 721, 724, 725 and 726 respectively. Each of
these oscillator circuits is substantially the same as circuit 721
shown in detail in FIG. 10.
In oscillator circuit 721, the inductance of inductor 711 and
capacitors 731, 732, 733 and variable capacitor 734 form a resonant
circuit. Capacitor 733 may be a temperature compensating capacitor.
Variable capacitor 734 is used for tuning the resonant circuit.
Capacitors 731 and 732 form a high frequency voltage divider, the
voltage across capacitor 732 being applied between ground and the
emitter of common base oscillator transistor 735, which may be a
type 2N3856A type transistor, through a 200 ohm max. adjustable
resistor 736, which adjusts the positive feedback to stabilize the
oscillator. The signal applied to the emitter appears amplified and
in phase between ground and the collector of transistor 735,
resulting in a self-sustaining oscillation. The DC emitter bias of
the transistor 735 is established by resistor 737, which is in
series with an HF blocking inductance 738. Positive DC voltage is
applied to the collector of transistor 735 through HF blocking
inductor 739, which is in series with a 100 ohm resistor 740 which
lowers the Q of inductor 739 sufficiently that it doesn't
significantly affect the resonant circuit. Resistors 741 and 742
establish the base bias of the transistor 735, and by-pass
capacitors 743 and 744 prevent high frequency fluctuations of the
15V supply and of the base potential.
At the output of each of the oscillators 721, 724, 725 and 726 is a
high Q HF detector circuit, 751, 754, 755 and 756 respectively.
Each of these detector circuits is substantially the same as
detector circuit 751 shown in FIG. 10 and is connected to its
respective oscillator as indicated in that figure.
The input signal for detector circuit 751 is the voltage across
capacitor 732 of the oscillator 721. The signal is applied to a
two-stage 455 kHz filter 761, such as Murata type SF-455-D ceramic
filter distributed by The Murata Corp. of America, New York, New
York. Two 300 ohm resistors 762 and 763 are provided to properly
match the impedance of the filter 761. Capacitor 764 couples the
two stages of the filter 761; its value selected to provide the
desired bandpass of the detector 751. Diodes 765 and 766 form a
peak rectifier, the voltage at the output of diode 766 being
representative of the peak-to-peak voltage at the output of the
filter 761. Filtering is provided by capacitor 767 and resistor
768. The filtered signal from resistor 768 is applied to the base
of the common emitter DC switching transistor 769 such as a type
2N2925 transistor. When a sufficient amplitude signal is applied to
the base of transistor 769, its impedance switches from high to
low, causing the collector voltage, supplied from a 5,600 ohm
resistor 770, to drop from the supply voltage (5 volts DC) to
nearly ground potential. A 1 microfarad capacitor 771 connected
from the collector of transistor 769 to ground provides extra
filtering to assure a clean waveform substantially free of
oscillator frequency variations and noise.
In the case of some of the oscillators, such as oscillators 721 and
726, it may be desirable to have a detector, such as detectors 757,
758 and 759, which are tuned to a frequency other than that of the
other detectors 751, 754, 755 and 756, and have a lower Q than
those other detectors. A typical detector of this type, detector
758, is also shown in FIG. 10. Transformer 781 is a conventional,
adjustable-core IF transformer of the type commonly used in radio
receivers and capacitor 782 is a capacitor of the type
conventionally used and packaged with such IF transformers.
Resistor 783 is an impedance matching resistor selected to match
transformer 781. Diode 784 provides a rectified output
representative of the amplitude of the signal at the transformer
output tap to which the cathode of the diode 784 is attached.
Capacitor 785, resistor 786, switching transistor 787, capacitor
788 and resistor 789 each performs the same functions as the
corresponding components of detector 751.
The low frequency (LF) oscillator 722 produces a low harmonic
content sine wave of approximately 5 kHz. As shown in FIG. 11, its
resonant circuit is formed by the inductance of the primary coil
811 of the transformer 810 and capacitors 813 and 814. The voltage
across capacitor 813 is applied to the base of a common collector
connected transistor 815, which produces a current gain at its
emitter which is used to drive the emitter of a common base
connected transistor 816. Both the transistor 816 and the
transformer 810, to which the collector of the transistor 816 is
connected at a tap near the DC end of the primary coil 811, provide
gain so that the overall loop gain is unity. A suitable type of
transistor for use as transistors 815 and 816 is type 2N3856A. The
value of resistor 817 is selected to provide the desired amount of
feedbakc. Resistor 818 provides appropriate emitter bias for
transistor 815. Resistors 819 and 820 provide the emitter bias for
transistor 816. They also affect stability and the amount of
feedback. Resistors 821 and 822, which have equivalent values,
provide the bias for the base of transistor 816. Resistor 823
provides signal isolation between the bases of the transistors 815
and 816 while leaving their operating points substantially the
same. Capacitor 824 is the base by-pass capacitor for transistor
816.
The output of the LF oscillator 722 from the secondary coil 812 of
transformer 810 is applied to bridge circuit 752. The value of the
resistor 834 in one of the leads from the oscillator 722 to the
bridge 752 is selected to provide the desired amount of oscillator
voltage to the bridge 752, thereby affecting the sensitivity of all
of the LF detection circuits. Two legs of the bridge circuit 752,
those comprising resistor 831, and inductors 712 and 713 and
resistors 832 and 833, are used in common with all three of the low
frequency detector circuits 774, 775 and 776. The other two legs of
the bridge comprise a portion of each individual detector circuit,
only detector 774 being shown in detail in FIG. 11.
The LF inductors 712 and 713 are connected in series in one leg of
the bridge 752 so that when a coin passing between the LF inductors
affects the magnetic field between them, both the amplitude and
phase of the LF voltage applied across the inductors 712 and 713
changes. The value of resistor 831 has been selected to have
substantially the same impedance in the absence of coins and other
field influencing objects between the inductors 712 and 713, as
that of the leg comprising the inductors and resistors 832 and
temperature compensating resistor 833, which compensate for changes
in impedance due to the heating of the wires of the inductors 712
and 713.
Each of the LF detectors 774, 775 and 776, the 5-cent, 25-cent and
10-cent LF detectors respectively, is similar to detector 774 shown
in FIG. 11 and is similarly connected at its input as a part of
bridge 752. One leg of the bridge 752 in detector 774 comprises a
fixed resistor 835 in series with a variable resistor 836, the
resistors being in parallel with a series connected to variable
capacitor 837 and temperature compensating capacitor 838 (to
compensate for changes in the reactive component in the bridge by
heating of the wires of the inductors 712 and 713). The variable
resistor 836 and variable capacitor 837 are adjusted so that when a
genuine coin of the associated denomination (a 5-cent piece in the
case of detector 774) passes between the LF inductors 712 and 713,
the bridge will be brought substantially into balance.
The active elements of the detector 774 comprise an operational
amplifier 840, e.g.: a Fairchild type 741 amplifier, a peak
detector comprising two diodes 853 and 854, and a switching
transistor 860. In order to make the amplifier 840 linear for small
input signals, in the vicinity of a null of the bridge 752, the
non-inverting input (terminal 3) is biased to midway between the DC
power supply voltage and ground potential by equal value resistors
841 and 842. Resistor 842 is bypassed by capacitor 843 to maintain
one side of the bridge 752 at LF ground potential. The inverting
input (terminal 2) of the amplifier 840 is isolated from the DC
bias potential by blocking capacitor 846. Resistors 844 and 845 are
large (e.g.: 100,000 ohms) and the input impedance of the amplifier
840 is high, so resistors 844 and 845 have substantially no effect
on the operating point of the amplifier 840. The output of the
amplifier (terminal 6) reproduces the inverse of the signal applied
to the inverting input (terminal 2). Feedback from the output
terminal to the inverting input is provided by the network of two
100,000 ohm resistors 847 and 848, and capacitor 849 to stabilize
the quiescent point of amplifier 840 at the value of the
non-inverting input voltage. The divider primarily comprising
resistors 847 and 848 is in parallel with resistor 851 connected to
the output of the amplifier 840 and provides negative feedback to
stabilize the LF gain at approximately 200.
A DC blocking capacitor 852 couples the LF output of amplifier 840
to a peak detector comprising diodes 853 and 854. Two resistors 855
and 856 and two capacitors 857 and 858 comprise a filter to smooth
the rectified output of the diodes 853 and 854. The output of that
filter is applied to the base of a common-emitter coupled switching
transistor 860, which may be a type 2N3392 transistor. The DC base
bias of the transistor 860 is established by the divider comprising
resistors 859, 856 and 855 and diodes 854 and 853. A small
capacitor 861 (e.g.: 0.0018 microfarad) between collector and base
of the transistor 860 and a capacitor 862 (e.g.: 0.1 microfarad)
from collector to ground provides further filtering to assure a
smooth switching waveform from transistor 860. A power supply
filter capacitor 863 is connected between the source of detector
power and ground.
When the bridge 752 is unbalanced, its normal quiescent condition
in the absence of an acceptable coin of the proper denomination
from between the LF inductors 712 and 713, the rectified signal
voltage from the diodes 853 and 854 holds the transistor 860 "off,"
so that the collector of transistor 860 is at substantially the
collector supply potential (here, 5 volts DC). When a coin or other
object causes the inductance of the inductors 712 and 713 to change
so that the bridge 752 is substantially balanced, the input to the
base of transistor 860 will drop below the switching threshold,
transistor 860 will switch "on," substantially all of the collector
supply voltage will be applied across the collector supply resistor
864 and the output of the detector 774 at the collector of
transistor 860 will be substantially ground potential.
In order to discuss the operation of coin selector 600, we take for
example the examination of a genuine 10-cent piece. After the coin
is dropped into coin entrance 620 and falls into the first coin
track 631, it first approaches and passes arrival inductor 711,
causing the oscillator 721 to shift upwards in frequency from its
idling frequency of approximately 386 kHz.
The oscillator 721 has been designed and its idling frequency has
been selected so that any non-magnetic electrically conductive
coin-like object passing the arrival inductor 711 will cause the
frequency of oscillator 721 to rise at least to 10 kHz above idling
frequency. One of the arrival detectors 758 is tuned to this higher
frequency, and therefore produces an output whenever any object
passing the arrival inductor 721 causes a shift to that frequency.
If the object passing inductor 711 has characteristics similar to a
single coin of a denomination with which the coin selector 600 is
intended to operate, the frequency from oscillator 721 will pass
twice through the bandpass of the first arrival detector 758, first
as the frequency increases and then as it decreases, causing the
detector 758 to produce two output pulses. The pulses from the
detector 758 are amplified and shaped by amplifier 901 and applied
to a NAND gate 902 and the triggering input of a J-K flip-flop 903.
In the usual case when a coin test is started flip-flops 903 and
904 which are arranged as a four-bit counter have been reset, and
they and the amplifier 901 are producing an output signal of the
same polarity. When the arrival detector 758 produces its first
pulse, the output of amplifier 901 is switched momentarily to the
opposite polarity, causing a pulse to appear at the output of the
NAND gate 902 and triggering flip-flops 903 and 904. Both before
and after this first pulse, both inputs to NAND gate 905 from the Q
outputs of the flip-flops 903 and 904 are the same, so no signal
appears at the output of the NAND gate 905. The pulse from the NAND
gate 902 is coupled by capacitor 906 to switching transistor 907,
turning it on and producing a pulse at its output which drives the
reset amplifier 909 at its input point 910. Resistor 908 is the
base bias resistor for transistor 907.
When a second pulse is produced by detector 758, the signals
applied to each of NAND gate 902 and NAND gate 905 are all of the
same polarity and therefore each produces no output. In the event
that two closely spaced coins pass the arrival inductor 711;
detector 758 produces a third and a fourth pulse. The third pulse
does not affect the output of NAND gate 902, but NAND gate 905 is
caused to generate an output by the third pulse, which triggers
monostable 911 causing it to produce an 800 millisecond pulse which
in turn activates the reset amplifier 909 for that period and
thereby prevents the coin selector 600 from examining and accepting
either of the coins present on the flight deck at that time. This
third pulse is counted by the contiguity counter (flip-flops 903
and 904) which enable NAND gate 905. Flip-flops 903 and 904 are
reset each time a coin departs from the coin selector by a signal
from the departure detector 757.
The oscillator 721, inductor 711 and the second arrival detector
751 have been adjusted so that any genuine coin of a denomination,
which the coin selector 600 is intended to accept, passing the
inductor 711 will cause the frequency of the oscillator 721 to rise
above 455 kc, producing a pulse which sets flip-flop 912 producing
a continuous output which drives an amplifier 913 and enables the
collector terminal 916 of transistor 915 for purposes which will be
described below in connection with the departure detector 757.
In the event that the object passing the arrival inductor 711 has
exceptionally high conductivity as for example copper or lead, the
frequency from the oscillator 721 increases to well above 455 kHz.
In the case of a coin selector designed to accept only nickel and
cupronickel clad coins, such objects are rejected. This rejection
is accomplished in the coin selector 600 of FIG. 9 by use of a
copper detector circuit 759, which is similar to arrival detector
circuit 758 but tuned to have a frequency bandpass above the
maximum frequency which the oscillator produces for geniune coins,
e.g.: approximately 472 kHz. In the event that the frequency of the
oscillator 721 reaches the frequency to which the copper detector
759 is tuned, the copper detector 759 produces a pulse which is
amplified by an amplifier 917 and applied to the input of
monostable 911 which activates the reset signal in the manner
previously described.
After passing the arrival inductor 711, the 10-cent coin moves
under the force of gravity to the low frequency inductors 712 and
713. As it passes those inductors, the appropriate detector 776
produces an output pulse triggering and setting flip-flop 976,
flip-flops 974 and 975 being left in the reset condition since the
10-cent coin will not cause the frequencies produced by oscillators
724 and 725 to rise to the tuned frequency of detectors 774 and
775. As in the preceeding embodiment, in the event that a coin
passing one of the HF inductors has characteristics which cause its
associated oscillator to rise above the tuned frequency of its
detector; that detector will produce two output pulses as the coin
passes the inductor which will first set and then reset the
associated flip-flop.
The 10-cent coin then drops from the first coin track 631 to the
second coin tract 632 and moves successively past HF inductors 714
and 715. A 10-cent piece will not cause the frequencies of the
respective oscillators 724 and 725 to be shifted sufficiently from
their idling frequencies of approximately 396 kHz and 403 kHz to
reach the 455 kHz tuned frequency of HF detectors 754 and 755. In
the case of inductor 716 and oscillator 726, however, a genuine
10-cent piece will cause the frequency of the oscillator 721 to
change from its idling frequency of approximately 411 to, but not
above, the bandpass centered on 455 kHz of the 10-cent HF detector
756. The detector 756 therefore produces a single pulse which
triggers and sets 10-cent HF flip-flop 956.
In addition to participating in the HF examination for 10-cent
coins, 10-cent oscillator 756 drives the departure detector circuit
757, which is similar to the first arrival circuit 758 and is
similarly tuned approximately 5 to 10 kHz above the idling
frequency of the oscillator with which it is associated. When the
frequency of oscillator 726 first passes through the pass band of
the departure detector 757, flip-flop 918, which acts as a two-bit
counter, is triggered into the set condition. This, however, does
not affect switching transistor 915, the base of which is coupled
to the Q output of flip-flop 918 by capacitor 919, because of the
polarity of the pulse from capacitor 919 and the bias of the base
by resistor 920. When the frequency of the oscillator 726
approaches the idling frequency again, however, a second pulse from
departure detector 757 again triggers flip-flop 918, which this
time causes a pulse of the appropriate polarity to be applied from
capacitor 919 to the base of switching transistor 915. The
transistor 915 is then switched off permitting the collector
terminal 916 of transistor 915 to go to the potential produced by
amplifier 913. If amplifier 913 is producing a signal as a result
of the second arrival detector 751 having set flip-flop 912 and
nothing having caused flip-flop 912 to be reset, a pulse enabling
signal or strobe is applied to AND gates 934, 935 and 936. In the
event that the other two inputs of any of these gates are then each
receiving a signal, as is true for AND gate 936 in the case of a
genuine 10-cent coin, that gate produces an output signal which is
indicative of the acceptability and denomination of the coin
examined. The signal from each of the AND gates 934, 935 and 936 is
transmitted to OR gate 937 and to the accumulator 950. The base of
common collector switching transistor 940 is coupled by a capacitor
938 to the output of OR gate 937. When a signal is applied to any
of the inputs of OR gate 937, switching transistor 940 is
momentarily switched on activating the solenoid 942 which controls
the coin acceptance gate 943.
The accumulator 950 has a straightforward design of the type known
to those skilled in the art. It transmits a signal by means
represented by line 751 to the controlled equipment or vending
machine 960 indicating that the coin selector 600 has accepted
sufficient funds to satisfy the amount required as indicated by a
signal by means represented by line 951 from the controlled
equipment 960. In addition, the accumulator 950 receives a signal
by means represented by line 962 from the controlled equipment 960
indicating that the desired response, e.g.,: vending, is occurring;
which signal is used to reset the accumulator 950. The accumulator
also provides a signal by means represented by line 952 to control
a change giver 970.
The coin selector 600 has two other reset functions not previously
described. The first is a power source monitoring reset 980 which
transmits a signal to the accumulator 950 and a signal to the input
910 of reset amplifier 909 for a fixed period after each time when
the power to the coin selector 600 is turned on. This circuit tends
to prevent interference with the proper operation of the
accumulator 950 by clamping the accumulator reset line until the
power provided for its operation has stabilized. The second is
controlled by the strobe pulse at the collector terminal 916 of
transistor 915. A common emitter switching transistor 990 is
triggered on by a signal at its base at a time after the strobe
pulse which is defined by RC circuit comprising resistors 991 and
992 and capacitor 993. The collector of this transistor 990 is also
connected to the input 910 terminal of reset amplifier 909, so that
the flip-flops 912, 918, 954, 955, 956, 974, 975 and 976 of the
coin selector 600 will be reset following the departure of each
coin.
The power of both the method and apparatus utilizing LF and HF
examinations of coins for discriminating between acceptable and
unacceptable coins has been demonstrated in a test of a prototype
apparatus of the type described which was designed and adjusted to
accept greater than 95 percent of genuine U. S. 5-cent, 10-cent and
25-cent coins. None of 138 foreign coins and slugs which were
examined by the prototype apparatus were accepted, although many of
the coins and slugs were selected for their ability to pass
conventional coin selectors. Of these unacceptable coins and slugs,
16.7 percent were rejected only as a result of the LF examination
and 24.6 percent were rejected only as a result of the HF
examination, 2.9 percent were acceptable as different denominations
on the HF and LF examinations but were rejected as a result of the
requirement that the coin examination indicate acceptance with
respect to the same denominations at both the low frequency and the
high frequency. The remaining 55.8 percent were rejected as a
result of both the HF and LF examinations.
THIRD EMBODIMENT
A coin selector 1000 formed in accordance with the present
invention having a mechanical arrangement 1010 of certain
components is shown in FIG. 12. A coin may be introduced into the
coin selector 1000 through the coin entry 1020. The coin then falls
under the influence of gravity onto the deflector 1030, which is
sloped downwards in a direction away from the coin entry 1020. The
deflector 1030 onto which the coin initially falls so that the
vertical motion of a coin entering the coin selector 1000 through
the coin entry 1020 under the influence of gravity will be
transformed into motion along the first coin track 1031 with a
minimum of coin bouncing.
Adjacent and contiguous to the deflector 1030 and the coin track
1031 is a sidewall 1050 which is canted at a sufficient angle from
the vertical to cause the face of a coin to bear against the wall
1050, when the edge of a coin is resting on the coin track 1031. An
angle from the vertical greater than 5.degree. and less than
25.degree. is acceptable for the sidewall 1050; an angle of
9.degree. having been found particularly satisfactory. A second
sidewall 1040 is arranged generally parallel to the sidewall 1050
and is spaced away from sidewall 1050 by a distance slightly
greater than the thickness of the thickest coin which is to be
selected by the coin selector 1000. The coin track 1031 is
ordinarily arranged at a right angle to the sidewall 1040. In FIG.
12, the lower portion of the sidewall 1050 is not shown. The
deflector 1030 and the coin track 1031 and the sidewalls 1040 and
1050 form a coin passageway 1060. The sidewall 1040, the deflector
1030 and the coin track 1031 may conveniently be molded from the
same piece of material. The accept gate (block 1243 in the
electrical portion of the diagram) is located approximately as
indicated at 1070.
In a coin selector 1000, which is designed to examine and accept
genuine coins of three different denominations, a set 1110 of four
inductors 1111, 1112, 1113, and 1114 are located along the coin
passageway 1060. Each of the inductors 1111-1113 is similar to the
typical pot core inductor 200, shown in and described with respect
to FIGS. 5 and 6 above. Inductor 1114 in the embodiment shown in a
18 mm .times. 13 mm E-core inductor, arranged with the three pole
pieces in a line generally parallel to the coin track.
In one coin selector constructed in accordance with this invention
for use with U.S. coins of the 5-cent, 10-cent, and 25-cent
denominations, the first or arrival inductor 1111 which is
encountered by a coin moving through the coin selector 1000 is a
coil wound on an 18 mm diameter pot core and is designed for
operation in an oscillator circuit at frequencies in the vicinity
of 400 to 500 kHz. It is located in a sidewall, e.g.: the sidewall
1050 against which the coins are caused to bear by gravity and the
angle off vertical of the sidewalls 1040 and 1050, at a position
where it will be passed by all acceptable coins entering the coin
selector when they fall onto the first coin track 1031. The lower
edge of the inductor 1111 is located approximately 1 mm. above the
first coin track 1031.
The second and third inductors are low frequency inductors, 1112
and 1113, which are two series connected coils each wound on 14 mm.
pot cores located opposite each other on either side of the
passageway 1060 in sidewalls 1040 and 1050 respectively. The series
connected inductors 1112 and 1113 are used in a low frequency
bridge circuit 1152 which is driven by oscillator 1122, similar to
the bridge circuits shown in FIGS. 7 and 11. The low frequency (LF)
inductors 1112 and 1113 are located at the lower end of the first
coin track 1031 to permit the coin being tested to become
stabilized on the track before entering their field. The lower edge
of the pot core of each of the inductors 1112 and 1113 is located
approximately 4 mm. below the coin track 1031.
The fourth inductor 1114 is located in the opposite sidewall 1040
of the passageway 1060 from the first inductor 1111. Like the first
inductor 1111, the fourth inductor 1114 is for use in a high
frequency (HF) circuit. In the embodiment shown, the fourth
inductor 1114 is located above inductors 1112 and 1113, with its
bottom edge approximately 14 mm. above the track, and aligned with
the centers of its three pole pieces parallel to the coin track
1031 at that point. The center poles of all three inductors 1112,
1113 and 1114 are located on a line orthogonal to the track.
The above-described arrangement of inductor locations has been
selected for a particular set of coin denominations. The location,
size and operating frequency of the first HF inductor 1111 cause
the examination results to be a function of both diameter and
surface material characteristics of the coin. Similarly, the
results of examination by the second HF inductor 1114, which is on
the opposite side of the coin passageway from the sidewall 1050 on
which the face of the coin bears, are a function of diameter and
surface material characteristics, and also of distance of the
conductive material of the coin from the inductor 1114. Because the
two HF examinations are made independently from opposite sides of
the coin, the coin selector 1000 is particularly secure against
slugs which might be made by laminating non-conductive material to
conductive material in an effort to simulate the conductivity of a
different conductive material which is used in genuine coins.
Each of the HF inductors 1111 and 1114 is connected in an
oscillator circuit 1121 and 1124 respectively; or alternatively a
single oscillator circuit may be provided, along with appropriate
switching circuitry, for use with both of the HF inductors; as the
two HF inductors are utilized sequentially. Each of these
oscillator circuits is substantially the same as circuit 721 shown
in FIG. 10. As the output of each of the oscillator circuits 1121
and 1124 is a plurality of high Q HF detector circuits 1154-1156
and 1158 and 1194-1196 and 1157 respectively. Each of these
detector circuits is substantially the same as detector circuit 751
or detector circuit 758 shown in FIG. 10, however, the bandpass
frequency of the element of the detector circuits corresponding to
filter 761 of detector 751 is not necessarily 455 kHz.
The idling frequency of oscillator 1121 is approximately 420 kHz.
The first HF or arrival detector 1158 is a circuit such as the
arrival detector 758 of FIGS. 9 and 10. tuned to a frequency
slightly above the idling frequency (e.g.,: 430 kHz.), and operates
in the same fashion as detector 758.
Detectors 1154, 1155 and 1156, circuits similar to detector 751 of
FIGS. 9 and 10, are tuned to the appropriate peak oscillator
frequency caused by a genuine 5-cent, 25-cent and 10-cent coin,
respectively, passing inductor 1111. In one coin selector these
frequencies were approximately 470, 495 and 420 kHz respectively.
Similarly, detectors 1194, 1195 and 1196, circuits monitoring the
output of oscillator 1124 which are also similar to detector 751,
are tuned to the approximate peak oscillator frequency caused by a
genuine 5-cent, 25-cent and 10-cent coins, respectively, passing
inductor 1114. In one coin selector these frequencies were
approximately 460, 460 and 420 kHz respectively when the idling
frequency of the oscillator 1124 was 400 kHz. When as, in this
case, the detector frequency is the same for two acceptable
denominations, one of the detectors can be eliminated by
appropriate changes in logic circuitry. The oscillator frequency
characteristics and the precise frequency and bandwidth of each of
the detectors is a matter of selection for the desired tolerances
by adjustment of the location and design of the inductors 1111 and
1114 and the design of the oscillator circuit.
The remaining detector is the departure detector 1157, a circuit
similar to circuit 758 of FIG. 10. It is tuned, like detector 1158
to a frequency slightly above the idling frequency of the
oscillator 1124, the output of which it monitors; however, like
detector 757, detector 1157 is connected to logic circuitry
arranged to identify the second time when the frequency of
oscillator 1124 goes through its bandpass as an indicia of the
departure of a coin from the inductor regions of the track
1031.
Appropriate logic circuitry for use in connection with the output
of the detectors of this embodiment may be constructed in
accordance with the principles discussed in previous embodiments.
The logic circuit should in each case provide an output signal
indicative of the presence of an acceptable coin of a given
denomination only in the event that, during the period between an
arrival and a departure signal, (1) the peak frequencies of
oscillators 1121 and 1124 are within the respective bandpass for
that denomination, (2) the appropriate branch of bridge 1152 for
that denomination is nulled, and (3) that the null of bridge 1152
and the peak detected by the detector 1194, 1195 or 1196 occur
within a predetermined tolerance of simultaneity. Alternatively, HF
inductor 1114 may be offset along the line of coin movement from
the LF inductors 1112 and 1113, in which case the logical
relationship between the output of the detectors associated with
each for optimum performance should include an appropriate time
delay, e.g.,: by use of a monostable multivibrator.
The basic operating block diagram of suitable logic for this
embodiment is suggested by the remainder of FIG. 12. If a genuine
coin of an acceptable denomination is inserted into the coin
selector 1000, upon approaching inductor 1111, the increase in
frequency of oscillator 1121 is detected by the arrival detector
1158 and flip-flop 1258 is set, thereby producing an output signal
at its terminal Q. As the coin passes the inductor 1111, the
frequency continues to rise to a peak frequency within the range of
one of the detectors 1154-1156, depending upon its denomination.
The detectors operate in the same fashion as the detectors 754-756
shown in FIG. 10, producing one output pulse for each time the
oscillator frequency passes through its bandpass; this producing a
single pulse only when the peak oscillator frequency is within the
detector's bandpass. The outputs of the detectors 1154-1156 are
each applied to one input of AND gates 1264-1266, respectively; the
other input of each of the AND gates being connected to the Q
output of flip-flop 1258, the arrival signal from which enables the
pulses to pass to flip-flops 1254-1256, respectively. Depending
upon the denomination of the coin tested, at least one of the
flip-flops 1254-1256, is set and remains set after the coin has
passed the inductor 1111. The remaining flip-flops either are not
set at all or are set and then reset in the manner previously
described with respect to FIG. 10.
When the frequency of oscillator 1121 decreases nearly to idling
frequency, it again passes through the bandpass of arrival detector
1158, providing an output pulse which triggers flip-flop 1258 into
reset condition. The Q output of flip-flop 1258 produces an output
which sets flip-flop 1259 and thereby enables AND gates 1294-1296,
as described below.
As the coin approaches inductors 1112-1114, the frequency of
oscillator 1124 associated with inductor 1114 increases. The
increase is first detected by departure detector 1157 which
produces an outut pulse as the frequency passes through its
bandpass; which output pulse sets flip-flop 1277, causing the Q
output of the flip-flop to supply an enabling signal to AND gates
1294-1296. In the event that one of the detectors 1194-1196 (in
this example, the detector for the same denomination previously
indicated) detects a peak oscillator frequency within its bandpass,
in the manner previously described, it produces a single output
pulse. If this occurs during the period when the one of the LF
detectors 1174-1176 for the same denomination coin detects a null
in the output of bridge 1152, then there is a coincidence of
signals on all of the inputs to the one of the AND gates 1294-1296
corresponding to that denomination coin, and a pulse is passed to
and sets the corresponding flip-flop 1274, 1275 or 1276. In the
event that the frequency of the oscillator 1124 passes twice
through the bandpass of one of the detectors 1194-1196 while the
corresponding one of the LF detectors detects a null, as a result
of a peak oscillator frequency above its bandpass, the
corresponding flip-flop 1274, 1275 or 1276 is first set and then
reset. In the event that one of the LF detectors 1174-1176 produces
two nulls, one as the coin approaches and one as the coin departs
from inductors 1112-1113, the pulse produced by the LF detectors
will not coincide with a single pulse from the corresponding HF
detector 1194-1196, and there will be no coincidence of signals at
the corresponding AND gate 1294, 1295 or 1296 and the corresponding
flip-flop 1274, 1275 or 1276 will not be set.
When the coin departs from inductor 1114 and the frequency of
oscillator 1124 again approaches idling frequency, the frequency
passes through the bandpass of departure detector 1157 producing a
pulse which causes flip-flop 1277 to be reset. The transient at the
Q output of the flip-flop 1277 passes through capacitor 1278,
momentarily increasing above ground potential the voltage of the
common point between capacitor 1278 and resistor 1279 and thereby
applying a pulse to one input of each of the AND gates 1234-1236.
If, when the AND gates receive that pulse, one of them is receiving
a signal from the Q output of its corresponding flip-flop 1274,
1275 or 1276, the signal is passed to the accumulator 1260 as an
indication of denomination and via OR gate 1237 and AND gate 1239
to activate solenoid 1242 to remove the accept gate 1243
(designated by 1070 in the mechanical portion of the Figure) from
the coin path. Alternatively, a coin presence indicative signal
produced by a coin presence sensor 1072 along the coin path above
the accept gate 1243 (1070) and an appropriate logic circuit 1238
may be used to activate the solenoid 1242. The accepted coin then
falls past a coin presence sensor 1073, which operates in
conjunction with the logic circuit 1238 to produce a signal when
the coin has cleared the accept gate 1243 (1070) which is applied
to inhibit AND-gate 1239, deactivating the solenoid 1242, and is
also applied to reset all of the flip-flops by means omitted from
FIG. 12. This signal from the logic circuit 1238 is also applied to
the accumulator 1260 to cause it to accept the indication of
denomination.
FOURTH EMBODIMENT
FIG. 13 shows a coin selector 1300 having a mechanical arrangement
1310 of components similar to the mechanical arrangement 1010 of
coin selector 1000 of FIG. 12, except that only a single inductive
sensing station 1314 is utilized. The inductive sensing station
1314 may comprise a single inductor such as the pot core inductor
200 shown in FIGS. 5 and 6, or a pair of inductors on opposite
sides of the coin passageway as described with respect to FIG. 12.
The inductive sensing station 1314 is connected in a multileg
bridge circuit 1320, similar to the bridges shown in FIG. 7 or FIG.
11, in which the station 1314 and resistor 1326 comprise the common
leg of the bridge 1320. Unlike the previously described bridge
circuits, however, the oscillator input signal to the bridge 1320
is an AC coupled high frequency signal from HF oscillator 1311 and
an AC coupled lower frequency signal from LF oscillator 1312 which
is connected in parallel with HF oscillator 1311. Thus both a HF
and a LF signal are concurrently applied to the same inductive
sensing station 1314. The LF leg of the bridge 1320, comprising
resistor 1331, capacitor 1332, variable capacitor 1333, resistor
1335 and variable resistor 1336, is tuned by adjustment of the
component values so that the bridge will be balanced with respect
to the LF component of the input signal when a genuine coin of a
particular denomination is directly adjacent the inductive sensing
station 1314. The output signal from this LF leg passes through a
filter 1336, which blocks the HF component of the signal, to a
differential amplifier or comparator 1337 producing an output
signal which is rectified by diode rectifier 1338 and converted to
a digital signal by limiting amplifier 1339 for use by subsequent
logic circuitry 1350 in a manner as is described with respect to
FIG. 7 or FIGS. 9 and 11. Similarly, the HF leg of the bridge 1320,
comprising resistor 1341, capacitor 1342, variable capacitor 1343,
resistor 1344 and variable resistor 1345 is tuned for a balance of
the HF component of the input signal when the same coin is in the
described position. The output signal from this HF leg passes
through a filter 1346, which blocks the LF component of the signal,
to a comparator 1347 producing an output signal which is rectified
by diode rectifier 1348 and converted to a digital signal by
limiting amplifier 1349 for subsequent use by logic circuitry 1350
in a similar fashion to the digital signal desired from the LF leg
of the bridge 1320. When the logic circuitry 1350 receives
concurrent signals indicative of an acceptable coin from the LF and
HF comparators 1337 and 1347 for the same denomination, it produces
a signal indicative of the acceptability of the coin and of its
denomination.
It will be readily apparent that a coin selector such as coin
selector 1300 can be constructed for a plurality of denominations
of coins by providing additional legs on the bridge 1320. As an
alternative to AC coupling of the two oscillators 1311 and 1312 in
parallel and using a single bridge for both high and low frequency
tests; a separate HF and LF bridge can be used, each having a
separate inductor winding or windings on common inductor core or
cores.
FIFTH EMBODIMENT
A coin selector 310 formed in accordance with the present invention
and employing digital frequency identification techniques is shown
in FIG. 8. The differences between this coin selector and the coin
selectors previously described are in the electric circuit. Like
the circuit of FIG. 4, this circuit employs four oscillators 380,
384, 386 and 388, one in connection with each of the four inductors
372, 374, 376 and 378. The mechanical structure and location of
inductors 372, 374, 376 and 378 may be the same as those shown in
FIGS. 1 and 2 or FIG. 3; however, the method and apparatus
described below may be readily adapted to other embodiments. Each
of the oscillators normally oscillates at its idle frequency in the
absence of conductive objects in the vicinity of the associated
inductor. The frequency changes when a conductive object is in the
circuitry of its associated inductor. A clock 450 generates pulses
at a rate selected for example, in the range of 300 to 400 pulses
per second, each pulse being employed to trigger on the monostable
multivibrator (or "one shot") 451 for a precise period of 2
milliseconds.
The output of monostable 451 is applied to one input of each of the
AND gates 400, 401, 402 and 403. The outputs of the oscillators
380, 384 386 and 388 are connected to another input of their
respective AND gates 400, 401, 402, 403. Each of the four outputs
of a conventional two-stage counter 452, is connected to the third
input of one of the gates 400, 401, 402 and 403. The counter 452,
the input of which is connected to the clock 450 output, cyclically
produces one output pulse on each output for every four clock
pulses; the duration of each such output pulse from the counter 452
being approximately the period between clock pulses, which is
longer than the period of the output pulse of the monostable
451.
When a pulse from the counter 452 is applied to one of the AND
gates, for example gate 400, the gate will be activated during the
precision period established by the pulse from the monostable 451,
permitting the output pulses from the oscillator 380 to pass
through the gate 400. Similarly gates 401, 402 and 403 pass pulses
from their respective oscillators 384, 386 and 388 when activated
by both a pulse from the monostable 451 and the two-stage counter
452.
The outputs of the AND gates 401, 402 and 403 are applied to the
inputs of OR gate 404, the output of which is applied to the input
of frequency divider 405 which divides the pulse rate of signals
received from gate 404 by a factor of 16. The purpose of this
divider is to simplify the use of a single multistage counter 407
for counting both the high frequency outputs of oscillators 384,
386 and 388 and the low frequency output of oscillator 380. The
output signals from AND gate 400, which is associated with
oscillator 380, and the output signals from divider 405 are
connected to OR gate 406 and thence are applied to the multistage
counter 407.
The parallel output of the counter 407 is connected to a number of
decoders 420 through 429; one being shown here for each item to be
decoded, although in some practical devices it will be possible to
use a single decoder for more than one function when the number to
be decoded is significant in more than one way. The functions of
the decoders are for the lower and upper limit counts respectively
of the various tests as follows: 5.cent. bulk 420 and 421, 10 and
25.cent. bulk 422 and 433, 5.cent. high frequency 424 and 425,
10.cent. high frequency 426 and 427, and 25.cent. high frequency
428 and 429. The output of each of the lower limit decoders in 420,
422, 424, 426 and 428 is connected to the set input of its
respective flip-flop 430, 432, 434, 436 or 438. When the count for
a particular lower limit decoder is reached in the counter 407, the
flip-flop associated with that decoder will be set. The outputs of
each of the upper limit decoders 421, 423, 425, 427 and 429 are
connected to one input of its respective OR gate 431, 433, 435, 437
or 439; the output of which is connected to the reset input of
respective flip-flop 430, 432, 434, 436 or 438. When the count for
a particular upper limit decoder is reached the associated
flip-flop will be reset. At the conclusion of each counting period,
determined by the length of the pulse from one shot 451, a short
duration pulse on lead 498 is applied to one input of each of the
AND gates 440, 442, 444, 446 and 448. The other inputs of each of
these gates are connected to the outputs of flip-flops 430, 432,
434, 436 and 438 respectively. If any of these flip-flops have been
set and not reset during the preceding sampling period, an output
signal will be applied to an input of one of the gates 440, 442,
444, 446 or 448. The pulse which is then produced at the output of
the gate will increase the count by 1 in the associated two-stage
counter 441, 443, 445, 447 or 449. The pulse on lead 498 is also
applied to the reset input of counter 407, resetting it to starting
condition, and after a delay caused by delay cicuit 499 the pulse
is applied via OR gates 431, 433, 435, 437 and 439 to reset
flip-flops 430, 432, 434, 436 and 438.
The outputs of the two-stage counters 441, 443, 445, 447 and 449
are each connected to one or more of the AND gates 454, 456 and 458
which are associated with 5-cent, 10-cent and 25-cent pieces
respectively. The inputs of AND gate 454 include the outputs of
counters 441 and 445; the inputs of gate 456 include the outputs of
counter 443 and 447; and the inputs of gate 458 include the outputs
of counters 443 and 449. The third input of each of the AND gates
454, 456 and 458 is the previously described lead 498. When one of
the two-stage counters 441, 443, 445, 447 or 449 has received four
pulses from its input AND gate, that counter produces an output
pulse indicating that the associated oscillator has been operating
at the frequency indicative of an acceptable coin for four
inspections. When all three inputs of one of the AND gates 454, 456
or 458 concurrently receive a signal, that gate produces an output
pulse to the accumulator 410 indicating the presence of an
acceptable coin of its associated denomination.
* * * * *