Frequency Lock Loop Employing A Gated Frequency Difference Detector

Abstract

This invention relates to a gated frequency difference detector for use in a frequency lock loop. The gated frequency difference detector consists of a dual outut hybrid quadrature mixer, two parallel video signal processing channels, a digital phase/frequency detector, a digital scaler and a digital-to-analog converter. The difference is frequency between the RF input and the output of a local oscillator is measured. Two orthogonal frequency difference outputs are first generated one of which either leads or lags the other depending on the sense of the difference. Signals are then bandwidth limited and amplified in two video channels and converted to logic levels. The phase and frequency are finally digitally detected and processed to generate a bipolar voltage proportional to the magnitude and sense of the frequency difference.

Description

BACKGROUND OF THE INVENTION

This invention relates to a frequency lock loop circuit employing a gated frequency difference detector.

It has been found that the well-known phase lock loop circuit requires a limiter to maintain the loop gain constant. The phase detector output is the product of both the input amplitude and the sine of the phase angle. The above-mentioned limiter maintains the input amplitude constant for varying input RF levels and in this way keeps the loop gain constant. This limiter is usually very costly and physically very large.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a circuit which avoids the above-mentioned disadvantages and therefore eliminate the need for an RF limiter.

According to a broad aspect of the invention there is provided a gated frequency detector for a frequency lock loop circuit comprising a first source of a pulsed frequency input signal, a second source of a variable frequency reference signal, a third source of a control gate pulse synchronous with said first source, first means coupled to said second source for generating first and second phase quadrature frequency difference outputs, means coupled to said first and second outputs for detecting the frequency difference between said first and second outputs and second means coupled to said means for detecting for generating a DC voltage proportional to said frequency difference, said DC voltage applied to said second source for varying the output of said second source.

The above and other objects of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a functional block diagram of a frequency lock loop circuit employing a gated frequency difference detector according to the invention;

FIGS. 2a and 2b are curves illustrating the video and digital processing steps carried out in conjunction with the block diagram of FIG. 1;

FIG. 3 is a logic diagram of the digital phase/frequency detector employed in the block diagram of FIG. 1; and

FIG. 4 is a composite drawing illustrating how frequency difference count varies as a function of starting phase for a constant difference frequency .

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to FIG. 1, the gated frequency difference detector consists of a dual output hybrid quadrature mixer 1, two parallel video signal processing channels 2 and 3, a digital phase/frequency detector 4, and up/down counter 5, a scaler 6 and a digital-to-analog converter 7. A separate pulse detector circuit 18 operates in parallel with the video and digital phase/frequency processing channel from the two bandwidth limited outputs of the quadrature mixer and consists of combined positive and negative threshold detectors similar to 8 and 9. The RF input consists of high frequency pulses, and a voltage control oscillator 10 supplies CW to power divider 11. The output of the frequency difference detector is a voltage proportional to the frequency difference during the RF pulses and of a polarity which is determined by the sense of the frequency difference.

Hybrid quadrature mixer 1 generates two orthogonal difference frequency outputs A and B, one of which is either leading or lagging the other depending on the sense of the frequency difference between the RF input (F.sub.IN) and the output of voltage controlled oscillator 10 (F.sub.LO). Outputs A and B are bandwidth limited in filters 12 and 13 which determine the system selectivity and interference rejection. The outputs of filters 12 and 13 are then amplified in video amplifiers 14 and 15. The outputs of video amplifiers 14 and 15 feed threshold detector 8 and threshold detector 9 respectively which are designed to supply outputs which are standard logic levels.

Each threshold detector detects a signal which is above a first predetermined threshold and below a second predetermined threshold. Therefore, threshold detector 8 supplies two inputs to digital phase/frequency detector 4, and threshold detector 9 supplies two inputs to digital phase/frequency detector 4. Digital phase/frequency detector 4 detects the unique order of input logic combinations for a lead or lag condition represented by the outputs of threshold detectors 8 and 9.

The output of digital phase/frequency detector 4 is a pulse in real time for every half cycle of the frequency of the two inputs, each from one of the threshold detectors.

Digital phase/frequency detector 4 has three outputs. One output is applied to the up input of binary up/down counter 5 if a lead condition exists and a second is applied to the down input if a lag condition exists. A third output indicates a lead or lag condition. The output of binary up/down 5 is a parallel binary number and represents the total of 180.degree. phase increments of lag or lead between the RF carrier input and the voltage control oscillator input over the duration of the RF carrier input pulse. Since two 180.degree. increments make a cycle, this number can also be expressed as the product of twice the average frequency difference times the pulse width, 2.DELTA.f.tau.. The parallel output of counter 5 is applied to a digital scaling circuit 6 where it is scaled by a term proportional to the inverse of the RF carrier pulse width .tau.. This cancels the pulse width term of the counter output expression leaving only the 2.DELTA.f term.

The count in the counter is held until just before the receipt of the next RF pulse at which time it is a reset via the leading edge of the gate reset pulse on line 16. The reset pulses are derived using a predictive process similar to range gating from the input rf pulses. However, this does not represent a part of the invention and a further discussion is not deemed necessary. This eliminates detection of all pulses not synchronous with the gate reset pulse.

The output of scaler 6 is in effect a sample and hold measurement of the frequency difference. The scaling is accomplished by digitally shifting the binary point in steps to cover the width of the RF input pulses. Shifting may be accomplished by applying the outputs of counter 5 to a plurality of serially cascaded 4-line to 1-line data selectors of the type manufactured by Texas Instruments, Inc. bearing Part Nos. SN54153 and SN74153. Each of the Texas Instruments circuits comprises two 4 to 1 data selectors containing data input terminals and terminals to which external control may be coupled. Under the control of pulse width decode 19, scaler 6 comprising the above identified devices has the capability of shifting the binary point of the output of counter 5 from zero to four places, depending on the output of pulse width decode 19. This capability is completely provided for by the above identified TI circuits. The output of digital scaling circuit 6 is applied to a bipolar digital-to-analog converter 7 to generate a voltage which is the input to the analog loop integrator 17. The sense output of the digital phase/frequency detector controls the sense of the output of D/A converter 7 to make it either positive or negative.

FIGS. 2a and 2b illustrate the video and digital processing steps of the two orthogonal signals from IF quadrature mixer 1, which generates a net count in up/down counter 5. The curves shown in FIG. 2a correspond to a situation where the frequency of the local oscillator is greater than the frequency of the RF input for arbitrarily chosen frequency difference and pulse width of 2.DELTA.f.tau.=6 and initial starting phase of 0.degree.. Output B then corresponds to sin 2.pi.(f.sub.LO - f.sub.IN) t + 0.degree. and lags output A in phase by 90.degree.. FIG. 2b corresponds to the situation where the frequency of the local oscillator is less than the frequency of the RF input. In this case, output B corresponds to -sin 2.pi.(f.sub.LO - f.sub.IN) t + 0.degree. and leads output A in phase by 90.degree..

Lines a and b of FIGS. 2a and 2b show the outputs A and B for the two possible situations described above, and also shows the positive and negative thresholds which are detected by threshold detectors 8 and 9. On lines c, d, e and f of FIGS. 2a and 2b are shown curves which correspond to the outputs c, d, e and f of threshold detectors 8 and 9. From these outputs it is easy to see how the combination codes which are input to digital phase/frequency detector 4 are constructed. The codes are shown in FIGS. 2a and 2b for the duration of time for which they exist. For example, between time t.sub.1 and t.sub.2, output c is high, output d is low, output e is high and output f is low resulting in a code 1010. Because FIG. 2a corresponds to a situation where the frequency of the voltage control oscillator is greater than the frequency of the RF input, and output will appear only on the up output of digital phase/frequency detector 4 and no output will appear on the down output. This is shown in lines g and h of FIG. 2. It should be noted that the opposite situation occurs in FIG. 2b where the frequency of the voltage controlled oscillator is less than the frequency of the RF input.

In the example shown in FIGS. 2a and 2b, the waveforms are drawn for a normalized condition of 2.DELTA.f.tau. equal to six half cycles, or three cycles. Thys, if .tau., the RF pulse width, were 1 microsecond, then the difference frequency, .DELTA.f would be 3 MHz. Normalization is accomplished by detecting the filtered orthogonal outputs of filters 12 and 13 in reference pulse detector 18, combining these outputs to form a single pulse, measuring its pulse width in pulse width decode 19 and applying a signal to scaler 6.

Referring again to FIGS. 2a and 2b, the trigonometric waveforms are shown for an arbitrarily chosen initial phase at the start of the RF pulse of 0.degree.. Since there is no phase correlation between the voltage controlled oscillator frequency and the RF input frequency, this initial phase will be random from pulse to pulse. This random initial phase and also the random phase of cut off at time t = .tau. results in a variation of the net count from pulse to pulse of count for the same frequency difference. The relationship of the threshold levels to the peak signal level in lines a and b of FIGS. 2a and 2b are not drawn to scale but are illustrative of how the threshold is set above the peak noise level and also as close to the zero crossing of the signal as possible.

Digital phase/frequency detector 4 operates from the logic level outputs of each of the threshold detectors. One implementation of a digital phase/frequency detector is shown in FIG. 3. It consists of a one of four decoder 25 comprising gates 26, 27, 28 and 29 to decode the four different combinations of inputs, two prior state memory flip-flops 30 and 31, two AND/OR circuits 32 and 33 to generate the up output or the down output, inverters 34 and 35, and reset unit 36 comprising gates 37 and 38 which generates a reset signal for the prior state flip-flops after an "up" or "down" signal has been generated. Block 39 in FIG. 3 represents the first stage of counter 5 comprised of emitter-coupled logic, and block 40 represents an emitter-coupled logic (ECL) to transistor-transistor logic (TTL) converter to which the outputs of flip-flops 41 and 42 are coupled. Converter 40 would be necessary if the remaining stages of counter 5 are comprised of TTL logic. The input combination code of the four threshold detector outputs as shown in FIG. 2, is sorted by the decoder into one or none of four outputs.

The four states which generate decoder outputs are the four shown containing combinations of two ones. The four logical zeros in the transitional states contain only one logical one (not shown in FIG. 2) result in no output. Comparing the sequence of these states for the two conditions of of f.sub.LO >f.sub.IN and f.sub.LO <f.sub.IN it is seen that for the f.sub.LO >f.sub.IN condition, a 0110 state is followed by a 0101 state and a 1001 state is followed by a 1010 state. For the condition f.sub.LO LOf.sub.IN, a 0110 state is followed by a 1010 state and a 1001 state is followed by a 0101 state. The 0110 state is used to set one of the memory flip-flops and the 1001 state is used to set the other. The flip-flops are crossed coupled so that the setting of one will clear the other if it has been set from a prior state. The outputs of the two flip-flops and AND'ed with the 1010 and 0101 states, and pairs of the AND outputs are OR'ed to generate either an up output or a down output as shown in FIGS. 1 and 3. In FIG. 3, the appearance of an output also clears the flip-flops to prevent any possibility of subsequent erroneous outputs.

Referring to FIG. 4, there is shown a composite drawing showing how both the count varies as a function of starting phase for a constant difference frequency, i.e., 2.DELTA.f .tau. is a constant, and how the count approaches zero as the difference frequency approaches zero. The drawing shows only the case where the frequency of the voltage control oscillator is greater than the frequency of the RF input. However, for the case where the frequency of the voltage controlled oscillator is less than the frequency of the RF input, the drawing would be exactly the same except the cyclic variation of the pulse output and count would be shifted by 90.degree. and the pulse would appear on the down output of the digital phase/frequency detector. The code input was transcribed from the input combination code shown in FIG. 2 for f.sub.LO greater than f.sub.IN starting at the designated phase and covering the number of decoder states prescribed by the product of 2.DELTA.f.tau.. Thus, if 2.DELTA.f.tau. equals 11/2, this would be three-fourths of a cycle of the difference frequency and, since each decoder state covers one-fourth of a cycle, .tau. would cover a span equal to three complete states.

The figure shows how the time in each state varies as starting phases vary. For the example of 2.DELTA.f.tau. equals 11/2 and 0.degree.<.theta..sub.I <90.degree., if .theta..sub.i were 0.degree. the two center states would move to the right and the code sequence would be 0000, 1010, 0110, 0101 and 0000. If .theta..sub.I were 45.degree., it would be as shown in the diagram, and the time in the 1010 state and 1001 state would correspond to only one-eighth of the cycle of the difference frequency. If .theta..sub.I were 90.degree., the two center states would move to the left and the sequence would drop the first state of 1010 and the 1001 state at the end would correspond to a time of one-fourth of a cycle of the difference frequency. For all initial phases of 0.degree. to 90.degree. the UP output pulse would be as shown. Moving on to 90.degree.<.theta..sub.I <180.degree., if .theta..sub.I is just slightly greater than 90.degree., the width of the second output pulse would be very small. If .theta..sub.I is just slightly less than 180.degree., both output pulses would have a width of a full 1/4 cycle of the difference frequency, but the duration of 0110 state which is used to trigger the prior state memory flip-flop would be very small. The relationships for 180.degree. to 270.degree. are the same as described for 0.degree. to 90.degree.. The relationships for 270.degree. to 360.degree. are the same as described for 90.degree. to 180.degree.. The average count is the sum of the counts divided by the portions of a cycle of starting phase over which they appear.

As is obvious, FIG. 4 represents an idealized system. There are no differential delays of finite threshold levels to reduce any of the decoder output pulse widths from one-fourth of the width of a cycle. Also, a count can be registered to a vanishly small segmented decoder stage. Under this condition, the average net count is exactly equal to the product of 2.DELTA.f.tau.. For this same example, 2.DELTA.f.tau. = 11/2, the effect of a finite time should trigger the prior state flip-flop and the bit 1 counter input flip-flop is to make the two portions of a cycle of starting phase over which the count is 2 to less than 90.degree. so that the average count will be less than the limit of 11/2 but never less than 1. The effect of differential delays will have no effect on the average count if the frequency .DELTA.f is less than the maximum difference frequency. The effect of the differential delay is to shift the cyclic variations of the pulse output in count by something less than 90.degree..

It should be clear that the boxes shown in the block diagram of FIG. 1 are standard and well known elements, and that their implementation is left to the choice of the designer.

It is to be understood that the foregoing description of specific examples of this invention is made by way of example only and is not to be considered as a limitation on its scope.

Claims

1. A gated frequency detector for a frequency lock loop circuit comprising:

a first source of a pulsed input signal;

a second source of a variable frequency reference signal;

first means coupled to said first and second source for generating first and second phase quadrature frequency difference outputs;

means coupled to said first and second outputs for detecting the frequency difference between said first and second sources, said detecting means comprising

a first threshold detector having first and second outputs, said first output being a logical pulse output which is high when said first phase quadrature frequency difference output is above a first predetermined threshold and said second output being a logical pulse output which is high when said first phase quadrature frequency difference output is below a second predetermined threshold;

a second threshold detector having first and second outputs, said first output being a logical pulsed output which is high when said second phase quadrature frequency difference output is above said first threshold and said second output is a logical pulse output which is high when said second phase quadrature frequency difference output is below said second threshold;

a digital phase frequency detector coupled to the output of said first and second threshold detectors for generating a first pulse signal during the duration of said input pulse which corresponds to said frequency difference and a second signal which corresponds to the sense of said frequency difference; counting means coupled to said first pulsed signal for counting the number of pulses;

second means coupled to said means for detecting for generating a DC voltage proportional to said frequency difference, said DC voltage applied to said second source for varying the output of said second source; and

a third source of a control gate pulse having an output coupled to said second means and synchronous with said first source for enabling and

2. A gated frequency detector according to claim 1 wherein said first means includes:

a 90.degree. phase shifter coupled to said first source;

a first mixer having inputs coupled to said first source and said second source and generating at its output said first phase quadrature difference frequency output; and

a second mixer having inputs coupled to said second source and the output of said 90.degree. phase shifter for generating at its output said second

3. A gated frequency detector according to claim 1 wherein said second source includes:

an integrator having as its input said DC voltage; and

4. A gated frequency detector according to claim 3 further including:

a first low pass filter coupled to said first phase quadrature signal; and

a first video amplifier coupled to the output of said first low pass

5. A gated frequency detector according to claim 4 further including:

a second low pass filter coupled to said second phase quadrature output; and

a second video amplifier coupled to the output of said second low pass

6. A gated frequency detector according to claim 5 further including:

a pulse width decoder for measuring the width of the input pulse; and

a scaler coupled to the output of said pulse width decoder and said binary counter for scaling the output of said binary counter by a term proportional to the inverse of the input pulse width.