Device For Carrying Out Two-dimensional Interpolation In Conjunction With A Fixed Word Store

Abstract

A device for use with a fixed word store for multidimensional interpolation of function values not stored in the store by adding stored functional support values which surround the desired value on a coordinate basis. Analog/digital converters and digital/analog converters cause analog signals to be received and emitted by the device which otherwise operates in a purely digital mode. As used with an internal combustion engine two fixed value stores may be rendered effective in separate calculating cycles to control respective engine control functions such as ignition and fuel injection.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a device for carrying out multidimensional interpolation in conjunction with a fixed word store, and more particularly to a device for solving the problem of assigning values Z to all possible combinations of input values x and y, wherein Z is a function of x and y.

2. Description of the Prior Art

Interpolation devices are well known in the art. One such device is described in the publication Electronics, Sept. 11, 1972 at Pages 121-125 wherein an assignment is carried by a fixed word store in which the values x and y are input as addresses and wherein the value Z is stored in associated storage positions. The capacity of such a fixed word store is kept as low as possible in that a storage position is provided in the fixed word store only for a specific part of all of the possible combinations of x and y and that the combinations of x and y for which no storage position is provided, approximated values are determined by interpolation from the four adjacent support values for which a storage position is provided in the fixed word store.

The interpolation is carried out, in this particular prior art structure, in analog form.

A disadvantage of such a device consists in the fact that the analog technique requires adjustment and is not well suited for large scale integration.

SUMMARY OF THE INVENTION

The object of the present invention is to provide a device, as is generally described in the introductory portion of this specification, by means of which the aforementioned problem may be solved, in particular with a very low outlay in components.

According to the invention, the foregoing object is achieved in an interpolation device in that for the interpolation of digital input words x.sub.o, y.sub.o, in each case the higher value bits MSB (x.sub.o) and MSB (y.sub.o ) are utilized to characterize the support point with the next lower abscissa and ordinate, respectively, and the lower value bits LSB (x.sub.o) and LSB (y.sub.o) are employed for interpolation between the four adjacent support values. A selector circuit is in each case provided with the aid of which the higher value bits of x.sub.o and y.sub.o are fed, as addresses, to the fixed word store. The selector circuits may be controlled, in each case, by one electric control signal in such a manner that the higher value bits are optionally fed direct to the fixed word store, or that the number represented by these bits is, in each case, increased by 1 so that with the aid of the control signals, each of the four adjacent support values may be operated.

A counter is provided which contains as many bits as the number of low value bits of the two input words together. The counter is operated through all of its positions consecutively in a calculating cycle, and for each input word there is provided a test circuit which compare the numbers represented by the low value bits of the input words x.sub.o and y.sub.o with the numbers .xi. and .eta. represented by the assigned bits of the counter. Whenever a number represented by the count is higher than the number represented by the low value bits of an input word, the relevant selector circuit is operated in such a manner that the higher value bits (MSB (x.sub.o) and MSB (y.sub.o) respectively, of the input word are fed directly to the fixed word store, and whenever a number represented by the count is lower than the number represented by the low value bits of the input word, the number represented by the higher value bits of the input word is increased by 1 and is thus fed to the fixed word store.

An adder circuit is also provided which, with the aid of a register which is cleared at the beginning of a calculating cycle, adds up the individual function values Z present at the output of the fixed word store when each of the counts is passed through, wherein the addition may be controlled by a control component which ensures that there is synchronization between the operation of the counter and the transfer of the output signal of the adder circuit to the register. When the counter is passed through all of its counts, the interpolation value is contained in the register.

An essential advantage of a device constructed in accordance with the invention results from the fact that digital techniques are used, and that consequently such a device is suited for large scale integration. Accordingly, and as a consequence of the simplified structure, a device constructed in accordance with the invention contains only relatively few digital components.

Preferably, such a device is utilized when it is possible to accept a longer calculating duration--a result of the simplicity of the structure.

Advantageously, the device constructed in accordance with the invention is suitable for use in all cases in which function values of two variables are stored at a low storage outlay.

A device constructed in accordance with the invention is preferably utilized for measuring and control purposes. Advantageously, such a device may be utilized to control an internal combustion engine in which a value, e.g. the gasoline injection duration Z, is controlled in dependence upon two other values, e.g. the gas pedal positions x and the speed y of the motor.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects, features and advantages of the invention, its organization, construction and operation will be best understood from the following detailed description of a preferred embodiment of the invention, taken in conjunction with the accompanying drawings, on which:

FIG. 1 is a schematic illustration, in block circuit form, of a device constructed in accordance with the invention;

FIG. 2 illustrates the input values of such a device represented in a coordinate system;

FIG. 3 is a schematic block diagram illustration of a device constructed in accordance with the invention for use in controlling internal combustion engines; and

FIG. 4 is a block circuit diagram which schematically illustrates an interpolation device constructed in accordance with the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIGS. 1 and 2, a device constructed in accordance with the invention, and the mode of operation thereof, receives analog input words x.sub.o ' and y.sub.o ' at a pair of input converters 29 and 30 which convert the analog input words into equivalent digital values x.sub.o and y.sub.o. The higher value bits of the digital values x.sub.o and y.sub.o are referenced MSB (x.sub.o) and MSB (y.sub.o) and the lower value bits LSB (x.sub.o) and LSB (y.sub.o) in FIG. 1, where MSB signifies the "most significant bit" and LSB signifies the "least significant bit." A value Z is, in each case, stored in a fixed word store 24 for a number of all the possible combinations of x.sub.o and y.sub.o. In order to keep the capacity of the store small, a storage position is not provided for all the possible combinations of x.sub.o and y.sub.o. The function values of combinations of x.sub.o and y.sub.o for which no storage position is provided are calculated by a two-dimensional interpolation of four adjacent support values for which storage positions are provided in the store.

In FIG. 2, four support values Z (n,m), Z (n, m+1), Z (n+1, m), and Z (n+1, m+1) are illustrated. A value Z.sub.o (x.sub.o, y.sub.o) for which no storage position is provided in the fixed word store 24 is also entered in the diagram. For the interpolation of the value Z.sub.o from the input words x.sub.o and y.sub.o, the higher value bits MSB (x.sub.o) and MSB (y.sub.o) are fed, by way of a selector circuit 23 and 25, respectively, as addresses to the fixed word store 24. The selector circuits 23 and 25 may be controlled by electric control signals in such a manner that the higher value bits MSB (x.sub.o ) and MSB (y.sub.o) can be optionally fed directly to the fixed word store, or that the number represented by these bits is increased by 1. Therefore, the storage position of each of the four support values adjacent to x.sub.o, y.sub.o may be operated with the aid of the electric control signals.

At the beginning of each calculating cycle, a counter 28 is started. The counter 28 possesses as many bits as the number of the low value bits of both input words taken together. When the counter is started, it runs through all of its positions represented by .xi., .eta., consecutively in a calculating cycle. In accordance with its position, all of the combination values from .xi. 1 to .xi. a and .eta. 1 to .eta. b are consecutively produced at its outputs. These values .xi. and .eta. are fed, together with the low value bits of the input word LSB (x.sub.o) and LSB (y.sub.o) to a test circuit 26 and a test circuit 27, respectively. The test circuits 26 and 27 compare the number represented by the low value bits of the input words x.sub.o and y.sub.o with the number .xi. and .eta. represented by the assigned bits of the counter 28. If the number .xi. and .eta. represented by the count is higher than the number LSB (x.sub.o) and LSB (y.sub.o) represented by the low value bits of the input words, the selector circuits 23 and 25 are controlled in such a manner that the higher value bits MSB (x.sub.o) and MSB (y.sub.o) of the input words are fed directly to the fixed word store 24. If, on the other hand, the number .xi. and .eta. represented by the count is lower than the number represented by the low value bits LSB (x.sub.o) and LSB (y.sub.o) of the input words, the test circuits 26 and 27 feed an electrical control signal to the selector circuits 23 and 25 which causes the number represented by the higher value bits of the input words to be increased by 1 in the selector circuits 23 and 25.

In the above described manner, with the aid of the electric control signals from the test circuits 26 and 27, it is possible to read out each of the four support values Z (n, m), Z (n, m+1), Z (n+1, m) and Z (n+1, m+1) which are adjacent to the position (x.sub.o, y.sub.o) from the fixed value store 24. The function values of the support points are available at the output of the fixed word store 24. With the aid of an adder circuit 22 and a register 221, the latter being cleared at the beginning of the calculating cycle, the function values Z which are produced with every count at the output of the fixed word store 24, are added. With each count .xi., .eta. in the area Fn, m the function value Z (n, m), with each count .xi., .eta. in the area Fn, m+1 the function value Z (n, m+1), with each count .xi., .eta. in the area Fn +1, m the function value Z (n+1, m), and with each count .xi., .eta. in the area Fn+1, m+1 the function value Z (n+1, m+1) are added.

A control component 31 connected to the counter 28 and to the register 221 ensures synchronization between switch-over of the counter and transfer of the output signal of the adder and aids in controlling addition. When the counter has run through all of its counts .xi. 1 to .xi. a, .eta. 1 to .eta. b, the register of the adder contains the interpolation value multiplied with F.

Z.sub.o = [Fn, m.sup.. Z(n,m)+Fn+1, m.sup.. Z(n+1, m)+Fn, m+1.sup.. Z(n, m+1)+ Fn+1, m+1.sup.. Z(n+1,m+1)]

wherein Fn, m, Fn+1, m, Fn, m+1 and Fn+1, m+1 are the areas illustrated in FIG. 2 or the number of possible counts in the relevant areas. F = Fn, m + Fn+1, m + Fn, m+1 + Fn+1, m+1

When the number of possible counts F is a power of 2, the value Z.sub.o is obtained from the final count of the register simply by an arithmetical shift.

The digital value Z.sub.o is converted by the converter 21 into an analog control value Z.sub.o '.

In accordance with the invention, the principle thereof may also be applied to more than two-dimensional interpolation. For example, for a three-dimensional interpolation of a function Z(x.sub.1, x.sub.2, x.sub.3), i.e., with the three input words x.sub.1, x.sub.2, x.sub.3, there must be provided three test circuits and three selector circuits and a counter having a number of outputs corresponding to the sum of the low value bits of the three input words.

The mode of operation of the individual test circuits and selector circuits, together with the counter, is in accordance with the mode of operation described in association with the two-dimensional interpolation. Instead of four, eight support values must be provided as permanently stored function values. The counter runs through all of the combinations of its three basic numbers. The interpolated function value is, in each case, produced by the addition of the relevant eight support values, the sum produced by the addition being divided by the volume. This is in accordance with the above expression for two-dimensional interpolation.

Referring to FIG. 3, the control of an internal combustion engine by means of a device constructed in accordance with the invention is illustrated. For example, an internal combustion engine 2 comprises a spark ignition engine with a waste gas pipe 3 and an air intake pipe 4. A crank shaft 5 drives a drive shaft which is not illustrated.

The air intake pipe 4 contains a throttle valve 8 which is mechanically coupled to a gas pedal 9 and may be adjusted by the gas pedal 9. Also arranged on the air intake pipe 4, between the throttle valve 8 and the internal combustion engine 2 is a magnet valve 13, which is provided as a device for injecting fuel into the air intake pipe 4. The magnet valve 13 is arranged in the vicinity of the throttle valve 8. The valve's fuel input is connected to a fuel pump 14 which pumps liquid fuel out of a tank 15 into a fuel supply line 13a to the magnet valve 13. In order to keep the pressure constant in the fuel supply line 13a, a pressure control device 16 is also connected to the fuel supply line 13a and allows fuel to flow back from the fuel supply line 13a into the tank 15 when the pressure in the line is exceeded.

The spark plugs of the internal combustion engine 2 are connected by way of an ignition distributor 18 to an electric ignition device 19.

The control terminal of the magnet valve 13 and the electronic ignition device 19 are connected to the digital/analog converter 21 of a device constructed in accordance with the invention. The analog/digital converter 29, which serves to accommodate the input word x.sub.o ', is connected to a scanner 23a which is arranged opposite the crankshaft 5 of the internal combustion engine 2. The scanner 23a emits a sequence of voltage pulses which are assigned in respect of their phase state to the upper dead centers of the internal combustion engine 2. It is apparent that the pulse frequency of this pulse sequence is proportional to the speed of the internal combustion engine.

The input word y.sub.o ' which corresponds to the position of the throttle valve 8 or gas pedal 9 is fed to the input of the analog/digital converter 30. The function values Z calculated from the input words x.sub.o ', y.sub.o ' are provided at the output of the fixed word store 24. If the instantaneous input words x.sub.o ' of the revolution duration of the internal combustion engine and/or y.sub.o ' of the gas pedal or throttle valve position are not equal to the discrete values of the revolution duration and/or the gas pedal or throttle valve position for which a storage position is provided in the fixed word store 24, then with the aid of the device in accordance with the invention, in the manner described above, a function value Z.sub.o associated with the instantaneous input words x.sub.o ' and y.sub.o ' is determined by two-dimensional interpolation from the four adjacent support values.

In the characteristic field illustrated in FIG. 2, for the example of the control of an internal combustion engine, the input words x.sub.n and x.sub.n +1 of the rotation duration are plotted on the abscissa, and the input words y.sub.m and y.sub.m.sub.+1 of the gas pedal and throttle valve position are plotted on the ordinate.

FIG. 4 schematically illustrates an interpolation circuit, realized with few digital components, for a device constructed in accordance with the invention as illustrated in FIG. 3. Each input word x.sub.o of the rotation duration consisting of low value and higher value bits, and each input word y.sub.o of the gas pedal and throttle valve position, which again consists of low value and higher value bits, are again assigned to an individual test circuit 26 and 27, respectively. Also, again individual selector circuits 23 and 25 are provided for respective input words. The counter 28 corresponds to the counter already described in association with FIG. 1.

FIG. 4 illustrates a flow control device 45 which feeds a resetting signal from its output 45b to the counter 28 and the register 221. This flow control or sequence control device 45 also emits transfer signals from its outputs 45c and 45d to the register 221 and to the digital/analog converter 21. The control device 45 is actuated by the request signal at the input 45a at the beginning of each calculating cycle. The control device 45 is fed by a pulse generator 46 which also feeds the counter 28 by way of a gate 47. The gate 47 is connected to the output 45e of the sequence control device 45 and its control is dependent upon the sequence control device 45 by which it is opened at the beginning of a calculating cycle so that the counter 28 sequentially passes through all of its counts.

The register 221 receives a transfer signal from the sequence control device 45 whenever the counter 28 has been stepped on by one count. The adder 22 adds the output value of the fixed word store 24 to the contents of the register 221 so that at the end of a calculating cycle, at the output of the adder 22, there is provided an item of information Z.sub.o (x.sub.o, y.sub.o) in accordance with the above interpolation formula, which information is fed into the digital/analog converter 21 as a result of a transfer signal from the sequence control device 45.

In FIG. 4, a broken line represents a further fixed word store which is connected in parallel to the fixed word store. The fixed word stores are individually referenced 24a and 24b and are connected to the outputs 45f and 45g of the sequence control device 45, and their control is dependent upon the sequence control device 45. During a calculating cycle, under the control of the sequence control device, the fixed word store 24a assigned to the one control valve e.g. the injection duration, is switched on, and during the following calculating cycle the fixed word store 24b assigned to the other control valve, e.g. the ignition time, is switched on alone.

The test circuits 26 and 27 can also be constructed from a digital comparator for each input word x.sub.o and y.sub.o, wherein the comparators are simultaneously fed with the number .xi. or .eta. which corresponds to the particular count and is assigned to the input word x.sub.o or y.sub.o, and with the low value bits LSB (x.sub.o) or LSB (y.sub.o) assigned to the input word x.sub.o or y.sub.o. The comparators emit at the output a zero when the comparison proves that .xi. is greater than LSB (x.sub.o) or .eta. is greater than LSB (y.sub.o), and emit a one when the comparison proves .xi. to be smaller than or equal to LSB (x.sub.o) or .eta. to be smaller than or equal to LSB (y.sub.o). For each selector circuit 23, 25 assigned to the input words there can be provided a respective digital adder, the adder assigned to the input words x.sub.o or y.sub.o being fed with the higher value bits MSB (x.sub.o) or MSB (y.sub.o) and with the bit present at the output of the comparator assigned to the input word x.sub.o or y.sub.o.

The following components may be employed in constructing an interpolation device in accordance with the present invention.

______________________________________ Fixed word store (24, 24a, 24b) INTEL 1302 INTEL 1602 Selector circuit (23, 25) TI SN 7483 Test circuit (26, 27) TI SN 7485 Counter (28) TI SN 7493 Adder circuit (22) TI SN 7483 Register (221) TI SN 7475 ______________________________________

Although I have described my invention by reference to particular illustrative embodiments thereof, many changes and modifications of the invention may become apparent to those skilled in the art without departing from the spirit and scope of the invention. I therefore intend to include within the patent warranted hereon all such changes and modifications as may reasonably and properly be included within the scope of my contribution to the art.

Claims

I claim:

1. A device for carrying out multi-dimensional interpolation in response to coordinate digital input words x.sub.o, y.sub.a each having higher value bits MSB (x.sub.o), MSB, (y.sub.o) which are used to characterize a support value with the next lower abscissa and ordinate, respectively, and lower value bits LSB (x.sub.o), LSB (y.sub.o) for use in interpolating between four adjacent support values; a fixed value store; a pair of selector circuits for receiving respective one of the digital input words and feeding the address inputs of said fixed value store in response to receipt of control signals, said selector circuits operable to optionally feed the number represented by the higher value bits directly to said store or to provide the digital number in each case increased by 1; a counter having as many bits as the number of lower value bits of said two input words together and operating consecutively through each counting position during a calculating cycle; a pair of test circuits for the respective input words x.sub.o, y.sub.o for comparing the low value bits of the respective words with numbers .xi. and .eta. represented by assigned bits of the counter and operable whenever a number represented by the count is higher than a number represented by the lower value bits of an input word to operate the respective selector circuits to feed the higher value bits MSB (x.sub.o), MSB (y.sub.o) directly to said fixed word store, and whenever a number represented by the count is less than the number represented by the lower value bits of an input word the number is increased by 1 and fed to said fixed word store; a register; an adder circuit connected to said fixed word store to add the individual function values therefrom and transfer the addition to said register which is erased at the beginning of a calculating cycle; and means for controlling said adder circuit and transfer of information to said register, the interpolated information being stored in said register upon completion of operation of said counter through all of its counting positions.

2. A device according to claim 1, comprising a digital comparator for each input word x.sub.o, and y.sub.o which simultaneously receives the number .xi. or .eta. corresponding to the particular count and assigned to the input word in the form of a multi-digit digital value, and the low value bits LSB (x.sub.o) or LSB (y.sub.o) assigned to the input words x.sub.o or y.sub.o and the comparator assigned to the input word x.sub.o or y.sub.o emits a zero at the output when .xi. is greater than LSB (x.sub.o) or .eta. is greater than LSB (y.sub.o), and emits a one when .xi. is smaller than or equal to LSB (x.sub.o) or .eta. is smaller than or equal to LSB (x.sub.o) and wherein each selector circuit has a respective digital adder, the adder assigned to the input word x.sub.o or y.sub.o being fed with the higher value bits MSB (x.sub.o), or MSB (y.sub.o) and the bit present at the output of the comparator assigned to the input word.

3. A device according to claim 1, comprising a pair of analog/digital converters connected to respective one of said selector circuits for receiving coordinate analog input words x.sub.o ', y.sub.o ' and converting the same to corresponding digital input words x.sub.o, y.sub.o.

4. A device according to claim 1, comprising a digital/analog converter connected to said adder circuit for converting the interpolation value to an analog control signal.

5. A device according to claim 3 for controlling an internal combustion engine having a rotating member and a movable control member wherein the analog input words x.sub.o ' and y.sub.o ' correspond to the rotation duration and control member positions, fuel injection means for said engine, a second fixed word store connected in parallel with the first-mentioned word store, said fixed word stores each operable to provide a respective control value for controlling the ignition time and duration of fuel injection calculated in separate calculating cycles in response to the analog input words, and means for operatively connecting the two parallel fixed word stores to said adder circuit during respective separate calculating cycles, and means connecting said adder circuit to said fuel injection and ignition means.

6. A device according to claim 4 for controlling an internal combustion engine having a rotating component, comprising an inductive scanner associated with the rotating component of the engine and connected to one of said analog/digital converters and operable to provide an input signal thereto representing revolution duration, a throttle valve for said engine connected to the other of said analog/digital converters and operable to supply a signal thereto indicative of the position of said throttle valve, an electronic ignition device connected to said digital/analog converter for controlling injection duration from the multi-dimensional interpolation.

7. A device according to claim 4 for controlling an internal combustion engine having a rotating component, comprising an inductive scanner associated with the rotating component of the engine and connected to one of said analog/digital converters and operable to provide an input signal thereto representing revolution duration, a throttle valve for said engine connected to the other of said analog/digital converters and operable to supply a signal thereto indicative of the position of said throttle valve, a magnet valve connected to said digital/analog converter for controlling injection duration in response to multi-dimensional interpolation.

8. A device according to claim 4 for controlling an internal combustion engine having a rotating component, comprising an inductive scanner associated with the rotating component of the engine and connected to one of said analog/digital converters and operable to provide an input signal thereto representing revolution duration, a throttle valve for said engine connected to the other of said analog/digital converters and operable to supply a signal thereto indicative of the position of said throttle valve, an electronic ignition device and a magnet valve connected to said digital/analog converter for controlling ignition and injection duration, and an additional fixed word store alternately connected in circuit with the first-mentioned store in separate calculating cycles for controlling said magnet valve and said ignition device, respectively.