U.S. patent number 3,859,634 [Application Number 05/300,770] was granted by the patent office on 1975-01-07 for digital lock system having electronic key card.
This patent grant is currently assigned to Arthur D. Little, Inc.. Invention is credited to John T. Fowler, Robert R. Perron.
United States Patent |
3,859,634 |
Perron , et al. |
January 7, 1975 |
DIGITAL LOCK SYSTEM HAVING ELECTRONIC KEY CARD
Abstract
An electronic lock system in which a coded data word is stored
in a key and, upon insertion of the key into a lock, compared with
a master code. A predetermined correspondence between the key code
and the master code causes the provision of an output signal for
actuation of the lock or other utilization apparatus. Lack of
correspondence between the key code and master code will not cause
production of the output signal and can be employed to cause
actuation of an alarm indication. Digital circuitry is employed in
both the key and lock and is configured to permit easy alteration
of the stored code to greatly enhance system security.
Inventors: |
Perron; Robert R. (Beverly,
MA), Fowler; John T. (Winthrop, MA) |
Assignee: |
Arthur D. Little, Inc.
(Cambridge, MA)
|
Family
ID: |
26830611 |
Appl.
No.: |
05/300,770 |
Filed: |
October 25, 1972 |
Related U.S. Patent Documents
|
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
Issue Date |
|
|
132671 |
Apr 9, 1971 |
|
|
|
|
Current U.S.
Class: |
235/382 |
Current CPC
Class: |
G07F
7/0866 (20130101); G07C 9/00309 (20130101); G07C
9/00857 (20130101); G07C 2009/00761 (20130101); G07C
9/00817 (20130101) |
Current International
Class: |
G07F
7/08 (20060101); G07C 9/00 (20060101); G11b
009/02 () |
Field of
Search: |
;340/149,149A,274,276,164R ;317/134 ;70/277 ;235/61.11 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Pitts; Harold I.
Attorney, Agent or Firm: Stein and Orman
Parent Case Text
RELATION TO OTHER APPLICATIONS
This application is a continuation-in-part of copending application
Ser. No. 132,671, filed Apr. 9, 1971, now abandoned in favor of
continuation application Ser. No. 273,529, filed July 20, 1972.
Claims
What is claimed is:
1. An electronic lock system operative in response to more than one
key code and comprising:
key means adapted for use with an associated lock means and having
a multistage electronic data memory operative to store an
electrically alterable multiple bit key code and means for
conveying said key code serially from said electronic data memory
to said lock means in response to a command signal;
lock means adapted for operation with said key means and
including
a multiple bit electronic data memory having at least two different
predetermined groups of bit positions for storing respective key
codes;
means for applying a key code from said key data memory to said
lock data memory for storage therein;
a least first and second decoder means each having a plurality of
inputs for receiving a respective key code defined by said
different predetermined groups of bit positions and each operative
to provide an output signal in response to receipt of said
respective key code; and
logic means for receiving said output signals and operative to
provide a utilization signal in response thereto.
2. An electronic lock system according to claim 1 wherein said lock
data memory is a shift register having different predetermined
groups of bit positions respectively coupled to the inputs of each
of said decoder means.
3. An electronic lock system according to claim 1 wherein said
means for coupling said key code from said key data memory to said
lock means includes;
means coupled to said key data memory for providing light signals
representing said key code; and
means operative in response to said light signals for providing
electrical signals representing said key code to said lock data
memory.
4. An electronic lock system comprising:
key means adapted for use with an associated lock means and having
an electronic data memory therein with a plurality of
interconnected stages operative to store a multiple bit key code
and means for coupling said key means to an associated lock means
by which said key code can be conveyed serially from said
electronic data memory in response to a command signal;
lock means adapted for operation with said key means and including
receptacle means for said key means in operative association
therewith;
an electronic data memory for storing a key code received from said
key data memory;
at least two decoder means each having a plurality of inputs
coupled to different predetermined bit positions of said lock data
memory and each operative to provide an output signal in response
to receipt of a respective code from said lock data memory
represented by corresponding bit positions of said lock data
memory; and
logic means operative in response to each of said output signals
from said decoder means to provide a utilization signal.
5. An electronic lock system comprising:
a key adapted for use with an associated lock and including
a first multistage electronic data memory each stage being
operative to store a respective bit of a multiple bit key code;
a second multistage electronic data memory each stage being
operative to store a respective bit of a multiple bit received
enable code;
comparator means coupled to said first and second data memories and
operative to compare said key code with said enable code and to
provide a command signal upon correspondence between said codes;
and
encoder means operative in response to said command signal to
provide a coded output signal;
a lock adapted for operation with said key and including
an electronic data memory for storing a multiple bit master
code;
means for receiving said coded output signal from said key;
means operative to compare said coded output signal with said
master code and to provide a signal indication upon receipt of a
coded output signal from said key corresponding to said master
code; and
logic means operative in response to said signal indication to
provide a utilization signal.
6. An electronic lock system according to claim 5 wherein said lock
includes means for providing said enable code to said second data
memory of said key.
7. For use in an electronic lock system wherein a lock includes a
data memory for storing a master code and logic means for comparing
said master code with a coded output signal received from a key and
for providing an output indication upon correspondence between said
master code and said key code, a key comprising:
a first multistage electronic data memory each stage being
operative to store a respective bit of a multiple bit key code;
a second multistage electronic data memory each stage being
operative to store a respective bit of a multiple bit received
enable code;
comparator means coupled to said first and second electronic data
memories and operative to compare said key code with said enable
code and to provide a command signal upon correspondence between
said codes; and
encoder means operative in response to said command signal to
provide said coded output signal to said lock.
8. An electronic lock system comprising:
a key adapted for use with an associated lock and including
decoder means operative to receive self-clocking data from said
lock and to provide in response thereto a clock signal and a
received data code;
a first multistage electronic data memory operative in response to
said clock signal to store said received data code therein;
a second multistage electronic data memory operative to store a
first key code;
comparator means for receiving said first key code and said
received data code and for providing a trigger signal upon
correspondence therebetween;
a third multistage electronic data memory operative to store a
second key code;
clock means operative in response to said trigger signal to provide
a second clock signal to said third memory to cause readout of the
second key code contained therein; and
encoder means operative in response to data from said third data
memory and to said second clock signal to provide a self-clocking
output code to said lock;
a lock adapted for operation with said key and including
an electronic data memory for storing a master code;
means for receiving said output code from said key; and
logic means operative to compare said output code with said master
code and to provide an output signal indication upon correspondence
between said output code and said master code.
9. An electronic lock system according to claim 8 wherein said
third electronic data memory is operative to retain the code stored
therein even after readout of said code.
10. An electronic lock system according to claim 8 wherein said
clock means includes
counter means operative in response to said second clock signal to
increment to a predetermined final count and to provide a stop
signal to said clock means to discontinue said second clock signal
after a predetermined number of counts.
11. An electronic lock system according to claim 10 including
gate means for coupling the code contained in said third electronic
data memory to said encoder means, said gate means being enabled by
the trigger signal from said comparator means.
12. In an electronic lock system which includes a key circuit
operative to store a key code, and a lock circuit operative to
receive said key code and to provide an output signal upon receipt
of a key code which corresponds with a master code stored in said
lock circuit, means for energizing said key circuit including
a transformer having a primary coil coupled to and physically
associated with said lock circuit and a secondary coil coupled to
and physically associated with said key circuit; and
rectifier means included in circuit between said secondary coil and
the power inputs of said key circuit for application of energizing
power to said key circuit.
13. The invention according to claim 12 including a battery
connected to the power inputs of said key circuit and operative to
provide power thereto in the absence of interconnection of said key
circuit with said lock circuit.
14. The invention according to claim 12 wherein said rectifier
means includes
first and second diodes each connected between a respective end of
said secondary coil and one power input of said key circuit;
and
filter means connected between said diodes and the power inputs of
said key circuit.
15. An electronic lock system comprising:
a key having a structural member adapted for coupling with an
associated lock;
an electronic data memory within said structural member and having
plural interconnected stages each operative to store a bit of a
multiple bit key code; and
means operative to provide light signals representing said key
code;
lock means adapted for operation with said key and including
a receptacle for receiving the structural member of said key;
means operative in response to said light signals to provide
corresponding electrical signals representing said key code;
and
logic circuitry receiving said corresponding electrical signals and
operative to compare said key code with a stored master code and to
provide an output indication upon correspondence between said key
code and master code.
Description
FIELD OF THE INVENTION
This invention relates to lock systems and more particularly to an
electronic lock system employing active digital electronic
circuitry in both the key and lock.
BACKGROUND OF THE INVENTION
Electronic locks have been proposed in which an electronic circuit
in a lock is energized to activate the lock by use of a key
containing circuitry cooperative with the lock circuit. The
circuitry employed in a key has generally been of a type in which a
plurality of coded interconnections is provided to appropriately
energize an associated lock circuit. Such key circuitry, however,
usually contains a fixed code which is alterable only be rewiring
of the key circuit. There is little versatility of coding in such
conventional systems. In addition, the configuration of the key
circuit can be ascertained by appropriate analysis and the code
thereby duplicated. As a further disadvantage, such keys usually
require a relatively large number of interconnections with the
lock, with attendant increase in system cost and complexity.
SUMMARY OF THE INVENTION
In accordance with the present invention, a highly reliable and
secure electronic lock system is provided in which active data
storage means are provided within a key containing a readily
alterable coded data word corresponding to a master code stored in
an associated lock circuit. Upon insertion of the key into the
lock, the data stored in the key is compared with a master code in
the lock, a predetermined correspondence therebetween causing
actuation of the lock. In the event that there is not proper
comparison between the master code and the key code, an alarm can
be actuated and the key can also be seized within the lock to
prevent its removal therefrom. By immediate actuation of an alarm
in the event of detection of one or more incorrect bits of the key
code, there is little opportunity to attempt duplication of the key
code, thus materially enhancing system security. Analysis of the
data storage circuitry within the key will not reveal the data code
stored therein and even if the stored data were read out by
interrogation of the key, the data can be selectively coded such
that it would be, in practice, substantially impossible to analyze
and decode the data content thereof.
In a typical embodiment of the invention, the key contains an
electronic data memory such as a multiple bit shift register or
read-only memory for storing the key code therein and is typically
of integrated circuit type having extremely low energy
requirements. Power can be provided by a small battery source
located within the key. Alternatively, the data memory can be of
the non-volatile type requiring no external power, in which case no
battery need be employed. Data provided between the key and lock is
preferably in serial form to minimize the number of
interconnections required between the key and the associated lock.
Various interconnection configurations are contemplated by the
invention. Two data connections can be provided, one for
transferring data from the key to the lock, and one for
transferring data from the lock back into the key. Or, a single
data line can be shared for bidirectional transmission. A clock
line can be provided depending upon whether a self clocking data
code is employed, and a ground connection is also usually employed.
Connection between the key and lock can be made by various well
known coupling means suited to particular system requirements, such
as electrical contact elements, or inductive, photoelectric or
other noncontacting coupling.
It will be appreciated that the invention is not limited to use in
actuating a lock as such, but is generally useful in security
systems wherein an output signal is applied to utilization
apparatus only upon the requisite comparison between a master code
and a key code. For example, the invention is useful to operate
many different key actuated devices in addition to locks, such as
electrical switches, identification apparatus and the like.
Moreover, the key can contain other data in addition to the key
code as may be desirable in particular instances. The key can, for
example, also contain data representing the identity of the key
holder, an account number or various other data to suit operational
requirements. Such additional data can be employed as part of the
decoding process to cause an output indication, or the additional
data can be separately decoded for distinct purposes, as
required.
DESCRIPTION OF THE DRAWINGS
The invention will be more fully understood from the following
detailed description taken in conjunction with the accompanying
drawings, in which:
FIG. 1 is a simplified block diagram representation of a lock
system according to the invention;
FIG. 2 is a block diagram of an alternative key circuit embodying
the invention;
FIG. 2A is a block diagram of a further key circuit embodying the
invention;
FIG. 3 is a partial block diagram of an alternative lock circuit
embodying the invention;
FIG. 4 is a block diagram of yet another lock circuit according to
the invention;
FIG. 5 is a more detailed block diagram of a lock system according
to the invention;
FIG. 6 is a block diagram of a self-clocking key circuit embodying
the invention;
FIG. 7 is a partial schematic and partial block diagram of a key
energizing technique according to the invention;
FIG. 8 is a pictorial view, partly in section, illustrating a
typical key configuration embodying the invention; and
FIG. 9 is a block diagram of a photoelectric coupling technique
useful in the invention.
DETAILED DESCRIPTION OF THE INVENTION
Referring to FIG. 1 there is shown an electronic key 10 having a
memory 12 powered by a suitable energy source such as a battery 14.
The memory is typically a shift register of the low power type
constructed by monolithic integrated circuit techniques and is,
therefore, of extremely small physical configuration capable of
being readily mounted in a small key member. The battery is
typically a low power mercury battery also adapted for mounting in
the key member and capable of energizing memory 12 for a long
period of time. The power requirements of an integrated circuit
shift register are sufficiently small that the effective life of
battery 14 is determined more from the shelf life thereof rather
than the power drain. The key 10 is cooperative with an electronic
lock 16 and is coupled thereto by three lines, labeled data out,
data in and clock. The data out line carries data from memory 12 to
the lock circuit, the data in line carries data from the lock
circuit back into memory 12, and the clock line carries clock
pulses for shifting of data in and out of memory 12. In actual
implementation, a ground line may also interconnect key 10 and lock
16.
The lock circuit 16 includes a data gate 18 connected to a memory
20, and operative to couple data from memory 12 to memory 20, and
to recirculate data from memory 12 back into memory 12 for
restorage of a key code therein. The memory 20 has an output
thereof coupled to a comparator 22 which also receives data from a
master code generator 24. The output of comparator 22 is connected
to logic circuitry 26 which provides a first output signal for
actuation of associated utilization means, and a second output
signal for providing an alarm indication in the event that an
improper key code is employed.
Memory 20 and associated components of the lock 16 can also be
typically implemented by integrated circuits. Timing of data from
the key to the lock circuit is accomplished by means of a clock 28
providing clock signals to memory 12 and to a control circuit 30
which governs operation of memory 20 and also provides master
timing signals to the lock system. An insertion detector 32 is
provided in the lock for sensing the presence of key 10 therein and
for providing, in response to key detection, a start signal to
clock 28 for initiation of the key identification process. As will
be described, the insertion detector 32 can also cause mechanical
clampling of the key within the lock to prevent its premature
withdrawal during the code recognition cycle and also to capture
the key in the event that an improper key code is detected.
In operation, a multiple bit data word specifying a key code is
stored in memory 12 representative of a unique key identity, this
code being identical to a master code provided by generator 24
located in the lock circuitry. The key code contained within memory
12 is compared with the master code, positive identity between the
two codss enabling actuation of the lock. Noncorrespondence between
one or more bits of the key code and the master code causes
actuation of an alarm, indicating an attempt to utilize an improper
key. Upon insertion of key 10 into lock 16, the presence of the key
as determined by insertion detector 32 cuases enabling of clock 28.
Clock pulses from clock 28 are applied to memory 12 and cause
readout of the data stored therein to data gate 18 and thence to
memory 20.
The data being shifted out of memory 12 is also recirculated via
data gate 18 back into memory 12 to reload the key code for
subsequent use. Upon loading of the data word into shift register
20, comparator 22 is operative to compare the data contents of
register 20 with that of master code generator 24 and to provide
output signals to logic 26 indicative of whether or not the coded
data from key 10 corresponds to the master code pattern. Comparison
of the key code with the master code can be accomplished on a bit
by bit basis or on the entire code word after it is shifted into
memory 20. If upon comparison between the master code and the key
code, there is correspondence of all bits therebetween, logic 26
provides an output signal to actuate the associated lock or other
utilization means.
It will be appreciated that the lock 16 can be associated with any
utilization means which is to be key operated, such as a locking
mechanism for a door, vault or the like, or electrical apparatus.
If there is a lack of correspondence between one or more bits of
the master code and the key code, logic 26 provides an alarm signal
indicative of an erroneous key code. The alarm signal can
immediately actuate an alarm indicator or can be employed with
suitable counting circuitry to permit a selected number of decoding
attempts before an alarm is actuated. Delayed alarm actuation is
useful, for example, to prevent a transient condition, such as
momentary contact loss, from causing an alarm.
For some purposes an alarm signal is not needed to indicate
detection of an erroneous key code, and in this event the logic
circuitry 26 will provide an output signal to the utilization means
if a proper key code is detected, and this output signal will not
be provided upon detection of an erroneous key code. The production
of an output signal indicative of an alarm condition is desirable,
however, for many purposes. The security of the present system is
considerably enhanced by the feature by which any attempt to employ
an incorrect key code will serve to actuate an alarm. There is thus
no opportunity to try different possible key codes in an attempt to
actuate the lock, as the first wrong code will cause an alarm
indication. It is possible to cause readout of data stored in
memory 12 to ascertain its data content and thereby reproduce the
key code. However, a key code can be employed as part of the data
in memory 12 such that interrogation thereof will not reveal the
key code. For example, data stored in memory 12 can be configured
such that the code itself is contained at predetermined bit
positions within a longer stored word and coding schemes can be
selected with are extremely difficult if not practically impossible
to decode. The length of the data word stored in memory 12 also
serves to enhance security of the system; for example, a 32 bit
memory permits 2.sup.32 possible coding combinations.
The necessary correspondence between the key and master codes
required to produce an output utilization signal is of course a
matter of choice to suit operational circumstances. For high
security, it will usually be desired to require exact
correspondence between a key code and master code to produce an
output signal. However, for many purposes a key code can be
considered correct even though some small numbers of bits are
different than the corresponding bits of the master code. In other
words, the key code need only be correct to an intended degree of
tolerance.
System security can be enhanced by use of a key which communicates
data to the lock circuit only upon receipt by the key of a proper
interrogation code. Such a technique is illustrated in FIG. 2 which
shows a first memory 34 coupled to a comparator 36 which, in turn,
is coupled to a second memory 38. Each of the memories 34 and 38
are typically integrated circuit shift registers as described
above. The memory 34 contains a predetermined code word which is
compared in comparator 36 with an enable code which can be provided
by the lock circuit. Upon detection by comparator 36 of
correspondence between the enable code and the code stored in
memory 34, a read command is provided to memory 38 to cause readout
of a different code stored in memory 38. The code word from memory
38 is operative to actuate the lock after correspondence is
established between this code and the master code stored in the
lock circuit, as described above.
Upon interrogation of the key by an enable code which does not
compare with the preprogrammed data in memory 34, comparator 36 can
provide an alarm signal to the associated lock circuit. An alarm
indication can also be provided, as above, upon non-identity
between the master code in the lock and the code from memory 38.
The technique of FIG. 2 thus affords a dual encoding arrangement
which is of a higher order of security than the coding arrangement
of FIG. 1. Additional levels of coding can also be readily provided
according to the principles of this invention since small, low
power digital circuitry can achieve the key function.
An alternative embodiment of the key circuitry of FIG. 2 is
depicted in FIG. 2A wherein the key contains a memory 35 operative
to receive the enable code and to convey this code to a comparator
37 which also receives a key code stored in memory 39. The output
of comparator 37 is connected to an encoder 41, the output of which
serves as the key output signal. Upon receipt of an enable code
which is of requisite identity to the key code, the comparator 37
provides a signal to encoder 41 which, in turn, provides a coded
output signal for application to the associated lock or other
utilization means. The signal from comparator 37 can itself be the
key output; however, in this latter instance the security of the
system is diminished as the noncoded comparator output signal may
be wrongfully duplicated.
In addition to storage in the key of a key identification code for
gaining access to the associated lock, the key can also contain
additional data representing the identity of the particular key, an
account number or the like. The system disclosed in FIG. 1 can be
modified as indicated in FIG. 3 to accommodate such additional
data. Referring to FIG. 3, data from a key is composed of a first
word representing the key code and a second word representing other
data such as a key number. This data is applied from the key to a
pair of memory stages. The key code word is stored in memory 20A
while the other identification code is stored in 20B. The key code
is compared with the master code in comparator 22 in the same
manner as described hereinabove.
The output of the comparator is applied to one input of an AND gate
23. The output of memory 20B is applied to a decoder 25, the output
of which is applied to the second input of AND gate 23. The code
processing cycle is governed by a counter 21 operative in response
to clock signals from clock 28, the counter providing a timing
sequence sufficient for loading data from the key into memories 20A
and 20B. Upon identification of the key code in comparator 22, an
output signal is provided by AND gate 23 for actuation of the lock.
Failure to detect a proper key code will prevent a lock actuation
output. In the embodiment of FIG. 3 failure to detect a proper code
in memory 20B will also prevent lock actuation. It is evident that
an output signal from decoder 25 representative of the additional
identity code stored in the key can be employed to record such key
identity, for example to denote the time that a particular key was
employed with the associated lock.
The key can also be coded for use with a master key system in which
one or more tiers of master keying can operate associated classes
of locks, while non-master keys can operate only specific
associated locks. Referring to FIG. 4, there is shown, in typical
embodiment, lock circuitry operative to decode two or more
individual codes contained within different key data memories. A
data memory, such as a shift register 43, receives a key code from
an associated key and has a first group of outputs from selected
bit positions of memory 43 connected to a decoder 45, and a second
group of outputs from selected bit positions connected to a second
decoder 47. Other decoders can be similarly connected to
predetermined bit positions of memory 43 depending upon the levels
of master coding desired. The output of each decoder 45 and 47 is
coupled to logic circuitry 49, the output of which is the lock
output signal.
In operation, the detection of a predetermined code in the bit
positions associated with decoder 45 causes the decoder to provide
an output signal to logic 49 which, in turn, produces an output
signal for lock actuation or other utilization purposes. Similarly,
detection of a code in the bit positions associated with decoder 47
causes this decoder to provide an output signal to logic 49 for
production of the output signal. It will thus be appreciated that
keys containing either code will cause production of the output
signal. Such multiple key codes, each decodable by the lock
circuitry, can be employed in various master lock systems in which
different classes of locks can be actuated by different classes of
keys, or more generally, various levels of security provided by the
different levels of key coding. As a further alternative, the logic
49 can also be implemented to provide respective output signals in
response to respective signals from each decoder to thereby
indicate which key code has been detected.
A more particular embodiment of the invention is illustrated in
FIG. 5. The key includes and has disposed therein a shift register
40 typically of the monolithic integrated circuit type and capable
of storing a predetermined number of data bits which comprise a key
code. Register 40 is powered by a suitable battery 42 which is also
of small physical size to fit within a key element. Data from shift
register 40 is communicative with the lock circuit by way of a data
gate 44 operative to recirculate data back into shift register 40
to retain the same key code, or to load register 40 with new data
to provide a new key code, as will be described.
Data from register 40 is applied to a digital comparator 46 which
also receives information from a master code register 48. Register
48 contains a master code word as provided by a master code
selector 50, which is used for comparison with the key code
contained in the shift register 40. System timing is governed by a
clockk 52 which is started upon receipt of a start signal from a
key insertion detector 32, such as described above. Detector 32
also energizes key clamp 33 which captures the key in the lock
during the identification cycle. A clock provides two output
signals, labeled respectively .phi.1 and .phi.2, which are clock
pulses recurring at the same clock rate but shifted in phase one
from the other by a predetermined amount, typicallly 180.degree..
The clock pulses .phi.1 are advanced in phase from the clock pulses
.phi.2 and are employed to control data bit transitions, while the
delayed clock pulses .phi.2 are employed to control bit
comparisons. Thus, it will be appreciated that bit comparisons are
accomplished at the midpoint of a bit interval to assure that such
comparisons are performed after transients which may occur during
bit transitions.
The clock pulses .phi.1 are applied to register 48 and also to a
counter 54 operative to count the number of bits shifted out of
register 48. By means of a counter decoder 56, the last bit shifted
out of register 48 is recognized to denote the end of the code
comparison process. The key insertion detector 32 is operative to
clamp the key in the lock to prevent its premature removal prior to
completion of the decoding process. Detector 32 also provides a
signal to flip-flop 58 to set the flip-flop to one logical state,
the output signal thereof being applied to one input of an AND gate
62. Data in key register 40 and master register 48 are clocked out
bit by bit by clock pulses .phi.1 and are compared bit by bit in
comparator 46. The comparator is operative to provide a first
output, say zero, if the bit from the key register is identical to
the bit from the master register, and to provide a second output,
say one, if there is not correspondence between the received data
bits. The output of comparator 46 is couopled to an AND gate 60
which also receives the clock pulses .phi.2, the output of gate 60
being applied to the reset input of flip-flop 58. The output of
flip-flop 58 is coupled to one input of an AND gate 62, the other
input of which is the output signal from counter decoder 56 for
enabling gate 62.
Upon correspondence between a data bit from key register 40 and a
data bit from master register 48, AND gate 60 will remain disabled
and no reset signal will be applied to flip-flop 58. Thus,
flip-flop 58 remains in its set state so long as there is identity
between the key code and the master code providing an output signal
to gate 62. Upon detection of the last bit of the master code by
decoder 56, an output signal is provided for lock actuation. The
signal from decoder 56 is also employed to release key clamp 33 to
permit removal of the key from the lock. The output signal from
gate 62 is the system output signal for activating the associated
lock or other utilization means upon detection of a proper key
code.
If, during comparison of any bit of the key code, a lack of
identity is found between this bit and the associated bit of the
master code in register 48, the output signal from comparator 46
will cause enabling of AND gate 60 and consequent resetting of
flip-flop 58 which causes removal of the flip-flop output signal to
gate 62. No actuation signal can be provided by reason of the
disabling of gate 62. An output signal from gate 60 is provided
only upon detection of an error between a bit of the key code and a
corresponding bit of the master code, and this output signal is
also employed to activate an alarm circuit 64 to indicate detection
of an erroneous key code. Upon sensing of an alarm condition, a
stop signal can be generated by alarm circuitry 64 to stop clock 52
and discontinue the decoding process and to prevent the release of
the key clamped in the lock by clamp 33.
In one mode of operation, the master code stored in register 48 is
recirculated back into this register so that the code is available
for subsequent data comparison. Similarly, the code in shift
register 40 is recirculated therein by means of data gate 44 so
that the same key code can later be employed. To further enhance
the security of the novel lock system, however, the invention is
also operative in another mode wherein the code residing in shift
register 40 and master code 48 is replaced with a new code. Such
new code can be replaced on a regular basis or from time to time
depending on particular security requirements.
To employ such a new code, the output signal of gate 62 provided
upon correspondence between the key code and the master code, is
applied via a switch 63 to set a flip-flop 66, one output of which
is employed to energize a timing circuit 67 which, in turn,
provides a start signal to clock 52. The other output of flip-flop
66 is applied to an AND gate 68 which also receives clock signals
.phi.1. The output of gate 68 is applied to the clock input of a
new code register 70 which has stored therein a new data code
provided by a new code selector 72. The output of new code register
70 is applied to data gate 44 for coupling of such new data into
key shift register 40. The new data is also applied to the master
code register 48 for use in a subsequent data comparison. In this
latter mode of operation, clock 52 is enabled for only a sufficient
period of time determined by timing circuit 67 to permit shifting
of the new code data into the key shift register 40 and to prevent
reinstitution of the digital comparison process until the key is
again inserted into the lock at a subsequent time.
The new code selector 72 can be implemented in several different
ways and can include a binary word generator which is manually
actuable, such as by an array of switches, or automatically
actuable for example by means of a computer. By use of a digital
computer, a new key code can be provided from a random number
sequence generated by the computer such that the code is readily
identifiable only in computer memory and need not be known to
operating personnel in order to alter the key code. The master code
can be updated immediately after completion of a particular
decoding process or, alternatively, can be updated on a periodic
basis. For example, in some circumstances it is desirable to
reprogram the key code immediately after use of the key and to
reprogram the master code on a daily basis to permit use of the key
only once per day.
Rather than employing a separate clock signal for conveying data in
the present system, a self clocking code can be employed which is
advantageous in eliminating the need for a separate clock line and
associated terminals. Key circuitry operative in a self clocking
mode with associated lock circuitry is depicted in FIG. 6. A data
memory 51 is employed to store a predetermined code and has an
output coupled via an AND gate 53 to an encoder 55 which also
receives clock signals from a clock 57 within the key. The encoder
is, for example, a Manchester encoder for providing a self clocking
output signal for conveyance to the associated lock circuitry. The
key clock 57 also provides clock signals to memory 51 and to a
counter 59 operative to provide a stop signal to clock 57 after a
predetermined number of clock signals.
A self clocking data stream from the lock circuitry is received by
a Manchester decoder 61 operative to provide decoded data to memory
63 as well as clock signals thereto. Memory 63 is operative to
convey the data therein in parallel to a comparator 65 which also
received parallel data from a memory 67 which stores a
predetermined key code. Upon detection of an identical code
contained in memories 63 and 67, comparator 65 provides a trigger
signal to clock 57 and also to gate 53 as an enable signal
therefor.
The trigger signal initiates a clock cycle to enable the shifting
out of the code in memory 51 which is conveyed via gate 53 to the
encoder 55 for conversion to a self clocking format for transfer to
the lock circuitry. Gate 53 is enabled by the trigger signal form
comparator 65 for a sufficient period of time to permit transfer of
data from memory 51. The clock cycle is discontinued by a stop
signal from counter 59. The data in memory 51 remains in storage
either by being recirculated therein or by use of a non-volatile
memory in which data is not destroyed upon readout. It will be
evident that the embodiment of FIG. 6 is similar to that of FIG. 3
wherein a double coding arrangement is employed within the key to
enhance system security. The embodiment of FIG. 6 can also be
employed with a separate clocking signal, in which case the
Manchester encoder and decoder would not be necessary.
As described above, the circuitry of the key can typically be
powered by a small battery source. Alternatively, it may sometimes
be desirable to supplement the battery source or to entirely
replace the battery source by power applied externally of the key.
This can be accomplished as shown in FIG. 7 wherein the lock
circuit is operative to electromagnetically convey power to the key
circuitry. The lock circuit 69 includes means for providing energy
to the primary coil 71 of a transformer 99 for propagation of
electromagnetic energy which is received by a secondary coil 73
which is part of the key and which has its respective ends coupled
via respective diodes 75 and 77 to a resistor 79, and thence to the
key logic circuitry 81. The center tap of coil 73 is also connected
to a power input of logic circuitry 81, and a capacitor 83 is
connected across the power inputs thereto. A code signal input to
the key logic circuitry 81 is provided by an input line from the
junction of diodes 75 and 77. A battery 85 can also be connected
across the power input leads as illustrated.
By the circuit of FIG. 7 both energizing power and signals are
applied to the key. Typically, a pulse modulated carrier is
employed to convey energy and information to the key, with power
being detected by means of the rectifier and associated filter, and
with the signal being separately coupled to the key logic. Various
other modulation techniques, per se well known, can also be
employed to provide energy and data to the key circuitry. The
battery 85 is employed to provide power to the key data memory or
memories to retain the information stored therein in the absence of
connection to the lock circuit. If, however, non-volatile memories
are employed, the battery 85 is not required. Coupling of
energizing power from the lock to the key circuit can also be
otherwise accomplished, such as by photoelectric coupling.
The key can be implemented in a variety of mechanical
configurations to suit particular operating requirements. The key
can, for example, be in a form much like an ordinary mechanical
key, as illustrated in FIG. 8. In this instance the key 80 is
formed of a nonconductive material such as an epoxy and has the
memory encapsulated therein. The battery, in the form of a small
button cell, is contained within a battery compartment located in
the handle portion of key 80, access thereto being provided by a
removable cover 84. Electrical connection is provided at the distal
end of key 80 by means of four conductive bands 86 provided on the
end thereof, each being of generally U-shaped configuration as
illustrated.
The key is inserted within a keyway 88 of an associated lock, the
contact bands 86 being cooperative with an electrical connector 87
disposed at the inner end of the keyway to provide connection
between the key and the lock circuitry. Also disposed at the inner
end of the keyway is a microswitch 90 which includes an actuation
arm 92 disposed for actuation by the end of key 80 upon its
insertion into the lock. The switch 90 is part of insertion
detector 32 (FIG. 1) and is operative to provide a key insertion
signal to the system clock for commncement of the key decoding
process. A notch 94 is provided in one side of key 80 and is
cooperative with a rod 94 associated with solenoid 96 to prevent
removal of the key during the decoding process. The solenoid 96 is
typically energized by a signal from key insertion detector 32.
As described hereinabove, an alarm signal can be provided by the
invention in the event that there is lack of comparison between the
key code and the master code of the lock. Premature withdrawal of
the key could also cause an alarm condition and to prevent such an
occurrence, the key is clamped within the lock by solenoid 96 until
completion of the decoding cycle. The key can also be retained in
the lock in the event that an erroneous code is detected to prevent
its removal in such event. The key code can be arranged such that
the first bit to be read out of the key is always at ground
potential such that ground potential exists on all terminal
contacts 86 when the key is not in use, to thereby prevent
accidental shorting of the key which could destroy the stored data.
The key terminals could alternatively be deactivated when the key
is not in use by a suitable switch arrangement.
Electrical connection between the key and associated lock can also
be provided by other than electrical contacts such as illustrated
in FIG. 8. Electrical connection can also be made by noncontacting
means such as inductive or photoelectric coupling. One such
noncontacting coupling is shown in FIG. 9 wherein the key logic 87
has its data output connected to a light emitting diode 89 or other
suitable light source, and its data input connected to a
photosensor 91. The lock logic 93 similarly has its data input
connected to a photosensor 95 and its data output connected to a
light source such as a light emitting diode 97.
In use, with the key in operative association with the lock, the
photosensor 91 is in light receiving relationship with light
emitting diode 97, while the photosensor 95 is in light receiving
relationship with the light emitting diode 89. The key code
provided in the form of electrical pulses by logic 87 is applied to
light emitting diode 89 which provides corresponding light pulses
for receipt by photosensor 95 which, in turn, produces electrical
pulses to logic 93 for decoding in the manner described above.
Similarly, signals from the lock logic 93 are transduced
photoelectrically between light emitting diode 97 and photosensor
91 for application to key logic 87. The signals from logic 93 can
be data applied to the key data memory for re-entering a new key
code or can be an enabling signal for initiating the key decoding
process depending upon the specific embodiment. In the event that a
separate clock signal is employed, this clock signal can also be
photoelectrically coupled from the lock to the key.
From the foregoing it will be evident that an electronic lock
system has been provided which is both reliable and highly secure
and which can be constructed in an efficient and commercially
realistic manner. Various modifications and alternative
implementations will occur to those versed in the art without
departing from the spirit and true scope of the invention. For
example, data can be conveyed between the key and the lock in a
parallel rather than a serial manner, and various levels of coding
can be provided to suit the desired level of security. The
electronic circuitry and its mechanical housing can take a wide
variety of forms adapted to specific installation requirements.
Accordingly, it is not intended to limit the invention by what has
been particularly shown and described, except as indicated in the
appended claims.
* * * * *