Electronic Identifying Security System

Abstract

An electronic identifying security system for use with one or more locks can be actuated only by valid keys that have a pattern of internal electrical conductors capable of applying an authorized permutation of binary signals to a plurality of input conductors of the security apparatus. The security apparatus has a lock opening mechanism and an alarm device. The alarm device is actuated either by application of a binary "one" signal to an input conductor for which a binary "zero" is proper, or else by a binary "one" on at least one but fewer than all of the input conductors for which a binary "one" is proper. In addition to the foregoing internal conductors, additional internal conductors are permuted to identify the keys in groups and individually. Lost keys can be prevented from working without changing the general combination by reprogramming the apparatus to specifically exclude them. A portion of the system is switchable from a mode of operation in which it excludes individual keys to a mode of operation in which it excludes groups of keys. In a security system that has a plurality of door locks, groups of keys can be made capable of unlocking some doors but not others.

Description

BACKGROUND OF THE INVENTION

A key actuated electronic security system was disclosed in a patent to R. A. Hedin et al. U.S. Pat. No. 27,013, reissued on Dec. 22, 1970. That patent relates to security systems such as could be used for entrance door locks and the like, and more particularly to a key actuated electronic security system employing keys having electrical contacts which are permuted in a binary code, to create various combinations of keys and electronic key responsive locks.

In a typical installation of such a system, a key receptacle is located in a conveniently exposed position adjacent a door which is to be locked. Electrically conductive keys are provided which, when inserted in the key receptacle, establish binary "one" signals on certain of the input conductors in the receptacle and binary "zero" signals on others of the input conductors. The key provides conducting paths from a power conductor in the receptacle to the input conductors which are to have binary "ones" thereon and functions as a switch between those input conductors and the power conductor. For brevity, those ones of the receptacle's input conductors to which a logic "one" voltage is applied by a proper key are referred to herein as the true input conductors, while those to which a proper key applies no voltage, which is a logic "zero," are termed the false input conductors. When a key applies a proper pattern of binary signals to the input conductors, internal decoding circuitry actuates an electrically operable lock to unlock the door. Keys having an incorrect permutation, and other picking devices, are recognized by the system, which is not actuated by them. The apparatus actuates an alarm signal when some picking devices are employed.

In the above-cited prior art, the lock mechanism took account of signals on both the true and the false inputs, but the alarm device considered only the latter. Only the input conductors of the combination for which binary "zero" signals were proper, were capable of actuating the alarm device, which they did when a binary "one" was present instead of the expected binary "zero."

Another key actuated security system of the prior art had provision for individually identifying a plurality of keys which were capable of opening the lock, by providing additional bits in the keys and in the key receptacle beyond the number of bits employed for the combination of the lock. The internal decoding circuitry could be programmed with patch cords to invalidate one or more of the keys, such as lost keys, without having to change the combination of the lock, which was present on only some of the input conductors. Individual keys that were thus ruled out were thereafter incapable of operating the lock mechanism but did actuate the alarm device.

SUMMARY OF THE INVENTION

The present invention is an electronic identifying security apparatus having subcircuits for actuating a lock and an alarm device.

In the preferred embodiment all of the true input conductors of the key receptacle, which should have logic "one" signals, are connected by means of patch cords to inputs of an AND gate, which is referred to herein as the true AND gate. All of the false input conductors, which should have "zeros," are connected by patch cords to inputs of an OR gate, which is referred to as the false OR gate. When all of the input signals to the true AND gate are "ones" and all of the input signals to the false OR gate and "zeros," the lock is unlocked.

The alarm device, unlike the lock, is preferably actuated in response to an attempted entry in which at least one of the true input conductors does not have a binary "one" applied to it, and at the same time, at least one of the true input conductors does have a binary "one" applied to it. The alarm device is also actuatable by the occurrence of a binary "one" signal on false input conductors.

The alarm device is made responsive to the attempted entry described above in which less than all of the true inputs have binary "ones" by providing, in addition to the true AND gate which receives signals from all of the true input conductors, an alarm OR circuit which ascertains whether or not at least one binary "one" signal is present at the true input conductors. The alarm OR circuit is a different OR circuit than the false OR gate mentioned above. The outputs of the true AND gate and the alarm OR circuit are combined to produce a first signal capable of actuating the alarm when at least one but less than all of the true input conductors has a logic "one" signal.

The alarm device is made responsive to the above-mentioned occurrence of a binary "one" signal on false input conductors by utilizing a second signal, derived from the output of the false OR gate. The first and second signals are combined in a further OR circuit so that either the true or the false input conductors can serve as sources of alarm, to actuate the alarm device.

One particular false conductor is preferably arranged to inhibit unlocking if a binary "one" is present thereon, but not to actuate the alarm. This prevents a tamperer from determining the general combination by deliberately actuating the alarm from one input conductor at a time.

To avoid having to change the general combination, and hence to change all of the keys, every time that a key is lost, provision is made for "ruling out" individual keys by programming means such as patch cords. Each key has extra digits for identifying it. Individually ruled-out keys cannot open the lock even though they have the correct general combination.

The present invention preferably also has a logic circuit which can be switched, by means such as patch cords, to enable the same logic circuitry to be used in either of two modes of operation, namely to exclude or rule out individual identified keys such as lost keys, or to rule out an entire subgroup of keys while still permitting other keys to operate the equipment as before.

The invention has further patch cord switching provisions for enabling particular logic subcircuits to be employed either (a) to rule out a greater number of individual identified keys, or else (b) to increase the security of the system by increasing the number of statistical permutations available for individual identification of keys, as will be described more fully hereinafter.

Accordingly, one object of the present invention is to provide an electronic identifying security apparatus to which a valid combination of binary signals must be applied by a key to actuate a lock mechanism, and also having an alarm device responsive to tampering, the alarm device being actuatable either (a) by simultaneous existence of an input signal indicative of an attempted entry and an invalidity-indicating signal produced by a logic "zero" on a true input conductor, or (b) by a logic "one" signal on a false input conductor.

A further object is to provide an electronic identifying security apparatus as noted immediately above and in which the signal indicating an attempted entry is a binary "one" signal on a true input conductor.

Still another object is to provide an electronic identifying security apparatus as above and in which at least one input conductor, when subjected to an improper signal, inhibits unlocking of the mechanism but does not actuate the alarm, to baffle a tamperer.

Another object is to provide an electronic identifying security apparatus as noted in the first object and in which, in addition, a means is provided for delaying the actuation of the alarm device for a time after binary input signals are applied to the apparatus.

Yet another object of the invention is to provide an electronic identifying security apparatus for use with a plurality of keys that are differently encoded in subgroups, and having a first decoding device for accepting all of the plurality of keys to unlock the mechanism, and having a second decoding device for overruling the acceptance of keys belonging to a predetermined subgroup of the plurality of keys, and in which the keys have additional encoding digits for differentiating individual keys of the subgroup from each other, the apparatus also having switching means for making the second decoding device operative and inoperative to overrule the first decoding device, to prevent unlocking by any of the keys of the predetermined subgroup.

Yet a further object is to provide an electronic identifying security apparatus as noted in the immediately preceding object and in which the switching means cooperates with logic circuit portions of the second decoding device to render the apparatus responsive either to prevent unlocking by individual keys or to prevent unlocking by all keys of a subgroup.

Another object is to provide an electronic identifying security apparatus having a plurality of decoder subcircuits each having a predetermined number of code digits for identifying individual keys to be ruled out, and having switching means for interconnecting the decoder subcircuits to provide fewer decoder subcircuits each having more digits and thereby to provide more possible encoding permutations with a resulting increase in security.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and features of the invention will become more apparent upon consideration of the accompanying description and drawings, in which:

FIG. 1 is a block diagram of an electronic identifying security apparatus incorporating a preferred embodiment of the present invention including a decoding circuit;

FIG. 2 is a block diagram showing various subcircuits of the decoding circuit of FIG. 1;

FIG. 3 is an electronic schematic diagram of an input circuit portion of the decoding circuit; and

FIG. 4 is an electronic schematic diagram of an output portion of the decoding circuit.

DESCRIPTION

In a preferred embodiment of the invention a door 10 shown in FIG. 1 is equipped with a locking bolt 12, which is moved in and out of locking engagement with the door 10 by an electric lock device 14. At a location 16 near the door, provision is made for insertion of a special key 18 which is shown schematically at the left side of FIG. 1. To unlock the door 10 the key 18 is inserted into a key receptacle 20 at the location 16, in which the key 18 performs connecting functions by making contact with input conductors 22 in the key receptacle. A number of patch cords 24 are inserted to connect the input conductors 22 to a number of input terminals 26 of decoding circuit 28. The decoding circuit 28 includes a power supply 30 by which dc power is applied to one conductor 32 of the key 18 by way of a circuit path comprising one of the terminals 26, one of the patch cords 24, one of the input conductors 22, and the conductor 32 of the key 18. Upon insertion of the key 18 in the key receptacle 20 the voltage on the conductor 32 is applied by other internal conductors of the key 18 to certain ones of the input conductors 22 and not to others. Thus the various input conductors 22 receive a set of input signals in accordance with a predetermined permutation of continuous and discontinuous conductors in the key 18. The binary pattern of input signals established by the key 18 is automatically examined by the decoding logic circuit 28, which responds by supplying a signal to the electric lock 14 to unlock the door 10 when a proper authorized key 18 has been inserted.

When an unauthorized key is inserted in the receptacle 20, an improper pattern of electrical signals is applied to the input conductors 22, and the electric lock 14 does not operate to unlock the door. The decoding circuit 28 is arranged to minimize the probability that the door 10 can be unlocked by the application of spurious signals of any type to the input conductors 22 from an unauthorized key or other picking device. Such other devices include sources of external voltage arranged for application at the key receptacle 20 in attempts to pick the lock 14. Certain types of improper signals at the input conductors 22 stimulate the decoding circuit 28 to produce an actuating signal for an alarm circuit 34. The alarm circuit has provisions for operating an audible or visual alarm device or an information circuit indicating that an attempt is being made or has been made to pick the lock 14.

The decoding circuit 28 includes lock logic circuits, alarm logic circuits, rule-out logic circuits and miscellaneous circuits. The lock logic circuits are included in portions of FIGS. 2, 3, and 4, which show the decoding circuit 28 in more detail. A group of true input terminals 26T, FIG. 2, is connected to an AND gate 35, which provides an output signal to a combining circuit 37, the output of which actuates the electric lock 14.

Other terminals 26F, each of which receives a logic "zero" voltage upon insertion of a valid key 18 into the receptacle 20, have connections to an OR circuit 39. The OR circuit 39 provides a second input for the combining circuit 37, to assist the combining circuit 37 in determining whether it should or should not supply an actuating signal to unlock the electric lock 14. FIG. 2 has been simplified for clarity.

As shown on FIG. 3, the true input terminals 26T of the logic circuit 28 are connected to the logic AND circuit 35 comprising diodes 38 and a resistor 42. So long as all of the terminals 26T have logic "one" voltages applied to them, all of the diodes 38 are back-biased slightly, and only a relatively small current flows in resistor 42, so that the voltage at an output terminal 40 of the AND gate 35 remains relatively high. When one or more of the input terminals 26T is subjected to a relatively low voltage, representing a logic "zero" signal, a relatively large current flows through the resistor 42, through the respective diode 38, and through a respective small resistance 36 of the input circuit having the logic "zero," and the voltage of the AND-gate output terminal 40 is made relatively low.

The combining circuit 37 is fundamentally an AND circuit for combining signals from the true AND gate 35 and the false OR gate 39.

The combining circuit 37 receives a signal from the AND gate output terminal 40, and passes that signal through a time delay filter circuit comprising a resistor 44 in series and a capacitor 46 in shunt, as shown in FIG. 4. The signal at the junction of the resistor 44 and the capacitor 46 is applied to the base electrode of a first transistor 48 of an amplifier which includes transistors 48, 50 and 52. At the base of the transistor 48 the signal derived from the true AND gate output terminal 40 is combined with a signal from the false inputs in a manner to be described hereinafter.

The transistor amplifier 52 operates the electric lock 14. A collector terminal of the transistor 52 is connected to one terminal 54 of a strike-actuating coil 55 of the electric lock 14, and the emitter of the transistor 52 is connected to ground potential. A second terminal 56 of the strike-actuating coil 55 is connected to the power supply 30. When a logic "one" signal appears at the base of transistor 48, the transistor 52 effectively connects the terminal 54 to ground, energizing the strike-actuating coil 55 of the electric lock 14. The strike-actuating coil 55 then causes withdrawal of the bolt 12 from locking engagement with the door 10 to unlock the door. When a logic "zero" signal exists at the true AND-gate output terminal 40, the transistor amplifier 52 is in a non-conducting state, and no current flows through the strike-actuating coil 55 so that the door 10 is not unlocked.

Each of the true terminals 26T of the decoding circuit 28 is connected to the anode of a respective series-connected diode 43, whose purpose is to prevent a tamperer from obtaining information about the proper lock combination by making voltmeter or ohmmeter readings at the input conductors 22 of the key receptacle 20. The diodes 43 together with the shunt resistors 36 give the true input terminals 26T an appearance like that of the false input terminals 26F, as by from measuring devices employed at the key receptacle 20.

The false input terminals 26F are connected so as to prevent the lock 10 from opening unless they all have logic "zero" signals. Each of the false input terminals 26F is connected to the anode of a diode 58, FIG. 3 whose cathode is connected to the cathodes of all of the other diodes 58 in common to an OR output terminal 60. The diodes 58, together with two resistors 62, 64 of FIG. 4, from the diode OR circuit 39. When a positive voltage, representing a logic "one" signal, is wrongfully applied to any one or more of the false input terminals 26F, a logic "one" voltage appears at the OR output terminal 60, and the electric lock 14 is prevented by the combining circuit 37 from operating. A logic "one" signal at the OR output terminal 60 causes a current to flow in a series resistor 66 to the base electrode 68 of an NPN transistor 70, FIG. 4.

The OR output terminal 60 is also connectd through a diode 69 to a shunt-connected capacitor 71 from which a series-connected resistor 73 carries a signal to the same base electrode 68 of the transistor 70 to insure a fast rise and relatively slow decay of the signals being transmitted from the terminal 60 to the electrode 68. The capacitor 71 together with the resistor 73 forms a time delay circuit which provides a time delay only for removal of the signals as experienced at the base electrode 68.

Signals from the false OR gate 39 are passed through the transistor 70 and combined with signals from the true AND gate 35 to control the lock. The emitter of the transistor 70 is connected to ground and the collector is connected to the cathode of a diode 72 whose anode is connected to the base electrode of the transistor 48. A logic "one" signal on the false OR output terminal 60 causes the transistor 70 to conduct collector current and therefore to short-circuit the base electrode of the transistor 48 to ground through the diode 72. This short-circuiting action prevents the amplifier consisting of the transistors 48, 50, and 52, from operating to unlock the door 10. Thus, the base circuit of the transistor 48 functions as a two-input AND circuit, one of the inputs being a signal from the resistor 44 representing the true input terminals 26T, and the other input being a signal received through the diode 72 and representing the false input terminals 26F. Acceptable signals must be present at both of the inputs of this AND circuit in order to unlock the door. An acceptable pattern of signals is, of course, one in which all of the true input terminals 26T have binary "one" signals applied to them and all of the false input terminals 26F have binary "zeros."

Logic circuits for actuating the alarm circuit 34 are shown in portions of FIGS. 2, 3, and 4. The alarm combining circuit 75 of FIG. 2 receives input signals from the true AND gate 35, and combines them with another input signal derived from the false OR gate 39. The output of the alarm combining circuit 75 is connected to the alarm circuit 34 to actuate the alarm circuit 34 when improper signals are applied to either the true input terminals 26T or the false input terminals 26F. The combining circuit 75 for alarm signals is more fully shown in FIG. 4.

With regard to actuation of the alarm by signals from the true input terminals 26T, two requirements must be fulfilled to cause an alarm: (a) an entry must be attempted, and (b) at least one of the true terminals 26T must have a logic "zero." The output terminal 40 of the true AND gate 35 supplies a signal through a series resistor 74 and through two series-connected voltage-dropping diodes 76 to a base terminal 78 of an NPN transistor 80. A logic "zero" exists at the base terminal 78 when one or more of the true input terminals 26T has a logic "zero" signal.

The fact that an entry is being attempted is detected in the preferred embodiment by an OR circuit comprising diodes 81 and 83 and resistors 85 and 87, FIG. 4. This circuit is indicated symbolically on FIG. 2 by the line 77. The anodes of the diodes 81 and 83 are connected respectively to two of the inputs of the true AND circuit 35 at the junctions of the resistors 36 and diodes 38, FIG. 3. Additional diodes could be connected in the same way to the other inputs of the true AND circuit 35 also, if desired. A logic "one" signal at either of the true input terminals 26T to which the diodes 81, 83 correspond creates a logic "one" signal at the OR circuit load resistor 85. A voltage on the OR circuit load resistor 85 is applied to a series resistor 87 leading to the collector terminal of the transistor 80.

The series resistor 87 is one of two inputs to an AND gate, transistors 80; the base circuit 78 of the transistor 80 is inverted second input to the AND gate 80. The OR circuit diodes 81, 83 whose outputs are connected through the resistor 87 serve as a collector voltage source for the transistor 80 when an entry is being attempted. An output voltage appears at the collector of the transistor 80 only if the OR circuit resistor 87 is transmitting a logic "one," AND the base electrode 78 of the transistor 80 simultaneously has a logic "zero." The base electrode 78 has a logic "zero" only when the output terminal 40 of the true AND gate 35 has a logic "zero," and this occurs only when less than all of the true input terminals 26T have a logic "one" input. Thus it may be seen that if one or more of certain ones of the input terminals 26T corresponding to the diodes 81 and 83 has a logic "one," and one or more logic "one" signals is absent from the array 26T of true input terminals, an alarm can occur.

The foregoing signal at the collector of transistor 80, derived from the true input terminals 26T, is connected through circuitry to an OR gate whose other input is derived from the false input terminals 26F. The collector of transistor 80 is connected to a series resistor 82 and thence to a shunt capacitor 84, to cause a time delay or low-pass filtering effect on any signal that occurs at the collector of the transistor 80. A junction 86 of the resistor 82 and the shunt capacitor 84 is connected to the base of an NPN transistor 88 whose emitter is connected through a resistor 90 to a junction 92 of the aforementioned resistors 62 and 64. The resistors 90 and 62 are two inputs of a wired OR circuit having the output terminal 92. At the OR output terminal 92, alarm signals from the true input terminals 26F are combined with alarm signals from the false input terminals 26F.

The OR output terminal 92 is connected to the gate electrode of a silicon control rectifier 94 whose anode circuit is connected in series with the alarm device 34. A logic "one" signal on the terminal 92 results in actuation of the alarm circuit 34. A capacitor 96 is connected in parallel with the resistor 64 to provide a time delay and filtering action on signals at the terminal 92.

Alarm signals from the false input OR circuit 39 at output terminal 60, pass through the resistor 62 and are delivered to the terminal 92. Thus either an improper signal from the false input terminals 26F or an improper signal from the true input terminal 26T, actuates the alarm circuit 34, because they are both conducted into the OR circuit represented by the resistors 62 and 90, which controls the alarm.

The security apparatus has circuits which provide for invalidating one or more particular keys which may previously have been valid, and which it is subsequently desired to exclude from operating the equipment, or for invalidating, as a group, a particular group of keys. An example of a situation in which it may be desired to invalidate a particular key is one in which the security system is being utilized to lock an industrial plant, one of whose key-carrying employees has been discharged but has not returned his key. The key of the discharged employee can be invalidated without changing the general combination of the entire system. This is possible because each key is provided with digits which identify that particular key and which are not examined by the true and false input circuits 35, 39 in ascertaining whether or not the key conforms to the lock's general combination.

The extra binary digits of each key, being unique, identify it and make possible the invalidation of one or more particular keys by inserting patch cords in a patch board. The patch cords connect the identifying digits of each key to a rule-out decoder circuit R, FIG. 2. The rule-out decoder circuit recognizes ruled-out or invalidated keys by their identifying digits and prevents the electric lock 14 from being opened by such keys, even though they have the correct general combination. Moreover, an attempted entry with a ruled-out key causes the alarm circuit 34 to be actuated. Rule-out patchboard terminals 26R, and the rule-out AND gates, which are principally decoders for recognizing ruled-out keys, are shown in relation to other sub-circuits of the apparatus in FIG. 2.

To rule out a particular key the input terminals of one specific rule-out AND gate are connected by patch cords to the particular ones of the input conductors 22 which serve as identifying binary "one" inputs for the particular key which is to be ruled out. When that particular key is inserted in the receptacle 20, it causes binary "one" signals to appear on those particular ones of the input terminals 22, and therefore to appear on all of the inputs of the specific AND gate which has been connected to serve as a rule-out AND gate for that particular key. The output of that AND gate thereupon has a logic "one" signal. That logic "one" signal on the AND gate output terminal is transmitted through an OR circuit and is amplified to create a first output signal to inhibit the lock, and a second output signal to actuate the alarm.

Schematically, the rule-out circuit 79, as shown in FIG. 3, comprises a plurality of rule-out AND gates 98 to which the rule-out terminals 26R are connected as inputs. The outputs of the AND gates 98 are all connected together to the base 100 of an NPN transistor amplifier 102. The amplifier 102 is an emitter follower having two outputs, 104 and 106.

The first output 104 is provided for preventing actuation of the electric lock 14 despite the presence of a correct general combination in a ruled-out key as indicated by valid signals at the true and false input terminals 26T and 26F respectively. The first output 104 connects through a series resistor 108 to the base terminal 68 of the transistor 70. This represents one of a plurality of OR inputs to the transistor 70, any one of which is capable of preventing the lock from opening.

The second output 106 of the transistor 102, which is provided for actuating the alarm circuit 34 when a ruled-out key is employed, passes through a series-connected diode 110 to the output terminal 60 of the false OR circuit 39. The circuit 106 serves therefore as an additional input to the false OR circuit 30, whose other inputs comprise the false input terminals 26F.

Typical interior connections of the diode AND gates 98 are shown for two of them, 98a, 98b. The AND circuit rule-out gate 98a comprises diodes 114, and a resistor 116. The occurrence of a logic "zero" signal on any input of the AND gate 98a establishes a logic "zero" signal and an output terminal 120 of the AND gate. The output terminals of the AND gates 98 are all connected through OR diodes 122 to the base 100 of the transistor 102. Consequently, if at least one of the AND gates 98 has a logic "one" signals at all of its input terminals, a logic "one" signal appears at the base 100. Such a logic "one" signal at the base 100 maintains the door locked by means of the circuit 104, and causes the alarm circuit 34 to be actuated by means of the circuit 106.

In a security system employing a plurality of locks and keys, it is sometimes desirable to rule out certain groups of keys from operating certain locks. For example, all of the keys may have a general combination for opening the outside doors of a plant, and only certain ones of those keys may give the bearer access to the accounting department but not to the engineering department, while others of those keys may give the bearer access to the engineering department but not to the accounting department. This is accomplished by encoding the general combination digits of the keys all alike, but encoding the identifying digits in groups so that some of the identifying digits are alike for all of the keys of one group but are different from the identifying digits of a different group. In addition to the group-identifying digits, each key has digits which uniquely identify the individual key. The rule-out circuits 79 have provision for ruling out groups, using a two-bit code for identifying groups. To use the rule-out AND gates 98a, for example, for group rule-out, a jumper 124 is removed to create two two-input AND gates instead of one four-input AND gate 98a. In order to complete the conversion from a four-input AND gate to two two-input AND gates, a diode similar to the diode 122 must be inserted in a socket 126, and a resistor similar to the resistor 116 must be inserted in another socket 128. Any key which has two group-identifying digits that correspond to digits that are patched to the input terminals 130, 132 establishes a logic "one" at the AND gate output terminal 120, which is transmitted through the OR diode 122 to actuate the amplifier 102, which prevents unlocking of the lock and actuates the alarm. The groups rule-out capability does not preclude ruling out of individual keys with other rule-out AND gates 98.

In the preferred embodiment, at least one of the digits, i.e., internal conductors, of each key is employed for a power supply connection to the key 18 from the key receptacle 20. Some other digits of each key are used for establishing the binary signals that are required for fulfilling the general combination of the lock. Others of each key's digits can be employed for group identification. Still other digits are used for uniquely identifying each key. The remaining digits are merely to improve security by their numerical presence; the apparatus is indifferent to the signals, if any, on these last-named digits. More permutations of inputs for individually identifying keys can be obtained by a connection which can be effected by means of a patch cord interconnecting two of the diode AND gates 98. The terminals at which such a connection are made are the terminals 134 of FIG. 3. Insertion of a patch cord to connect together the terminals 134 effectively converts two four-input AND gates 98 to one eight-input AND gate. Although this makes fewer rule-out AND gates available for ruling out keys, it makes possible the issuance of a greater number of uniquely encoded and identified keys while retaining the rule-out capability for a limited number of keys, and is convertible by patching.

A further feature of the invention prevents an alarm when the lock 14 is being unlocked. A connection is provided from the collector terminal of the transistor 48 to the collector terminal of the transistor 88, FIG. 4. The collector terminal of the transistor 48 is connected to the power supply 30 by a series resistor 138. When the transistor 48 is conducting collector current, which occurs whenever the electric lock 14 is to be unlocked, the voltage at the collector terminal of the transistors 48 and 88 is relatively low because of resistive voltage drop in the resistor 138, and the transistor 88 is therefore prevented from transmitting an alarm signal through the resistor 90 to the electrode 92.

A further miscellaneous important feature of the invention involves an input terminal 140 of the decoding circuit 28, FIG. 3. This terminal 140 is provided to prevent tamperers from discovering the general combination of the lock by ringing the alarm. When the terminal 140 is energized by an externally applied signal at the key receptacle, the lock mechanism 14 is prevented from unlocking, and the alarm device 34 is prevented from being actuated.

When a tamperer applies a probing signal voltage to one input conductor 26 at a time, the terminal 140, which is actually a false input terminal from the standpoint of the lock mechanism 14, appears to the tamperer be a true input, because it results in no alarm indication. The tamperer will consequently include the terminal 140 in the group of terminals to which he simultaneously applies binary "one" signals when he attempts to open the lock. A binary "one" signal on the terminal 140 frustrates the attempt by silently maintaining the lock mechanism in a locked condition.

These results are accomplished by conducting a signal from the terminal 140 through a resistor 142 to the base 68 of the transistor 70. The resistor 142 is one of many inputs of the wired resistive OR circuit whose OR output terminal is the base terminal 69. A logic "one" at the base 68 prevents the lock 14 from opening.

Silencing of the alarm upon a "one" signal at the terminal 140 involves a diode 136, FIG. 4. Diode 136 is connected from the collector terminal of the transistor 80 to the collector of the transistor 70. A logic "zero" at the transistor 70, such as occurs if a logic "one" signal exists on the special false input terminal 140, results in conduction of current from the collector of the transistor 80 through the diode 136 and through the collector-to-emitter circuit of the transistor 70 to ground. In this way, the transistor 70 short-circuits to ground any logic "one" signal which may otherwise exist at the collector terminal of the transistor 80 and thereby prevents the alarm device 34 from being actuated through one of its actuation channels, namely the channel having the resistor 90. Improper signals on the other false input terminals 26F actuate the alarm through a different one of the alarm's actuation channels, namely the channel having the resistor 62, and hence are not affected by the diode 136.

If the programmer wishes to do so, he may instead employ the circuitry of the terminal 140 to act as a total rule-out circuit. This is accomplished by energizing the terminal 140 at will by means of an external switch, to rule out everyone. The switch can be conveniently connected through a resistor to the terminals 144 of the apparatus with patch cords at the patch panel, FIG. 3.

Claims

I claim:

1. An electronic identifying apparatus having a device to be unlocked in response to the establishment of a predetermined binary code or codes, a plurality of input conductors including first and second subsets, each conductor of said first and second subset capable of having a signal of first and second binary states respectively established thereon, an alarm device, first circuit means connected with said first subset for producing a first control signal in the absence of said first binary state on at least one conductor of said first subset, second circuit means connected with said second subset for producing a second control signal in the absence of said second binary state on at least one conductor of said second subset, third circuit means connected to receive a binary signal from at least one of said plurality of conductors upon attempted connection of said first and second subsets to said first and second circuit means for producing a third control signal, and combining circuit means for actuating said alarm device upon occurrence of said third control signal and either said first or said second control signals.

2. An electronic identifying apparatus as defined in claim 1 and wherein said third circuit means comprises fourth means for making the third circuit means responsive to a binary signal of only said first binary state to produce said third control signal and wherein said combining circuit means comprises logic means for actuating said alarm device either in response to said second control signal or upon a concurrence of said third control signal and said first control signal.

3. An electronic security apparatus as defined in claim 2 and wherein said fourth circuit means is responsive only to a binary signal on at least one of the input conductors of said first subset.

4. An electronic security apparatus as defined in claim 1 and further comprising signal delay means connected therein for delaying actuation of said alarm device for a time after binary signals are applied to said plurality of input conductors.

5. An electronic identifying apparatus for use with valid binary code unlocking devices which establish a first binary code and a second binary code or codes comprising, input circuit means having a plurality of input means on which said binary codes are to be established, first decoding means connected to said input means responsive to said first binary code on said input means for actuating a lock mechanism, second decoding means responsive to said second binary code for overriding the first decoding means to prevent actuation of said mechanism thereby, switching means for selectively enabling and disabling said second decoding means to provide selective actuation of said mechanism by unlocking devices having a particular second binary code.

6. An electronic identifying apparatus as defined in claim 5 and wherein said input circuit means comprises means for receiving various third binary codes for differentiating between individual unlocking devices which establish said second code and wherein said switching means comprises means for switching said second decoding means to be responsive to overrule actuation by every device of said subgroup irrespective of said third binary codes.

7. An electronic identifying apparatus as defined in claim 6 and wherein said switching means comprises means for switching said second decoding means to be responsive either to overrule actuation by at least one of said third binary codes of an individual device or to overrule actuation by every device of said subgroup.

8. An electronic identifying apparatus as defined in claim 5 and further comprising means for actuating an alarm device upon establishment of a binary code on said plurality of input means when said code results in nonactuation of said lock mechanism.

9. An electronic identifying apparatus having a plurality of input conductors upon which a valid code of binary signals must be applied to identify valid devices for actuating an unlocking mechanism and activating an alarm for invalid devices, said apparatus being for use generally with a plurality of said devices, said code including a first group of binary signals for signifying compliance of the devices with a general predetermined permutation and a second group of binary signals for identifying ruled-out devices of the plurality which are to be specifically excluded from actuating the mechanism, comprising first decoding means for automatically examining said first group of signals and for providing a first control signal upon said compliance, second decoding means for automatically examining said second group of binary signals and for producing a second control signal upon identifying ruled-out devices, first combining means for actuating the unlocking mechanism in response to devices that comply are not ruled out, and second combining means for actuating the alarm in response to devices that are ruled out.

10. An electronic identifying apparatus as defined in claim 9 and wherein said second group has an initial number of binary signals and said second decoding means comprises a multiplicity of separate decoding means for identifying ruled-out devices based on said second group having said initial number of binary signals, and including switching means for combining said separate decoding means into fewer decoding means for identifying fewer ruled-out devices based on said second group having a number of binary signals greater than said initial number.

11. An electronic identifying apparatus having a device to be unlocked in response to the establishment of a predetermined binary code or codes on a plurality of input conductors including first and second subsets, on each conductor of which a signal of first and second binary states respectively is to be established, means for inhibiting unlocking of the device upon a lock inhibit signal, an alarm device, first combining means connected with said second subset for producing said lock inhibit signal and an alarm control signal in the absence of said second binary state on at least one predetermined conductor of said second subset, and second combining means for actuating said alarm device upon said alarm control signal, said first combining means having means for producing said lock inhibit signal but not said alarm control signal in the absence of said second binary state on at least one other preselected conductor of said second subset.