U.S. patent number 3,849,270 [Application Number 05/295,795] was granted by the patent office on 1974-11-19 for process of manufacturing semiconductor devices.
This patent grant is currently assigned to Fujitsu Limited. Invention is credited to Hajime Kamioka, Kazufumi Nakayama, Mikio Takagi, Chiaki Terada.
United States Patent |
3,849,270 |
Takagi , et al. |
November 19, 1974 |
PROCESS OF MANUFACTURING SEMICONDUCTOR DEVICES
Abstract
A process of manufacturing semiconductor devices is described
which comprises the steps of: Forming an insulating layer having a
closed pattern on one surface of a semiconductor substrate, Forming
a coating layer on the entire surface of the semiconductor
substrate at least a portion of the coating layer deposited on the
insulating layer being conductive, and then Carrying out
electrolytic etching in such a manner that the portion of said
coating layer on the insulating layer is connected as an anode
whereby said portion of said coating layer on the insulating layer
is removed and the portion of said coating layer encompassed by the
insulating layer remains. The resulting semiconductor devices have
a far more flattened surface.
Inventors: |
Takagi; Mikio (Tokyo,
JA), Nakayama; Kazufumi (Kawasaki, JA),
Terada; Chiaki (Kawasaki, JA), Kamioka; Hajime
(Tokyo, JA) |
Assignee: |
Fujitsu Limited (Kawasaki-shi,
JA)
|
Family
ID: |
13707313 |
Appl.
No.: |
05/295,795 |
Filed: |
October 10, 1972 |
Foreign Application Priority Data
|
|
|
|
|
Oct 11, 1971 [JA] |
|
|
46-80047 |
|
Current U.S.
Class: |
438/400; 205/656;
438/637; 438/672; 438/969; 257/E21.571 |
Current CPC
Class: |
H01L
21/76294 (20130101); H01L 23/522 (20130101); H01L
21/00 (20130101); H01L 23/485 (20130101); H01L
2924/00 (20130101); H01L 2924/0002 (20130101); H01L
2924/0002 (20130101); Y10S 438/969 (20130101) |
Current International
Class: |
H01L
23/52 (20060101); H01L 21/70 (20060101); H01L
21/00 (20060101); H01L 23/48 (20060101); H01L
23/522 (20060101); H01L 21/762 (20060101); H01L
23/485 (20060101); C23b 001/00 (); C23b 003/02 ();
B23p 001/00 () |
Field of
Search: |
;204/129.1-129.7 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Tufariello; T. M.
Attorney, Agent or Firm: Maleson, Kimmelman and Ratner
Claims
What we claim is:
1. A process of manufacturing semiconductor devices which comprises
the steps of:
forming an insulating layer having a closed pattern on one surface
of a semiconductor substrate,
forming a deposited layer on the entire surface of the
semiconductor substrate, the deposited layer being thin in the
proximity of the edges of the surface of the insulating layer, and
at least the portion of the deposited layer located on the
insulating layer being conductive, and,
dipping the semiconductor substrate so treated in a bath of an
etching solution wherein electrolytic etching is effected in a
manner such that said portion of the deposited layer of conductive
material on the insulating layer is connected as an anode whereby
said portion of the deposited layer on the insulating layer is
removed and the portion of the deposited layer encompassed by the
insulating layer remains substantially unchanged.
2. A process according to claim 1 wherein said insulating layer
consists of silicon dioxide.
3. A process according to claim 1 wherein said insulating layer
consists of phosphosilicate glass.
4. A process according to claim 1 wherein said deposited layer
consists of metal.
5. A process according to claim 4 wherein said metal is
aluminium.
6. A process according to claim 1 wherein said deposited layer
consists of semiconductor.
7. A process according to claim 6 wherein said semiconductor is
silicon semiconductor.
8. A process according to claim 6 wherein said semiconductor is
polycrystalline silicon semiconductor.
9. A process according to claim 6 wherein said semiconductor is
silicon semiconductor doped with impurities.
10. A process of manufacturing semiconductor devices which
comprises the steps of:
forming a circuit element at one region on one surface of a
semiconductor substrate,
covering the entire surface of the semiconductor substrate with a
first insulating layer,
forming an opening in the first insulating layer to expose a
portion of said one region,
forming a first wiring layer on the first insulating layer, the
first wiring layer being electrically in contact with said circuit
element,
covering the entire surface of the semiconductor substrate, so
treated, with a second insulating layer,
forming a viahole in the second insulating layer to expose a
portion of the first wiring layer for the interconnection between
wiring layers,
forming a deposited layer of metal on the entire surface of the
semiconductor substrate, the deposited layer being thin in the
proximity of the edge of the surface of the second insulation
layer, and the portion of the deposited layer of metal on the
viahole being at a lower level than the portion of the deposited
layer of metal on the second insulating layer, and,
dipping the semiconductor substrate so treated in a bath of an
etching solution wherein electrolytic etching is effected in a
manner such that said portion of the deposited layer of metal on
the second insulating layer is connected as an anode whereby said
portion of the deposited layer on the second insulating layer is
removed and the portion of the deposited layer on the viahole layer
remains substantially unchanged.
11. A process according to claim 10 wherein said semiconductor
structure is further subjected to the steps of:
covering the entire surface of said semiconductor structure with a
third insulating layer,
forming a groove in the third insulating layer to expose at least a
portion of the metal buried in the viahole,
forming a deposited layer of wiring metal on the entire surface of
the semiconductor device, the deposited layer being thin in the
proximity of the edge of the surface of the third insulating layer,
and the portion of the deposited layer of wiring metal on the
groove being at a lower level than the portion of the deposited
layer of wiring metal on the third insulating layer, and,
dipping the semiconductor structure so treated in a bath of an
etching solution wherein electrolytic etching is effected in a
manner such that said portion of the deposited layer of wiring
metal on the third insulating layer is connected as an anode
whereby said portion of the deposited layer on the third insulating
layer is removed and the portion of the deposited layer on the
groove remains substantially unchanged as a second wiring
layer.
12. A process according to claim 10 wherein said circuit element is
transistor.
13. A process according to claim 10 wherein said first insulating
layer consists of silicon dioxide.
14. A process according to claim 10 wherein said second insulating
layer consists of phosphosilicate glass.
15. A process according to claim 10 wherein said first wiring layer
and said coating layer of metal consist of aluminium.
16. A process according to claim 10 wherein said deposited layer of
metal consists of aluminium and said electrolytic etching is
carried out in a bath of aqueous phosphoric acid solution.
17. A process according to claim 11 wherein said third insulating
layer consists of phosphosilicate glass.
18. A process according to claim 11 wherein said second wiring
layer consists of aluminium.
19. A process of manufacturing semiconductor devices which
comprises the steps of:
preparing a semiconductor substrate having an active region of a
circuit element formed on one surface of the semiconductor
substrate and an insulating layer, coated thereon, having at least
one window for exposing portion of said active region,
forming depositing a semiconductor layer on the semiconductor
substrate, the semiconductor layer being thin in the proximity of
the edge of the surface of the insulating layer, and the portion of
the semiconductor layer deposited on the said window being at a
lower level than the portion of the semiconductor layer deposited
on the insulating layer,
dipping the semiconductor substrate so treated in a bath of an
etching solution wherein electrolytic etching is effected in a
manner such that said portion of the semiconductor layer deposited
on the insulating layer is connected as an anode whereby said
portion of said semiconductor layer deposited on the insulating
layer is removed and the portion of the semiconductor layer
deposited on the window remains substantially unchanged, and,
forming a wiring layer on the insulating layer, the wiring layer
being electrically in contact with said semiconductor layer.
20. A process according to claim 19 wherein said semiconductor
layer consists of polycrystalline.
21. A process according to claim 19 wherein said semiconductor
layer consists of polycrystalline doped with impurities.
22. A process according to claim 19 wherein said active region
consists of a base region in which emitter of transistor is formed
by diffusing into said semiconductor substrate impurities doped in
said semiconductor layer.
23. A process according to claim 19 wherein said wiring layer
consists of aluminium.
24. A process of manufacturing semiconductor integrated circuits
which comprises the steps of:
preparing a semiconductor substrate having a buried layer on one
surface of said semiconductor substrate and an insulating layer of
a closed pattern at an isolation region, said insulating layer
encompassing said buried layer,
forming a semiconductor layer by epitaxial growth on the entire
surface of the semiconductor substrate, the portion of the
semiconductor layer deposited on said semiconductor substrate
encompassed by the insulating layer being at a lower level than the
portion of the semiconductor layer deposited on the insulating
layer, the former portion consisting of monocrystalline and the
latter portion consisting of polycrystalline,
dipping the semiconductor substrate so treated in a bath of an
etching solution wherein electrolytic etching is effected in a
manner such that the portion of said semiconductor layer deposited
on the insulating layer is connected as an anode whereby said
portion of said semiconductor layer deposited on the insulating
layer is removed and the portion of said semiconductor layer
encompassed by the insulating layer remains substantially unchanged
to form islands, and
forming a circuit element on the island.
25. A process according to claim 24 wherein impurities are diffused
into the semiconductor layer, prior to the electrolytic
etching.
26. A process according to claim 24 wherein said insulating layer
is formed by the steps of:
forming on the entire surface of the semiconductor substrate a
silicon oxide layer having substantially the same thickness as that
of a semiconductor layer to be formed by epitaxial growth,
forming a silicon nitride layer on the entire surface of said
silicon oxide layer,
patterning said silicon nitride layer in a manner such that said
silicon nitride remains on said isolation region, and then
removing selectively said silicon oxide layer by using said silicon
nitride layer as a mask.
Description
This invention relates to a process for preparing semiconductor
devices, and more particularly to a process for preparing diffused
planar semiconductor structures wherein three regions emitter, base
and collector come to the same planar surface of the semiconductor
device.
Semiconductor devices particularly those having large scale
integrated circuits involve multilayer wirings for the
interconnections to ensure highly densified circuits. In general,
the multilayer wirings involve a silicon dioxide insulating layer
formed on a silicon substrate. The insulating layer has one or more
holes formed therein wherein wirings of the outer adjacent layer
are formed. A metal layer used for such wiring usually includes an
aluminium layer, or layers of chromium-copper-chromium combination,
in view of the adhesion to silicon dioxide and the electric
conductivity. Each of the metal layers and the silicon dioxide
insulating layers usually has a thickness of approximately 1
micron.
However, semiconductor devices involving these multilayer wirings
have some serious problems. When a conductive metal is deposited
onto the semiconductor device by vacuum evaporation the resulting
metal layer is thiner at the top edge of the sides of the holes
formed in the silicon dioxide insulating layer than at the other
portions. This is due to the altitude difference of approximately 1
micron between the bottom of hole and the outer surface of the
insulating layer. Consequently, the metal layer tends to separate
at the top edge of the sides of the hole. Further, when a silicon
dioxide insulating layer having a thickness of approximately 1
micron is formed by chemical vapor deposition on the stripes of
wiring having a thickness of approximately 1 micron, and then other
stripes of wiring are formed on the silicon dioxide insulating
layer in a direction intersecting with the embedded stripes of
wiring, there is a fear that the two stripes of wiring will
short-circuit each other at the points of intersection. This is
because the intermediate silicon dioxide insulating layer is thiner
at the edge of the embedded stripes of wiring than at other
portions. To sum up, multilayer wirings involved in conventional
semiconductor devices do not have a high degree of reliability.
In a planar transistor, the metal of the electrode is contacted
with an emitter through a window formed in the oxidized layer.
However, in the case where the emitter junction is shallow, the
emitter junction tends to be destroyed by the sintering of the
metal of electrode. In order to mitigate or avoid this defect, it
has been proposed to build up a semiconductor material layer by a
selective epitaxial growth process in the window to protect the
emitter against migration phenomena of the metal of electrode.
However, it has been very difficult to stably carry out the
selective epitaxial growth because the limits of the condition at
which semiconductor material is built up are severe.
Further, in the preparation of integrated circuits, a procedure has
been employed wherein an oxide film is formed for dielectric
isolation, i.e., to isolate islands of semiconductor. The formation
of the oxide film is usually carried out by selective oxidation of
a silicon substrate using a masking agent such as silicon nitride.
Thus, a planar surface of the substrate is obtainable. This
procedure is called an "isoplanar" process. In general, the
isoplanar process is accompanied prior to oxidation, by the step of
etching at least the surface portion of the silicon substrate which
is to be oxidized, in order to result in a substantially planar
surface. However, it has been very difficult to strictly control
the amount of silicon etched away for producing a completely planar
surface and the oxidizing of the entire depth of the epitaxial
layer.
Therefore, it is an object of the present invention to provide
semiconductor devices having a far more flattened conductor
surface, over which metal wiring runs, as compared to those of
conventional planar semiconductor structures.
It is another object to provide semiconductor devices involving
metal wiring layers, with the layer on the semiconductor surface
being at substantially the same level as the semiconductor
surface.
It is still another object to provide semiconductor devices
involving metal wiring layers which possess high degrees of
reliability.
It is a further object to provide a process wherein planar
semiconductor devices described above can be manufactured in a
simple and easy way.
In accordance with the present invention, there is provided a
process of manufacturing semiconductor devices which comprises the
steps of:
forming an insulating layer having a closed pattern on one surface
of a semiconductor substrate,
forming a coating layer on entire surface of the semiconductor
substrate, at least a portion of the coating layer deposited on the
insulating layer being conductive, and then
dipping the semiconductor substrate so treated into a bath of
etching solution wherein electrolytic etching is effected in such a
manner that the portion of said coating layer of conductive
material deposited on the insulating layer is connected as an anode
whereby said portion of said coating layer deposited on the
insulating layer is removed and the portion of said coating layer
encompassed by the insulating layer remains.
The term "insulating layer" used herein means a layer consisting of
the material which exhibits a specific electric resistance of
higher than 10.sup.2 times that of the conductive coating layer
deposited on the insulating layer.
One preferred embodiment of the process of the present invention
comprises the steps of:
a. forming a circuit element at one region on one surface of a
semiconductor substrate,
covering the entire surface of the semiconductor substrate with a
first insulating layer,
b. forming an opening in the first insulating layer to expose a
portion of said one region,
c. forming a first wiring layer on the first insulating layer, the
first wiring layer being electrically in contact with said circuit
element,
d. covering the entire surface of the semiconductor substrate, so
treated, with a second insulating layer,
e. forming a viahole in the second insulating layer to expose a
portion of the first wiring layer for the interconnection between
wiring layers,
f. forming a coating layer of metal on the entire surface of the
semiconductor substrate, the portion of the coating layer of metal
deposited on the viahole being at a lower level than the portion of
the coating layer of metal deposited on the second insulating
layer, and then
g. dipping the semiconductor substrate so treated into a bath of
etching solution wherein electrolytic etching is effected in such a
manner that a portion of said coating layer of metal deposited on
the second insulating layer is connected as an anode whereby said
portion of said coating layer deposited on the second insulating
layer is removed and the portion of said coating layer deposited on
the viahole layer remains: and further,
a'. covering the entire surface of said semiconductor structure,
thus obtained, with a third insulating layer,
b'. forming a groove in the third insulating layer to expose at
least a portion of the metal buried in the viahole,
c'. forming a coating layer of wiring metal on the entire surface
of the semiconductor device, the portion of the coating layer of
wiring metal deposited on the groove being at a lower level than
the portion of the coating layer of wiring metal deposited on the
third insulating layer, and then
d'. dipping the semiconductor structure so treated into a bath of
etching solution wherein electrolytic etching is effected in such a
manner that a portion of said coating layer of wiring deposited on
the third insulating layer is connected as an anode whereby said
portion of said coating layer deposited on the third insulating
layer is removed and the portion of said coating layer deposited on
the groove remains as a second wiring layer.
Another preferred embodiment of the process of the present
invention comprises the steps of:
a. preparing a semiconductor substrate having an active region of a
circuit element formed on one surface of the semiconductor
substrate and an insulating layer, coated thereon, having window(s)
for exposing a portion of said active region,
b. forming a semiconductor layer on the semiconductor substrate,
the portion of the semiconductor layer deposited on the window(s)
being at a lower level than the portion of the semiconductor layer
deposited on the insulating layer,
c. dipping the semiconductor substrate so treated into a bath of
etching solution wherein electrolytic etching is effected in such a
manner that a portion of said semiconductor layer deposited on the
insulating layer is connected as an anode whereby said portion of
said semiconductor layer deposited on the insulating layer is
removed and the portion of said coating layer deposited on the
window(s) remains, and then
d. forming a wiring layer on the insulating layer, the wiring layer
being electrically in contact with said semiconductor layer.
Still another embodiment of the process of the present invention
comprises the steps of:
a. preparing a semiconductor substrate having a buried layer on one
surface of said semiconductor substrate and an insulating layer of
a closed pattern at an isolation region, said insulating layer
having a closed pattern and encompassing said buried layer,
b. forming a semiconductor layer by epitaxial growth on the entire
surface of the semiconductor substrate, the portion of the
semiconductor layer deposited on said semiconductor substrate
encompassed by the insulating layer being at a lower level than the
portion of the semiconductor layer deposited on the insulating
layer, the former portion consisting of monocrystalline and the
latter portion consisting of polycrystalline,
c. dipping the semiconductor substrate so treated into a bath of
etching solution wherein electrolytic etching is effected in such a
manner that a portion of said semiconductor layer deposited on the
insulating layer is connected as an anode whereby said portion of
said semiconductor layer deposited on the insulating layer is
removed and the portion of said semiconductor layer encompassed by
the insulating layer remains to form islands, and then,
d. forming a circuit element on the island.
In the preferred embodiment last set forth, impurities may be
diffused into the semiconductor layer, prior to the electrolytic
etching.
Further, in the preferred embodiment last set forth, the
insulating
a. forming on the entire surface of the semiconductor substrate a
silicon oxide layer having substantially the same thickness as that
of a semiconductor layer to be formed by epitaxial growth,
b. forming a silicon nitride layer on the entire surface of said
silicon oxide layer,
c. patterning said silicon nitride layer in a manner such that said
silicon nitride remains on said isolation region, and then
d. removing selectively said silicon oxide layer by using said
silicon nitride layer as a mask.
The invention will now be illustrated by means of the following
examples and by reference to the accompanying drawing.
IN THE ACCOMPANYING DRAWINGS,
FIG. 1 through FIG. 6 are cross sectional views illustrative of one
embodiment of the process of the invention wherein a wiring metal
is buried in an insulating layer,
FIG. 7 and FIG. 8 are cross sectional views illustrative of another
embodiment of the process of the present invention wherein a
semiconductor material is built up, after base diffusion, in a
window for emitter diffusion, and
FIG. 9 through FIG. 15 are cross sectional views illustrative of
still another embodiment of the process of the present invention
wherein a semiconductor integrated circuit is prepared.
EXAMPLE 1
Examples 1 and 2 illustrate one embodiment of the process of the
present invention wherein multilayer wiring is buried in an
insulating layer which provides a planar surface. Example 1 relates
to the first-half step wherein metal material is buried in a
viahole formed in a second insulating layer over which viahole
multilayer wiring passes.
In FIG. 1, a circuit element such as, for example, transistor is
formed at one region one one surface of a semiconductor substrate 1
by preferably using a diffusion technique. A first insulating layer
2 is formed the entire surface of the semiconductor substrate 1. An
opening is formed in the first insulating layer 2 to expose a
portion of the region. The first insulating layer consists of, for
example, silicon dioxide. Then, a first aluminium wiring layer 3 is
formed on both the insulating layer 2 and the portion of the
semiconductor substrate 1 not covered by the first insulating
layer. Thus, the first insulating layer is electrically contact
with the circuit element. The first aluminium wiring layer 3 is
covered with a second insulating layer 4. This layer is, for
example, phosphosilicate glass layer 4 having a thickness of 1
micron. Finally, a viahole 5, for connecting wiring layers, is
formed by a photo-etching process.
In FIG. 2, aluminium is deposited by a vacuum evaporation process
on the entire surface to form an aluminium coating layer 6 of a
thickness of 1 to 1.5 micron. The portion of the aluminium coating
layer 6 deposited on the viahole 5 is at a lower level than the
portion deposited on the second insulating layer 4.
The semiconductor substrate so treated is dipped in a bath of
aqueous phosphoric acid solution maintained at a temperature of
approximately 30.degree.C, wherein electrolytic etching is carried
out in the following manner. The coating layer of aluminium 6 is
deposited on the second insulating layer 4 connected as an anode. A
platinum plate located in said solution confronts said substrate at
a distance maintained within the range from 10 to 100 cm. Thus, the
platinum plate is connected as a cathode, and the electrolytic
etching of the aluminium 6 is carried out with a direct current at
a constant voltage of 1.2 volt.
In this example, aluminium 6 is etched away at a rate of 2,500 to
3,000 angstrom minute. In contrast, etching is carried out only at
a rate of approximately 150 angstrom/minute, in chemical
etching.
As the electrolytic etching proceeds, a part of the aluminium layer
deposited in the viahole 5 is separated from the other part
deposited on the second insulating layer 4, as shown in FIG. 3.
After this separation, the part of the aluminium layer in the
viahole 5 is not subjected to electrolytic etching but merely to
chemical etching.
However, the electrolytic etching of the part of the aluminium
layer 6 deposited on the second insulating layer 4 is continued.
This electrolytic etching takes place so rapidly that the part of
the aluminium layer 6 deposited on the second insulating layer 4
has entirely disappeared from the surface when a substantial part
of the aluminium in the viahole 5 still remains therein. The
electrolytic etching is continued until the etching current
exhibits a sudden decrease which means the completion of the
removal of the aluminium layer 6.
Aluminium, thus buried in the viahole 5, provides a substantially
planar surface on which a second aluminium wiring layer is to be
coated. This aluminium in the viahole 5 allows a second wiring
layer to be firmly and effectively connected to the first wiring
layer 3. The preparation of the second wiring layer will be
illustrated in the succeeding example.
In this example, only aluminium is illustrated. However, other
metals may also be buried in the viahole with satisfactory
results.
EXAMPLE 2
This example illustrates a step succeeding the step described in
Example 1. This step involves the flattening of a multilayer wiring
layer wherein a metal for wiring is buried in a third insulating
layer in such a manner that the surface of the metal buried is at
substantially the same level as that of the third insulating
layer.
In FIG. 4, after the aluminium 6 is buried in the viahole 5, the
entire surface is covered with the third insulating layer 7 by
chemical vapor deposition. This layer is, for example, a
phosphosilicate glass layer having a thickness of 2 micron. In the
third insulating layer 7 a groove 8, having a pattern corresponding
to that of a second wiring layer to be formed, is formed as shown
in FIG. 5. Thus, at least one portion of the metal buried in the
viahole 5 is exposed.
Thereafter, aluminium is deposited by vacuum evaporation on the
entire surface to form an aluminium coating layer (not shown in the
figure) having a thickness of 2.0 to 2.5 micron. The portion of the
aluminium coating layer deposited on the groove 8 is at a lower
level than the portion deposited on the third insulating layer 7.
Then, electrolytic etching of the aluminium layer is carried out in
the same manner as described in Example 1 with reference to FIGS. 1
through 3. As etching proceeds, the portion of the aluminium
deposited in the groove 8 is separated from the other portion
deposited on the third insulating layer 7. After the separation,
only the portion of the aluminium deposited on the third insulating
layer 7 is rapidly etched and finally, completely removed. Thus,
the portion of the aluminium remaining in the groove 8 provides the
second aluminium wiring layer 9, the surface of which is
substantially the same level as that of the third insulating layer
7, as shown in FIG. 6.
If the preparation of a third, a fourth or more succeeding wiring
layers is required, the above procedure may be repeated. In other
words, the following steps may be repeated. First, the
semiconductor substrate is covered with an insulating layer, and
then a viahole is formed at the position in the insulating layer in
which interconnection between wiring layers is to be formed. The
insulating layer is, for example, phosphosilicate glass layer.
Secondly, aluminium is deposited onto the entire surface, and then
the aluminium is etched away by an electrolytic etching procedure,
except for the portion of aluminium deposited in the viahole.
Thirdly, an insulating layer, for example, a phosphosilicate glass
layer is again coated on the surface and then, a groove having a
pattern corresponding to that of the succeeding wiring layer is
formed. Finally, aluminium is buried in the groove in a similar
manner as in the second step above.
EXAMPLE 3
This example illustrates another embodiment of the process of the
present invention. After a base diffusion, semiconductor material
is built up by expitaxial growth in window(s) formed in an oxidized
surface layer for emitter diffusion so as to provide a planar
surface ready for contact with a wiring metal.
In FIG. 7, a base 11 is formed in the silicon substrate 10 by a
conventional selective diffusion procedure. Then a window 13 for
emitter diffusion is opened in an insulating layer (oxidized
surface layer) 12 at the position where the emitter is to be
diffused into the base 11. A layer of semiconductor such as
polycrystalline silicon 14 doped with a large amount of phosphorous
is then formed on the whole surface. The portion of the
semiconductor layer 14 deposited on the window 13 is at a lower
level than the portion deposited on the insulating layer 12. This
formation of the layer of polycrystalline silicon 14 is preferably
effected by decomposing monosilane (SiH.sub.4) and phosphine
(PH.sub.3 ) in a furnace at a temperature of 600.degree.C to
700.degree.C. The gaseous components so generated by such heat
decomposition are condensed on the surface of the silicon substrate
in the furnace to build up the polycrystalline silicon. In this
step, a large amount of phosphorous can be doped into the
polycrystalline silicon in excess of the solubility limit.
As a modification of this step, single crystals of silicon may be
built up in the window 13 in substitution for the polycrystalline.
This can be achieved by heating the furnace at a temperature of
1100.degree.C to 1200.degree.C. Through this step, polycrystalline
silicon is built up on the oxidized layer 12.
Then, the silicon substrate so treated is dipped in a bath of
etching solution wherein electrolytic etching is effected in such a
manner that a portion of the polycrystalline silicon layer 14
deposited on the insulating layer 12 is connected as an anode. The
etching solution is prepared for example, by mixing 8 percent by
weight of aqueous phosphoric acid having a concentration of 85
percent or more; 2 percent by weight of aqueous hydrofluoric acid
having a concentration of 47 percent or more; and, 90 percent by
weight of water. Alternatively, the etching solution may be
prepared by mixing 100 parts of 99 percent aqueous acetic acid, 10
parts of 62 percent aqueous nitric acid, and 1 part of 50 percent
aqueous hydrofluoric acid all by weight. The temperature of the
bath is preferably maintained at 35.degree.C.
The polycrystalline silicon 14 deposited on the insulating layer 12
is easily etched away at a rate of 1000 to 2000 angstrom/minute
through electrolytic etching. However, as the electrolytic etching
proceeds the polycrystalline silicon (or single crystals of silicon
in the modified step) remaining in the window 13 is subjected to
little or no etching after it is separated from the polycrystalline
silicon deposited on the insulating layer 12. Thus, flattening is
effected. This procedure is similar to that described in Example 1
with reference to FIGS. 1 through 3.
The silicon substrate so treated is then heated, whereby
phosphorous in the polycrystalline silicon (or single crystals of
silicon) remaining in the window 13 is diffused into the silicon
substrate to form an emitter, as shown in FIG. 8. Thereafter, a
metal 15 for wiring is deposited on the flattened surface.
In this planar semiconductor device, the polycrystalline silicon,
or the single crystals, in the window 13 is interposed between the
wiring metal 15 and the emitter junction, as an intermediate
conductor which connects the wiring metal with the emitter.
Therefore, the wiring metal 15 does not reach the emitter junction
even though the wiring metal diffuses into the intermediate
conductor.
The planar semiconductor structure illustrated above is
particularly useful as semiconductor devices possessing shallow or
narrow junctions, such as high frequency transistors.
EXAMPLE 4
This example illustrates a step of flattening a semiconductor
surface of the semiconductor integrated circuit. This step is
concerned with an improved "isoplanar process" wherein no selective
oxidation is utilized.
In FIG. 9, a buried layer 17 of N-type is formed on one surface of
a semiconductor substrate 16 of P-type by the diffusion of antimony
at a high concentration.
In FIG. 10, an insulating layer, e.g. a silicon dioxide layer, 18
of a closed pattern is formed at an isolation region, for example,
by a thermal oxidation technique. The thickness of the insulation
layer is from 2 to 3 micron. It is apparent that the selective
oxidation technique is not applied. For example, a layer of silicon
dioxide having a thickness of 2.2 micron can be formed by heating
the silicon semiconductor substrate in a furnace at a temperature
of 1250.degree.C over a period of 310 minutes while steam of
100.degree.C is blown thereinto.
In FIG. 11, the insulating layer is subjected to photoetching in a
way that a portion of the silicon dioxide remains only at the
isolation region. The isolation region has a closed pattern.
In FIG. 12, then, a semiconductor 19 (e.g. N-type silicon layer
having a thickness of 2.5 to 3.5 micron) is formed. A conventional
epitaxial growth technique using monosilane may be applied to form
the silicon layer. Single crystals 20 of silicon and
polycrystalline silicon 21 are connected on the silicon substrate
and on the insulating layer (silicon dioxide) 18, respectively,
under ordinary conditions of the epitaxial growth.
In FIG. 13, an island of the single crystal 20 is separated from
the many other islands 20 laid on a surface of the silicon
substrate. This separation is realized by means of electrolytic
etching of the present invention, wherein the polycrystalline 21 is
etched away in the same manner as described in Example 3. It will
be apparent from FIG. 13 that isolation of the single crystal 20 is
ensured by both the silicon dioxide layer 18 of a closed pattern
and the P.N. junction previously formed between the single crystal
20 and the semiconductor substrate.
In FIG. 14, the silicon semiconductor substrate so treated is then
subjected to thermal oxidation to form a silicon dioxide layer 22
on each silicon single crystal layer 20. This silicon dioxide layer
22 is at substantially the level of the surface of the silicon
dioxide layer 18. Thereafter, a circuit element is formed (not
shown in FIG. 14) on each isolated single crystal island 20,
wherein the silicon dioxide layer 22 described above is used as a
mask against diffusion.
In this Example, the formation of the silicon dioxide layer 18
having a closed pattern as illustrated in FIG. 11 may also be
carried out by etching, using a silicon nitride mask 23 as shown in
FIG. 15. In accordance with this procedure, the succeeding
separation of the silicon single crystal layer 20 by electrolytic
etching may be easily carried out because of the silicon nitride
layer 23 deposited on the top of the silicon dioxide layer 18 as
shown in FIG. 15.
In this example, prior to the electrolytic etching illustrated in
FIG. 12, impurities such as, for example, phosphorous may be
diffused into the silicon semiconductor layer 19 at a high
concentration. This pre-treatment has an advantage that the portion
21 of the silicon semiconductor layer 19 deposited on the
insulating layer (silicon dioxide layer) 18, i.e., the portion
comprising polycrystalline silicon, is etched away far more rapidly
as compared to the portion 20 comprising single crystals of silicon
deposited on the silicon semiconductor substrate 16, and therefore,
separation of the single crystal layers 20 is readily achieved.
This is because the diffusion velocity of phosphorous into the
polycrystalline silicon 21 is twice or three times that into the
single crystals 20. This pre-treatment is advantageously applied to
the etching of the silicon layer particularly one having a high
specific resistance, e.g., of several ohm-cm or more.
Although the invention has been illustrated with a high degree of
particularity, it is understood that the disclosure has been made
only by way of example and is not to be considered as limiting in
any sense.
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