Time Accumulator Man-hours Expended

Abstract

The device is for accumulating the time expended by a predetermined number of workers over any selected time interval, and continuously displaying a cumulative reading. The device may comprise a plurality of separate accumulator banks each having a multiple switch array, each said switch corresponding to the predetermined number of workers, a power on-off switch, a switch for enabling counting at either regular time or time and one-half, and a resetable display for registering accumulated time preferably in increments of a tenth of an hour. The time accumulation is continuous as long as the device is operating and whether the predetermined number of workers increases or decreases.

Description

FIELD OF THE INVENTION

The present invention relates in general to a time accumulator or clock. More particularly, this invention relates to a time accumulator for registering man-hours expended by a predetermined number of workers over a selected time period, wherein said predetermined number is alterable.

BACKGROUND OF THE INVENTION

Electronic clocks for accumulating time are generally known. These clocks may be used by an individual by setting the clock at the commencement of a job, to determine the number of hours expended by the individual in completing the job. Clocks of this type are adequate when monitoring a single individual, however, a problem arises when there are many workers assigned to a particular task. It is a common procedure to have each of the workers fill out a time card which designates the amount of hours previously expended by the individual workers on a particular job. If the manager of the job then desires to determine the total hours expended to date on the job it is necessary to add up the hours expended by each individual. This becomes a laborious task and many times the hours recorded by the worker are not completely accurate. Also, it is quite possible that some of the time that is expended is not at the normal rate and if some of the work is expended at, for example, a time and one-half rate then this as to be taken into account which further complicates the task of arriving at a total number of man-hours expended.

The problem is complicated still further when one particular manager is required to handle a number of different jobs.

Accordingly, one object of the present invention is to provide a device for accumulating the time expended by a predetermined number of workers over a preselected time interval.

Another object of the present invention is to provide a time accumulating device that can be used for monitoring the man-hours expended on a number of different jobs or tasks.

A further object of the present invention is to provide a device in accordance with the preceding objects and that is provided with means for accumulating time at a rate other than the normal time rate, such as at a time and one-half rate.

Still a further object of the present invention is to provide a device that can be used by a manager for keeping track of a number of jobs that he is responsible for and for displaying a cumulating total of hours expended on each particular job.

Another object of the present invention is to provide a device in accordance with the preceding object and that cumulatively counts in time increments that vary be virtue of an increase or decrease in the predetermined number of workers.

SUMMARY OF THE INVENTION

In accordance with the present invention there is provided an accumulator for registering man-hours expended. This accumulator generally comprises means for providing a basic clock signal at a predetermined repetition rate, means for generating from said basic clock signal a plurality of different frequency signals, a counter means including means for displaying a cumulative count, and selection means including a plurality of switch means, each said switch means being mutually exclusively operable for selectively coupling one of said different frequency signals to the counter means.

In the disclosed embodiment, the basic clock signal is derived from the conventional AC line and the selection means includes a switch array having a number of switches mechanically intercoupled so that only one switch at a time can be operated.

In accordance with one of the features of the present invention, there is provided logic means for enabling counting at a time and one-half rate when so desired. In the present invention, this feature is implemented by causing the generation of an extra count pulse every other time a pulse is directed to the counter.

In accordance with another aspect of the present invention, there is disclosed an embodiment of the invention that is partially electronic and partially mechanical using optical techniques disclosed in more detail hereinafter.

BRIEF DESCRIPTION OF THE DRAWINGS

Numerous other objects, features and advantages of the invention should now become apparent upon a reading of the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a perspective view showing one embodiment for the accumulator of the present invention employing only one accumulator bank;

FIG. 2 shows the count pulse circuitry partially in block form of the present invention;

FIG. 3 is a logic circuit diagram showing primarily the circuit for providing different counting rates;

FIG. 4 shows various waveforms associated with the circuitry of FIGS. 2 and 3; and

FIG. 5 shows an alternate electro-optical arrangment for a portion of the circuitry shown in FIG. 2.

DETAILED DESCRIPTION

FIG. 1 shows a time accumulator of the present invention in a perspective view including a housing structure 10 that may be provided with a plurality of time accumulator banks 12 only one of which is shown in FIG. 1. Each bank includes a power on-off switch 14, a time rate switch 16, a multi-switch array 18, and a display panel 20. The switch 16 is for selecting time accumulating at either a normal rate or a time and one-half rate, for example. It would also be within the scope of the present invention to provide a switch 16 having more than two postions so that for example a double time rate could also be accumulated.

The multi-position switch 18 preferably includes ten mutually exclusively operated switches 22, each said switch corresponding to the number of persons assigned to the particular job then associated with bank 12. The display panel 20 includes a display window 24 which displays accumulated time at a rate of tenths of an hour, for example. The display panel 20 also includes a reset button 26 for resetting the panel at the commencement of a job.

The apparatus shown in FIG. 1 may also include other banks for keeping track of other jobs. These other banks would be susbstantially identical to the one shown in FIG. 1.

Reference is now made to FIGS. 2 and 3 which show a specific circuit configuration for providing the time accumulation. FIG. 2 shows the circuit means including power supply means for establishing discrete count pulse lines. FIG. 3 shows the switch array 18 for selecting the desired count pulse line and logic circuit means for providing either a normal count rate or a time and one-half count rate. The circuitry shown in FIGS. 2 and 3 may be readily contained within the structure shown in FIG. 1.

FIG. 2 shows the power plug 28 which connects by way of fuse 29 and power on-off switch 14 to the primary winding of transformer T1. The secondary winding of transformer T1 includes a number of taps which selectively couple to diodes CR1-CR3. The cathode of diode CR1 establishes a high voltage DC level that may be used to activate the counter shown in FIG. 3. The diodes CR2 and CR3 form a full-wave bridge circuit and the commonly tied cathodes of these diodes couple by way of diode CR4 to power supply 30. Diode CR4 is important in that it prevents capacitor C from discharging into transistor Q2 and references line 38 to about zero volts. Power supply 30 may be of conventional design and is shown in FIG. 2 as primarily comprising integrated circuit power supply device 32 and transistor Q1. The device 32 may be of the type sold by National Semi-Conductor and designated as their series LM300 device.

Transistor Q1 increases the current capability of device 32. Power supply 30 which also includes biasing resistors and coupling capacitors, as shown, establishes a DC voltage level of plus 5 volts on line 34. This 5 volt level is used in the circuit shown in both FIGS. 2 and 3, as indicated.

The cathodes of diodes CR2 and CR3, which represent the full-wave signal, also couple by way of line 38 and resistor 39 to the base of transistor Q2, rendering transistor Q2 conductive for the majority of the AC waveform, and non-conductive as the AC signal approaches zero potential. The waveforms shown in FIG. 4 are representative of certain points shown in the circuits of FIGS. 2 and 3. FIG. 4 shows the typical 60 cycle signal, the full-wave signal, and the pulse output from transistor Q2. As the AC signal goes to ground transistor Q2 turns off causing its collector to go positive. The pulse signal occurs at a 120 pulse per second rate, and is the pulse which initiates the entire counting down operation.

As previously indicated, it is probably most desireable to record time at tenths of an hour intervals. Accordingly, it is necessary to divide the pulse output from transistor Q2 down to a much lower frequency. For that purpose, FIG. 2 includes divider devices 40, 41, 42, 43, 44, and 45. Each of these devices is of conventional design and receives power from the five volt line. Device 40, for example, which is a divide by ten device, simply provides one pulse output for every ten pulse inputs from transistor Q2. The devices 40-45 may typically include a bistable counting circuit and associated gating means for providing the appropriate number of pulses in dependence upon the number of pulses occurring at the input.

The device 41 is also a divide by 10 device and devices 42 and 43 are each divide by three devices. Accordingly, the pulse rate on line 46 occurs at a rate of 8 pulses per minute or 480 pulses per hour. This rate is determined by dividing 120 pulses per second by 900 which is in turn the division created by the devices 40, 41, 42 and 43.

The pulse rate on line 46 of 8 pulses per minute or 48 pulses per one-tenth hour is coupled to divider device 44 which is also of conventional design and includes three output lines 48, 50, and 52. The output line 48 is a divide by six line providing a pulse repetition rate of 8 pulses per one-tenth hour. Line 50 is a divide by 12 line which provides a pulse rate of 4 pulses per one-tenth hour. Line 52 is also a divide by 12 line which is coupled to the remaining divider device 45. The divider device 45 includes output lines 54 and 56. Output line 54 is a divide by two line which generates a pulse repetition rate of 2 pulses per one-tenth hour. Output line 56 is a divide by four line which generates a one-pulse per one-tenth hour pulse rate.

FIG. 4 shows the pulses on these output pulse lines 48, 50, 54, and 56. For example, the waveform shown on line 50 is derived from the waveform on line 48 wherein the waveform of line 50 goes through a transition each time the waveform on line 48 goes through a negative transition.

The circuit shown in FIG. 2 also includes differentiators 49, 51, 55, and 57, each of which typically includes a capacitor and resistor and each of which is connected to the respective lines 48, 50, 54 and 56. The circuits 49, 51, 55 and 57 differentiate the positive going transitions occurring on their respective lines. The differentiated outputs from lines 48, 50, 54 and 56 couple to the diode matrix 60 of FIG. 2. The diode matrix 60 receives the differentiated signals on lines 62, 63, 64 and 65 and combines the signals to provide a plurality of discrete outputs which are shown in FIG. 2 as discrete outputs 01 through 012.

As an example, let us consider the output that is generated on line 05. The pulse train on line 50 couples by way of differentiator 51 to line 63 and from there to diode CR8. Another pulse train is differentiated by circuit 57 and passes to diode CR9. The output 05 is thus a combination of pulses as depicted in FIG. 4 wherein the pulses A are generated from positive-going transitions on line 50 and the pulses B, which are interleaved with the pulses A, are generated from positive-going transitions on line 56.

In FIG. 4 one particular sequence of waveforms on lines 48, 50, 54 and 56 has been shown wherein the toggling occurs on the negative-going transition. Obviously, the toggling could have occurred on the positive-going transition. If the toggling occurs on the negative-going transition then the positive transition is differentiated in order to provide the proper pulse combination. If the toggling occurs on the positive transition then the negative transition is differentiated to obtain the proper combination of pulses.

The diode matrix 60 also includes a plurality of other diodes which are selectively coupled to the lines 62 through 65. These lines are appropriately designated by the corresponding binary notations 8-4-2-1. Thus, for example, the output 011 is a combination of the output pulses from binary lines corresponding to the binary numbers 1, 2, and 8 in a binary coded decimal (BCD).

The outputs 01-012 are coupled to the switch array 18 shown in FIG. 3.

FIG. 3 shows, in addition to the switch array 18, a logic circuit for providing either a normal counting rate or a selectable time and one-half counting rate. The switch array 18 includes a plurality of switches 22 as shown in FIG. 1 each of which is a simple on-off switch. The array is preferably mechanically interconnected so that not more than the particular one of the switches 22 corresponding to a number of workers can be closed at any one time. The outputs 01-012 from FIG. 2 couple to the moveable contacts of each of the corresponding switches 22 shown in FIG. 3. The fixed contacts of the switches 22 couple in common to line 73.

Thus, depending upon which of the switches 22 is closed one of the output signals 01-012 is coupled to line 73. If, for example there are five workers, it is the signal 05 that is coupled to line 73, as shown in FIG. 4, and there are five pulses created in the one-tenth hour basic time cycle. These pulses are fed by way of line 73 and resistor 63 to transistor Q3. These pulses are positive pulses that cause transistor Q3 to conduct during the duration of the pulse, and to be non-conductive between pulses. The output or the collector of transistor Q3 couples to substantially identical timing circuits 64 and 70. FIG. 4 shows waveforms associated with the circuitry of FIG. 3 and in particular with the timing circuits 64 and 70.

The circuit 64 includes NAND gate 65 and 66, timing capacitor 67 and transistor 68. When there is no pulse yet present on line 73 the output of transistor 63 is at its high level, the output of gate 65 is at its low level and there is no charging of capacitor 67 by way of resistor 69. However, when a negative-going pulse occurs at the collector of transistor Q3, gate 65 has a high output and capacitor 67 charges by way of resistor 69 to the low output provided at the output of gate 66. The interconnecting lines from the outputs of gates 65 and 66 to the opposite inputs provide a latching arrangement wherein the output of gate 66 stays at its low level even after the pulse at the collector of transistor Q3 terminates. The circuit 64 may conventionally be termed a one-shot circuit.

The voltage across capacitor 67 is initially zero volts and when the output of gate 65 goes high transistor 68 immediately conducts. After a time determined by the value of capacitor 67 and resistor 69, transistor 68 can no longer sustain its conduction and the output of gate 66 reverts to its low level. This in turn causes the output of gate 65 to revert to its low level thereby terminating the pulse on output line 71. A waveform in FIG. 4 shows the output from circuit 64 as having a pulse of a width on the order two seconds, for example. This width is determined by the value of capacitor 67 and resistor 69.

The circuit 70 is substantially identical to circuit 64 with the exception that its capacitor 72 is of a smaller value. FIG. 4 shows the output of circuit 70 which is a pulse of shorter duration and may be on the order of one-half second long.

The signal at the collector of transistor Q3 is also coupled by way of lines 75 to flip-flop 76, and the line 75 serves as a clock input line for the flip-flop 76 and line 79 serves as and an assertion output 79 which couples to a moveable contact of switch 16. The flip-flop 76 changes state each time a pulse is received on line 75 and thus the output on line 79 switches between its high and low level as each pulse is received by the flip-flop 76. If the switch 16 is closed then this alternating signal on line 79 is coupled to logic gate 80. The signal on line 79 controls the time and one-half counting, generating an extra count pulse for every other pulse sensed by transistor Q3.

FIG. 3 shows one NAND gate 84 which is used to combine the output signals from circuit 64 and 70. The output of gate 84 is shown in FIG. 4 and is essentially the inversion of the output pulse from circuit 70. Thus, when the output of gate 84 goes to its low level this causes the output of inverter gate 85 to go to its high level causing transistor Q4 to conduct thereby generating a current through counter coil C1 causing a counter-increment. This increment is specifically identified in one-tenths of an hour per pulse.

The logic operates so that if switch 16 is opened because counting is only to take place at a normal rate then the output of gate 80 is always high and the output of gate 86 is always low thereby preventing any conduction of transistor Q4 by way of the gates 80 and 86. However, when switch 16 is closed the bottom input to gate 80 can either be high or low depending upon the condition of flip-flop 76. The sensing of the state of flip-flop 76 occurs on the trailing edge E of the output of circuit 64. When the signal on lines 71 thus reverts back to ground this ground-going signal is passed by way of diode 89 to the input of circuit 70 causing circuit 70 to relatch which in turn generates a second output pulse as depicted in FIG. 4. If the output of flip-flop 76 is high during the time that the second pulse appears then the output of gate 80 is low, the output of gate 86 is high and an additional count is created.

On the other hand, if the output of flip-flop 76 is low then no additional count is generated during the second time that circuit 70 is enabled. The net effect of including switch 16 and flip-flop 76 is to provide an extra count pulse for every other pulse received by transistor Q3 thereby counting at a time and one-half rate.

FIG. 5 shows an electro-optical arrangement which may be substituted for the divider chain shown in FIG. 2. This arrangement shows an aperture plate 90 having a light source 92 disposed thereabove. The aperture plate includes coaxially arranged aperture sets including one, two, four, and eight concentrically disposed apertures. It is noted that the apertures are radially non-coincident so as to provide the proper pulses. Located below each aperture set is a corresponding sensing transistor identified in FIG. 4 as transistors 91, 92, 93 and 94. The outputs of these transistors coupled to a shaper circuit 95 and the output of the shaper circuits is the equivalent of the outputs developed on lines 62, 63, 64 and 65 shown in FIG. 2.

Having described a limited number of embodiments of this invention, it should now be apparent that numerous modifications can be made therein without departing from the spirit and scope of this invention. For example, a number of accumulator banks can be used, some of which may be disposed remotely from others. Also, many different rates can be accommodated such as double or triple time rates. Moreover, the device can be used to accumulate with one predetermined number of workers, and the time accumulation can readily continue when the number of workers changes to either more or fewer workers.

Claims

Having thus described the invention what we desire to claim and secure by Letters Patent is:

1. An accumulator for registering time expended by one or more operating units, which accumulator comprises;

means for establishing a plurality of different frequency signals, each of which signals is representative of a particular number of operating units,

counting means including means for visually displaying a cumulative count corresponding to expended time,

and selection means including a plurality of mutually exclusive switch means that individually correspond to a different one of said frequency signals and are individually employed for coupling a corresponding one of said frequency signals to the counting means.

2. The accumulator of claim 1 for registering time in man-hours expended wherein said display means indicates time expended in time intervals as small as fractions of an hour.

3. The accummulator of claim 1 including means for permitting said counting means to count at a time and one-half rate or higher.

4. The accummulator of claim 3 wherein said permitting means includes a switch for inhibiting or enabling said permitting means, said permitting means being coupled between said selection means and counting means.

5. The accummulator of claim 4 wherein said permitting means includes first and second timing circuits and a bistable device, said frequency signal being represented by a repetitive pulse which is coupled to said bistable device.

6. The accummulator of claim 5 wherein said first and second timing circuits each include mono-stable multivibrators, said first timing circuit having a longer output pulse width than said second timing circuit.

7. The accummulator of claim 6 including a first gate responsive to the outputs of both said multivibrators for passing a signal to said counting means during the period that both output pulses are present.

8. The accummulator of claim 7 including means coupled from the first timing circuit to the input of the second timing circuit for generating a second output pulse from the second timing circuit at the termination of the output pulse of the first timing circuit.

9. The accummulator of claim 8 including a second gate responsive to the output of the second timing circuit and the bistable device for passing a singal to said counting means during the period of said second output, but only when said bistable device is in one of its states.

10. The accummulator of claim 1 including means for providing a basic clock signal from which said plurality of different frequency signals are derived.

11. The accummulator of claim 1 wherein said means for establishing said plurality of different frequency signals includes means for providing a plurality of different binary pulse trains each successive train of a higher frequency.

12. The accummulator of claim 11 including means for combining at least two of said pulse trains to provide said different frequency signals.

13. The accummulator of claim 12 wherein said pulse trains are synchronized on the leading edge of the pulses and said combining means includes means responsive to the trailing edge to provide a different frequency signal that is not synchronous.

14. The accummulator of claim 13 wherein said combining means includes a diode matrix.

15. The accumulator of claim 11 wherein said means for providing a plurality of different binary pulse trains includes a plate having concentric apertures, a light source disposed on one side of said plate, and a plurality of photo-detector means, disposed on the other side of said plate and periodically responsive to light passing through the apertures in the plate.

16. The accumulator of claim 1 wherein said counting means continues to count cumulatively even when another of said switch means is selected.