Device For Use In Varying Output Voltage

Abstract

A condenser is connected between the ground and the gate of a MOS type field effect transistor, while the base of an NPN transistor is connected to the source of the FET. The base of a PNP transistor is connected to the drain of the FET. When the condenser is charged and thus the gate potential of the FET is increased, then the potential at a first output terminal connected to the collector of the PNP transistor will be increased, while the potential at a second output terminal connected to the NPN transistor will be lowered. When the gate potential of the FET is lowered, then the potential at the first and second output terminals will be varied in the reverse fashion to that described earlier. Accordingly, the gradual variation in the charged level of the condenser may provide a gradual variation in the voltage across both of the output terminals.

Description

BACKGROUND OF THE INVENTION

This invention relates to a device for use in varying the output voltage, and more particularly, to a non-contact type device for use in gradually varying an output voltage.

Hitherto, a variable resistor is generally known as a device for use in varying an output voltage. However, such a device possesses inherent limitations because of the use of mechanical contacts and, in addition, fails to serve a useful function for some applications, as the case may be.

SUMMARY OF THE INVENTION

It is accordingly an object of the present invention to provide a device which is useful for varying an output voltage and is simple in construction as well as positive in operation.

According to the present invention, a condenser is connected between the ground and the gate of the MOS type field effect transistor (which will be referred to as FET hereinafter). The base of an NPN transistor is connected to the source of the aforesaid FET and the base of a PNP transistor is connected to the drain of the aforesaid FET. The output from the device of the invention may be obtained between one terminal which is connected to the collector of the aforesaid PNP transistor and another terminal which is connected to the collector of the aforesaid NPN transistor.

When the gate potential at the aforesaid FET is increased, with said condenser being charged, then the potential at the output terminal of the aforesaid PNP transistor will be increased, while the potential at the output terminal of the aforesaid NPN transistor will be lowered. If the gate potential at the aforesaid FET is lowered, then the potentials at the respective output terminals will be varied in the reverse fashion to that described previously. Accordingly, the variation in the charge level of the condenser described may result in the variation in the voltage appearing between the both output terminals.

These and other objects, features and advantages of the invention will be apparent from the ensuing description taken in conjunction with the accompanying drawing and an embodiment which will be described hereinafter .

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an electric circuit of an output-voltage-variable device as used in one embodiment of the invention;

FIG. 2 is a plot showing the relationship of the voltage variation to the gate voltages of the MOS type field effect transistor at the points A and B shown in FIG. 1;

FIG. 3 is a plot showing characteristics of a collector current versus those of the base current of a PNP transistor;

FIG. 4 is a plot showing characteristics of a collector current versus those of a base current of a NPN transistor; and

FIG. 5 is a plot showing the voltage variation appearing at the output terminals, as the gate voltage at the MOS type field effect transistor is varied in the circuit of FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring now to FIG. 1, shown at 1 and 2 are a positive and a negative terminal which are connected to the positive and negative electric power sources (not shown), respectively. Designated at 3 is a central terminal adapted to contact with, or to be detached from the aforesaid contacts 1 and 2. Shown at 4 is an input resistor which is interposed between the central terminal and the gate of a MOS type FET 5. Represented by 6 is a non-polar condenser, one end of which is connected to the gate of the aforesaid FET 5 and the other end of which is connected to the ground. Shown at 7 is a drain resistor connected between a D.C. electric power source V.sub.D and the drain of the transistor 5, and at 8, an output resistor connected between the source of the transistor 5 and the ground. Shown at 9 is a NPN transistor, whose base is connected through a resistor 10 to the source of the MOS type FET, while the collector thereof is connected through a resistor 11 to the aforesaid D.C. electric power source V.sub.D, and the emitter thereof is grounded. Shown at 12 is a PNP transistor, whose base is connected through a resistor 13 to the drain of the MOS type FET, while the emitter thereof is connected to the D.C. electric power source V.sub.D, the collector thereof being grounded via a resistor 14. Designated at 15 is an output terminal provided on the collector side of the transistor 9, and at 16, an output terminal provided on the collector side of the transistor 12.

In operation, when the MOS type FET 5 remains in a cut-off condition, the potential at the point A on the drain side of the transistor 5 will be the potential at the voltage of the D.C. source V.sub.D, since there is no current-flowing through the resistor 7. On the other hand, the potential at the point B on the source side of the transistor 5 will be zero, because there is no current-flowing through the resistor 8.

Subsequently, when the central terminal 3 is connected to the positive terminal 1 and thus +V.sub.i is applied to the circuit, then the condenser 6 will be charged through the input resistor 4. When the condenser 6 is thus charged, i.e., when the gate voltage of the MOS type FET 5 is increased, then the current will flow from the drain side of the transistor 5 to the source side thereof, commensurate to the gate voltage generated. As a result, the potential at the point A on the drain side of the FET 5 will be lowered below the potential at the D.C. electric power source V.sub.D, due to the voltage drop caused by the current-flowing through the resistor 7. Meanwhile, the potential at the point B on the source side of the FET 5 will be increased to a higher level from zero due to the current-flowing through the resistor 8. When the central terminal 3 is brought into an off-condition at an arbitrary time under such conditions, then the current flow through the resistor will be interrupted, thereby maintaining constant the electric charge which has been accumulated in the condenser thus far. In other words, this maintains at a constant value, the potential difference between the points A and B.

In the subsequent step, when the central terminal is connected to the negative terminal 2 and thus -V.sub.i is applied to the circuit, then the electric charge in the condenser 6 will be decreased, i.e., the gate voltage at the MOS type field effect transistor 5 will be lowered, while the current will be decreased in amount until the transistor 5 is brought into a cut-off condition. This then causes the potential at the point A to increase up to the voltage V.sub.D at the D.C. electric power source, while lowering the potential at the point B to zero potential. At an arbitrary time during the aforesaid course of operation, when the central terminal 3 is set to the offposition, then the potentials at the points A and B will be maintained to given values, commensurate to the voltages thus generated.

It follows then that the drain current may be set to a position between the cut-off condition and the saturated condition of the MOS type FET 5, by applying +V.sub.i or -V.sub.i voltage to the central terminal 3 or by bringing the central terminal 3 into an off-condition. Now, suppose that the resistances of the resistor 7 and resistor 8 be R.sub.7 and R.sub.8 are of equal values and that the internal resistance (r) at the time of the saturation created between the drain and the source of the MOS type FET 5 at r <<R.sub.7 = R.sub.8, then the voltage V.sub.A at the point on the drain side of the FET 5 and the voltage V.sub.B at the point B on the source side thereof will be expressed as follows, with the proviso that the FET 5 is in the saturated condition;

V.sub.A = V.sub.D - R.sub.7 V.sub.D /R.sub.7 + r + R.sub.8, V.sub.B = R.sub.8 V.sub.D /R.sub.7 + r + R.sub.8.

Since R.sub.7 V.sub.D /R.sub.7 + r + R.sub.8 = R.sub.8 V.sub.D /R.sub.7 + r + R.sub.8 .apprxeq. V.sub.D /2, then,

V.sub.D .gtoreq. V.sub.A .gtoreq. V.sub.D /2, V.sub.D /2 .gtoreq. V.sub.B = 0.

Thus, V.sub.A and V.sub.B may vary within the above range. In this connection, FIG. 2 shows the relationship of V.sub.A, V.sub.B to the gate voltage of the FET 5. Here, the voltage V.sub.A is lowered as the gate voltage increases, while the voltage V.sub.B is increased therewith.

Subsequently, the aforesaid voltages V.sub.A and V.sub.B are applied to the bases of the PNP transistor 12 and NPN transistor 9, respectively. FIGS. 3 and 4 show collector current characteristics to the base currents of the PNP transistor 12 and NPN transistor 9. When the MOS type FET 5 remains in a cut-off condition, the voltage V.sub.A at the point A will the +V.sub.D, while the voltage V.sub.B at the point B will be zero potential. At this time, there will be no current-flowing through the resistor 14, since the potential at the emitter of the PNP transistor 12 is equal to that of the base thereof, thereby causing no current flow. On the other hand, there will be no current flowing through the resistor 11, since the potential at the emitter of the NPN transistor 9 is equal to that of the base thereof, thereby causing no current flow, such that the potential at the output terminal will be +V.sub.D.

Next, when the gate voltage at the MOS type field effect transistor 5 is increased, V.sub.A will be lowered, whereas V.sub.B will be increased. Then, this causes a decrease in the base potential at the PNP transistor 12, whereby current will flow through the emitter and base. It follows that under these conditions the current flows through the resistor 14 and the potential V.sub.01 at the output terminal will be increased. This further causes the base voltage at the NPN transistor 9 to increase, thereby causing the current to flow through the emitter and base thereof. Then, this further results in the current flowing through the resistor 11, thereby lowering the potential V.sub.02 at the output terminal 15. In this respect, if the values of the resistor 13 and resistor 10 are such that when the MOS type FET 5 is saturated, PNP transistor 12 and NPN transistor 9 are saturated, then the potentials V.sub.01 and V.sub.02 at the output terminals 16 and 15 will be such as shown in FIG. 5.

Accordingly, as has been described, when the central terminal 3 is connected to the positive terminal 1 or the negative terminal 2, then the potential at one output terminal will be increased from zero, and the potential at the other terminal will be lowered from +V.sub.D. It follows that the charge or discharge of the condenser 6 may create a voltage of an arbitrary value between the both terminals. In addition to this, the output voltage therebetween may be maintained to a given value at an arbitrary time.

As is apparent from the foregoing description, that the output voltage variable device of the present invention thus constructed provides a wider range of application. A further advantage thereof is that the device of the present invention may be operated in a manner analogous to conventional type variable resistors while enabling non-contact operation.

It will be understood that above description is merely illustrative of preferred embodiment of the invention. Additional modifications and improvements utilizing the descoveries of the present invention can be readily anticipated by those skilled in the art from the present disclosure, and such modifications and improvements may fairly be presumed to be within the scope and purview of the invention as defined by the claims that follow.

Claims

1. A device for use in varying an output voltage, comprising an MOS field effect transistor having a source, a gate and a drain; a capacitor; means for selectively charging and discharging said capacitor to a plurality of arbitrary potentials; means for connecting said capacitor across said gate and source of said field effect transistor; whereby the potential across the capacitor is provided across the gate and source of the field effect transistor; an NPN transistor having a base, an emitter and a collector; means for connecting the base of the NPN transistor to the source of the field effect transistor; a PNP transistor having a base, an emitter and a collector; means for connecting the base of the PNP transistor to the drain of said field effect transistor; and separate output terminals connected to the collectors of the NPN and PNP transistors; whereby upon the application of a positive bias across the source and drain of the field effect transistor, across the collector and emitter of the NPN transistor and across the emitter and collector of the PNP transistor, the collector current of the PNP transistor varies directly and the collector current of the NPN transistor varies inversely with respect to the charge on the capacitor, thereby varying said output terminal voltage.

2. A device as set forth in claim 1, wherein said means for selectively charging and discharging said capacitor comprises means for providing a positive potential, means for providing a negative potential, and switch means connected to said capacitor for selectively connecting said capacitor to said means for providing said positive potential, to said means for providing said negative potential and for disconnecting said capacitor from any low impedance discharge path, whereby said capacitor may be charged and discharged to any arbitrary potential and whereby said potential may be selectively retained on said capacitor.