U.S. patent number 3,819,951 [Application Number 05/318,760] was granted by the patent office on 1974-06-25 for polarity guard.
This patent grant is currently assigned to Microsystems International Limited. Invention is credited to Arthur D. Moore.
United States Patent |
3,819,951 |
Moore |
June 25, 1974 |
POLARITY GUARD
Abstract
The invention relates to a polarity guard for insertion between
terminals connected across a potential supply and a load means, the
input polarity of which load means must be constant regardless of
the polarities of the potential supply terminals. The invention has
particular application to, but is by no means limited to the field
of telephony wherein a transducer must often be capable of
operation from a telephone line, the polarity of which is variable
but the transducer requiring a constant polarity input. Typical of
such a transducer is a headset amplifier for powering an electret
or similar microphone in place of the traditional carbon
microphone.
Inventors: |
Moore; Arthur D. (Stittsville,
Ontario, CA) |
Assignee: |
Microsystems International
Limited (Montreal, Quebec, CA)
|
Family
ID: |
4095111 |
Appl.
No.: |
05/318,760 |
Filed: |
December 27, 1972 |
Foreign Application Priority Data
Current U.S.
Class: |
361/77; 363/127;
327/576; 327/538 |
Current CPC
Class: |
H04M
1/6008 (20130101); H04M 1/6016 (20130101); H02H
11/002 (20130101); H04M 19/08 (20130101); H02M
7/2195 (20210501); H02M 7/219 (20130101); Y02B
70/10 (20130101) |
Current International
Class: |
H02H
11/00 (20060101); H04M 19/08 (20060101); H03k
017/00 () |
Field of
Search: |
;307/202,262,236,127
;317/39,43 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Rolinec; Rudolph V.
Assistant Examiner: Davis; B. P.
Attorney, Agent or Firm: Pascal; E. E.
Claims
What is claimed is:
1. A polarity guard having first and second input terminals for
connection to a potential supply, and first and second output
terminals for connection across a load, said polarity guard
characterized by first, second, third and fourth transistors, said
first and second transistors being of one conductivity type, and
said third and fourth transistors being of another conductivity
type, the control electrodes of said first and fourth transistors
being connected via first and fourth resistors respectively to said
first input terminal and the control electrodes of said second and
third transistors being connected via second and third resistors
respectively to said second input terminal, said first input
terminal being connected through said second transistors to said
second output terminal and through said third transistors to said
first output terminal and said second input terminal being
connected through said first transistor to said second output
terminal and through said fourth transistor to said first output
terminal.
2. The polarity guard as defined in claim 1 characterized in that
said first, second, third, and fourth transistors are bipolar
transistors, the control electrodes of said first, second, third
and fourth transistors being the base electrodes of said first,
second, third and fourth transistors.
3. The polarity guard as defined in claim 2 characterized in that
the first and second transistors are n.p.n. bipolar transistors and
the third and fourth transistors are p.n.p. bipolar
transistors.
4. The polarity guard as defined in claim 1 characterized in that
the first and second transistors are n.p.n. bipolar transistors,
the third and fourth transistors are p.n.p. bipolar transistors,
the collector electrodes of the second and fourth transistors being
respectively connected to the second and first output terminals,
and the emitter electrodes of the first and third transistors being
respectively connected to said second and first input
terminals.
5. The polarity guard as defined in claim 2 characterized in that
the first and second transistors are n.p.n. bipolar transistors,
the third and fourth transistors ar p.n.p. bipolar transistors, the
collector electrodes of the second and fourth transistors being
respectively connected to the second and first output terminals,
and the emitter electrodes of the first and third transistors being
respectively connected to said second and first input
terminals.
6. The polarity guard as defined in claim 1 characterized in that
the first and second transistors are N-channel enhancement type
field effect transistors and the third and fourth transistors are
P-channel enhancement type field effect transistors.
7. The polarity guard as defined in claim 6 characterized in that
the control electrodes of said first, second, third and fourth
field effect transistors are the gate electrodes of said field
effect transistors.
Description
The present invention relates to a polarity guard for insertion
between terminals connected across a potential supply and a load
means, the input polarity of which load means must be constant
regardless of the polarities of the potential supply terminals.
The invention has particular application to, but is by no means
limited to the field of telephony wherein a transducer must often
be capable of operation from a telephone line, the polarity of
which is variable but the transducer requiring a constant polarity
input. Typical of such a transducer is a headset amplifier for
powering an electret or similar microphone in place of the
traditional carbon microphone.
Two basic types of polarity guard have been employed in this
application -- one being a full-wave diode bridge rectifier and the
other comprising two amplifiers connected in opposite senses, so
that whichever way round the amplifiers are connected to the
supply, one will always be polarized correctly. The latter of these
approaches is difficult to achieve in practice, uneconomical and
expensive. The full-wave diode rectifier is simple, but the voltage
drop thereacross is too great for telephone use, as will
hereinafter be explained.
The circuit of the present invention provides a simple and
efficient means of ensuring a constant output polarity with low
potential drop through the circuit and has the further advantage of
being usable with either field-effect or bipolar transistors.
Thus, according to the present invention, a polarity guard
comprises first and second input terminals for connection to a
potential supply and first and second output terminals for
connection across a load means; first, second, third and fourth
transistors, said first and third transistors being of opposite
conductivity type, said second and fourth transistors being of
opposite conductivity type and said first and second transistors
being of the same conductivity type, the control electrodes of said
first and fourth transistors deriving enabling potential from said
first input terminal and said second and third transistors deriving
potential from said second input terminal, said first input
terminal connected through said second transistor to said second
output terminal and through said third transistor to said first
output terminal and said second input terminal connected thorugh
said first transistor to said second output terminal and through
said fourth transistor to said first output terminal.
The invention will now be described further by way of example only
and with reference to the accompanying drawings, wherein:
FIG. 1 is a circuit diagram of a full-wave diode bridge rectifier
used as a polarity guard according to prior art;
FIG. 2 is a diagram of a polarity guard circuit according to the
present invention; and
FIG. 3 is a circuit diagram of one embodiment of the present
invention.
Referring now to the drawings, and in particular FIG. 1, there is
shown a polarity guard according to the prior art. The polarity
guard is in fact a full-wave diode bridge rectifier having diodes
D.sub.1 to D.sub.4 inclusive, input terminals A and B for
connection across a potential supply and output terminals C and D
for connection across a load. Terminal A is connected to the anode
of D.sub.1 and the cathode of D.sub.4. The cathode of D.sub.1 is
connected to terminal D and the anode of D.sub.4 is connected to
terminal C. Terminal B is connected to the anode of D.sub.3 and the
cathode of D.sub.2. The cathode of D.sub.3 is connected to terminal
D and the anode of D.sub.2 is connected to terminal C.
If the potential appearing at terminal A is positive, D.sub.1
conducts and the potential appearing at terminal D is the same as
at terminal A minus one diode drop. Similarly, diode D.sub.2 will
conduct since terminal B is negative, and terminal C will attain
the same potential as terminal B, minus a diode drop. If the input
polarities are reversed, diodes D.sub.4 and D.sub.3 will conduct
instead of D.sub.1 and D.sub.2, respectively and the result will be
terminal D positive and terminal C negative. Thus, the polarities
of terminals C and D are the same, regardless of the polarities of
terminals A and B. However, in each case, the potential across C
and D is two diode drops less than that across A and B and,
particularly in telephone applications, this could be a substantial
percentage loss in the available output voltage.
The basic circuit of the present invention is shown in FIG. 2. It
comprises input and output terminals A, B and C, D, respectively --
input terminal A being connected to output terminal D through a
transistor Q.sub.3 and input terminal B connected to output
terminal C through a transistor Q.sub.1 -- Q.sub.1 and Q.sub.3
being of opposite conductivity type. Terminal A is connected to
terminal C through transistor Q.sub.2 and terminal B is connected
to terminal D through transistor Q.sub.4 - Q.sub.2 and Q.sub.4
being of opposite conductivity type. As stated above, transistors
Q.sub.1 to Q.sub.4 inclusive may be either field-effect or bipolar
transistors, depending upon the environment to which the polarity
guard is applied. Suppose it is required that terminal D always be
positive and terminal C always be negative. Let terminal A be
positive and terminal B be negative. Thus it is required that
transistors Q.sub.1 and Q.sub.3 both be enabled to make the A - D
and B - C connections. Now let terminal A be negative and terminal
B be positive. Now it is required that transistors Q.sub.2 and
Q.sub.4 be enabled to make the A - C and B - D connections. This is
achieved by making Q.sub.1 and Q.sub.2 of the same conductivity
type - i.e. both conducting current to or from terminal C,
depending upon the required polarity thereof -- but selectively
enabled by tying the control electrode of Q.sub.1 to terminal A and
the control electrode of Q.sub.2 to terminal B. Thus if terminal C
is required to be negative, the current flow through Q.sub.1 or
Q.sub.2 would be from A to C or B to C, respectively -- depending
upon which of Q.sub.1 or Q.sub.2 is enabled. Thus Q.sub.1 and
Q.sub.2 both require positive enabling potentials and if terminal A
is positive Q.sub.1 will be enabled, completing the B - C
connection and if terminal B is positive Q.sub.2 will be enabled,
completing the A - C connection. Thus terminal C is unconditionally
negative.
Transistors Q.sub.3 and Q.sub.4 are connected in precisely
analogous fashion to ensure the unconditionally positive polarity
of terminal D. Clearly, to enable the transistors, the minimum
potential applied is the enabling potential, which for field-effect
devices is V.sub.T and for bipolar transistors is V.sub.BE.
However, when the appropriate transistors are enabled, the only
series drop is across the input and output electrodes of the
transistors which is considerably smaller than the corresponding
drop across the conventional diode rectifier bridge. Also, by
connecting the control electrodes of the transistors as shown, the
appropriate enabling potentials are automatically applied,
dependent upon the input terminal polarities, and the need for
separate logic control circuitry is obviated.
FIG. 3 shows an embodiment of the circuit of FIG. 2, using bipolar
transistors.
The circuit comprises input terminals A and B adapted for
connection to a power-supply. Terminal A is connected through first
resistor R.sub.1 to the base electrode of a transistor T.sub.1. The
emitter of T.sub.1 is connected to terminal B.
Terminal A is also connected to the emitter electrode of a
transistor T.sub.2, the collector of which is connected to a
terminal C. The base electrode of T.sub.2 is connected through a
second resistor R.sub.2 to terminal B.
Terminal B is connected through third resistor R.sub.3 to the base
electrode of a transistor T.sub.3. The emitter of T.sub.3 is
connected to terminal A.
Terminal B is also connected to the emitter electrode of a
transistor T.sub.4, the collector of which is connected to a
terminal D. The base electrode of T.sub.4 is connected through a
fourth resistor R.sub.4 to terminal A.
Transistors T.sub.1 and T.sub.2 are both NPN type and T.sub.3 and
T.sub.4 are PNP type. Suppose now a positive potential is applied
to terminal A. This potential is applied to the base of T.sub.1
through first resistor R.sub.1 and through fourth resistor R.sub.4
to the base of T.sub.4. Now, since T.sub.4 is a PNP transistor,
positive potential at its base will not cause it to conduct.
T.sub.1, however, conducts. Since a positive potential is applied
to terminal A, a negative potential is applied to terminal B. Since
T.sub.1 is enabled, a negative potential obviously appears at
terminal C. The negative potential at terminal B is also applied to
the base of T.sub.3 through R.sub.3 and the base of T.sub.2 through
T.sub.2. Since T.sub.3 is an PNP type, the negative terminal at its
base electrode causes it to conduct and a positive potential
therefore appears at output terminal D.
Consider, now, the case where terminal A is negative and terminal B
is positive. Now, instead of T.sub.1 and T.sub.3 conducting,
T.sub.2 and T.sub.4 conduct, and the potential polarity of terminal
B is therefore passed to terminal D -- i.e., positive. Conversely,
terminal C is negative. Thus, terminal D must be positive and
terminal C negative, regardles of the polarity of terminals A and
B.
For this circuit, the total series voltage drop is across two
collector-emitter junctions and is, therefore, (V.sub.CESAT of
T.sub.1) + (V.sub.CESAT of T.sub.3) or (V.sub.CESAT of T.sub.2) +
(V.sub.CESAT of T.sub.4).
Within practical limitations these drops may be made almost
negligible and using conventional bipolar silicon planar technology
and with suitable device design, the total drop in the circuit may
be as low as 150mv.
Various alternatives and modifications to the embodiments disclosed
herein will be readily apparent to those skilled in the art without
departing from the spirit and scope of the invention as described
by the disclosure and defined by the claims appended hereto.
* * * * *