Digitally Controlled Phase Shifter

Abstract

A delay line has its output taps connectable through the base-emitter circuits of individual transistors and then through the output terminals of a standard one-of-sixteen multiplexer or decoder to a load. In response to a four bit digital control signal a selected one of the sixteen multiplexer output terminals is connected to the load while the other multiplexer output terminals have a relatively high voltage impressed thereon thereby back-biasing all transistors except the selected transistor.

Description

BACKGROUND OF THE INVENTION

This invention relates to phase shifters and more particularly to digitally controlled phase shifters of the type which are particularly useful in phased array radar systems.

In phased array radar systems, the radar beam is steered by varying the relative phase of the radio frequency waveforms transmitted and received by a plurality of antenna elements on the radar face. Large phased array radar systems may use many thousands of antenna elements, both transmitting and receiving elements. Each receiving antenna element usually has a separate R.F. receiver and phase shifter associated with it. The phase shifter operates in response to digital signals to adjust the phase of the receiver.

The present invention provides a digitally controlled phase shifter which can be quite easily implemented in microelectronic form, particularly as a thick film hybrid microcircuit and which is adapted to use a standard commercially available one-in-sixteen multiplexer to select the desired phase shift in response to a digital control signal. The multiplexer, which is used as a one-of-sixteen decoder, has four inputs and sixteen active output terminals. In response to a binary code applied to the inputs, one of the output terminals connects to a further terminal on the multiplexer while the other taps have a relatively high d.c. voltage impressed thereon. A delay circuit or line, which performs the actual phase shift, is disposed about the multiplexer. The delay circuit is comprised of inductances and capacitors and has a plurality of output taps which are connected through various transistors to the active output terminals of the multiplexer. The signal whose phase is to be shifted is applied at the input to the delay line. In response to the binary code, one transistor has its emitter connected to the multiplexer further terminal while the other transistors are back-biased. In operation, the signal whose phase is to be shifted flows into the delay line and out through the delay line output tap whose transistor is forward biased and hence through the multiplexer and then to a load.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Refer now to the FIGURE which is a modified schematic of an embodiment of the invention. The embodiment illustrated is of a prototype circuit which operates at a frequency of 170 MHz. Phase shift is switched in sixteen 22.5.degree. steps from 0.degree. to 337.5.degree. in response to a four bit digital control signal. The entire circuit was fabricated as a thick film hybrid microcircuit on a 1 inch .times. 2 inch substrate. All delay line conductors and capacitors were formed by the conductive pattern silk screened on the substrate. The inductors L, and capacitors C and C/.sub.2 form a fifteen section lumped constant 50 ohm transmission line wherein the phase delay of each section is 22.5.degree. at 170 MHz. The transmission line which comprises the delay line is disposed in a rectangular configuration about a microcircuit chip 20 comprising a one-of-sixteen decoder. A decoder suitable for use here is multiplexer Model 9311, made by Fairchild-Semiconductor. The decoder is controlled by digital signals applied at terminals A.sub.0, A.sub.1, A.sub.2 and A.sub.3 which in this embodiment are applied through a buffer 22 which allows external CMOS logic to drive the T.sup.2 L logic of the Model 9311 decoder. The decoder includes sixteen active terminals, 1 through 16, and a further terminal 25. In response to the digital control signals applied at terminals A.sub.0 to A.sub.3 one of the decoder terminals, 1 through 16, will be connected directly to terminal 25 while the other terminals, 1 through 16, will have impressed thereon a relatively high voltage, the relatively high voltage being the V+ bias voltage applied at terminal 28.

A voltage divider comprised of resistors 30 and 32 is connected across the voltage source. In this embodiment resistor 30 is made equal to resistor 32 so that the junction point between the resistors has a voltage potential V+/.sub.2 impressed thereon. The junction point between resistors 30 and 32 is connected to one end of the delay line while the other end of the delay line is connected to one plate of capacitor 34 whose other plate is connected to the signal input terminal 36. A signal to be delayed is impressed across terminals 36 and 38. Terminal 38 is at a common potential, such as ground. The input signal is thus capacitively coupled through capacitor 34 to the delay line which is comprised of the serial string of inductors L and shunt capacitors C and C/.sub.2. The delay line is suitably a lumped constant 50 ohm terminated by resistor 42 and capacitor 44.

Each delay line output tap, that is, each point at the end of an inductor L, is connected to the base electrode of an NPN transistor, transistors Q.sub.1 through Q.sub.16 being provided for this purpose. The collector electrodes of the various transistors are connected through a 50 ohm transmission line formed by the interconnecting tracks 42 and 43 on the substrate to the positive voltage supply at terminal 28. Resistors 46 and 47 terminate this transmission line. The purpose of the transmission line is to reduce R.F. impedance in the collector circuits of the transistors and thus minimize the R.F. voltage excursion on the interconnecting track to thus reduce undesired signal coupling to the other circuit elements. The decoder output terminals 1 through 16 are connected respectively through resistors R.sub.1 through R.sub.16 to the emitter electrodes of transistors Q.sub.1 through Q.sub.16.

A capacitor 48 connected between terminal 28 and ground removes any R.F. frequencies from the d.c. power line.

In operation, a four bit digital control signal indicative of the phase shift desired is applied in parallel-by-bit format to terminals A.sub.0 through A.sub.3. In accordance therewith, as previously discussed, one of the decoder output terminals 1 through 16, as determined by the digital control signal, will be connected directly to terminal 25 while potential level V+ will be applied at the other decoder output terminals. All the transistors, Q.sub.1 through Q.sub.16, will now have their base-emitter diode back-biased except for that transistor whose emitter is connected through the decoder to line 25. That transistor will become conductive and will permit the signal passing through the delay line to be drawn from the delay line and through terminal 25 to an external load represented at 50 by an inductor 54 and shunt capacitor 52. This load is suitably a parallel resonant circuit tuned to the frequency of the delayed R.F. signal, in this embodiment 170 MHz. This load also provides a d.c. ground for the decoder.

In essence, the various transistors operate as switches which connect a selected delay line output tap to a load. The decoder generates signals which selectively operate the switches in response to a digital control signal.

2N5179 transistor chips were used in the aforementioned prototype phase shifter. Phase shift from the base to emitter in this type transistor is negligible at 170 MHz. In addition, R.F. signal delay through the Model 9311 decoder chip is negligible since the R.F. path through that chip is through saturated transistor switches.

It should be understood that the specific circuit parameters discussed herein are only illustrative and not intended to limit the invention to the exact values shown. One skilled in the art will now be able to design and construct a phase shifter identical to that described or differing only by obvious modifications and alterations. Accordingly, the invention is to be limited only by the true scope and spirit of the appended claims.

Claims

The invention claimed is:

1. A digitally controlled phase shifter comprising:

a delay line having a plurality of output taps;

a plurality of transistors, one associated with each said output tap, each said transistor having a base electrode connected to its associated output tap, an emitter electrode and a collector electrode, all the collector electrodes being connected in common with one another;

means for applying a first d.c. bias potential on said delay line;

means for applying a second d.c. bias potential on the common collector electrodes;

a digital decoder having a plurality of output terminals and a plurality of input terminals, at least one said output terminal for each said transistor, each one of said output terminals being associated with and connected to one of said transistors emitter electrodes, said decoder having a further terminal, said decoder being responsive to a digital signal comprised of a parallel by bit binary word applied in parallel by bit format to said plurality of input terminals for selectively connecting one of said output terminals to said further terminal and for applying a relatively high d.c. bias potential to the output terminals not so selected whereby the transistors associated with the terminals not selected are back-biased; and,

load means connected to said further terminal and tuned to the frequency of the delayed signal for providing a d.c. ground for said decoder.

2. A digitally controlled phase shifter comprising:

a delay line having a plurality of output taps;

a plurality of electronic switch means, each having an input terminal. for allowing a signal applied at an input terminal to pass therethrough when the respective switch means is closed and for blocking a signal applied at an input terminal from passing therethrough when the respective switch means is opened, each said switch means being associated with one of said output taps and having its input terminal connected to its associated output tap, each said switch means having an output terminal whereupon a signal passing therethrough appears;

decoder means having a plurality of output terminals and a plurality of input terminals, each said decoder output terminal being associated with a predetermined one of said switch means and including means for electrically communicating its associated switch means output terminal with its associated decoder means output terminal,

said decoder means being responsive to digital control signals comprised of parallel by bit binary words applied to said decoder means input terminals for generating a switch close signal on one of said decoder means output terminals determined by the parallel by bit binary word applied to said decoder means input terminals and for generating a switch open signal on the other of said decoder means output terminals, said decoder means including a further terminal and being responsive to digital signal applied to said decoder means input terminals for connecting the terminal on which said switch close signal is generated to said further terminal, a switch means being responsive to a switch close signal at its output terminal for closing said switch means and being responsive to a switch open signal at its output terminal for opening said switch means; and,

load means connected to said further terminal and tuned to the frequency of the delayed signal for providing a d.c. ground for said decoder.

3. A phase shifter as recited in claim 2 wherein said load means comprises a parallel resonant circuit tuned to the frequency of the delayed signal connected to said further terminal.

4. A phase shifter as recited in claim 2 wherein each said switch means comprises a transistor having an emitter and base electrode, said base electrode being said switch input terminal and said emitter electrode being said switch output terminal, the transistors additionally including collector electrodes connected together; and wherein said decoder means comprises,

means for applying a first d.c. bias potential on said delay line whereby said first d.c. bias potential is impressed on the base electrode of each transistor; and,

means for applying a second d.c. bias potential on said common collector electrodes, said switch open signal comprising a third d.c. bias potential and said switch close signal comprising the absence of said third d.c. bias potential.

5. A phase shifter as recited in claim 4 wherein said third d.c. bias potential is higher than said first d.c. bias potential.

6. The digital phase shifter of claim 1 wherein said delay line comprises input terminals across which a signal to be delayed is applied and a serial string of a plurality of inductances, the junction point between said inductances comprising said output taps, said delay line additionally including a plurality of capacitors connected between said output taps and one of said input terminals.

7. The phase shifter of claim 6 wherein said inductances are equal to one another and wherein said capacitors are equal to one another, and additionally including further capacitors connected across the input terminals and terminating said delay line.