Biological Signals Monitor

Abstract

Biological signals (especially, e.g., fetal QRS complexes) are monitored with signal processing circuitry featuring, in various aspects, in the fetal heart rate monitor, automatic thresholding of maternal and fetal signals; a digital phase lock loop for generating fetal heart rate signals related to the loop frequency, the loop including means for estimating the rate during occurrences of blank spaces caused by removal of signals representing merged maternal and fetal heart beats; counter controlled means for disabling readout; low impedance preamplification of signals received from the body; and a low Q filter with significant useful output energy in the 50-100Hz range, 60Hz noise being removed by a notch filter.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to monitoring biological signals, and is particularly applicable to the measurement of fetal heart rate.

2. Description of the Prior Art

It is known that the patterns of change in fetal heart rate during labor contain information about the well-being of the fetus. Thus, efforts have been made to accurately measure fetal heart rate. Some of these efforts have employed direct acoustical pickup. Others have relied upon the doppler shift in an ultrasonic signal reflected from the moving wall of the fetal heart. Still others detect electrical signals, either directly from the fetal scalp, or through the maternal abdomen. Abdominal detection is complicated by the masking effect of the maternal heartbeat, which is many times stronger than, and frequently merges (i.e., occurs simultaneously) with, the fetal, and by a variety of other sources of noise that make accurate detection of the very weak fetal signals extremely difficult; existing devices for abdominal detection are difficult to operate and are not reliably accurate.

SUMMARY OF THE INVENTION

The invention makes possible real time monitoring of fetal heart rate (as well as analogous monitoring of other relatively weak components of complex biological signals, such as T and P waves in ECG signals) with improved accuracy and reliability, yet with equipment that is relatively inexpensive and easy to operate. The system is operable over a wide range of frequencies; excellent electrical isolation of the patient is provided; and excellent balance is achieved between avoiding readout of erroneous information and minimizing readout outages during which accurate information is lost (including, e.g., rapid recovery from outages caused by noise).

In general the invention features, in one aspect, a monitor for a first electrical signal representing a first component of a recurring complex biological signal including a second component that is stronger than the first component (the components respectively being fetal and maternal QRS complexes when the invention is embodied in a fetal heart rate monitor), the monitor comprising a signal processing path in which the first signals are detected and along part of which second signals representing occurrences of the second component are transmitted, automatic thresholding circuitry in the path for tracking signal magnitude and providing an output signifying the occurrence of the first component only upon receipt of a signal of magnitude bearing a predetermined relationship to previously tracked signal magnitude, and means for preventing effective response by the automatic thresholding circuitry to the second signals. In its several other aspects the invention, in general, features logic circuitry for generating readout signals, with the decision as to each readout signal being based in part upon a statistical prediction derived from the pattern of signals received in past time periods, including (in the fetal heart rate monitor) a phase lock loop for generating fetal heart rate signals related to the loop frequency, the loop including means for estimating the rate during the occurrences of blank spaces in the modified signal train caused by removal of signals representing merged maternal and fetal heart beats; a counter responsive to deviation between the time of signal receipt by the logic circuitry and the prediction thereof, the counter increasing upon an instance of deviation greater than a predetermined value, readout being disabled when the counter is above a first count, derivation of the prediction being reinitiated when the counter reaches a second, higher count; electrodes for picking up the signals from a human body, and a low impedance pre-amplifier followed by a high impedance isolation amplifier magnetically (or otherwise indirectly) coupled at its output to the rest of the signal processing circuitry; a delay for receiving signals including fragments of incompletely removed second (maternal) signals, and means for excluding those fragments from the effective output of the delay; and a low Q filter for linearly processed signals corresponding to fetal QRS complexes, the filter output having at least 25 percent of its signal energy in the 50-100Hz range (exclusive of 60Hz noise), and a notch filter for removing 60Hz noise. In preferred embodiments the invention features a digital phase lock loop adapted to produce repeating windows each sized and spaced to overlap a fetal signal on the basis of past spacing statistics despite variation within predetermined limits; means for updating under certain conditions the phase and frequency of the windows on the basis of the actual positions of the signals within the windows; a separate electrode for picking up maternal QRS complex signals, with signal processing circuitry which the maternal signals are transmitted in timed relationship to the transmission of maternal signals over the first path, the circuitry having a connection to the first path for the removal of maternal signals therefrom; and automatic thresholding means for both maternal and fetal signals, the fetal signal thresholding means including means for storing and decaying peak signal values, between an upper limit and a variable lower limit responsive to average signal value over the recent past.

Other advantages and features of the invention will be apparent from the description and drawings herein of a preferred embodiment thereof.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of the analog signal processing circuitry;

FIGS. 2a, b together comprise a circuit diagram corresponding to FIG. 1;

FIGS. 3-8 comprise voltage-time graphs illustrating the signal patterns at various stages of the circuitry of FIGS. 1, 2a, and 2b;

FIG. 9 is a flow chart of the digital phase lock loop and readout algorithm;

FIG. 10 is a block diagram of the digital phase lock loop and readout circuitry for implementing the algorithm illustrated in FIG. 9.

FIGS. 11a, b, c, d together comprise a circuit diagram corresponding to FIG. 10.

FIGS. 12 and 13 comprise circuit diagrams of timing pulse generators; and

FIG. 14 is a combined block and circuit diagram illustrating variable lower limit circuitry for the fetal signal peak detector.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to FIG. 1, electrodes 10 and 11 are provided for placement on the patient to pick up the maternal and fetal QRS signals and feed them through ultra-low noise gain of 30 amplifiers 12 and 13 to patient isolation amplifiers 16 and 18, respectively. Electrode 11 is placed on the abdomen, where the best fetal signal is available, and electrode 10 preferably in position (e.g., on the ribs) to maximize the maternal signal. Reference electrode 20 is placed on the hip.

Amplifiers 12 and 13 have a low impedance, of the order of 10.sup.5 ohms. As shown in the detailed circuitry of FIGS. 2a-, these amplifiers are shunted by 100K resistors and 0.01.mu.f capacitors. It has been discovered that such low impedance gives an improvement in signal-to-noise ratio which outweighs the corresponding reduction in overall signal level. Amplifiers 16 and 18 are transformer coupled to the rest of the system and to their power supply, and provide a very high impedance (of the order of 10.sup.12 ohms) between the electrodes and ground, thus protecting the patient from shock.

The amplified maternal signal passes through a low Q (less than 10, and preferably 1/2 to 1) band pass active filter 28 centered at 17Hz (the optimum in a preferred center frequency range of 15-25Hz), the center of peak energy in the maternal QRS waves. The amplified fetal signal is passed through a cascaded pair of similarly low Q band pass active filters 30, 32 centered at 32Hz (the optimum in a preferred range of 25-40Hz for center frequency), the center of peak energy in the fetal QRS waves, thay energy extending roughly from 5Hz to 100Hz. (In the detailed circuitry of FIG. 2, filters 28 and 30 are incorporated into amplifiers 16 and 18, which respectively provide gains of 20 and 40 with Q = 1.) These low Q filters provide excellent transient response (equivalent to that of matched filters) to the thus far linearly processed signals they receive. The filtering characteristics of the cascaded pair of filters 30, 32 multiply, narrowing the bandwidth and providing a very flat characteristic. The output of filter 32 has at least 25 percent of the signal energy in the 50-100Hz range (exclusive of 60Hz noise), since important useful energy of the fetal waves lies there. By thus increasing the effective utilization of the fetal wave energy, and dealing separately later with the accompanying 60Hz noise, improved signal-to-noise ratio is ultimately achieved.

The signals from filters 28 and 30 fed voltage controlled oscillators 29 and 31 which convert the input voltage into a frequency which bears a linear relationship to the input voltage, in effect generating an FM signal of th input wave form. The output voltages from the oscillators pass through isolation transformers which are coupled into demodulating and analog circuitry including analog phase lock loops 33 and 35 which convert the signal back into a wave form identical with that which was fed into the voltage controlled oscillators.

After further amplification of the maternal signal in amplifier 34, the maternal and fetal signals pass through 60Hz twin T notch filters 36, 38 for attenuation of 60Hz noise, and are fed to precision full wave rectifiers 40 and 42, respectively. FIG. 3 illustrates the maternal and fetal waveforms 44 and 46 (waveform 46 of course still including maternal as well as fetal signals), respectively, at the rectifier inputs, and the corresponding outputs 48 and 50. The rectifiers eliminate any need to consider varying signal polarity.

Considering now the maternal signal, the output of rectifier 40 is fed both to peak detector 52 and comparator 54. The peak detector stores and gradually decays toward zero the value of peak amplitude of a signal reaching it, until it receives another signal having a peak amplitude higher than the instantaneous value to which the originally stored peak has decayed; the new peak value is thus stored, and so on. The second input to comparator 54 is 90 percent (the preferred range is 70-90 percent) of the value stored in the peak detector. The comparator fires whenever the output of rectifier 40 has a peak greater than 90 percent the value stored in the peak detector. In effect, then, automatic thresholding of the maternal signal train is provided, with the decision as to the presence or absence of a maternal QRS wave at any given time being based upon the most recent history of such waves. Accurate detection is thus provided, despite changes in the general signal level. An upper limit is built into the peak detector so that a momentary large burst of noise will not drive the stored value to a misleadingly high level.

The output of comparator 54 is used to fire a one shot (mono-stable multi-vibrator) 56 having a pulse width (e.g., 140 milliseconds) as wide as the widest expected maternal QRS signal.

FIG. 4 illustrates the output 57 of peak detector 52, the output 58 of comparator 54, and the output 59 of one shot 56.

Returning now to the fetal signal, the output of rectifier 42 is fed to Paynter averaging filter 60, which in effect provides a moving average (over a time span of some 17 milliseconds (the optimum in a preferred range of 12 to 20 milliseconds), a time constant chosen to match the expected duration of fetal QRS waves) of signal value, further improving the ratio of fetal to maternal signal strengths. FIG. 5 illustrates the Paynter output 62, which includes fetal pulses 64 and maternal pulses 66, the latter of course masking the former whenever the fetal and maternal heartbeats merged.

The output of Paynter filter 60 and one shot 56 are fed to analog gate 70, which closes during each firing of the one shot, thus gating out of the Paynter output all but the leading edges of the maternal pulses. The result is illustrated in FIG. 6, where the spikes 72 are the leading edges of the blocked maternal pulses.

The result is passed through amplifier 74 to both a peak detector 76 and a comparator 78, which, just as did peak detector 52 a comparator 54 for maternal pulses, provide for detection of fetal pulses 64 with automatic thresholding. (The charging time constant of the peak detector, about 3-4 milliseconds, is such that the maternal spikes 72 will not cause a reset.) Upper and lower limits are provided in the peak detector, the lower limit being set to avoid mistaking low level noise for a fetal pulse. Although the lower limit may rarely block out very weak fetal pulses, the device preferably is set up so that a direct display of the output of filter 32 can be switched on, this feature not being described in detail here. While the lower limit may be fixed, greater accuracy (in the face of changing general noise or fetal signal levels) is obtained if the limit value is caused to change in accordance with average signal value reaching the peak detector over a recent prior period, e.g., over the past 10 seconds. Circuitry 79 providing such a variable lower limit equal to, e.g., twice that average signal value, is shown in FIG. 14. The outputs 80 and 82 of the peak detector and the comparator are illustrated in FIG. 7. Pulses 84 correspond to fetal waves, the spikes 86 to the leading edges of the maternal waves.

The output 82 of comparator 78 is then passed through a shift register 90 (FIGS. 1, 11a) which provides a 32 millisecond delay. The output of one shot 56 is used, each time it fires, to zero register 90, thus blocking spikes 86. Thus, all remnants of the maternal pulses are removed (though at the temporary cost of any fetal pulses merged in the maternals) regardless of variation in the maternal pulse rate. The shift register output 85 is illustrated in FIG. 8. The register is gated to produce a four millisecond pulse 87 coinciding with the falling edge of each pulse 84 (it having been discovered that the time between the falling edges is a more accurate representation of the pulse spacing than the time between the leading edges).

The resulting signal train will, in general, in comparison to the real sequence of fetal heartbeats, have some gaps corresponding to missing fetal signals, and will of course include some pulses (noise) which do not correspond to real beats. The digital circuitry to be described is designed to modify that signal train, so far as possible, by restoring the missing fetal pulses and removing the noise.

In general, the digital circuitry employs a phase lock loop, and a sequence of windows (each window being essentially the positive half of a square wave) is generated with a period and phase that are updated on the basis of the recent history of the output of shift register 90, in such a way as to tend to center the windows on pulses 87. Any pulse 87 received outside a window is ignored for readout purposes. The loop similarly ignores any two or more pulses that fall within a single window. The value read out is the actual time between pulses 87 when they occur singularly in consecutive windows. When only one of two consecutive windows has a single pulse, the readout is the time from that pulse to the center of the window. When neither of two consecutive windows has a single pulse, the readout is the time between the center of the windows. If too many windows occur without single pulses, or if too many pulses occur outside windows, readout is temporarily halted. Window phase is updated only when single pulse windows occur, and window period (frequency) is updated only when consecutive single pulse windows occur.

The algorithm employed in the phase lock loop is illustrated in the flow chart of FIG. 9. The window width (block 100) is roughly (a more precise definition appears below) half the running period of the loop, i.e., half the interval from the middle of one window to the middle of the next. As shown in the flow chart, the pulse pattern in the current and next previous windows controls the values of "New Period" (which ultimately provides the rate readout). "Average Period" (which in turn determines the actual window frequency, as well as window width), and "Interval Between Windows" (which in the absence of a window frequency adjustment, controls window phase). In particular, if the current window contains multiple pulses or no pulse, no adjustment is made in either New Period (block 102) or Average Period (block 104), and the Interval remains half the Average Period (block 106). If such a window is followed by one in which a single pulse occurs, New Period is adjusted to equal the time from the middle of the first window to the pulse in the second (block 108), Average Period is left unchanged (i.e., no frequency adjustment, block 110), and the Interval is adjusted to equal three-fourths of Average Period minus the time between the end of the current window and the pulse therein (block 112). That is, window phase is adjusted so that the next pulse 87 will be centered in its window (if pulse frequency has not changed), yet without changing window frequency, since the information in the previous window was unreliable and an erroneous frequency adjustment based upon that unreliable information would produce an error that would grow from window to window. Finally, when two consecutive windows contain single pulses, New Period is adjusted to equal the time between the successive pulses 87 (block 114), Average Period is adjusted to half the sum of the updated New Period and the old Average Period (block 116, thus giving a frequency adjustment, though only by enough to account for half of any changes in the interval between pulses 87, to avoid over-correction), and the Interval is adjusted to equal three-fourths of the new Average Period minus the time between the end of the current window and the pulse therein (i.e., phase is adjusted too, block 118). (It should be noted that the value readout is always New Period, which is not directly affected by the frequency and phase adjustments just described.)

Because of its digital nature, employing high resolution counters, the phase lock loop is able to operate over a wide range of frequencies (e.g., 60-240 pulses per minute), and makes it possible to postpone adjustment and readout decisions until the end of each window.

A counter keeps track of the relationship between pulses 87 that occur outside windows and those that occur singularly inside windows. The count is incremented one for each outside pulse (block 117) and decremented one half for each single inside pulse (block 119). (The counter ignores multiple inside pulses). When the count reaches 5 readout of New Period is halted (block 120). When the count returns to less than 5 readout is resumed (block 122). Should the count reach 8 or more, readout is halted (block 120), the counter is zeroed, and a Restart routine is initiated (block 124).

In the Restart routine it is arbitrarily assumed that the pulse 87 which caused the counter to reach 8 corresponded to a real fetal pulse, and the time to the next pulse 87 is measured (block 126). Should that next pulse arrive in less than 250 milliseconds it is ignored (block 128), because it would signify an unlikely fetal rate of more than 240 beats per minute. On the other hand, should that next pulse not arrive by 800 milliseconds, the counter is zeroed and, upon the arrival of the next pulse 87, the Restart routine is begun again (block 130); here again, restart at an unlikely (here too low) rate is prevented. (Although the absence of a pulse for 800 milliseconds corresponds to 75 beats per minute, rather than the lower limit of 60 beats per minute to which tracking is desired, allowing a restart at less than 75 would substantially increase the risk of restarting at half the true rate in the event that, over a period of time, maternal beats should mask every other fetal beat. If, nevertheless, restart should occur at half the true rate, the technique of counting pulses inside windows at only half the weight as outside pulses ensures an eventual reinitiation of the Restart routine.) Finally, still referring to block 126, should a second pulse arrive within 250-800 milliseconds, New Period and Average Period are set equal to the measured time between the two pulses (blocks 132, 134), and the counter is set arbitrarily at 6 (block 136). Then, if the count decrements to 4, readout is resumed; if it returns to 8, the Restart routine is reentered.

The algorithm thus set forth strikes an excellent balance between avoiding readout of erroneous information and minimizing readout outages during which accurate information is lost.

FIG. 10 illustrates in block diagram form the implementation of the phase lock loop and associated readout components. The detailed circuitry appears in FIG. 11a-d, 12, 13. Referring to those Figures, the signals from shift register 90 pass into New Period measurement circuitry 150 (FIG. 11b), composed of two four-bit counters 152, 154 with parallel loads a JK flip flop 156 for clearing the counters. The New Period data goes to four-bit full adders 158, 160 in Interval Between Window Generator 162 (FIGS. 11b, 11c), which adders also receive the Average Period data generated in block 164 (FIG. 11b). The signals from the full adders pass into the parallel loads of four-bit counters 166, 168, which generate the Interval Between Windows data. The counter 166, 168 start out preset to the sum of one-fourth the Average Period plus the value thus for counted in the New Period counters 152, 154 (the latter value being the time between the just previous pulse and the end of its window), and increment one during each clock cycle. Two four-bit binary comparators 170, 172 signal when the count on counters 166, 168 equals the stored Average Period value, signifying the end of the Interval Between Windows. That signal then passes to Window Generator 174 (FIG. 11c), which starts the window and, with four bit counters 176, 178 controls its width at half the Average Period value. Counters 176, 178 are loaded with half the value of the last Average Period, and decrement one during each clock cycle; at zero the correct width will have been generated.

Restart counting circuitry 180 (FIG. 11a) includes four-bit up-down counter 182 with parallel load, and a JK flip flop 184 which generates a count of one for every other input for counting down, providing the weighting factor described above.

The New Period value is stored in four-bit registers 190, 192 in block 194 (FIG. 11d), and goes to digital-to-analog converter 196 (FIG. 11d) for conversion into an analog voltage. That voltage, a measurement of period, passes to analog storage circuitry 198, which includes a junction FET 200 and a high input impedance operational amplifier 202, as well as logical circuitry to inhibit readout when counter 182 is at 5 or more. From the storage circuitry the signal goes to analog divider 204 which converts it to rate information by generating an analog signal proportional to the reciprocal of the period signal. The output from the divider is amplified and given some D.C. offset (to restore the level to the correct base line reference) in amplifier 206, and then is fed to digital voltmeter readout 208 and strip chart recorder 210.

The gain between the input to storage circuitry 198 and the output of divider 204 is adjusted so that each 10 millivolts of output corresponds to a rate of one heart beat per minute. Thus, a digital voltmeter which has a reading of 100 for a 1 volt input gives the exact count of the heart reat in beats per minute. Similarly, the strip recorder is set up for direct reading of the rate. Thus, off the shelf readout devices can be used.

FIG. 12 illustrates a 2KHz oscillator 220 which is a source of clock signals for the digital logic. The signal is divided down in four-bit counter 222 to a 256Hz square wave T, along with faster versions T' and T".

FIG. 13 illustrates a 1Hz oscillator 224 which generates a clock pulse to control the readout rate.

Key parts employed in the particular embodiment described are as follows:

1. Fairchild MA739C dual low noise operational amplifier is used for amplifiers 12 and 13.

2. Teledyne Philbrick 1319 is used for bandpass stages 28 and 30.

3. Oscillators 29 and 31 are Signetics NE566.

4. Analog phase lock loops 33 and 35 are Signetics NE565.

5. All other operational amplifiers in the analog circuitry are Fairchild MA741.

6. All analog comparators are National Semiconductor LM311.

7. All one shots are Fairchild 9601.

8. FET 200 is Motorola 2N4220.

9. The preamplifier power supply output transistors are Texas Instruments 2N3704, and all other transistors are Fairchild 2N4275.

10. Matched diode pairs are Fairchild FA2000, and all other diodes are Motorola 1N914.

11. Analog divider 204 is Teledeyne Philbrick 4452.

12. Digital to analog converter 186 is Analog Devices MDA8H.

13. The logic elements comprise Texas Instruments:

Sn 7400 quadruple two input NAND Gate

Sn 7402 quadruple two input NOR Gate

Sn 7408 quadruple two input AND Gate

Sn 7404 6 input inverter

Sn 7410 triple input NAND Gate

Sn 74107 jk flip Flop

SN 7483 4 bit full adder

Sn 7485 4 bit comparator

Sn 74193 4 bit counter (up-down) with parallel load.

Sn 7498 4 bit register with dual parallel load.

Sn 74164 8 bit serial shift register.

Other embodiments (e.g., picking up both fetal and maternal signals with the same abdominally placed electrode; or for fetal rate monitoring with scalp electrodes using a single filter train for the fetal QRS; or for detecting, in any ECG signal, T waves by elimination of the QRS, or even P waves by successive removal of QRS and T waves, thus using three finter trains, this being useful, e.g., for synchronizing the taking of X-rays in diastole or systole; or for other sorts of physiological monitoring; or "removing" maternal signals other than in the manner shown, as, e.g., by tracking the maternal signals and inhibiting any response thereto by the peak detector and the comparator; etc.) are within the following claims.

Claims

We claim:

1. In a fetal heart rate monitor having a pickup for electrical signals received through the body of the mother, and means for providing an output relating to fetal heart rate,

input circuitry means defining a signal processing path and responsive to said pickup for producing along said path a signal train including first signals representing maternal heart beats and second signals representing fetal heart beats, some of said first signals also representing fetal heart beats which occurred simultaneously with maternal heartbeats,

removal means for removing from said path at least the major portions of said first signals, whereby blank spaces are left by such removal of those of said first signals representing fetal heart beats which occurred simultaneously with maternal heart beats and

circuitry means defining a phase lock loop having a frequency and including means responsive to the thus modified train of signals for generating fetal heart rate signals related to said frequency, said phase lock loop including means responsive to the spacing characteristics between said signals in said modified train for estimating fetal heart rate during the occurrence of said blank spaces in said modified train,

said circuitry means defining said phase lock loop including means for producing repeating windows spaced to overlap a fetal signal on the basis of past spacing statistics despite variation within predetermined limits, said circuitry means further including updating means for detecting the position of successive fetal signals within the respective windows and for varying future windows spacing on the basis of the detected position of the signals in the windows.

2. The fetal heart rate monitor of claim 1 wherein means are provided for producing, at said phase lock loop, a train of digital signals, each representing a fetal QRS complex, including means for disabling said updating means upon the occurrence of no pulse or more than one pulse in said window, thereby continuing the use of the past spacing setting.

3. The fetal heart rate monitor of claim 2 wherein said updating means includes means to relocate the next window upon the occurrence of a single pulse in the present window by pulse shift of the past spacing in the event no single pulse appeared in the last preceding window.

4. The fetal heart rate monitor of claim 2 wherein said updating means includes means to relocate the next window upon the occurrence of a single pulse in the present window by alteration of the loop frequency in the event a single pulse appeared in the last preceding window.

5. The fetal heart rate monitor of claim 2 wherein said updating means includes means to relocate the next window upon the occurrence of single pulses in two successive windows by alteration of the loop frequency so that the corresponding altered window period is between the window period prior to said alteration and the spacing between said two single pulses.

6. The fetal heart rate monitor of claim 1 including a counter, means for incrementing said counter upon the occurrence of signals outside said window and means for decrementing said counter upon the occurrence of signals inside said window, including means for weighing more heavily in said count the signals outside said window and means for resetting said phase lock loop upon the occurrence of a count greater than a predetermined value.

7. The fetal heart rate monitor of claim 1 further comprising circuitry means defining a second signal processing path and for transmitting along said second path third signals representing maternal heart beats, said removal means having a connection to said circuitry means defining said second path and being responsive to occurrence of said third signals in said second path.

8. The fetal heart rate monitor of claim 7 including in said circuitry means defining said second path, preceding said connection, an automatic threshold means for generating from a signal derived from a maternal QRS complex a signal representative thereof.

9. The fetal heart rate monitor of claim 8 including as said threshold means a peak detector including means for fixing predetermined limit and for storing a value less than said limit and allowing said stored value to decay over time, and a comparator effectively connected to said peak detector and to said circuit means defining said second path for generating an output signal when a signal in said second path exceeds the decayed value of the preceding peak stored in said detector.

10. The fetal heart monitor of claim 9 including a monostable multivibrator effectively connected to said comparator foor energization upon the occurrence of said output signal, said monostable multi-vibrator having a time constant substantially corresponding to the maximum width of the maternal QRS complex.

11. The fetal heart rate monitor of claim 7 wherein there is included in said circuitry means defining said first path an automatic threshold means for generating from a fetal QRS complex wave a signal representative thereof.

12. The fetal heart rate monitor of claim 11 including as said threshold means a peak detector including means for fixing a predetermined limit and for storing a value greater than said limit and allowing said stored value to decay over time, and a comparator effectively connected to said peak detector and to said circuitry defining said first path for generating an output signal when a signal exceeds the decayed value of the preceding peak stored in said detector.

13. The fetal heart rate monitor of claim 12 including means in said first path effectively connected to said comparator and responsive to signals in said second path for removing output signals from said comparator which coincide in time with a maternal QRS complex, thereby to remove portions of maternal signals present in the output of said comparator.

14. The monitor of claim 1 wherein said phase lock loop is digital.

15. In a monitor having a pickup for a first electrical signal representing a first component of a recurring complex biological signal including a second component that is stronger than the first component, and output circuitry means including means for providing an output related to occurrences of said first component,

circuitry means defining a signal processing path in which said first signals are detected and along part of which second signals representing occurrences of said second component are transmitted, and

automatic thresholding means in said path for tracking the magnitude of signals other than said second signals and providing an output to said output circuitry means signifying the occurrence of said first component only upon receipt of a signal other than a said second signal and of magnitude bearing a predetermined relationship to the magnitude of the next previously tracked signal but being independent of signals tracked prior to said next previously tracked signal.

16. The monitor of claim 15 further comprising circuitry means defining a second signal processing path and for transmitting therealong, in timed relationship to said transmission of said second signals along said first path, third signals representing said occurrences of said second component, and means for detecting said third signals and, in response to said detection, for preventing effective response by said automatic thresholding means to said second signals.

17. The monitor of claim 16 for use in monitoring the rate of fetal heartbeats, wherein said pickup includes a plurality of electrodes for placement on the mother in separate positions respectively optimizing the pickup of maternal and fetal QRS complex signals, and said circuitry means defining said paths includes separate preamplification means effectively connected to said electrodes for respectively receiving and amplifying said maternal and fetal signals, whereby said first and second signal paths are separate at their front ends.

18. The monitor of claim 16 wherein said second path includes automatic thresholding means for tracking signal magnitude and providing an output to said automatic thresholding means in said first path signifying the occurrence of said second component only upon receipt of a signal of magnitude bearing a predetermined relationship to previously tracked signal magnitude.

19. The monitor of claim 15 wherein said automatic thresholding means includes

means for storing and decaying over time the peak value of a received signal, and

a comparator effectively connected to said means for storing, said comparator including means for providing said output when a received signal is greater than a predetermined percentage of the decayed value presently stored.

20. The monitor of claim 19 wherein means are provided for fixing said predetermined percentage at 70-90 percent.

21. The monitor of claim 19 wherein said means for storing includes means for preventing the value stored therein from decaying below a limit, including means for establishing said limit.

22. The monitor of claim 21 wherein said means for establishing said limit includes means for monitoring the past history of signals reaching said automatic thresholding means and for varying said limit in accordance with said history.

23. The monitor of claim 21 wherein said means for establishing said limit includes means for fixing said limit.

24. The monitor of claim 15 further comprising

removal means for removing at least the major portions of said second signals from said path, while leaving leading edges of said second signals,

delay means for receiving signals from said removal circuitry, including signals representing said leading edges, and

means for excluding from the effective output of said delay means said signals representing said leading edges.

25. The monitor of claim 24 further comprising means for detecting the falling edges of said first signals and for causing said output of said delay means to be responsive to the occurrences of said falling edges.

26. In a fetal heart rate monitor, electrode means for picking up electrical signals corresponding to fetal QRS complex signals,

signal processing circuitry means effectively connected to said electrode means and including

a pre-amplifier for receiving said electrical signals from said electrode means,

a filter for the amplified signals, said filter having Q less than 10 and including means to provide an output in which at least 25 percent of the signal energy is in the 50-100 Hz range, exclusive of line frequency noise, and

a notch filter for removing said line frequency noise, and

means effectively connected to said signal processing circuitry for providing an output relating to fetal heart rate.

27. The monitor of claim 26 comprising automatic thresholding means effectively connected between said filters and said readout for tracking signal magnitude and providing an output signalling the occurrence of a fetal QRS complex only upon receipt of a signal of magnitude bearing a predetermined relationship to previously tracked signal magnitude, said thresholding means including means for determining said relationship.

28. The monitor of claim 27 further comprising additional signal processing means for electrical signals corresponding to maternal QRS complex signals, and means connected in the signal path leading to said automatic thresholding means for preventing at least the major portion of electrical signals corresponding to maternal QRS complex signals from reaching said automatic thresholding means, said means for preventing being responsive to detection of said electrical signals processed by said additional signal processing means.

29. The monitor of claim 26 wherein said processing circuitry from said electrode means through said filter includes means to provide linear processing of input signals.

30. In a fetal heart rate monitor having a pickup for electrical signals received through the body of the mother, and output circuitry means including means for providing an output relating to fetal heart rate,

input circuitry means defining a signal processing path and responsive to said pickup for producing along said path a signal train including first signals representing maternal heart beats and second signals representing fetal heart beats, some of said first signals also representing fetal heart beats which occurred simultaneously with maternal heart beats,

removal means for removing from said path at least the major portions of said first signals, whereby blank spaces are left by such removal of those of said first signals representing fetal heart beats which occurred simultaneously with maternal heart beats,

circuitry means defining a phase lock loop having a frequency and including means responsive to the thus modified train of signals for generating and providing to said output circuitry means fetal heart rate signals related to said frequency, said phase lock loop including means responsive to the spacing characteristics between said signals in said modified train for estimating fetal heart rate during the occurrence of said blank spaces in said modified train, and

circuitry means defining a second signal processing path and for transmitting along said second path third signals representing maternal heart beats, said removal means having a connection to said circuitry means defining said second path and being responsive to occurrence of said third signals in said second path,

said circuitry means defining said second path including, preceding said connection, input means for a maternal QRS complex signal, a notch filter for removing line frequency noise, and a band pass filter having Q less than 10 and a center frequency between 15 Hz and 25 Hz.

31. In a fetal heart rate monitor having a pickup for electrical signals received through the body of the mother, and output circuitry means including means for providing an output relating to fetal heart rate,

input circuitry means defining a signal processing path and responsive to said pickup for producing along said path a signal train including first signals representing maternal heart beats and second signals representing fetal heart beats, some of said first signals also representing fetal heart beats which occurred simultaneously with maternal heart beats,

removal means for removing from said path at least the major portions of said first signals, whereby blank spaces are left by such removal of those of said first signals representing fetal heart beats which occurred simultaneously with maternal heart beats,

circuitry means defining a phase lock loop having a frequency and including means responsive to the thus modified train of signals for generating and providing to said output circuitry means fetal heart rate signals related to said frequency, said phase lock loop including means responsive to the spacing characteristics between said signals in said modified train for estimating fetal heart rate during the occurrence of said blank spaces in said modified train, and

circuitry means defining a second signal processing path and for transmitting along said second path third signals representing maternal heart beats, said removal means having a connection to said circuitry means defining said second path and being responsive to occurrence of said third signals in said second path,

said circuitry means defining said first path including, preceding said connection, input means for a fetal QRS complex signal, a notch filter for removing line frequency noise, and a band pass filter having Q less than 10 and a center frequency between 25 Hz and 40 Hz.

32. In a fetal heart rate monitor having a pickup for signals emanating from the fetus,

input circuitry means responsive to said pickup for producing a signal train including signals representing fetal heart beats,

prediction circuitry means responsive to said input circuitry for predicting occurrences of said signals representing fetal heart beats, based upon past occurrences of such signals in said train, and

output circuitry means responsive of said input and prediction circuitry means for providing an output relating to fetal heart rate, said output circuitry means including means for basing said output on said signals representing fetal heart beats when such signals occur within a predetermined range of predicted occurrences thereof and for otherwise basing said output on said predicted occurrences,

said prediction circuitry means including means for basing said predictions at least in part upon selected previous predictions upon which said output was based.

33. The improvement of claim 32 wherein said prediction circuitry means includes means for referring the phase of a said predicted occurrence to the next previous said predicted occurrence if said output was based thereupon, and otherwise to the next previous said signal representing a fetal heart beat upon which said output was based.

34. The improvement of claim 32 wherein said output circuitry includes means for basing said output upon a said predicted occurrence whenever more than one pulse in said signal train occurs within said predetermined range of said predicted occurrence.

35. In a monitor having a pickup for a first electrical signal representing a first component of a recurring complex biological signal including a second component that is stronger than the first component,

input circuitry means responsive to said pickup for producing a signal train including signals representing occurrences of said first component,

prediction circuitry means responsive to said input circuitry for predicting occurrences of said signals representing occurrences of said first component, based upon past occurrences of such signals in said train, and

output circuitry means responsive to said input and prediction circuitry means for providing an output related to occurrences of said first component, said output circuitry means including means for basing said output on said signals representing occurrences of said first component when said signals occur within a predetermined range of predicted occurrences thereof and for otherwise basing said output on said predicted occurrences,

said prediction circuitry means including means for basing said predictions at least in part upon selected previous predictions upon which said output was based.

36. In a fetal heart rate monitor having a pickup for signals emanating from the fetus,

input circuitry means responsive to said pickup for producing a signal train including signals representing fetal heart beats with attendant noise signals and with some heart beats unrepresented in the signal train,

prediction circuitry means responsive to said input circuitry for predicting occurrences of said signals representing fetal heart beats, based upon past occurrences of such signals in said train, and

output circuitry means responsive to said input and prediction circuitry means for providing an output relating to fetal heart rate,

said prediction circuitry means including means for repeatedly producing a window overlapping the predictable point in time of the next heart beat based upon past occurrences, said output circuitry means responsive to a signal occurring in a window to treat said signal as a detected heart beat and agjust the output according to the position of the signal in the signal train, said output circuitry means further including means for disregarding as noise any signals occurring outside of said window, means causing said prediction circuitry to continue to operate when a heart beat is not detected in a window to produce a window for the next succeeding heart beat, said window having a duration sized to overlap a fetal heart beat signal in the presence of a predetermined amount of predicted change in fetal heart rate which may occur over a plurality of heart beat intervals.

37. The monitor of claim 36 wherein said output circuitry includes means for disregarding as noise occurrences of multiple signals in a single window.

38. The monitor of claim 36 wherein the duration of each said window is approximately one half of a predicted fetal heart beat interval.

39. The monitor of claim 38 wherein said prediction circuitry establishes the duration of said windows based upon the duration of the currently predicted heart beat interval.

40. In a monitor having input circuitry means including a pickup for a train of signals, including true and false signals, representative of a selected component of quasi-periodic, complex physiological electrical signals, signal-to-signal spacing being variable, and output circuitry means including means for providing an output relating to real and expected occurrences of said component:

means for receiving said train of signals from said input circuitry means;

window means responsive to said input circuitry means for producing windows spaced in accordance with the previous history of said train of signals for enabling said receiving means to effectively receive said signals only during an interval prescribed by each said window; and

output means coupled to said receiving means and window means for producing and providing to said output circuitry output signals indicative of real and expected occurrences of true quasi-periodic signals occurring in said train.

41. The monitor of claim 40, further comprising:

quality means responsive to said input circuitry means and said window means for providing a quality signal indicative of the occurrence of true signals relative to false signals from said train of signals; and

control means responsive to said quality means for controlling the operation of said window means in accordance with said quality signal.

42. The monitor of claim 41, wherein:

said quality means includes counter means for counting signals occurring between said windows; and

said control means operates to reset said window means to its initial condition in the event the number of such counts exceeds a predetermined magnitude.

43. In a monitor having input circuitry means including a pickup for recurrent complex electrical physiological signals having a first component weaker than a second component and in the presence of extraneous recurrent noise signals, and output circuitry means including means for providing an output relating to occurrences of said first component, processing circuitry means coupled to said input and output circuitry means and comprising:

band pass filter means having a Q under 10 for passing signals having a frequency content spanning the maximum energy in said first component;

notch filter means for excluding extraneous noise of a selected frequency; and

automatic threshold means responsive to said filtered first component for excluding signals below a threshold determined as a function of previously received filtered first component signals to produce and provide to said output circuitry means a train of signals representative of said first component.

44. In a monitor having a pickup for electrical signals representing occurrences of at least a component of a recurring complex biological signal,

input circuitry means responsive to said pickup for producing a signal train including said signals representing said occurrences,

prediction circuitry means responsive to said input circuitry means for making predictions of said occurrences based upon past history of said signals in said train,

output circuitry means responsive to said input and prediction circuitry means for providing an output relating to occurrences of said component, including elements for basing said output upon said predictions under predetermined circumstances,

quality circuitry means for determining deviation of said signals from said predictions and thereby evaluating the reliability of said output, and

restart circuitry means for reinitiating derivation of said predictions when said quality means indicates a predetermined degree of unreliability.

45. In the monitor of claim 44, output disabling means for preventing output when said quality means indicates a predetermined degree of unreliability, including means for requiring a higher reliability to permit output during said reinitiation than when said reinitiation is completed.

46. The monitor of claim 44 wherein the restart circuitry means includes means for requiring a higher degree of reliability for acceptance of an attempted reinitiation than the reliability required when said reinitiation is completed.