Electronic Time Measurement

Abstract

A display which includes a plurality of numeric indicators is driven at one of a number of frequencies such as 10, 100 and 1,000 Hz, for measuring time in increments such as tenths, hundredths or thousandths of a second. A switch is provided for enabling the user to change from one frequency to another. The switch also is connected to decimal point indicators on the display for automatically selecting the decimal point appropriate to the frequency selected.

Description

SUMMARY OF THE INVENTION

Time measurement system including a display and means, including counter means, coupled to the display for driving the same for causing it to display a quantity representing the count stored in the counter means. The system also includes means producing a plurality of alternating signals, each at a different frequency, and selector means for applying to the counter means a particular one of these signals for causing the counter to advance at the frequency of that signal. A preferred form of the invention includes means responsive to the selector means for indicating on the display the magnitude of the units of time represented by the quantity displayed thereon.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a stop watch according to one embodiment of the invention;

FIG. 2 shows in more detail the exclusive OR gates of FIG. 1 and their connections to segments of the numeric indicators;

FIG. 3 is a cross section taken along line 3--3 of FIG. 1 of the liquid crystal numeric indicator;

FIG. 4 shows a portion of the arrangement of FIG. 1 in modified form to make the circuit suitable for use both as a customary stop watch and as a reaction timer stop watch; and

FIG. 5 illustrates another modified system useful both as a customary stop watch and a reaction timer stop watch.

DETAILED DESCRIPTION

The stop watch of FIG. 1 includes a system time base, namely oscillator 10, which operates at a frequency such as 100 KHz. Preferably the oscillator is a stable oscillator such as one of the crystal controlled type. The oscillations produced by oscillator 10 are applied to frequency divider 12. The latter may have a number of 10 to 1 division stages for producing signals at frequencies of 1,000, 100 and 10 Hz respectively. These various signals may be unipolarity, symmetrical, square wave signals which, for example, may vary between two limits such as 0 and +15 volts. Zero volts may represent binary 0 and +15 volts binary 1.

Switch 14 connects one of the output terminals 15, 16 or 18 of the frequency divider 12 to one input terminal to NOR gate 20. The latter connects to counter 22 which has a plurality of output leads to decoder 24. The decoder connects to EXCLUSIVE OR gates 26 which, in turn, drive the segments of the numeric display panel 30.

The display panel includes several numeric indicators -- four are shown at 32a -- 32d by way of example, with decimal point indicators 33a, 33b and 33c positioned as shown. The panel is shown in cross section in FIG. 3 and as seen there includes a transparent front plate 6 and a back plate 7, in both cases, made of a material such as glass. A conductive back plate 1 is located on the inner surface of the glass plate 7 and the indicator segments A to G are located on the inner surface of the front plate 6. A liquid crystal 5 such as one of the nematic type which operates on the principle of dynamic scattering, is located between the glass plates.

The segments are formed of transparent conductors and the back plate, in the case of a transmissive type indicator, is also formed of a transparent conductor but in the case of a reflecting type indicator is formed of a reflecting conducting material. The decimal points, which are not shown in FIG. 3, are also located on the inner surface of front plate 6. In the present use, the back plate 1 may be common to all four indicators and the decimal points, that is, the back plate may extend over the entire area beneath the four indicators.

A 100 Hz display energizing signal produced by frequency divider 12 is applied to one input terminal to each EXCLUSIVE OR gate in block 26, to the conductive back plate of the indicator 30 and to the conductive region 50 of rotary switch 40. The 100 Hz energizing signal is inverted by inverter 34 and the inverted energizing signal (100Hz) is supplied to the conductive arm 36 of switch 40. Arm 36 is insulated from region 50. The switch 40 is ganged with the switch 14 and, as can be seen in FIG. 1, the arm 36 of switch 40 contacts the terminal for the decimal point corresponding to the counter driving frequency selected. In the present example, this is terminal 45. The other two terminals contact region 50 of switch 40.

In the operation of the stop watch of FIG. 1, the user first sets the ganged switches 14 and 40 to the scale desired. In the circuit illustrated, switch 14 is set to contact 15 so that arm 36 of switch 40 is at contact 45. With the switches in this position, a 10 Hz timing signal is applied to one input terminal to NOR gate 20, a 100Hz energizing signal is applied to decimal point 33c, and a 100Hz energizing signal continuously is applied to the conductive back plate 1. The energizing signals applied between decimal point 33c and the back plate are 180.degree. out of phase. The result is that an alternating electric field develops between the decimal point 33c and the back plate of sufficient intensity to cause the liquid crystal beneath decimal point 33c dynamically to scatter light.

With the remaining two decimal points 33a and 33b contaCting the conductive region 50 of the rotary switch 40, the 100Hz energizing signal is applied via region 50 to these two decimal points. Accordingly these two decimal points are energized in phase with the back plate 1, so that no voltage develops between decimal points 33a and 33b on the one hand and the back plate on the other hand. The liquid crystal behind these decimal points therefore remains in its unexcited or transparent condition.

Returning now to the upper portion of FIG. 1, NOR gate 20 receives the 10Hz signal. With switch 52 initially in the reset position, the control logic circuits 51 supply a voltage indicative of binary 1, such as +15 volts, to the NOR gate so that the gate continuously produces a low output indicative of binary 0. The NOR gate 20 can be considered disabled in this condition and the counter 22 does not count.

When it is desired to start the stop watch, switch 52 is moved from the reset position directly to the start position. In this position, the control logic circuits apply a voltage indicative of a 0 (such as ground) to the second input terminal to NOR gate 20. The NOR gate can be considered to be primed in this condition and it applies the 10 Hz signals to the counter 22 and the latter counts these signals. (In the process of passing through the NOR gate 20, the 10 Hz signals are inverted but this does not affect the operation.) The decoder gates 24 which are connected to the counter 22 are now enabled in accordance with the stored count.

There are a relatively large number of decoder gates in block 24. When such a gate is enabled by a particular combination of counter output signals, it produces an output representing a 1 and when a decoder gate is disabled, it produces an output representing a 0.For purposes of the present example, it is assumed that when it is desired that a number of segments go on, the decoder gates for these segments will produce 1's and when it is desired that segments be off, the decoder gates for those segments will produce 0's. (With minor circuit redesign the opposite convention would work just as well.)

One manner of connection of the decoder gates in block 24 to the EXCLUSIVE OR gates 26 is shown in more detail in FIG. 2. Each exclusive OR gate receives both a signal from the decoder and the 100 Hz energizing signal. Each exclusive OR gate connects to a segment of the display. For purposes of the present example, three such gates 60, 61 and 62 are illustrated and a number of the segments are illustrated. Gate 60 receives a 1. Accordingly, when the 100 Hz signal has an amplitude representing a 1, the gate 60 produces an output representing a zero and when a 100 Hz signal has an amplitude representing a zero, gate 60 produces an output representing a 1. It is clear therefore that when an exclusive OR gate receives a 1, the output 100 Hz signal it produces is complementary to (180.degree.out of phase with) the 100Hz signal it receives. It can also be shown that an exclusive OR gate such as 61 which receives a 0 at one input terminal, produces an output 100Hz signal which is in phase with the 100Hz signal it receives. Thus, in FIG. 2 the segment A of indicator 32a is energized (the liquid crystal beneath this segment dynamically scatters light) whereas the segment B of the same indicator is not energized. The energized segment is illustrated by cross-hatching. Energization at A occurs because the segment voltage is 180.degree. out of phase with the back plate voltage resulting in push-pull operation of the liquid crystal; segment B remains unenergized because the back plate voltage and segment voltage are in phase (push-push operation).

The display discussed above is especially advantageous for use with complementary symmetry metal oxide semiconductor (CMOS) integrated circuits. Such circuits may form the oscillator, frequency-divider, counter, decoder, EXCLUSIVE OR gates, and so on. With circuits of this kind, the alternating voltage signal produced is a unipolarity alternating voltage as described above, that is, it extends from a zero base line to say a plus value such as 15 volts (or alternatively from a zero base line to a negative value such as -15 volts). By operating the liquid crystal numeric indicator in the way described, the average direct current component through the liquid crystal is zero and it is necessary that this be so in the present state of development of liquid crystals to insure long life for the crystal.

In the operation discussed above, when it is desired to stop the stop watch, switch 52 is moved to the stop position. The control logic circuits 51 then supply a binary 1 signal (+15 volts) to the NOR gate disabling the latter.

When it is desired to reset the stop watch, switch 52 is moved to the reset position. This causes a +V reset voltage to be applied to the counter and the latter resets to its initial count which may be zero. The decoder may be arranged to cause all four indicators to display zeros under this set of conditions.

To change scale, the ganged switches 14 and 40 are moved to a new position. For example, to change from tenths of a second to hundredths of a second, switch 14 is moved to contact 16. This selects the 100Hz timing signal which, when switch 52 is placed in the start position, is applied through NOR gate 20 to the counter 22. When the switch 14 is moved to position 16, the rotary switch 40 connects the 100Hz energizing signal to decimal point 33b via arm 36 and contact 46. Decimal points 33a and 33c will concurrently receive the 100Hz energizing signal.

A feature of the present invention, in addition to the automatic decimal point selection when changing scale, is that the decimal point may be employed as a scale indicator. The decimal point remains on at all times. For example, with the stop watch selecting the one-tenth second scale, as shown in FIG. 1, decimal point 33c remains on regardless of the position of switch 52. This indicates to the user that the stop watch is set up to count in tenth of a second increments. The maximum count possible at this scale is approximately 1,000 seconds (actually 999.9 seconds). When moving to the next scale, that is, the one hundredths of a second scale, decimal point 33b goes on and the maximum count possible reduces to 99.99 seconds. At the third scale, the maximum count is approximately ten seconds.

While switch 52 is illustrated as a mechanical switch, it is to be understood that in some applications, for example when counting at thousandths of a second, that an electronic switch may be used instead. The switch may be a semiconductor device such as an MOS transmission gate which is normally maintained in the high impedance condition and which is turned on by an elecrical signal applied to a gate electrode thereof. A switch of this kind is desirable where measurements of time to high precision is of interest. The reset switch may also be an electronic switch, if desired.

FIG. 4 shows a modification of the circuit which permits it to be used either as a simple stop watch or as a reaction timer stop watch. In a reaction timer it is desired that the measurement of time start at some variable interval of time after switch 64 is moved from the off position to the reaction timer position 68.

The modified circuit of FIG. 4 includes the elements of FIG. 1 (only a few of which are shown) and also: ganged switches 64 and 66, switch 74, which is ganged to switch 52, variable delay means 62, and the lamp 70. The switch 66 is connected in series with the variable delay means 62, the lamp 70 and the switch 74.

In the operation of the arrangement shown in FIG. 4, when the switch 60 is in the stop watch position, the circuit operates exactly as described in connection with FIG. 1.

When it is desired to operate the system as a reaction timer, switch 52 initially is in the "reset" position and switch 64 and its ganged switch 66 are thrown to the "off" position. Switch 52 now is placed in the "start" position. In view of the fact that +V is disconnected from the switch 52, the control logic 51 continues to apply a 1 to NOR gate 20 disabling the NOR gate.

To start the reaction timer, ganged switches 64 and 66 are thrown to the "reaction timer" position. The voltage +V now connects through switch 66 to the variable delay means 62. After the delay interval inserted by the variable delay means, +V appears at the reaction timer terminal 68 causing the lamp 70 to go on and causing the control logic 51 to supply a 0 to NOR gate 20. This permits the counter 22 to start counting.

When it is desired to stop the counter, switch 52 is moved to the "stop" position. This concurrently causes the counter to stop counting and the lamp 70 to go off, the latter because of the opening of switch 74 which is ganged to switch 52. The count registered on the indicator panel 30 of FIG. 1 when the counter stops counting is the interval between the instant the lamp 70 went on and the instant the switch 52 is placed in the "stop" position.

The variable delay means 62 may either be electronic or mechanical in nature. In either case the delay introduced may be preset to one or a number of different values or it may be randomly variable. A randomly variable delay means is shown in FIG. 5.

A second form of combined customary stop watch and reaction timer stop watch is illustrated in FIG. 5. This circuit includes elements of FIG. 1, only some of which are shown, and additional elements. (The switch 52 of FIG. 1 is replaced with the single-pole, double-throw switch 52a, as discussed below). The control logic 51 is shown in detail and includes four triggerable flip-flops 80, 82, 84 and 86 and a decoder AND gate 88. The A output terminal of flip-flop 80 connects to the data input terminal (D) of flip-flops 82 and 84. The A terminal of flip-flop 80 connects to AND gate 88, to the reset terminal (R) of flip-flop 84 and to the "stop watch" terminal of switch 90. The B terminal of flip-flop 82 connects to the trigger terminal (T) of flip-flop 86. The B terminal of flip-flop 82 connects to AND gate 88. The C terminal of flip-flop 84 connects to the D terminal of flip-flop 86 and to the base electrode 92 of transistor 94. The C terminal connects to the "reaction timer" terminal of switch 90.

The circuit also includes a set-reset flip-flop 96 connected at its 0 output terminal to the trigger terminal of flip-flops 80 and 82. The push button control switch 52a normally connects +V to the set terminal and when depressed momentarily, connects +V to the reset terminal of flip-flop 96. The push button 98 normally is spring biased relative to chassis 97 to connect +V to the set terminal of flip-flop 96. The button and its shaft may be insulated from the switch 52a or may be formed of insulating material.

The variable delay means 62 is one which can be considered to be randomly variable. It consists of a frequency divider, such as a 100 to 1 divider, which receives a signal such as the 10Hz signal, from the frequency divider of FIG. 1. This frequency divider operates continuously and in this example applies one pulse every ten seconds to the trigger terminal of flip-flop 84.

The system also includes a second switch 99 mechanically ganged to switch 90. The switch 99 is in series with the lamp 70 and the collector-to-emitter path of transistor 94.

The conventions employed in the circuit of FIG. 4 are as follows. A triggerable flip-flop is triggered on the positive-going edge of an input signal. When the flip-flop receives such a positive-going leading edge, it assumes a state determined by the value of the signal present at its D input terminal. For example, when push button 98 is depressed to reset flip-flop 96, the signal present at its 0 output terminal changes to a 1 and triggers flip-flops 80 and 82. They then assume states indicative of the values of the F and A signals, respectively. Flip-flop 84 also has a reset (R) and a set (S) input terminal. When a 1 is applied to the reset terminal, the flip-flop becomes reset and when a 1 is applied to the set terminal, the flip-flop becomes set. If 1's are concurrently applied to the set and reset terminals, the flip-flop becomes set. As before, a 1 is defined as a relatively positive signal, such as +V.

The switch 52a of FIG. 5 performs a function analogous to that of the single-pole, three position switch 52 of FIG. 1. As will be shown shortly, when the push button 98 is depressed once, the circuit is placed in the "start" position; when it is depressed a second time, the circuit goes to the "stop" position; when it is depressed a third time, the circuit goes to the "reset" condition. Thereafter, that is, with the further depressions of button 98, the cycle repeats.

In the operation of the circuit of FIG. 5 as a customary stop watch, switches 90 and 99 are in the "stop watch" position. It may be assumed that the starting condition of the circuit is A=0, B=0, C=1, E=0 and F=1. When the push button is depressed, set-reset flip-flop 96 becomes reset and its output signal changes to a 1. This triggers flip-flops 80 and 82. Immediately prior to this time both flip-flops were reset, AND gate 88 was enabled and F was equal to 1. In response to the trigger signal, flip-flop 80 becomes set (A changes to 1). Flip-flop 82, however, remains reset since at the time the trigger signal occurs, A was equal to 0. Flip-flop 84 initially receives A=1 on its reset terminal and also receives a 1, via switch 99, at its set terminal. As already mentioned, under this set of conditions the flip-flop is set and C=1. When A changes to 0 flip-flop 84 remains locked in the set state by the 1 applied to its set terminal. As flip-flop 84 is set, C=1 and this maintains flip-flop 86 in the set condition so that E remains 0.

The A=0 signal is applied through switch 90 to the NOR gate 20 and primes this NOR gate. The counter 22 now counts the pulses it receives and the stop watch is effectively turned on.

When the push button 98 is released, flip-flop 96 becomes set. The change in signal level (from 1 to 0) at the 0 output terminal of flip-flop 96 has no effect on the flip-flops 80, 82. When push button 98 is again depressed, flip-flop 96 produces another trigger pulse. The result is to reset flip-flop 80 (as F=0) and to set flip-flop 82 (as A=1 at the time the trigger pulse occurs). Flip-flops 84 and 86 remain in their previous condition. When flip-flop 80 becomes reset, A changes to 1 and this disables NOR gate 20, stopping the counter. F remains equal to 0 as B=0.

When push button 88 is released, the signal produced has no effect on the control logic 51. When the button 98 is depressed a third time, the flip-flop 96 applies a third trigger pulse to the circuit. As F=0, flip-flop 80 remains reset. As A=0, flip-flop 82 becomes reset. Flip-flops 84 and 86 remain in the same state. However, AND gate 88 now receives inputs A=1 and B=1 so that F changes to 1. This F signal is the one which is applied to the reset terminal of the counter 22 and it resets the counter.

If the push button 98 is depressed a fourth time, the cycle discussed above starts over again. A complete cycle is shown in Table I below.

TABLE 1

STOP WATCH MODE No. of times button pressed A B C E F Remarks 0 0 1 0 1 Initial state 1 1 0 1 0 0 Start 2 0 1 1 0 0 Stop 3 0 0 1 0 1 Reset

To place the system in the reaction timer mode, the ganged switches 90 and 99 are thrown to the reaction timer position. This removes the voltage +V from the set terminal of flip-flop 84. At the same time, making the assumption, which is a valid one, that A=1, a reset signal is present at the reset terminal of flip-flop 84. Accordingly, this flip-flop is immediately reset. When flip-flop 84 is reset, a 0 (ground) is applied to the base of transistor 94 and it does not conduct. The transistor, in other words, appears like an open switch in series with the lamp 70.

Summarizing the above, when the switches are thrown to the reaction timer position, the initial circuit condition is: A=0, B=0, C=0, E=0 and F=1. Flip-flop 86 produces the signal E=0 because it has an F=1 signal applied to its set terminal.

When button 98 is depressed the first time, flip-flop 80 becomes set and the remaining flip-flops 82, 84 and 86 remain in their original condition. Assuming that C=1 at this time, the NOR gate 20 remains disabled. The frequency divider 62 is counting and after some unknown interval within the range of zero seconds to ten seconds, produces an output pulse. The reason the interval is unknown is that there is no synchronism between the time the push button 98 is depressed and the time the frequency divider last produced an output pulse and started counting again.

When the frequency divider produces an output pulse, flip-flop 84 becomes set as an A=1 signal is present at its D input terminal. At this same time, the A=0 signal is present at the reset terminal of flip-flop 84 and this leaves the flip-flop free to assume the set state.

When flip-flop 84 becomes set, C changes to 0. This is applied to NOR gate 20 priming the latter and the counter 22 starts. Also, C changes to 1 driving transistor 94 to the conducting state and the lamp 70 goes on.

When it is desired to stop the counter, the push button 98 is depressed a second time. This causes flip-flop 80 to become reset and flip-flop 82 to become set. Flip-flop 84 thereupon is reset by the change in A from 0 to 1. Flip-flop 86 remains in its set condition (E=1) because at the time B changes to 1, the signal C applied to its D input terminal, also is equal to 1. When flip-flop 84 becomes reset and C changes to 1, NOR gate 20 becomes disabled and the counter 22 stops. At the same time, C changes to 0 turning off transistor 94 and the lamp 70 goes off.

The third time push button 98 is depressed, the system is reset. The trigger signal produced at 96 resets flip-flop 82 and flip-flop 80 remains in its reset condition. Flip-flops 84 and 86 also remain reset. As A=B=1, AND gate 88 is enabled and F=1. This F=1 signal resets the counter 22 of FIG. 1.

It sometimes occurs that the push button 98 is depressed a second time prior to the time that the variable delay means 62 produces an output pulse. The first depression of the push button 98 has started the counter in the manner already discussed and the various flip-flops produce outputs A=1, B=0, C=0 and E=0. The premature depression of push button 98 causes B to change to 1 and, as at this time flip-flop 84 still is reset, C=0. Therefore, the B=1 trigger signal causes flip-flop 86 to become reset and E changes to 1. This signal is applied to an alarm circuit such as a buzzer or the like to indicate that the user has anticipated the start of the timer (in the case of an athletic event, the premature depression of the push button may correspond, for example, to a runner starting before the firing gun has gone off). In one particular form of the invention, the alarm may consist of a signal applied to the set terminal of the counter 22, causing the counter to store all 1's. This can be arranged to cause some predetermined signal on the display panel such as all four numeric indicators lighting up at the same time.

Table II below illustrates the reaction timer operation as discussed above.

TABLE II

No. of Reaction Timer Mode times button A B C E F Remarks depressed 0 0 0 0 1 Initial State 1 1 0 0 0 0 Start -- 1 0 1 0 0 Variable delay means produces an output and lamp goes on 2 0 1 0 0 0 Stop 3 0 0 0 0 1 Reset 4 1 0 0 0 0 Start 5 0 1 0 1 0 Push button depressed before variable delay means produces an output signal 6 0 0 0 0 1 Reset

It sometimes may occur, when the system of FIG. 5 initially is switched from the "reaction timer" to the "stop watch" position, that the initial count is A=0, B=0, C=0, E=0. However, when switch 99 closes, a 1 is applied to the set terminal of flip-flop 84 and this changes C to 1 even though A=1 is applied to the reset terminal of flip-flop 84.

A reaction timer of the type illustrated in FIGS. 4 and 5 is useful in certain athletic events, for example where it is desired that the time between the depression of a button and the time that a starting lamp (or buzzer or other indicator) goes on, be variable. It is also useful in performing certain tests to determine, for example, how long after an event occurs an individual is able to make a response to that event.

There are many alternatives which are possible to the embodiment of the invention discussed by way of example above. For example, rather than driving each numeric indicator directly as discussed, the indicators may be driven in multiplexed fashion. Here there should be individual backplates for each indicator. A number of ways of doing this are discussed in the article: Luce, "C/MOS Digital Wrist Watch Features Liquid Crystal Display," Electronics, Apr. 10, 1972, page 93.

It is also to be understood that while the invention is illustrated in terms of a liquid crystal display panel, it is equally applicable to other forms of displays such as light emitting diode displays, electroluminescent displays, plasma type displays and so on.

It already has been mentioned that electronic switches may be employed for the switch illustrated schematically at 52. In similar fashion, electronic switches may be employed for other of the switches such as switch 40 shown in FIG. 1.

A switch such as 52 may be employed in the FIG. 1 circuit or a switch such as 52a (shown in FIG. 5) controlled by a single push button may be used instead.

A number of alternatives are also possible for the control logic circuits and for other of the circuits illustrated. For example, an AND gate may be substituted for the NOR gate 20 with appropriate modifications of the voltages supplied by the control logic 51. A simple switch such as 14 can be substituted for the switch 40. In this case the non-selected decimal points simply are left open circuited whereas the selected decimal point has a 100Hz applied thereto as in the embodiment illustrated. In the operation of this embodiment, only the liquid crystal beneath the selected decimal point will be energized just as in the embodiment illustrated.

The various frequencies and voltages given are intended as examples only. For example, it is clear that the liquid crystal driving frequency can be different than 100Hz. The particular value chosen is a matter of engineering design depending upon the parameters such as resistivity of the liquid crystal and the frequencies which are conveniently available.

Claims

What I claim is:

1. An electronic stop watch comprising, in combination:

a display for displaying time comprising numeric indicators and decimal point indicators, each decimal point indicator located between a pair of numeric indicators, and said decimal point indicators including a tenths decimal point indicator and a hundredths decimal point indicator;

means, including counter means, coupled to said display for driving the same for causing it to display a quantity representing the count stored in said counter means;

means producing a plurality of alternating signals, each at a different frequency said different frequencies being related to one another by powers of ten and including 10Hzs. and 100Hzs. frequencies;

selector means for applying to the counter means any one of said signals for causing the counter means to advance at the frequency of said particular signal selected; and

means responsive to said selector means for energizing a different decimal point indicator and no other decimal point indicator for each different frequency selected by said selector means, for indicating on said display the magnitude of the units of time represented by the quantity displayed thereon and including means for solely energizing the tenths decimal point indicator when the 10Hzs. signal is selected and means for solely energizing the hundredths decimal point indicator when the signal is selected.

2. In the combination as set forth in claim 1, said display comprising a liquid crystal display.

3. In the combination as set forth in claim 1, said selector means comprising manually operable switch means.

4. In the combination as set forth in claim 3, said means responsive to said selector means comprising second switch means ganged to said manually operable switch means.

5. An electronic stop watch comprising, in combination:

a display for displaying time;

means, including counter means, coupled to said display for driving the same for causing it to display a quantity representing the count stored in said counter means;

means concurrently producing a plurality of alternating signals, each at a different frequency, and each at a different output lead;

selector means for connecting a particular one of said output leads to said counter means for causing the counter means to advance at the frequency of the particular signal present at the selected output lead;

starting means for producing an initiating signal; and

variable delay means receptive of said initiating signal for applying a start signal to said counting means after a variable interval of time.

6. An electronic stop watch as set forth in claim 5 wherein said variable delay means comprises a frequency divider coupled to one of the input leads of said means producing a plurality of alternating signals for producing an output signal in response to each n input signals it receives, and means responsive to said initiating signal for producing said start signal in response to the first output signal produced by said frequency divider after the occurrence of said initiating signal, where n is an integer substantially greater than 1.

7. An electronic stop watch as set forth in claim 5 wherein said display comprises a liquid crystal display.

8. An electronic stop watch as set forth in claim 5 further including:

alarm means responsive to the actuation of said starting means prior to the time said start signal occurs for producing an alarm signal.

9. An electronic stop watch comprising, in combination:

a display for displaying time;

means, including counter means, coupled to said display for driving the same for causing it to display a quantity representing the count stored in said counter means;

means producing a plurality of alternating signals, each at a different frequency;

selector means for applying to the counter means a particular one of said signals for causing the counter means to advance at the frequency of said particular signal;

means responsive to said selector means for indicating on said display the magnitude of the units of time represented by the quantity displayed thereon;

starting means for producing a start signal for said counting means; and

delay means receptive of said start signal for applying a delayed start signal to said counting means after an interval of time.