Device For The Processing Of Digital Symbol Data For The Purpose Of Displaying Text On A Television Monitor

Abstract

A computer terminal for the processing of supplied symbol data for the purpose of displaying lines of text on a television monitor. The buffer memory of the computer terminal comprises an input circuit and a plurality of cyclic submemories, where the input circuit provides for the storage of the data required for displaying one line of text in the respective submemory. The number of times this data is fed from the respective submemory to a symbol generator connected to the buffer memory, corresponds to the number of scan lines required for displaying one line of text, the symbol generator feeding the data of a desired scan line each time to said monitor.

Description

The invention relates to a device for the processing of symbol data presented in digital form for the purpose of displaying text on a television monitor. The device consists of a buffer memory, a symbol generator and a timing unit. The device can, on the one hand, present successive lines of text in the read direction to the television screen, and, on the other hand, replace symbols randomly allocated and already displayed by other symbols. A buffer memory is capable of storing the maximum number of symbols to be displayed on the screen, and there is provided at least one recirculating memory in which the data required for display, and referring to one line of text, can be stored in parallel form, while the number of times at which said data is fed to the symbol generator corresponds to the number of scan lines required for the display of one line of text. Each time the data required for display, and pertaining to a desired scan line, is fed to said monitor by the symbol generator.

The lines of text are made visible on the screen of the above-mentioned television monitor by means of "horizontal line scanning." Each line of text is formed by a fixed number of scan lines. To obtain these scan lines, the electron beam in the picture tube is deflected each time in the horizontal direction. With this deflection, the electron beam strikes the screen at the positions where the parts of the desired symbols pertaining to the respective scan line must be displayed. Such a part of a line of text, to be displayed in the horizontal direction is, owing to the rapidly fluctuating grid voltage in the picture tube, built up of a series of luminous points or luminous dashes, depending on the applied fluctuating grid voltage. When the electron beam has completed a horizontal scan, the beam performs a horizontal retrace on the presence of a line synchronization signal required for this purpose. The electron beam then starts a new horizontal scan, which is somewhat lower than the previous one, because the beam is deflected downward to some extent during each horizontal line scan. If the beam has arrived at the bottom side of the screen, the beam performs a vertical retrace on the presence of a conventional frame synchronization signal, whereupon the beam can start anew with horizontal line scanning. During such a retrace, a blanking signal ensures that the electron beam is suppressed, preventing the scanning of the picture screen. The above synchronization signals and the blanking signals can be supplied, for example, by the timing unit.

A symbol may already be recognized on the screen if it is displayed, for example, on 10 scan lines, using only a part of each scan line. The length of each of these parts of the scan lines is such that, for example, seven luminous and equidistant dots or dashes can be placed on each part. Hence, in this example, the projection area of one single symbol will consist of a matrix of ten by seven dots or dashes.

In addition to a space between two successive symbols pertaining to one line of text, the length of this space being such that, for example, four luminous dots or dashes can be placed on it, also a line space is required between the lines of text. The latter space may be obtained, for example, by leaving blank three scan lines preceding, and five scan lines following a line of text. Thus the picture screen field may be divided into matrices of eighteen by eleven dots, each of which allows the placing of one symbol only. In this way, when using a television monitor suitable for a C.C.I.R. 625-line standard signal, 32 lines of text can be displayed on the screen and 49 scan lines will still be left over. These scan lines are not used, however, because the time needed for making use of this is required to perform two vertical retraces, provided the generally applied principle of interlaced scanning is used; first the odd-numbered scan lines are traced sequentially and then, after a vertical retrace, the even numbered scan lines. The consecutively projected "frames" thus obtained, together form the desired display. For the sake of clarity of the description, the principle of interlaced scanning on the monitor will be deviated from, if necessary.

A device, as described in the opening paragraph is shown in the Dutch Patent application No. 6817586. In the device of this patent application the buffer memory comprises a closed magnetostrictive delay line, a shift register and a recirculating memory. The information relative to the total text to be displayed on the television screen and derived, for example, from a computer, is inserted serially into the above-mentioned delay line, and then cyclically shifted in this delay line. The part of this information which is required for displaying one single line of text, is presented each time to the shift register. This information is then read out per symbol in parallel form from the above shift register, and fed to the recirculating memory.

If at a certain moment, a symbol already displayed is to be replaced by another symbol, the corresponding symbol information in the buffer memory must be replaced by new information to this effect; this can be done only at the fixed write-in location of this buffer memory. Since the symbol information to be changed may be found at a random location in the buffer memory at the given moment, such information cannot be replaced directly. If a delay line, as described in the above-mentioned Dutch Patent Application, is employed, a relatively long waiting time must usually be taken into account before the symbol information can be changed at the fixed write-in location. This is because the symbol information must usually pass through half of the number of the available memory locations, before the write-in location has been reached. Since the time required by the symbol information to be shifted cyclically once in the delay line must be equal to the frame time, i.e. the time required to form an interlaced frame on the screen, the mean waiting time will be equal to half of the frame time. With the conventional frame frequency of 50 Hz, this mean waiting time is 10 msec, which implies that the communication line between computer and buffer memory is occupied a relatively long period.

In order to process in the buffer memory the presented symbol data in a simple and relatively rapid way, it is desirable to shorten the mean waiting time before symbol data can be stored.

Hence, the object of the invention is to provide a device, of the kind set forth in the opening paragraph, that fully meets this desire. In accordance with the invention, the buffer memory used in said device is provided with an input circuit and a plurality of cyclic submemories. The information required for displaying one specific line of text is written into the respective submemory with the aid of the input circuit.

If it is desired to replace symbol information in the buffer memory by other information, a waiting time is to be observed during which this information is shifted cyclically to the write-in location of the respective submemory; this usually takes a time that corresponds to the period during which the symbol information passes through half of the number of the available memory locations of the respective submemory.

In a first version of the device in accordance with the invention, one of the cyclic submemories is formed by said recirculating memory, while the remaining submemories are identical to this. The time, during which the information is shifted cyclically once in the recirculating memory, is equal to the time during which one scan line can be generated (scan line time). Consequently, the mean waiting time preceding the moment of storing new symbol information is equal to half of the scan line time. Taking into account the interlaced display, at which only half of the number of scan lines is displayed during the frame time, the scan line time will be 1/50 .sup.. 2/625 sec = 64 .mu.sec with the use of 625 scan lines for displaying text on a television screen, and therefore the mean waiting time for storing new symbol information will take 32 .mu.sec.

In a second version of the device in accordance with the invention, the symbol information of each line of text is written serially into the respective cyclic submemory. With the use of a specific shift register, this stored symbol information is extracted from the respective submemory per line of text, and presented in parallel form to the recirculating memory. The symbol information stored in the submemory must have been shifted cyclically once in the same time during which a line of text is being displayed on the screen. If such a line of text including line space is realized by making use of "2n" scan lines, the mean waiting time will be equal to half of the time in which "n" scan lines will have been generated; this waiting time is "n" times as large as that in the first-mentioned version, and thus is "n".times. 32 .mu.sec, which still is a reasonable reduction of the waiting time compared with the mean waiting time in the cited Dutch Patent Application.

The invention will further be explained with reference to the figures, of which:

FIG. 1 illustrates a block diagram of a first version of the device in accordance with the invention;

FIG. 2 illustrates a more detailed block diagram of the buffer memory incorporated in said device;

FIG. 3 illustrates a more detailed block diagram of a recirculating memory;

FIG. 4 illustrates a block diagram of a second version of the device in accordance with the invention;

FIG. 5A illustrates an example of a symbol to be displayed, while

FIG. 5B illustrates the accompanying diagram of video signals.

In these figures like parts are designated by like reference numerals.

FIG. 1 relates to a device for the processing of symbol data represented in digital form for displaying text on a television monitor, which device consists of a buffer memory 1, a symbol generator 2 and a timing unit 3.

The text to be displayed on the monitor may be composed of various kinds of symbols; usually this is limited, however, to alphanumeric symbols, viz, letters and numerals. In spite of this, other symbols may appear in a text, such as mathematical designations, reference marks, etc.

It is customary that the computer provides the symbol data; the data is then presented in the form of code words. These code words either refer to the type of symbol to be displayed, or to the location on the monitor where a symbol should be displayed. The length of the code words, in so far as they refer to the type of symbol to be displayed, depends on the maximum number of symbols to be used; if for the display a choice is made from 33 to 64 various symbols, a code word should then comprise six binary digits. For obtaining symbol data use may also be made of a keyboard, which is then provided with an encoder. The code words, in so far as these refer to the location where the symbols should be displayed on the monitor, will either contain information of the line of text, or information of the location on this line.

With the display of symbols on the screen in accordance with the horizontal scanning described hereinbefore, it is important that the information of the symbols to be displayed is available per scan line. Depending on the scan line to be generated, and on the symbol data presented, this information per scan line is supplied by the symbol generator 2. To this effect, the number of successive times at which the information referring to a line of text is presented to the symbol generator 2, must be equal to the number of scan lines used for displaying one single line of text including line space. The signals (video signals) thus supplied serially by the symbol generator 2 are fed to a combination circuit, which is not indicated, and are hence converted, together with the above-mentioned synchronisation and blanking signals, into a form suitable for presentation to the television monitor in the conventional manner. The latter signals provide the information of the grid-cathode voltage to be formed. With the aid of this voltage the luminous dots or dashes, comprising a part of the line of text to be displayed in a horizontal direction, are obtained on the screen.

In order to avoid continuous use of the computer for obtaining the symbol data required for display, the device is provided with a buffer memory 1 which precedes the symbol generator 2. The symbol data presented by the computer is stored in this buffer memory; the computer must be engaged only when the symbols displayed on the television screen are changed, so that in the buffer memory 1, the information corresponding to these symbols can be replaced by new information. To this effect, a recirculating buffer memory 1 is used, in which the symbol data passes through a certain cycle. At a given moment during this cycle, the information of a symbol to be displayed is extracted from the buffer register at a fixed location in the buffer memory and fed to the symbol generator 2.

In accordance with the invention, the buffer memory 1 is provided with a number of cyclic submemories 4a-z, connected in parallel, which number corresponds to the maximum number of lines of text to be displayed on the screen. Each submemory corresponds to a fixed line of text on the monitor. In the version in question, each code word, in so far as this refers to the type of symbol to be displayed, is written in parallel form into a cyclic submemory. Such a cyclic submemory should therefore contain a number of shift registers operating in parallel, which number corresponds to the number of binary digits, making up the written code word. The combination of a number of shift registers operating in parallel forms a recirculating memory. In the design in question, each of the cyclic submemories 4a-z can therefore be regarded as one recirculating memory.

In order that the symbol data, in so far as this refers to the type of symbol to be displayed, is written into the desired recirculating memory at the correct moment, the buffer memory 1 is provided with an input circuit 5 preceding the recirculating memories 4a-z. Since the respective symbol data is fed via a single communication line from the computer to the buffer memory, and this information is to be written in parallel form into one of the recirculating memories, the buffer memory comprises a serial-parallel converter 6 preceding the input circuit 5.

The sumbol data, once written in the recirculating memories 4a-z, is read out symbol after symbol in order of succession of the recirculating memories with the aid of a line selection switch 7 controlled by the timing unit 3, and said data is fed to the symbol generator 2.

In the symbol generator 2, the symbol data is fed to a fixed matrix memory 8. As will further be described hereinafter, also a signal indicating a specific scan line is fed to this matrix memory with the aid of a scan line switch 9. With these two kinds of data, the matrix memory 8 is able to provide per scan line the information referring to the symbols to be displayed, which information is again supplied in parallel form to a parallel-serial converter 11 with the aid of the timing unit 3. The series of signals obtained from the parallel-serial converter are fed as video signals to the monitor.

FIG. 2 shows a more detailed block diagram of the buffer memory. The function of the serial-parallel converter 6 contained in this memory is, besides to convert serial data to parallel data, to divide the supplied symbol data into: information referring to the type of symbol to be displayed (symbol-type information); information referring to the line of text in which the symbol must be placed (row information) and information regarding the position within this line of text on which the symbol should be displayed (column information). The symbol-type information is written into the symbol register 12. The row information is written into the row register 13 and then fed to the submemory selector 14. The column information is fed to the column condition circuit 15; this comprises a column register 16, into which said column information is written. Furthermore, the column condition circuit 15 comprises a symbol counter 17, in which the clock pulses T.sub.2 derived from the timing unit 3 are counted; these clock pulses have a repetition time which is equal to the time required to display a scan line part of one symbol on the television screen. The information of the digital position of the symbol counter 17, and also the column information stored in the column register 16, are applied separately to an equivalence circuit 18 incorporated in the column condition circuit 15; if the two kinds of information are identical, the equivalence circuit 18 sends a signal to the submemory selector 14.

In the version in question, the submemory selector 14 consists of a decoder which is provided with a number of outputs A.sub.a-z. This number corresponds to the number of recirculating memories 4a-z; each of the outputs A.sub.a-z is connected separately to one of the recirculating memories 4a-z.

The submemory selector 14 is activated by a signal originating from the equivalence circuit 18 and, consequently, causes the transmission of a control signal to the recirculating memory corresponding to the respective row information via the appropriate line A.sub.i (i = a, b, . . . , z). The working of these recirculating memories 4a-z will now be explained by a further description of the recirculating memory 4a, which is shown in FIG. 3. The recirculating memory 4a comprises, in addition to the afore-mentioned number of parallel-connected shift registers 19 - 24, an equal number of return lines 25 - 30 and gate circuits 31 - 36. The working of the parts incorporated in the recirculating memory 4a will be further explained with reference to the gate circuit 31, the shift register 19 and the return line 25, which elements are necessary, for example, for the processing of the first binary digit of a code word from the symbol register 12. The gate circuit 31 is a logical circuit of which the three inputs are indicated by A.sub.a, f and g and the output by h. The control signal from the submemory selector 14 is applied to the input A.sub.a. It should be noted that this control signal is also fed to the corresponding inputs of the gate circuits 32 - 36. The information, which is obtained from the symbol register 12, and which refers to the first binary digit of each code word, is applied to input f, while the information from the shift register 19 is fed sequentially to input g via the return line 25. The supplied information is fed to the shift register 19 via output h. The latter information may be indicated by the relationship

h = A.sub.a .sup.. f + A.sub.a .sup.. g.

Therefore, in the presence of the control signal A.sub.a, the information (f), which is derived from the symbol register (12,) and which refers to said binary digit, is written into the respective shift register 19 via the gate circuit 31. During this process the information, which is fed from the shift register 19 to the gate circuit 31 via the return line 25, will be eliminated. The control signal A.sub.a is applied each time for the duration of the writing of one binary digit. In the absence of the control signal A.sub.a, the information (g) derived from the shift register 19 is fed back to the shift register 19 via the return line 25 and the gate circuit 31, and is rewritten in this register.

The remaining binary digits of these code words are fed to the remaining gate circuits 32 - 36 in order to be written, after selection, into the shift registers connected to said gate circuits; the shift registers 19 - 24 operate with a shift frequency which is equal to the pulse repetition frequency of the clock pulses T.sub.2.

As shown in FIG. 2, the symbol-type information, once written in the recirculating memories 4a-z, is extracted from said memories by a line selection switch 7 and fed to the symbol generator 2. The line selection switch 7 comprises a counter 37, a decocer 38, and also a number of gate circuits 39a-z. The number of circuits 39a-z corresponds to the number of recirculating memories 4a-z, so that each gate circuit 31-36 can be connected to the symbol generator 2 via a separate gate circuit.

The counter 37 receives the clock pulses T.sub.4 from the timing unit 3 with a repetition time which is equal to the time required for displaying one complete line of text on the television screen. The digital position of the counter 37 obtained through the clock pulses T.sub.4 is decoded by the decoder 38. This causes the activation of the gate circuit 39i (i = a, b, . . . , z) determined by the count position via one of the outputs B.sub.a-z. The information in the recirculating memory 4i connected to this gate circuit can now be applied to the symbol generator 2. During the period of time between two successive clock pulses T.sub.4, said information is fed to the symbol generator 2 a number of times, which number corresponds to the number of scan lines required for displaying one line of text. For the processing of the symbol-type information, the afore-mentioned matrix memory 8 is incorporated in the symbol generator 2.

The scan line switch 9 in the symbol generator 2 comprises a line counter and a line decoder connected to said counter, which are, however, not shown separately in the figures.

Clock pulses T.sub.3 (see FIG. 2), of which the pulse repetition period is equal to the time required for displaying a scan line on the television screen and for performing a retrace, are supplied by the timing unit 3 to the line counter of the scan line switch 9. The count position acquired by said line counter is decoded by the line decoder connected to the line counter; this information enables the fixed matrix memory 8 to form, per scan line the corresponding symbol information which, is then fed to the parallel-serial converter 11.

Signals in serial form, viz., video signals, are obtained from the parallel-serial converter 11 with the aid of the clock pulses T.sub.1 provided by the timing unit 3. The pulse repetition frequency of these clock pulses T.sub.1 is identical to the frequency employed to obtain the rapid fluctuations in the grid-cathode voltage of the picture tube for the formation of the afore-mentioned luminous dots or dashes on the screen.

The operation of the above-described device will now be explained with the aid of an example.

It will be considered how the device operates, for example, by considering information relating to the letter "E" to be displayed at the tenth position of the first line of text on the screen. The computer will supply the serial-parallel converter 6, which is illustrated in FIG. 2, with the row information, the column information, and the symbol-type information required for displaying the letter "E" in the form of the code words, for example: (1,0,1,0,0,0,1), (1,0,1,1,0,0,1), and (1,0,1,0,0,0), respectively. In this serial-parallel converter, the three supplied code words are separated. The rwo information (1,0,1,0,0,0,1) is written into the row register 13, and then fed to the submemory selector 14. The column information (1,0,1,1,0,0,1) is written into the column register 16, and then fed to the equivalence circuit 18. Finally, the symbol-type information (1,0,1,0,0,0) is written into the symbol register 12.

When the symbol counter 17 has acquired a binary count position, which is identical to the column information (1,0,1,1,0,0,1), with the aid of clock pulses T.sub.2, the equivalence circuit 18 sends a signal to the submemory selector 14. Subsequently, in the submemory selector 14, activated by said signal, the row information (1,0,1,0,0,0) is decoded. This results in the example in question, in which the first line of text must be displayed, in a control signal at the output A.sub.a ; said control signal being applied to the recirculating memory 4a. Although the information written in the symbol register 12 is applied to all f-inputs of the gate circuits in the recirculating memories 4a-z, this information is accepted only by the gate circuits 31 - 36 activated by the control signal, and written into the corresponding shift registers 19-24. In this process, the first binary "1" of the symbol selection information (1,0,1,0,0,0) is applied to the first shift register 19 via the respective gate circuit 31, and the second binary "0" to the second shift register 20 via the respective gate circuit 32. The remaining binary digits are then processed similarly in the recirculating memory 4a.

When the digital position of the counter 37, which is illustrated in FIG. 2, indicates that the first line of text must be displayed on the screen, the decoder 38 activates the gate circuit 39a via the line B.sub.a ; the information written in the recirculating memory 4a is then fed to the symbol generator 2 via the gate circuit 39a.

In addition to supplying the information written in the recirculating memory 4a to the symbol generator 2, there is also a supply of identical information to the gate circuits 31 - 36 of the recirculating memory 4a via the return lines 25 - 30.

The information fed to the symbol generator 2 is accepted by the fixed matrix memory 8. During the processing of symbol data by the fixed matrix memory 8, an allowance must be made for a spaced needed between two successive lines of text; this space is obtained, on the one hand, by starting the symbol display, for which the information is processed by the fixed matrix memory 8, at the fourth scan line and, on the other hand, by adding another five scan lines after the last scan line (13th scan line) pertaining to such a display. Therefore, the letter "E" in this line of text is given such a form that a horizontal line segment is displayed on the 4th, 8th and 13th scan lines, at which the starting points of these line segments are joined by a vertical line segment, as shown in FIG. 5A.

With the aid of the information which is provided by the scan line switch 9, and which refers to the scan line to be displayed, the fixed matrix memory 8 is capable of delivering the information of the line of text per scan line, and to feed this information to the parallel-serial converter 11. With the delivery of information per scan line, the space between two successive symbols must be taken into account. Accordingly, the information provided by the fixed matrix memory 8 with reference to the letter "E" for the fourth scan line, may assume, for example, the form (0,0,0,1,1,1,1,1,1,0,0); the number of binary digits comprised by this information corresponds to the number of time intervals in which the period of time for displaying one symbol is divided. If the binary 1 is added to such a time interval, the electron beam will strike the screen; if the binary digit is 0, the electron beam will be suppressed during the respective time interval. If the information of the line of text of the fourth scan line has been fed to the parallel-serial converter 11, identical information will again be sent to the fixed matrix memory 8 on the presence of a line synchronization signal, after the latter information, returned via the lines 25 - 30, has been restored in the recirculating memory 4a.

Hence, the parallel-serial converter 11 provides the following information per scan line for displaying the letter "E":

(0,0,0,0,0,0,0,0,0,0,0) for scan lines 1 - 3

(0,0,0,1,1,1,1,1,1,0,0) for scan line 4

(0,0,0,1,0,0,0,0,0,0,0) for scan lines 5 - 7

(0,0,0,1,1,1,1,1,0,0) for scan line 8

(0,0,0,1,0,0,0,0,0,0,0) for scan lines 9 - 12

(0,0,0,1,1,1,1,1,1,1,0) for scan line 13

(0,0,0,0,0,0,0,0,0,0,0) for scan lines 14 - 18

Since the binary 1 results in a positive grid pulse, the above collection of information assigned per scan line corresponds with the video signals shown in the diagram of FIG. 5B, which signals are required for displaying the letter "E."

It must be emphasised that the complete data processing between the serial-parallel converter 6 and the parallel-serial converter 11, is carried out in parallel form. However, it is also possible to process the symbol information in a serial form in the buffer memory 1, whereupon this information is applied to the symbol generator 2 in parallel form. A version of the invention based on these lines will be explained with reference to FIG. 4. If parts of the device in this version are not further dealth with, then an analogous explanation, as given in the first version, will apply.

The buffer memory 1 comprises a symbol separation circuit 48, an input circuit 5, a plurality of cyclic submemories 4a-z, a line selection switch 7, a serial-parallel converter 47, a switchable memory 49 composed of a recirculating memory, and a recirculating memory 50.

The symbol separation circuit 48 divides the supplied symbol information into three kinds of information, viz,. the symbol-type information, the column information and the row information, where the column information and the row information are converted into parallel form and so processed. These three kinds of information are then fed to the input circuit 5, in which the symbol-type information is written in serial form, while the row and column information are processed into a control signal that must be applied to the desired submemory 4i at the correct moment, in order to write the symbol information stored in the input circuit 5.

The number of cyclic submemories is again equal to the number of lines of text to be displayed; however, now each of the cyclic submemories 4a-z is formed by a register, into which the symbol information of one single line of text is written in serial form. The symbol information written in each of the submemories 4a-z is then fed sequentially to a serial-parallel converter 47 via a line selection switch 7, and subsequently to the switchable memory 49. Since the information is stored in serial form in the shift registers 4a-z, and in parallel form in the switchable memory 49, the shift frequency of the switchable memory 49 will be smaller than that of the shift registers 4a-z by such a factor that corresponds with the number of binary digits of which a code word is composed. In order to operate the shift registers 4a-z and the symbol generator 2 at the same frequency, the shift frequency of the switchable memory 49 will, when this memory is provided with information of a complete line of text, change in such a way that this frequency corresponds to the operating frequency of the symbol generator 2. The information of the switchable memory 49 is applied with the latter frequency to a recirculating memory 50, which has a constant shift frequency that is equal to the operating frequency of the symbol generator 2. The number of times the information of the recirculating memory 50 is fed to the symbol generator 2, corresponds to the number of scan lines required for displaying one line of text.

Claims

1. A digital symbol diaplay device for the processing of symbol data presented in digital form for the purpose of displaying text on a television screen comprising a buffer memory, a symbol generator connected to said buffer memory, and a timing unit connected to said buffer memory and said symbol generator, said device, in a first instance, presenting successive lines of text in a read direction to the television screen, and, in a second instance, replacing symbols randomly allocated and already displayed by other symbols, said buffer memory being capable of storing the maximum number of symbols to be displayed on the television screen, said buffer memory being provided with a plurality of cyclic submemories in each of which data required for display and referring to one line of text can be stored in parallel form, while the number of times at which said data is fed to said symbol generator corresponds to the number of scan lines required for the display of one line of text, the data required for display, and pertaining to a desired scan line, each time being fed to said television screen by the symbol generator, the buffer memory being provided with an input circuit with each of said cyclic submemories connected to said input circuit, the information required for displaying one specific line of text being written into a

2. A device as claimed in claim 1, wherein the buffer memory comprises a serial-parallel converter, which precedes and is connected to the input circuit and via which the supplied serial information is fed in parallel form to said input circuit, said serial information being divided into symbol-type information, row information and column information whereby the row information indicates the cyclic submemory in which the symbol-type information must be stored, while the column information is for the purpose of determining the time at which the symbol-type information must be stored at a fixed write-in location of said cyclic

3. A device as claimed in claim 2, wherein the input circuit comprises a symbol register, a row register and a column condition circuit connected to the timing unit, to which, respectively, the symbol-type information, the row information and the column information are fed, and whereby also a submemory selector is present, which submemory selector is connected to the column condition circuit and the row register, and which delivers a control signal at a time to be determined by the column condition circuit, said control signal implementing the writing of said symbol-type

4. A device as claimed in claim 3, wherein the column condition circuit comprises a column register and a symbol counter, to which, respectively, the column information and clock pulses derived from the timing unit are fed, the column condition circuit also containing an equivalence circuit which is connected to said column register and said symbol counter, and which determines the moment at which the submemory selector delivers said

5. A device as claimed in claim 4, wherein a gate circuit is disposed in a return line of each cyclic submemory, the return line being interrupted when the control signal is applied to said gate circuit, during which the symbol information derived from the input circuit can be written into said

6. A device as claimed in claim 1, wherein the buffer memory is provided with a line selection circuit, via which the information of one specific line of text to be displayed is fed from a respective cyclic submemory to

7. A device as claimed in claim 6, wherein the line selection circuit is composed of a counter, to which required count pulses are applied by the timing unit, a decoder connected to said counter, and a number of gate circuits connected to said decoder, each of which is connected to one of the cyclic submemories, whereby a signal corresponding to the decoded counter position opens the gate circuit connected to an associated cyclic submemory, enabling information to be transferred from the associated

8. A device as claimed in claim 1, wherein the information required for displaying a line of text is stored in serial form in the respective cyclic submemory and wherein the buffer memory is provided with a line selection circuit, connected to said submemories whereby the information of the specific line of text to be displayed is fed, with the aid of the timing unit, from the respective cyclic submemory, via said line selection

9. A device as claimed in claim 8, wherein, said device contains means for employing the same shift frequency at the cyclic submemories and at the serial-parallel converter and said device being also provided with a switchable memory feeding a recirculating memory for whose functioning two different frequencies are available one frequency for storing the symbol information, which is written in serial form in the cyclic submemory, in the switchable memory capable to receive data in parallel form, and the other frequency for transmitting data from the switchable memory to the recirculating memory, the latter frequency being equal to that of the symbol generator.