U.S. patent number 3,784,803 [Application Number 05/328,001] was granted by the patent office on 1974-01-08 for multi-mode computing circuit.
This patent grant is currently assigned to Audn Corporation. Invention is credited to Thomas A. Brendle.
United States Patent |
3,784,803 |
Brendle |
January 8, 1974 |
**Please see images for:
( Certificate of Correction ) ** |
MULTI-MODE COMPUTING CIRCUIT
Abstract
A single electrical circuit is capable of alternatively
calculating an output voltage V.sub.O according to the general
formula, V.sub.O = V.sub.A (V.sub.C /V.sub. B).sup.n or V.sub.O = K
1n (V.sub.C /V.sub.B).sup.T , where V.sub.A, V.sub.B and V.sub.C
are circuit input voltages and n, K, and T.sub.1 are determinable
values of the circuit. A first relaxation oscillator may be
selectively coupled to a second relaxation oscillator or to a
chargeable capacitor supplied with constant current. The value of
V.sub.O is repeatedly adjusted as a function of decaying response
time. V.sub.O is computed when two response times are driven into
equality.
Inventors: |
Brendle; Thomas A. (Hamburg,
NY) |
Assignee: |
Audn Corporation (Hamburg,
NY)
|
Family
ID: |
23279069 |
Appl.
No.: |
05/328,001 |
Filed: |
January 30, 1973 |
Current U.S.
Class: |
708/838; 327/346;
327/350; 327/356; 327/360; 708/843 |
Current CPC
Class: |
G06G
7/24 (20130101) |
Current International
Class: |
G06G
7/00 (20060101); G06G 7/24 (20060101); G06g
007/16 () |
Field of
Search: |
;235/195,194,196,193
;307/246,293,294,229,230 ;328/146-149,129,78 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Ruggiero; Joseph F.
Attorney, Agent or Firm: Sommers & Weber
Claims
What is claimed is:
1. A multi-mode computing circuit capable of calculating an output
voltage V.sub.O as a function of three variable input voltages,
V.sub.A, V.sub.B, and V.sub.C, according to the general formula,
V.sub.O = V.sub.A (V.sub.C /V.sub.B).sup.n, where V.sub.C is
greater than V.sub.B and n is a determinable value of the circuit,
comprising:
first and second relaxation oscillator means;
energizing means for simultaneously charging said first oscillator
means with V.sub.C and said second oscillator means with V.sub.O
for a finite time period and for permitting decay of both of said
oscillator means after said time period expires;
first comparator means for comparing the voltage in said first
oscillator means with V.sub.B and for sensing the response time of
said first oscillator means during decay;
second comparator means for comparing the voltage in said second
oscillator means with V.sub.A and for sensing the response time of
said second oscillator means during decay;
correction means controlled by the voltages compared at said first
and second comparator means for adjusting the value of V.sub.O and
for urging the difference of said response times to decrease;
and
sequencing means operated by said first and second comparator means
for successively activating said energizing means after V.sub.O has
been adjusted to cause V.sub.O to be readjusted and to calculate
V.sub.O = V.sub.A (V.sub.C /V.sub.B).sup.n when said response times
are equal.
2. The circuit of claim 1 wherein said energizing means permits
simultaneous decay of both of said oscillator means.
3. The circuit of claim 1 wherein said energizing means is
adjustable to permit said finite time period to be varied.
4. The circuit of claim 2 wherein said first oscillator means
includes a RC circuit having a resistor R.sub.1 arranged in
parallel with a capacitor C.sub.1.
5. The circuit of claim 4 wherein said second oscillator means is a
RC circuit having a resistor R.sub.2 arranged in parallel with a
capacitor C.sub.2.
6. The circuit of claim 5 wherein n = R.sub.1 C.sub.1 /R.sub.2
C.sub.2.
7. The circuit of claim 6 wherein R.sub.1 is an adjustable resistor
for permitting n to be varied.
8. The circuit of claim 1 wherein said first comparator means is a
voltage comparator capable of generating a positive output signal
when the voltage in said first oscillator means is greater than
V.sub.B, a negative signal when such voltage is less than V.sub.B,
and a null signal when such voltage is equal to V.sub.B.
9. The circuit of claim 1 wherein said second oscillator means is a
voltage comparator capable of generating a positive output signal
when the voltage in said second oscillator means is greater than
V.sub.A, a negative signal when such voltage is less than V.sub.A,
and a null signal when such voltage is equal to V.sub.A.
10. The circuit of claim 3 wherein said energizing means includes
first electronic switch means between V.sub.C and said first
oscillator means, second electronic switch means between V.sub.O
and said second oscillator means, and a monostable multivibrator
operatively associated with said first and second electronic switch
means to close said switch means when said multivibrator is excited
into its quasi-stable state and to open said switches when said
multivibrator reverts to its stable state.
11. The circuit of claim 10 wherein said monostable multivibrator
is adjustable to vary said finite time period.
12. The circuit of claim 1 wherein said sequencing means includes
an AND gate.
13. The circuit of claim 1 wherein said correction means includes a
voltage supply circuit operated by said second comparator means to
increase V.sub.O when said response time of said second oscillator
means is less than said response time of said first oscillator
means.
14. The circuit of claim 13 wherein said correction means further
includes a voltage drain circuit operated by said first comparator
means to decrease V.sub.O when said response time of said first
oscillator means is less than said response time of said second
oscillator means.
15. The circuit of claim 14 wherein said correction means further
includes capacitor arranged in parallel with said voltage drain
circuit.
16. The circuit of claim 15 further comprising a buffer amplifier
between said correction means and said second comparator means.
17. A multi-mode computing circuit capable of calculating an output
voltage V.sub.O as a function of two variable input voltages,
V.sub.B and V.sub.C, according to the general formula, V.sub.O = K
1n (V.sub.C /V.sub.B).sup.T , where V.sub.C is greater than V.sub.B
and where C and T.sub.1 are determinable values of the circuit
comprising:
relaxation oscillator means;
a source of constant current;
capacitor means supplied with said constant current;
energizing means for simultaneously charging said oscillator means
with V.sub.C and for draining said capacitor means for a finite
time period and for permitting said oscillator means to decay and
said capacitor means to charge after said time period expires;
first comparator means for comparing the voltage in said oscillator
means with V.sub.B and for sensing the response time of said
oscillator means during decay;
second comparator means for comparing the voltage in said capacitor
means with V.sub.O and for sensing the response time of such
capacitor means during charging;
correction means controlled by the relative voltages compared at
said first and second comparator means to adjust V.sub.O for urging
the difference between said oscillator response time and said
charging capacitor means response time to decrease; and
sequencing means for successively activating said energizing means
after V.sub.O has been adjusted to cause V.sub.O to be readjusted
and to calculate V.sub.O = K 1n(V.sub.C /V.sub.B).sup.T when said
response times are equal.
18. The circuit of claim 17 wherein said energizing means
simultaneously permits said capacitor means to charge and said
oscillator means begins to decay.
19. The circuit of claim 18 wherein said oscillator means includes
an RC circuit having a resistor R.sub.1 arranged in parallel with a
capacitor C.sub.1.
20. The circuit of claim 19 wherein T.sub.1 = R.sub.1 C.sub.1.
21. The circuit of claim 20 wherein R.sub.1 is an adjustable
resistor for permitting T.sub.1 to be varied.
22. The circuit of claim 17 wherein said energizing means is
adjustable to permit said finite time period to be varied.
23. The circuit of claim 22 wherein said first comparator means is
a voltage comparator capable of generating a positive output signal
when the voltage in said oscillator means is greater than V.sub.B,
a negative signal when such voltage is less than V.sub.B, and a
null signal when such voltage is equal to V.sub.B.
24. The circuit of claim 18 wherein said second comparator means is
a voltage comparator capable of generating a positive output signal
when the voltage in said capacitor means is greater than V.sub.0, a
negative signal when such voltage is less than V.sub.O, and a null
signal when such voltage is equal to V.sub.O.
25. The circuit of claim 22 wherein said energizing means includes
first electronic switch means between V.sub.C and said oscillator
means, third electronic switch means arranged in parallel with said
capacitor means, and a monostable multivibrator operatively
associated with said first and third electronic switch means to
close said switch means when said multivibrator is excited into its
quasi-stable state and to open said switch means when said
multivibrator reverts to its stable state.
26. The circuit of claim 25 wherein said monostable multivibrator
is adjustable to vary said finite time period.
27. The circuit of claim 18 wherein said sequencing means includes
an AND gate.
28. The circuit of claim 18 wherein said correction means includes
a voltage supply circuit operated by said second comparator means
to increase V.sub.O when said response time of said capacitor means
during charging is less than said response time of said oscillator
means during decay.
29. The circuit of claim 28 wherein said correction means further
includes a voltage drain circuit operated by said first comparator
means to decrease V.sub.O when said response time of said
oscillator means during decay is less than said response time of
said capacitor means during charging.
30. The circuit of claim 29 wherein said correction means further
includes a capacitor arranged in parallel with said voltage drain
circuit.
31. The circuit of claim 30 further comprising a buffer amplifier
between said correction means and said second comparator means.
32. The circuit of claim 17 wherein said capacitor means is a
capacitor.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electrical circuit capable of
calculating an output voltage V.sub.O as a function of variable
input voltages, V.sub.A, V.sub.B, and V.sub.C, according to the
general formulae,
V.sub.O = V.sub.A (V.sub.C /V.sub.B).sup.n or V.sub.O = K 1n
(V.sub.C /V.sub.B).sup.T
where 1n represents a natural logarithm and n, K, and T.sub.1 are
determinable constants of the circuit.
2. Description of the Prior Art
A digital computer is capable of calculating a plurality of
mathematical modes, such as division, multiplication, and the like,
only if programmed to perform the desired function. However, many
of such digital computers involve complicated and expensive
structure, rendering their use impractical for many potential
users. Beyond the cost of the physical structure, the degree of
technical sophistication needed to program and operate such
computers further adds to their total cost.
A non-electrical system may often be reproduced in its electrical
equivalency by an analog computer. While many mechanical elements
have simple and inexpensive electrical analogs, still others
require costly electrical hardware. Additionally, the assembly and
operation of the analogous electrical circuit requires the exercise
of a high degree of technical skill.
Still other computers are hybrid combinations of digital and analog
logic. While unique capabilities may often be obtained with such
systems, the inherent high costs of structure, programming, and
operation are still present.
SUMMARY OF THE INVENTION
A single multi-mode computing circuit is capable of calculating an
output voltage V.sub.O as a function of variable input voltages
V.sub.A, V.sub.B and V.sub.C, according to the general
formulae,
V.sub.O = V.sub.A (V.sub.C /V.sub.B).sup.n or V.sub.O = K 1n
(V.sub.C /V.sub.B).sup.T ,
where V.sub.C is greater than V.sub.B and n, K, and T.sub.1 are
determinable constants of the circuit.
The circuit has enerigzing means for simultaneously charging a
first relaxation oscillator with V.sub.C and a second relaxation
oscillator with V.sub.O for a determinable finite time period.
After the time period expires, the oscillators are simultaneously
permitted to decay. The voltages and response times required for
V.sub.C to fall to V.sub.B and for V.sub.O to fall to V.sub.A are
sensed and compared in first and second comparator means,
respectively. Correction means are provided to adjust the value of
V.sub.O for urging the difference in the response times to
decrease. Sequencing means are operated by the comparator means for
causing V.sub.O to be successively recalculated. When the response
times are equal, the circuit calculates V.sub.O = V.sub.A (V.sub.C
/V.sub.B).sup.n. Alternatively, an element of the second relaxation
oscillator may be replaced; and a capacitor may be supplied with
constant circuit, selectively dischargeable to ground. While the
first relaxation oscillator decays, the capacitor is permitted to
charge. The correction means adjusts and calculates V.sub.O. The
sequencing means causes V.sub.O to be recalculated, thereby to
compute V.sub.O = K 1n (V.sub.C /V.sub.B).sup.T when the response
times are equal.
The time required by the circuit to calculate V.sub.O is adjustable
regardless of the general formula selected.
One object of the present invention is to provide a single
electrical circuit capable of calculating an output voltage V.sub.O
as a function of variable input voltages V.sub.A, V.sub.B, and
V.sub.C, according to the general formulae, V.sub.O = V.sub.A
(V.sub.C /V.sub.B).sup.n or V.sub.O = K 1n (V.sub.C /V.sub.B).sup.T
, where V.sub.C is greater than V.sub.B and n, K and T.sub.1 are
determinable constants of the circuit.
Another object is to provide a computing circuit which calculates
an output voltage V.sub.O by driving the response times of two
decaying relaxation oscillators into phase and frequency
equality.
Another object is to provide a computing circuit capable of
providing a variable analog output signal as a function of variable
analog input signals through the use of intermediate digital
logic.
Another object is to provide a computing circuit capable of varying
the time required to obtain a desired calculation.
Another object is to provide a computing circuit wherein the output
or calculated signal is sampled and employed as a feedback
signal.
Another object is to provide a computing circuit wherein the
calculation of V.sub.O is mathematically exact.
Still another object is to provide a relatively simple and
inexpensive computing circuit.
These and other objects and advantages will become apparent from
the foregoing and ongoing specification, the drawings, and the
appended claims .
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic representation of the circuit producing an
output voltage V.sub.O as a function of input voltages V.sub.A,
V.sub.B, and V.sub.C.
FIG. 2 is a schematic wiring diagram of the circuit depicted in
FIG. 1 and capable of performing the functions,
V.sub.O = V.sub.A A (V.sub.C /V.sub.B).sup.n or V.sub.O = K 1n
(V.sub.C /V.sub.B).sup.T ,
where n, K and T.sub.1 are determinable constants of the
circuit.
FIG. 3 is a graphical illustration of the operation of the circuit
in calculating V.sub.O = V.sub.A (V.sub.C /V.sub.B).sup.n, as the
input voltages are varied.
FIG. 4 is a graphical illustration of the operation of the circuit
in calculating V.sub.O = K 1n (V.sub.C /V.sub.B).sup.T , as the
input voltages are varied.
FIG. 5 is an elevational view of a cylindrical pipe discussed in
the hypothetical practical illustration.
FIG. 6 is a schematic view depicting the manner in which three
circuits and a differential amplifier may be combined to solve the
complicated equation of the hypothetical practical
illustration.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring to FIG. 1, the inventive multi-mode computing circuit is
generally indicated at 10 and is shown receiving three variable
input voltages, V.sub.A, V.sub.B, and V.sub.C, on circuit input
terminals 11, 12 and 13, respectively, and producing an output
voltage V.sub.O at circuit output terminal 15 as a function of the
input voltages. If V.sub.C is greater than V.sub.B, the single
circuit 10 is alternatively capable of producing V.sub.O according
to the following general equations:
(Eqn. 1) V.sub.O = V.sub.A (V.sub.C /V.sub.B).sup.n,
where n is a determinable constant or,
(Eqn. 2) V.sub.O = K 1n (V.sub.C /V.sub.B).sup.T , where K and
T.sub.1 are determinable constants.
As used herein, the term "mode" refers to a mathematical
calculation or computation, such as multiplication; division;
raising a number (or a ratio) to a power; extracting a root from a
number (or a ratio); taking the natural logarithm of a number (or a
ratio); or multiplying a natural logarithm by a constant to obtain,
for example, a logarithm to a different base. Either of the
alternative general formulae specified above are capable of
performing more than one mode of operation.
In Equation 1: if V.sub.B = 1 and n = 1, V.sub.O = V.sub.A V.sub.C
(simple multiplication); if V.sub.A = 1 and n = 1, V.sub.O =
V.sub.C /V.sub.B (simple division); if n = 1, V.sub.O = V.sub.A
(V.sub.C /V.sub.B) (a multiplier times a ratio); if V.sub.A = 1,
V.sub.B = 1, and n = 3, V.sub.O = V.sub.C.sup.3 (cube); if V.sub.A
= 1, V.sub.B = 1, and n = 1/3, V.sub.O = V.sub.C.sup.1/3 (cube
root); and so forth.
Similarly, in Equation 2: if V.sub.B, K, and T.sub.1 each equal 1,
V.sub.O = 1n V.sub.C (natural logarithm of a number); if K = a
constant, and V.sub.B and T.sub.1 = 1, V.sub.O = K 1n V.sub.C
(constant times a natural logarithm of a number); and so on. Thus,
several modes of operation may be obtained regardless of the
general equation selected.
THE CIRCUIT (FIG. 2)
A computing circuit capable of calculating V.sub.O as a function of
the variable input voltages according to the general formulae
specified in Equations 1 and 2 is schematically illustrated in FIG.
2.
The three input terminals 11, 12 and 13 are shown receiving their
respective voltages, V.sub.A, V.sub.B, and V.sub.C. The output
voltage V.sub.O is available at output terminal 15. The circuit
broadly includes two identical voltage comparators A.sub.1 and
A.sub.2, an AND gate, a monostable multivibrator, a voltage source
V, a constant current source i.sub.K, two RC relaxation
oscillators, a buffer amplifier, and a capacitor C.sub.s, along
with a plurality of electronic (ES) and manual (MS) switches and
resistors (R).
The identical voltage comparators A.sub.1 and A.sub.2 have a high
input impedance and receive their input voltages at terminals 2 and
3 to produce an output signal at terminal 6. If the voltage on
terminal 3 is greater than at terminal 2, the comparator will
produce a positive output signal at terminal 6; if the voltage at
terminal 3 equals that at terminal 2, the comparator will produce a
null or zero signal at terminal 6; if the voltage at terminal 3 is
less than that at terminal 2, the comparator will produce a
negative output signal.
The monostable multivibrator may be excited or triggered into its
quasi-stable state to produce a positive pulse output for a finite
period of time, t.sub.d, after expiration of which it reverts to
its stable state having a negative output. Preferably, the
multivibrator has an adjustable quasi-stable state to permit
t.sub.d to be varied, thereby to alter the length of time of the
triggered positive pulse. With the capability of adjusting the
length of time t.sub.d that the monostable multivibrator remains
excited in its quasi-stable state, the time required for the
circuit to calculate V.sub.O may be varied. This feature is of
tremendous significance. For example, if the circuit is merely to
perform a mathematical calculation, t.sub.d may be set to a very
small value, thereby enabling the circuit to rapidly calculate the
value of V.sub.O. However, if the circuit is employed to monitor a
chemical process or the like, t.sub.d can be set to a large value
to afford a "wait and see" capability of operation. In this latter
application, t.sub.d could be adjusted to equal or approach one of
the process parameters.
In the well known manner, the AND gate will produce a positive
output only if its input signals are both positive. If either or
both of its input signals are negative, the AND gate will maintain
a negative output.
The buffer amplifier has a high input impedance and a low output
impedance and has a gain of approximately one, which need not be
stable or linear.
Input voltage V.sub.A is applied to the computing circuit at input
terminal 11 and is directed to terminal 3 of comparator A.sub.2
through manual switch MS.sub.4 and conductor 20. Input voltage
V.sub.B is applied at input terminal 12 and is directed to terminal
3 of comparator A.sub.1 through conductor 21. Input voltage V.sub.C
is applied at terminal 13 and is directed to terminal 2 of
comparator A.sub.1 through conductor 22, electronic switch
ES.sub.1, and conductors 23, 24.
A first relaxation oscillator network is connected to terminal 2 of
comparator A.sub.1 between conductors 23 and 24 by a conductor
25.
The first relaxation oscillator has a variable resistor R.sub.1
connected to conductor 25 by a conductor 26, and connected to
ground wire 28 by conductor 29; and has a capacitor C.sub.1
connected in parallel with R.sub.1 by conductors 30, 31 connected
to conductor 25 and to ground wire 28, respectively. The first
relaxation oscillator means includes this first relaxation
oscillator network.
The calculated voltage V.sub.0 is supplied to terminal 2 of
comparator A.sub.2 from the buffer amplifier through conductors 33,
34 and 35, electronic switch ES.sub.2, and conductors 36, 37 and
38.
The second relaxation oscillator network is connected to terminal 2
of comparator A.sub.2 between conductors 37 and 38 by a conductor
39, manual switch MS.sub.1, and conductor 40. The second oscillator
has a resistor R.sub.2 connected to conductor 40 by conductors 41
and 42 and manual switch MS.sub.3, and connected to ground wire 43;
and has capacitor means such as a capacitor C.sub.2 connected in
parallel with R.sub.2 by a conductor 44 connected to conductor 40
and by conductor 45 connected to ground wire 43. The second
relaxation oscillator means includes this second relaxation
oscillator network.
Manual switch MS.sub.1 may be moved to its phantom position to
disconnect the second relaxation oscillator network from terminal 2
of comparator A.sub.2 and to connect conductor 40 to a constant
circuit source i.sub.K.
Manual switch MS.sub.2 may be selectively closed to provide a shunt
around electronic switch ES.sub.2 and is connected by conductor 46
between conductors 36 and 37, and by conductor 48 between
conductors 35 and 34.
Manual switch MS.sub.3 may be moved to its phantom position to
disconnect R.sub.2 from conductor 42 and to connect a branch in
parallel with C.sub.2 including conductor 49, electronic switch
ES.sub.3, and conductor 50 connected to ground wire 43.
Manual switch MS.sub.4 may be moved to its phantom position to
disconnect input voltage V.sub.A and to connect conductor 20 to
conductor 41 through an intermediate conductor 51.
The output signal produced at terminal 6 of comparator A.sub.1 is
received as a first input signal to the AND gate through conductor
52. Similarly, the output signal produced at terminal 6 of
comparator A.sub.2 is received as a second input signal to the AND
gate through conductor 53. If the signals in conductors 52 and 53
are both positive, the AND gate will trigger the monostable
multivibrator into its quasi-stable state through conductor 54.
When so excited, the multivibrator produces a positive pulse output
for a predetermined period of time, t.sub.d, which is employed to
close ES.sub.1, ES.sub.2, and ES.sub.3 for a corresponding period
of time, as shown schematically by dashed lines 55, 56, 58, 59 and
60. The sequencing means includes the AND gate.
A voltage source V is grounded through a series circuit including
conductor 61, electronic switch ES.sub.4, resistors R.sub.4 and
R.sub.3, electronic switch ES.sub.5, and ground wire 62. Electronic
switches ES.sub.4 and ES.sub.5 are operated by the comparator
output signals in conductors 53 and 52, respectively, as shown
schematically by dashed lines 63 and 64. Therefore, ES.sub.5 will
close when the output signal of comparator A.sub.1 is positive, and
open when it is negative. Similarly, ES.sub.4 will close when the
output signal of comparator A.sub.2 is positive, and open when it
is negative. The correction means thus comprises a voltage supply
circuit including voltage source V, ES.sub.4 and resistor R.sub.4 ;
and a voltage drain circuit including R.sub.3, ES.sub.5 and ground
wire 62.
A capacitor C.sub.s is grounded by ground wire 65 and is connected
between resistors R.sub.3 and R.sub.4 by series conductors 66 and
68. Conductor 32 is shown connected between conductors 66 and
68.
The energizing means includes the monostable multivibrator and
electronic switches ES.sub.1, ES.sub.2 and ES.sub.3. The first
electronic switch means comprises ES.sub.1 ; and second electronic
switch means comprises ES.sub.2 ; and the third electronic switch
means includes ES.sub.3.
The first and second comparator means includes comparators A.sub.1
and A.sub.2, respectively.
As used herein, the term "relaxation oscillator means" broadly
includes other known and functionally equivalent RC and RL circuits
wherein a voltage may be permitted to decay to a lower value in a
reproducible manner.
Derivation of V.sub.0 = V.sub.A (V.sub.C /V.sub.B).sup.n
With the four manual switches MS.sub.1, MS.sub.2, MS.sub.3 and
MS.sub.4 moved to the positions indicated by the solid lines in
FIG. 2, the circuit is prepared to calculate V.sub.0 = V.sub.A
(V.sub.C /V.sub.B).sup.n .
The three input voltages, V.sub.A, V.sub.B and V.sub.C, are each
applied to their respective input terminals, 11, 12 and 13. V.sub.C
is either selected or scaled to a greater value than V.sub.B.
Similarly, the internal voltage source V is provided at a greater
value than V.sub.0.
Assume that initially the circuit is arranged such that all
electronic switches are open and the several capacitors are
discharging to low values. V.sub.B and V.sub.A will be applied to
terminals 3 of comparators A.sub.1 and A.sub.2, respectively. Since
ES.sub.1 is open, V.sub.C will not be applied to terminal 2 of
comparator A.sub.1. Since ES.sub.2 is open, V.sub.0 will not be
applied to terminal 2 of comparator A.sub.2. Therefore, the voltage
at terminals 3 will be greater than that at terminals 2 of both
comparators A.sub.1 and A.sub.2.
At this instant, the output signals of both comparators will
simultaneously be positive. ES.sub.4 and ES.sub.5 will be closed,
grounding voltage source V through series resistors R.sub.3 and
R.sub.4 and charging capacitor C.sub.s to some value. Receiving two
positive input signals, the AND gate triggers the monostable
multivibrator into its quasi-stable state to close ES.sub.1 and
ES.sub.2 and to apply V.sub.C and V.sub.0 to comparators A.sub.1
and A.sub.2, respectively. Since V.sub.C is greater than V.sub.B,
the output of comparator A.sub.1 will flip from positive to
negative, opening ES.sub.5, and adjusting the value of V.sub.0.
If V.sub.0 is greater than V.sub.A, the output signal of comparator
A.sub.2 will simultaneously flip from positive to negative, opening
ES.sub.4. When ES.sub.4 and ES.sub.5 are both open, the voltage
across capacitor C.sub.s is fixed. Accordingly, the value of
V.sub.0 will be fixed.
ES.sub.1 and ES.sub.2 are closed when the multivibrator is
triggered into its quasi-stable state. During this time t.sub.d,
capacitor C.sub.1 is charged to V.sub.C and capacitor C.sub.2 is
charged to V.sub.0.
After time period t.sub.d expires, the multivibrator reverts to its
stable state, opening ES.sub.1, ES.sub.2, and ES.sub.3. Both
capacitors of the relaxation oscillator networks begin to decay
which is sensed at terminals 2 of the respective comparators.
During such decay, the current in the first oscillator is given by
the formula, i.sub.1 = i.sub.0 e .sup.- .sup.t/R .sup.C
Initially, i.sub.0 = V.sub.C /R.sub.1. Substituting, i.sub.1 =
(V.sub.C /R.sub.1) e .sup.-.sup.t/R .sup.C .
When the first relaxation oscillator decays to the flip voltage
V.sub.B, the current will be i.sub.at flip =V.sub.B /R.sub.1.
Substituting for i.sub.1 and and solving for .DELTA.t.sub.1, the
time required for this decay:
V.sub.B /R.sub.1 = (V.sub.C /R.sub.1)e .sup.-.sup..delta..sup.t
.sup./R .sup.C
v.sub.b /v.sub.c = e .sup.-.sup..delta..sup.t .sup./R .sup.C
v.sub.c /v.sub.b = e .sup.+.sup..delta..sup.t .sup./R .sup.C
.DELTA.t.sub.1 = 1n (V.sub.C /V.sub.B).sup.R .sup.C
where .DELTA.t.sub.1 = response time of first relaxation oscillator
to decay from V.sub.C to V.sub.B.
Similarly, the decaying current in the second oscillator is given
by the formula:
i.sub.2 = i.sub.o e .sup.-.sup.t/R .sup.C
When ES.sub.2 opens,
i.sub.o = V.sub.0 /R.sub.2
or,
i.sub.2 = (V.sub.0 /R.sub.2)e .sup.-.sup.t/R .sup.C
After the second oscillator decays from V.sub.0 to V.sub.A, the
flip voltage,
i.sub.2 at flip = V.sub.A /R.sub.2
Substituting and solving for .DELTA.t.sub.2 :
V.sub.A /R.sub.2 = (V.sub.0 /R.sub.2)e .sup.-.sup..delta..sup.t
.sup./R .sup.C
v.sub.a /v.sub.0 = e .sup.-.sup..delta..sup.t .sup./R .sup.C
v.sub.0 /v.sub.a = e .sup.+.sup..delta..sup.t .sup./R .sup.C
.DELTA.t.sub.2 = 1n (V.sub.0 /V.sub.A).sup.R .sup.C
where t.sub.2 = response time for second oscillator to decay from
V.sub.0 to V.sub.A.
If .DELTA.t.sub.1 is less than .DELTA.t.sub.2, ES.sub.5 will close
before ES.sub.4, draining C.sub.s and decreasing V.sub.0 until
V.sub.0 = V.sub.A. Conversely, if the second oscillator decays to
flip A.sub.2 before the first oscillator decays to flip A.sub.1,
.DELTA.t.sub.2 will be less than .DELTA.t.sub.1, closing ES.sub.4
before ES.sub.5 to charge C.sub.s and to increase V.sub.0. Thus,
the value of V.sub.0 is adjusted and caused to be readjusted on
every sequence to urge the response times to equal each other.
Finally, when the response times are equal such that .DELTA.t.sub.1
= .DELTA.t.sub.2,
1n (V.sub.C /V.sub.B) .sup.R .sup.C = 1n (V.sub.0 /V.sub.A) .sup.R
.sup.C
or,
V.sub.0 = V.sub.A (V.sub.C /V.sub.B) .sup.R .sup.C .sup./ R
.sup.C
If n = R.sub.1 C.sub.1 /R.sub.2 C.sub.2, the following derivation
obtains:
V.sub.O = V.sub.A (V.sub.C /V.sub.B) .sup.n
where n may be selectively varied by adjusting variable resistor
R.sub.1.
Derivation of V.sub.O = K 1n (V.sub.C /V.sub.B) .sup.T
With manual switches MS.sub.1, MS.sub.2, MS.sub.3, and MS.sub.4
moved to the positions indicated by the phantom lines of FIG. 2,
the circuit is prepared to calculate V.sub.O = K 1n (V.sub.C
/V.sub.B) .sup.T where K and T.sub.1 are determinable constants of
the circuit. When so moved to their phantom positions, MS.sub.1
connects C.sub.2 to a constant current source i.sub.K, MS.sub.2
provides a shunt around ES.sub.2, MS.sub.3 disconnects V.sub.A and
connects C.sub.2 to terminal 3 of comparator A.sub.2.
In this configuration, the constant current source i.sub.K is
continuously applied to capacitor C.sub.2. When ES.sub.3 closes,
the current source is grounded and C.sub.2 is permitted to
discharge.
With the monostable multivibrator in its stable state, ES.sub.1 and
ES.sub.3 are open. Voltage V.sub.B is applied to terminal 3 of
comparator A.sub.2, generating a positive A.sub.2 comparator output
signal to the AND gate and closing ES.sub.5. Since ES.sub.3 is
open, the current source begins to charge C.sub.2 which is also
sensed on terminal 3 of comparator A.sub.2. Capacitor C.sub.2
charges according to the formula, ##SPC1##
Since, i = i.sub.K, a constant, ##SPC2##
In some time interval .DELTA.t.sub.2, capacitor C.sub.2 will have
charged with a voltage E.sub.C equal to V.sub.O. Substituting and
solving for t.sub.2 :
E.sub.C = V.sub.O = i.sub.K /C.sub.2 (.DELTA.t.sub.2)
.DELTA.t.sub.2 = V.sub.0 C.sub.2 /i.sub.K
Again V.sub.O is adjusted and readjusted such that the response
time of the capacitor to the value of V.sub.O is urged to equal the
response time of the first relaxation oscillator during decay.
Finally, the response times will be urged into equality, or,
.DELTA.t.sub.1 = .DELTA.t.sub.2
.DELTA.t.sub.1 = 1n (V.sub.C /V.sub.B) .sup.R .sup.C
.DELTA.t.sub.2 = V.sub.0 C.sub.2 /i.sub.K
Substituting and solving for V.sub.0,
1n (V.sub.C /V.sub.B) .sup.R .sup.C = V.sub.0 C.sub.2 /i.sub.K
v.sub.0 = i.sub.K /C.sub.2 1n (V.sub.C /V.sub.B) .sup.R .sup.C
or,
V.sub.0 = K 1n (V.sub.C /V.sub.B) .sup.T
where T.sub.1 = R.sub.1 C.sub.1 and K = i.sub.K /C.sub.2, all
determinable constants of the circuit.
When performing this function, the relaxation oscillator means
includes first relaxation oscillator.
Operation of V.sub.0 = V.sub.A (V.sub.C /V.sub.B) .sup.n Function
(FIG. 3)
FIG. 3 graphically represents the operation of the circuit in
computing the function, V.sub.0 = V.sub.A (V.sub.C /V.sub.B) .sup.n
. The numbered pulses of the monostable multivibrator are
vertically aligned with the corresponding peak voltages in C.sub.1
above and C.sub.2 below, respectively.
At the first and second mono pulses, the circuit is depicted
calculating V.sub.0 = 4 when V.sub.A = 2, V.sub.B = 1, and V.sub.C
= 2. The response times .DELTA.t.sub.1 and .DELTA.t.sub.2 are shown
to be equal, indicating that V.sub.0 = 4 is the desired
calculation.
Voltage V.sub.A is then increased from 2.0 to 2.5 in the interval
between pulse 2 and the completion of pulse 3. Capacitor C.sub.1 is
again charged with V.sub.C and is permitted to decay to V.sub.B.
Since V.sub.0 = 4 is still greater than the increased value of
V.sub.A, capacitor C.sub.2 is again charged with V.sub.0 = 4, but
decays to the lesser value, V.sub.A = 2.5, faster than V.sub.C
decays to V.sub.B. In this situation, .DELTA.t.sub.2 is less than
.DELTA.t.sub.1. Hence, ES.sub.4 closes before ES.sub.5, increasing
V.sub.0 to some higher adjusted value, as illustrated at sequential
pulse 4. Voltage V.sub.C still decays to voltage V.sub.B in the
same time, .DELTA.t.sub.1. However, adjusted voltage V.sub.0 now
decays from a higher value, tending to increase .DELTA.t.sub.2. The
response between pulses 4 and 5 illustrates V.sub.0 at some
intermediately adjusted value. Upon decay, .DELTA.t.sub.2 is still
less than .DELTA.t.sub.1, again causing V.sub.0 to increase.
Sequential pulse 5 represents a readjusted value of V.sub.0. When
V.sub.0 has performed the desired calculation, .DELTA.t.sub.1 will
equal .DELTA.t.sub.2, as shown in the intervals between pulses 5
and 6 and pulses 7 and 8.
If V.sub.C is decreased from 2.0 to 1.5 between pulses 7 and 8,
capacitors C.sub.1 will charge to the now lowered value of V.sub.C
= 1.5. The change in V.sub.C is not immediately known to V.sub.0,
which again charges to V.sub.0 = 5. After t.sub.d expires, V.sub.C
will decay to V.sub.B before V.sub.0 will decay to V.sub.A or,
.DELTA.t.sub.1 is less than .DELTA.t.sub.2. ES.sub.5 will open
before ES.sub.4 to adjust V.sub.0 to some decreased value,
represented at pulse 9. Voltage V.sub.0 will be sequentially
readjusted until .DELTA.t.sub.1 equals .DELTA.t.sub.2, as
represented by the equal response times between pulses 10 and 11.
When .DELTA.t.sub.1 equals .DELTA.t.sub.2, V.sub.0 equals 3.75, the
desired computation.
Now if V.sub.B is decreased from 1.0 to 0.75 between pulses 11 and
12, capacitor C.sub.1 will take longer to decay to the decreased
value of V.sub.B than capacitor C.sub.2 will take to decay from the
previous V.sub.0 to V.sub.A or, .DELTA.t.sub.1 will be greater than
.DELTA.t.sub.2. Hence, ES.sub.4 will close before ES.sub.5, causing
V.sub.0 to increase as shown at pulse 13. Again V.sub.0 is
sequentially readjusted to urge .DELTA.t.sub.2 to equal
.DELTA.t.sub.1, which situation is illustrated between pulses 14
and 15, and pulses 15 and 16.
Voltages V.sub.C and V.sub.B are shown increased to 2.0 and 1.0,
respectively, between pulses 16 and 17. At pulse 17, C.sub.1 will
charge to the higher value of V.sub.C and take longer to decay to
the lower value of V.sub.B, as shown between pulses 17 and 18. If
V.sub.A is decreased to 2 between pulses 17 and 18, V.sub.0 will
also take longer to decay. Electronic switch ES.sub.4 will open
first, increasing V.sub.0 at pulse 18. Finally, .DELTA.t.sub.1 will
equal .DELTA.t.sub.2 and the desired computation will have been
performed, as in pulses 19 and 20, and pulses 21 and 22.
By varying adjustable resistor R.sub.1, the exponent n can be
varied according to the formula, n = R.sub.1 C.sub.1 /R.sub.2
C.sub.2. In the response graphically depicted in the rightward
portion of FIG. 3, R.sub.1 has been adjusted such that n = 2 to
perform a squaring function. The response times are initially shown
to be equal between pulses 28 and 29 and pulses 29 and 30 so that
V.sub.0 = 2.25 when V.sub.A = 1, V.sub.B = 1, and V.sub.C = 1.5. If
V.sub.C is increased to 2.0 between pulses 30 and 31, V.sub.C will
charge to this higher value at pulse 31. When ES.sub.1 and ES.sub.2
are open, the response time of the first oscillator to decay from
V.sub.C to V.sub.B will take longer than the corresponding decay of
the second oscillator from the previous V.sub.0 to V.sub.A. Hence,
.DELTA.t.sub.1 will be greater than .DELTA.t.sub.2, causing
ES.sub.4 to open first and adjust the value of V.sub.0, as
represented in sequential pulse 32. The adjustment of V.sub.0
continues until .DELTA.t.sub.1 equals .DELTA.t.sub.2, indicating
performance of the desired computation, as indicated at pulses 33,
34 and 35.
Operation of V.sub.0 = K 1n (V.sub.C /V.sub.B) .sup.T Function
(FIG. 4)
FIG. 4 graphically represents the operation of the circuit in
computing V.sub.0 = K 1n (V.sub.C /V.sub.B) .sup.T . If initially,
V.sub.B = 4, V.sub.c = 8, K = 1, and T.sub.1 = 1, the circuit is
initially shown as calculating V.sub.0 = 1n (2) at pulses 1, 2 and
3.
When the monostable multivibrator closes ES.sub.1 and ES.sub.3 for
time t.sub.d, C.sub.1 is charged with V.sub.C and C.sub.2 is
permitted to discharge through conductors 44, 41, 42, 49, 50 and
43. Hence, when C.sub.1 is permitted to charge, C.sub.2 is
permitted to discharge. After t.sub.d expires, ES.sub.1 and
ES.sub.3 open, permitting capacitor C.sub.1 to decay and permitting
capacitor C.sub.2 to be charged with i.sub.K. Hence, C.sub.1 is
decaying when C.sub.2 is charging.
If V.sub.B is decreased to 1.0 between pulse 4 and pulse 5, C.sub.1
will take longer to decay to the lowered value of V.sub.B. If
capacitor C.sub.2 charges to the value of V.sub.0 first,
.DELTA.t.sub.2 will be less than .DELTA.t.sub.1, causing ES.sub.4
to close first, increasing V.sub.0. Again the system urges
.DELTA.t.sub.1 to equal .DELTA.t.sub.2 as shown between pulses 6
and 7 and pulses 7 and 8. Thus, if V.sub.C = 8 decays to V.sub.B =
1 in .DELTA.t.sub.1, C.sub.2 will charge to a higher value of
V.sub.0 = 1n (8) in the same time, indicating performance of the
desired computation.
If V.sub.C is increased to 15 between pulses 7 and 8, C.sub.1 will
be charged with V.sub.C during pulse 8. Hence, .DELTA.t.sub.1 will
be longer for capacitor C.sub.1 to decay from 15 to 1; C.sub.2 will
cause ES.sub.4 to close first, increasing V.sub.0. At
.DELTA.t.sub.1 = .DELTA.t.sub.2, V.sub.0 = 1n (15) will be
calculated.
If V.sub.B is increased to 5 between pulses 10 and 11, the response
time of C.sub.1 in decay will be shortened, opening ES.sub.5 before
ES.sub.4, to decrease V.sub.0. As .DELTA.t.sub.2 is shortened,
capacitor C.sub.2 charges to a lower value, finally when
.DELTA.t.sub.1 = .DELTA.t.sub.2, V.sub.0 = 1n (5) is
calculated.
PRACTICAL ILLUSTRATION
For purposes of illustrating the utility of further combinations of
the inventive circuit, assume that it is desired to calculate the
heat conducted through some or all of the pipes in an oil
refinery.
Referring to FIG. 5, a long hollow pipe 80 is depicted as having an
inner radius r.sub.i and an outer radius r.sub.0. Assume that a
fluid heats the inner surface to T.sub.i while the outer surface is
at temperature T.sub.0. The rate of heat conduction, q.sub.K is
given by the general formula,
q.sub.K = 2.pi.KL (T.sub.i -T.sub.0)/1n (r.sub.0 /r.sub.i)
where
2.pi. = a constant
K = coefficient of thermal conductivity
L = length
T.sub.i = temperature inside pipe
T.sub.0 = temperature outside pipe
r.sub.0 = outer radius
r.sub.i = inner radius
Three circuits and a differential amplifier may be uniquely
combined to calculate q.sub.K as a function of multiple variables,
as best shown in FIG. 6.
In FIG. 6, circuit No.1 is prepared to calculate V.sub.0 = V.sub.A
(V.sub.C /V.sub.B) .sup.n.sup.=1 . The input voltages are selected
such that V.sub.A = K, a variable; V.sub.B = 1/2.pi., a constant;
and V.sub.C = L, a variable. Substituting the input voltages into
the general equation produces an output voltage V.sub.0 =
2.pi.KL.
Circuit No.2 is prepared to calculate V.sub.0 = (i.sub.K /C.sub.2)
1n (V.sub.C /V.sub.B) .sup.T , where T.sub.1 = 1, and i.sub.K
/C.sub.2 = K = 1. Input voltages V.sub.B and V.sub.C are selected
to represent the radii, r.sub.i and r.sub.0, respectively.
Substituting the input voltages of V.sub.B and V.sub.C into the
general equation produces an output signal V.sub.0 = 1n (r.sub.i
/r.sub.0).
A differential amplifier receives the voltages analog of two
temperatures, T.sub.i and T.sub.0, produces an output signal equal
to their difference, (T.sub.i - T.sub.0).
Circuit No.3 is prepared to calculate V.sub.0 = V.sub.A (V.sub.C
/V.sub.B) .sup.n.sup.=1 with n=1. The output voltage V.sub.0 of the
circuit No.1 is received as input voltage V.sub.A to circuit No.3;
the output voltage V.sub.0 of circuit No.2 is received as input
voltage V.sub.B ; and the output voltage of the differential
amplifier, (T.sub.i - T.sub.0), is received as input voltage
V.sub.C . Substituting these input voltages into circuit No.3
produces an output signal, V.sub.0 = 2.pi.KL (T.sub.i -
T.sub.0),/[1n (r.sub.i /r.sub.0)],
the desired computation. Thereafter, any of the variables K, L,
T.sub.i, T.sub.0, r.sub.i, and r.sub.0 may be varied.
The foregoing practical illustration is intended merely to
demonstrate that two or more of the unique circuits herein
disclosed may be combined to perform a more complicated
computation. The practical illustration further demonstrates that
the inventive circuit may be combined with a differential
amplifier, as needed. Should an equation involve addition, a
summing amplifier could be used.
The various electrical and electronic components discussed
hereinabove are well known to the skilled in the art and therefore
require no more specific description.
* * * * *