U.S. patent number 3,782,504 [Application Number 05/314,918] was granted by the patent office on 1974-01-01 for multiplex system for elevator control.
This patent grant is currently assigned to Reliance Electric Company. Invention is credited to Joseph F. Billmaier, Gordon P. Sprague.
United States Patent |
3,782,504 |
Billmaier , et al. |
January 1, 1974 |
MULTIPLEX SYSTEM FOR ELEVATOR CONTROL
Abstract
A system of transmitting control and indicator signals between
elements of an elevator system such as between a car movable along
a hatch-way and car control or supervisory equipment wherein the
signals are coded and transmitted in multiplexed form over a single
transmission line. A two station system between a car and a fixed
location is illustrated with a transmitter and receiver at each
station. The coded signals are time sequenced so that all signals
are considered cyclically.
Inventors: |
Billmaier; Joseph F. (Toledo,
OH), Sprague; Gordon P. (Toledo, OH) |
Assignee: |
Reliance Electric Company
(Euclid, OH)
|
Family
ID: |
23222060 |
Appl.
No.: |
05/314,918 |
Filed: |
December 14, 1972 |
Current U.S.
Class: |
187/380 |
Current CPC
Class: |
B66B
1/3446 (20130101); B66B 1/3415 (20130101); G08C
15/12 (20130101); B66B 1/34 (20130101) |
Current International
Class: |
G08C
15/00 (20060101); G08C 15/12 (20060101); B66B
1/34 (20060101); B66b 003/00 () |
Field of
Search: |
;187/29 ;340/19,21 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Gilheany; Bernard A.
Assistant Examiner: Duncanson, Jr.; W. E.
Attorney, Agent or Firm: Wilson & Fraser
Claims
What is claimed is:
1. A control system for an elevator including an elevator car, a
controller for said car, and drive means for driving said car
between a plurality of landings served thereby comprising a first
station having elevator controls; a second station having elevator
controls; a transmission line coupling said first station and said
second station; a plurality of signal inputs at said first station;
means to read said inputs individually in a predetermined order; a
transmitter at said first station coupled to said transmission line
for transmitting signals from said reading means in the order said
signals are read; a receiver coupled to said transmission line at
said second station; a plurality of signal storage means at said
second station; means to couple signals from said transmission line
individually to individual signal storage means in a predetermined
order corresponding to the order said signal inputs are read by
said reading means, said storage means corresponding to said signal
inputs; and signal outputs at said second station from said signal
storage means.
2. A control system according to claim 1 wherein said first station
is on said elevator and said second station is associated with the
controller remote from said elevator car; means on said car
responsive to car position coupled to one of said signal inputs to
apply a signal thereto; and coupling means to said drive means from
said signal output of said second station for said storage means
corresponding to said car position responsive signal input.
3. A control system according to claim 1 wherein said car includes
an entry; a closure for said entry; means sensing the position of
said closure in said entry and applying signals responsive thereto
to one of said signal inputs; and coupling means to said controller
for said car from said signal output at said second station
corresponding to said closure position responsive signal input.
4. A control system according to claim 1 wherein said car includes
an entry; a closure for said entry; controls for said closure for
applying signals to one of said signal inputs; and coupling means
to said controller for said car from said signal output at said
second station corresponding to said closure control signal
input.
5. A control system according to claim 1 wherein said car includes
means for registering car calls for service to the landings by
passengers within said car for applying signals to said signal
inputs; and coupling means to said controller for said car from
said signal outputs at said second station corresponding to said
car call signal inputs.
6. A control system according to claim 1 including a plurality of
means for generating different car operating signals mounted on
said car, means coupling each of a plurality of said signal
generating means to respective ones of said signal inputs as said
first station; and coupling means to said controller for said car
from said signal outputs at said second station corresponding to
said signal inputs for said car operating signals.
7. A control system according to claim 6 including a traveling
cable extending between said car and a fixed location in structure
severed by the car wherein said first station is on said elevator
car and said transmission line is incorporated in said traveling
cable.
8. A control system according to claim 1 including means to sense
the completion of the reading of predetermined inputs; and means to
enable a repetition of the reading of said inputs individually in
said predetermined order in response to said completion sensing
means.
9. A control system according to claim 1 including encoding means
to encode signals read by said signal reading means for
transmission by said transmission line; and decoding means to
decode encoded signals received by said receiver to a form for
application to said signal storage means.
10. A control system according to claim 9 wherein said encoding and
decoding means are for binary signals.
11. A control system according to claim 1 including a plurality of
signal inputs at said second station; means to read said inputs at
said second station individually in a predetermined order; a
transmitter at said second station coupled to said transmission
line for transmitting signals from said reading means at said
second station in the order said signals are read; a receiver
coupled to said transmission line at said first station; a
plurality of signal storage means at said first station; means at
said first station to couple signals from said transmission line
individually to individual signal storage means at said first
station in a predetermined order as received by said receiver at
said first station; signal outputs at said first station from said
signal storage means at said first station; means for enabling said
transmitter at said first station while inhibiting said receiver at
said first station; and means for enabling said transmitter at said
second station while inhibiting said receiver at said second
station.
12. A control system according to claim 11 including means for
enabling said receiver at said first station while inhibiting said
transmitter at said first station; and means for enabling said
receiver at said second station while inhibiting said transmitter
at said second station.
13. A control system for an elevator comprising a first station and
a second station; transmission line means coupling said first
station and said second station; a transmitter at each station
adapted to generate a regular cyclic sequence of signals for
discrete elevator operating functions; a receiver at each station
adapted to receive a sequence of signals for discrete elevator
operating functions corresponding to the sequence and functions of
the signals generated by said transmitter of the station coupled
thereto by said transmission line; and means to maintain each
received signal for said receivers until said signal is altered
during a regular cyclic sequence of signals from the transmitter
from which it was received.
14. A control system according to claim 13 including a plurality of
signal sources at each station for said signals for discrete
elevator operating functions; signal encoding means at each station
for encoding signals from said respective sources for said
respective transmitters; and signal decoding means at each station
for decoding signals received by said respective receivers for
application to said signal maintaining means.
15. A control system according to claim 14 including scanning means
for said transmitter at each station for scanning said sources at
said station; signal latch means for said transmitter actuated
during an initial portion of the scan of each source by said
scanning means to latch the currently scanned signal; and means
enabling said encoding means during a portion of the scan of each
source by said scanning means which is subsequent to said initial
portion to encode the latched signal.
16. A control system according to claim 13 wherein said transmitter
at said each station and said receiving means at said station are
connected in parallel to said transmission line means.
17. A control system according to claim 16 including means to
inhibit reception by the receiver at each station during
transmission of signals by said transmitter at said station.
18. A control system according to claim 16 including means to
enable reception by the receiver at each station upon completion of
each transmission of a cyclic sequence of signals by said
transmitter at said station.
19. A control system according to claim 13 including a plurality of
sources of discrete elevator operating signals at each station;
said transmitter at each station including means for scanning the
sources at said station in a predetermined sequence; means at each
station for encoding each signal as it is scanned; said receiver at
each station including means for scanning said signal maintaining
means in synchronism with said scanning means of said transmitter
at the opposite station; and means at each station for decoding
each signal received by said receiver.
20. A control system according to claim 19 including means to
generate clocking signals, said clocking signals actuating said
source scanning means; and means actuating said encoder in response
to said clocking signals and in synchronism with the scan of
individual signal sources.
21. A control system according to claim 19 including means to
define a signal characteristic of each encoded signal; and means
for actuating said signal maintaining scanning means in response to
said defined signal.
22. A control system according to claim 19 including means to
define a signal characteristic of each encoded signal; and means
for actuating said decoding means in response to said defined
signal.
23. A control system according to claim 19 including means
associated with the transmitter at each station to generate
clocking signals; means to advance said source scanning means in
response to said clocking signals; means to actuate said encoder in
response to said clocking signals and in synchronism with the scan
of individual sources; means to produce a signal characteristic of
an encoded signal for each encoded signal; means associated with
the receiver at each station to advance said signal maintaining
scanning means in response to said characteristic signal from the
transmitter at the opposite station; and means for actuating said
decoding means in synchronism with the advance of said receiver
associated scanning means in response to said characteristic
signal.
24. A control system according to claim 13 including individual
sequencing controls for said first and second stations for mutually
exclusive enabling of said transmitter and receiver of each
station.
25. A control system according to claim 13 including means to sense
an absence of synchronism in the sequence of signals transmitted by
the transmitter at one of said stations and the signals received by
the receiver at the station opposite said one station.
26. A control system according to claim 13 including means at each
station for said transmitter at said station for sensing the
completion of a cyclic sequence of signals generated by said
transmitter; means at each station for said receiver at said
station for enabling said receiver at said station in response to
completion of a cyclic sequence of signals generated by said
transmitter at said station; means at each station for said
receiver at said station for sensing the completion of reception by
said receiver of a predetermined number of signals generated by
said transmitter at said opposite station; and means at each
station to recycle said sequence of signals generated by said
transmitter for said station in response to the completion of
reception by said receiver at said station of said predetermined
number of signals.
27. A control system according to claim 26 including a timer
defining an interval initiated upon enabling a receiver at a
station and of a length exceeding the time required to complete
reception by said receiver of said predetermined number of signals;
and means responsive to expiration of said interval without
completion of reception of said predetermined number of signals to
recycle said sequence of signals generated by said transmitter for
said station.
28. In an elevator system including an elevator car movable in a
hatchway, a source of a plurality of first control signals in said
car, a control unit responsive to each of a plurality of second
control signals in said car, a prime mover, a fixed controller for
controlling said prime mover in response to each of said plurality
of first control signals, a source for said plurality of second
control signals in said controller and a communication system for
sending said pluralities of first and second control signals in
multiplexed coded binary form between said car and said controller,
said communication system comprising a first transmitting means for
said coded first control signals, a second transmitting means for
said coded second control signals, a first receiving means
responsive to each of said coded first control signals, a second
receiving means responsive to each of said coded second control
signals and connecting means between said first transmitting means
and said first receiving means and between said second transmitting
means and said second receiving means.
29. An elevator system according to claim 28 wherein said
connecting means is a flexible transmission line having said first
transmitting means and said second receiving means connected in
parallel to one end thereof and having said second transmitting
means and said first receiving means connected in parallel to the
other end thereof.
30. An elevator system according to claim 28 wherein said
transmitting means include means to generate a train of clock
pulses, means responsive to said clock pulses for generating an
enable signal and means responsive to said enable signal for coding
each of said plurality of control signals in sequence.
31. An elevator system according to claim 30 wherein said means for
coding includes multiplexing means responsive to said train of
clock pulses for selecting in sequence each of said plurality of
control signals, said control signals being either a binary "1" or
a binary "0"; and means responsive to said train of clock pulses
and said selected control signal for generating a four pulse coded
signal having as the first and fourth pulses binary "0", the second
pulse binary "1" and the third pulse binary "1" if said control
signal is binary "0" or binary "0" if said control signals is
binary "1".
32. An elevator system according to claim 30 wherein said receiving
means include means responsive to said coded control signals for
generating clock pulses, means responsive to said clock pulses for
generating an enable signal, means responsive to said enable signal
for decoding said coded control signals and means for storing said
decoded control signals.
33. An elevator system according to claim 32 wherein said means for
generating clock pulses includes a timer with a timing period equal
to the duration of 11/2 pulses of said coded control signals, means
responsive to the second pulse of said coded control signals for
initiating said timing period; and means responsive to the end of
said timing period for generating a clock pulse.
34. A control system according to claim 13 including a timer
defining an interval initiated upon enabling a receiver at a
station and of a length exceeding the time required to complete
reception by said receiver of a predetermined number of said
signals; and means responsive to expiration of said interval
without reception of signals to recycle said transmitter for said
station to transmit the sequence of signals generated by said
transmitter.
Description
DESCRIPTION OF THE PRIOR ART
In a modern elevator system there is the requirement for
communication of a large number of separate control and indicator
signals between the movable elevator car and a stationary elevator
controller and between various stations such as indicator panels
and controls and between controllers and system supervisory
controls. Heretofore, this communication has been accomplished by
providing one or more cables with individual wires for each signal
source to electrically link the stations such as the traveling
cable between the car and the controller. As more features are
added to the elevator system these cables become progressively more
heavy and costly and less flexible.
In an attempt to solve this problem the prior art has utilized the
transmission of different frequencies of a single transmission
line. Representative systems are disclosed in Cummins Patent
entitled "Radio Communication Means Between Elevator Cage and Motor
Control" issued as 3,203,506 on Aug. 31, 1965 and Geil U.S. Pat.
No. 3,519,105 entitled "Vehicle Control" issued July 7, 1970. Each
control signal is assigned a distinct frequency, either just a
carrier or a carrier with audio modulation, which is generated by
an oscillator At the receiving end of the transmission line there
are filters and detectors for each signal.
Although the frequency technique eliminates the bulky flexible
cable it also has the disadvantage of being complex and costly.
Each control signal must have its own oscillator, filter and
detector. Where there are a large number of signals involved the
available frequency spectrum may dictate bandwidth and spacing that
requires the use of relatively expensive components.
SUMMARY OF THE INVENTION
Communication between components of an elevator system such as the
elevator car and the elevator controller is achieved by coding
binary signals and transmitting them along a common data line in
multiplexed form. Conventional elevator control and indicator
signals are applied to individual inputs of a multiplex transmitter
and are repetitively read in a predetermined sequence and
transmitted to a remote receiver. The received signals are
sequenced in correspondence with their transmitter sequence and
stored in latches or memories for utilization by controlled
elements including switches and relays.
Bidirectional transmission is provided. Each station has a
transmitter and a receiver. When a local transmitter completes its
multiplex signal sequence or cycle, it enables a local receiver to
receive the multiplex signal sequence of the remote multiplex
transmitter. When a local receiver has received its full multiplex
signal sequence and the local transmitter has sent its full
multiplex signal sequence the local transmitter is cycled to again
read and transmit its multiplex signal sequence.
Signals are represented as a "true" or "false" state for each item
sensed. In the example, a 32 word multiplex signal sequence is
employed. A "true" condition for the word is signified by a short
interval logic "1" and a "false" condition is represented by a
longer interval logic "1". Each word is made up of four bits
defined by a transmitter clock such that the first and fourth bits
are always a logic "0", the second bit is always a logic "1" and
the third bit is a logic "0" if the condition is true and "1" if
the condition is false.
The receiver section of each multiplexer is sequenced by a counter
which is clocked from its opposite transmitter by each word it
receives by the rising leading edge of the signal during the second
bit interval of the word. Decoding of the word is by means of a
timer which senses the logic state of the received signal during
the third bit interval of the word.
Transitions in input conditions for a signal during that portion of
a signal cycle in which that signal is being transmitted is
prevented from altering the transmitted signal. A check of the
input at the beginning of the signal transmission for its word sets
a latch and prevents a change in the logic "1" duration dictated at
the setting of the latch. Thus, changes in a condition represented
by a word are indicated only during the next transmission of a
multiplex signal cycle at the time signal for that word is
read.
Synchronization of a transmitter multiplex signal cycle and the
inputs it reads with the receiver multiplex signal cycle and the
output latches it sets is sensed by the completion of a local
transmitter multiplex signal cycle and coincidence of completion of
a local receiver multiplex signal cycle. The failure to achieve a
coincidence of completed signal cycles for an excessive interval
resets the transmitter to force synchronization where the
transmitters of each station are arranged so they always complete
their signal cycles and upon completion always enable their local
receivers.
DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic representation of a two-car elevator system
having signal transmitting means according to the invention;
FIG. 2 is a block diagram of one multiplex unit utilized in the
multiplex system according to this invention;
FIG. 3 is a block diagram of two multiplex units coupled by a
transmission line;
FIG. 4 shows a portion of a multiplex signal sequence including
several coded signals for false and true inputs to the multiplex
unit;
FIG. 5 is a schematic representation of a transmitter section which
may be employed in the multiplex unit of FIGS. 2 and 3; and
FIG. 6 is a schematic representation of a receiver section
according to the preferred embodiment of the multiplex unit of
FIGS. 2 and 3.
DESCRIPTION OF THE PREFERRED EMBODIMENT
In an elevator system, such as the one shown in FIG. 1, there are
many requirements for transmitting control signals between two
fixed objects or a moving and a fixed object. For purposes of
illustration a two car system is depicted, however, the present
invention may be utilized with any number of elevator cars.
Elevator cars 20 and 21 are connected to one end of cables 22 and
23, while the other end of each cable is connected to
counterweights 24 and 25. The cables are placed over sheaves 26 and
27 which are rotated to raise and lower the elevator cars. The
sheaves are attached to the output shafts of motors 28 and 29.
Generators 31 and 32 have their armatures electrically connected to
the armatures of motors 28 and 29 to form a well-known Ward-Leonard
system of speed control for each elevator car. Each motor and
generator combination receives control signals from controllers 33
and 34. These controllers determine the movement of the elevator
car in response to control signals in the form of car calls, hall
calls and other running signals. Where two or more elevator cars
are to service the same landings, a supervisory control 35 is
provided to determine, for example, the distribution of the cars
and which controller will respond to a hall call.
It is apparent that there must be connections between the elevator
car and its controller and the landings and the supervisor in order
to transmit the necessary control signals. For example, in the five
floor building shown in FIG. 1, elevator car 20 contains a panel 36
with five pushbuttons, one for each floor, with which to register
car calls. The car also includes means sensing its location along
the hatchway such as an inductor notching switch 40 responding to
the car's passing critical positions in the hatchway and controls
responsive to the position of the door 50 providing a closure for
its entry from the landings it serves. In order to transmit a car
call,a door control signal,or a car position signal to the
controller, previous systems have utilized a travelling cable
containing separate wires for each switch responsive to those
factors. The present invention reduces the wires required for
transmitting control signals to a twisted pair no matter how many
floors are contained in the system. The pushbuttons on panel 36 are
the inputs via leads 36-I as are door control leads 50-I and car
position leads 40-I to multiplexer unit 37 mounted on elevator car
20. These signals are converted to coded signals and are
transmitted on twisted pair 38, which may be cabled with power and
telephone conductors to the car to a similar multiplexer unit 39
located near controller 33. The coded signal is decoded and sent to
controller 33 which will stop the elevator car at the proper
floor.
Multiplexers may also be used to send hall calls to the supervisor.
Each floor except the terminal floors has a set of up and down hall
call pushbuttons 41. Thus, according to prior practice separate
lines from each floor to the supervisor would be required. By
utilizing a multiplexer unit, hall calls from several adjacent
floors can be coded and transmitted on a twisted pair to another
multiplexer unit at the supervisor. In FIG. 1 the top two floors
have hall call pushbuttons 41 connected to multiplexer unit 42.
Coded signals are transmitted on twisted pair 44 to multiplexer
unit 46 where the signals are decoded and sent to supervisor 35.
The first, second and third floor hall call pushbuttons 41 are
connected to multiplexer unit 43 which transmits coded signals on
twisted pair 45 to multiplexer unit 47.
A further example of utilizing the present invention to reduce
wiring is illustrated by the indicator panel in the lobby.
Indicator panel 48 has a series of lighted numbers which present a
visual display of elevator car location and call registrations to
persons waiting for the car. Car position signals and hall call
signals from supervisor 35 are coded by multiplexer unit 49. The
coded signals are transmitted on twisted pair 51 to multiplexer
unit 52 where the signals are decoded and sent to indicator 48.
In many cases it may be desired to transmit signals in both
directions between two locations. In the case of elevator car 20,
car location signals from controller 33 may be used to actuate a
visual indicator in the car (not shown). Therefore, each
multiplexer unit contains a transmitter and a receiver which are
alternately activated. When the transmittor in unit 37 is
sending,the receiver in unit 39 is enabled. After a predetermined
period of time or the transmission of a predetermined pulse train
to the receiver in unit 39, the transmitter in 39 is enabled as is
the receiver of unit 37. FIG. 2 is a block diagram of a basic
multiplexer unit and FIG. 3 represents a pair of coupled
multiplexer stations. Transmitter section 111 and receiver section
112 are connected in parallel to data lines 113, typically a
twisted pair.
The transmitter 111 has as inputs a start signal on line 118 and a
plurality of input lines 114 which are connected to various control
signal sources. As in FIG. 1 these inputs could be from the car
call pushbuttons on panel 36, leveling switches as 40, door limit
switches, door safety switches, manual switches for door control,
and attendant-automatic service switches all on the car. When a
switch is actuated, the signal is multiplexed, transmitted to the
receiver section of the multiplexer unit at the elevator
controller, set into the proper output to the controller, and
processed by the controller. In the case of a car call, a signal
from the controller to illuminate the light of the car pushbutton
for the call which is registered is multiplexed at the controller
multiplexer unit, transmitted to the receiver of the elevator car
multiplexer unit and set into the proper output for the pushbutton
light. Similarly, the controller can send other signals to the car
such as position indicator controls, direction, arrows, and open
and close door signals.
As will be set forth in more detail the multiplexer transmitters
111 each include means to read the signals imposed on a plurality
of inputs in a predetermined order. Normally, the read sequence for
a station is repeated following the completion of a receive cycle
for that station which follows the read cycle. The signals are
coded as words at the initiation of their individual read intervals
and are transmitted to the receiver 112 of the opposite multiplexer
station over a transmission line 113. The receiver at the opposite
station is sequenced by the received word signals to apply decoded
individual word signals to signal storage means or latches having
outputs. The sequence of application of signals to the storage
means and outputs corresponds to the sequence of signal inputs read
at the opposite station transmitter. Coupled to the outputs are the
utilization circuits for the respective signals, which circuits can
be conventional for control of the car and its signals.
The start signal on line 118, which may be an indication that the
power has been turned on, activates a clock 116 and enables a ring
counter 117. The clock, which is an oscillator running at a
predetermined frequency, generates a train of pulses. Those pulses
are counted by ring counter 117 which in turn produce a binary
output count to binary to decimal decoder 119. The decimal count
from decoder 119 steps the multiplexer 115 so that each input
signal appears at the line driver 121 in a definite time sequence.
The line driver 121 transmits the multiplexed signals over data
lines 113 to the receiver section of another multiplex unit. When
the last coded signal has been transmitted, the clock 116 is
inhibited and the receiver section 112 of the car multiplexer unit
is enabled.
Inputs on input lines 114 are in the form of the presence of or
absence of a voltage of a predetermined magnitude. The presence of
the voltage indicates a "true" signal or logic "1" while the
absence of the voltage indicates a "false" signal or logic "0". The
input signals are coded in the form of a group of four pulses. As
shown in FIG. 4, "false" is represented by a "0" pulse, two
contiguous "1" pulses and another "0" pulse. A "true" signal is
represented by a "0" pulse, a single "1" pulse and two more "0"
pulses. The first and last pulses of the group serve to condition
the receiver to read and time the middle two pulses which carry the
information. In receiver section 112 each group of four pulses is
received by line receiver 122 and pulses advances ring counter 123
one count. The output of the ring counter is in binary form and is
converted to a decimal number by binary to decimal decoder 124. The
output of the decoder is utilized to sequence the 8-bit latches 125
so that information from the line receiver 122 is placed on the
proper output line of a plurality of output lines 126. After the
last group of pulses is read, the ring counter 123 resets the ring
counter 117 of its multiplexer unit and the transmitter section 111
of that unit begins transmitting again.
A typical encoding for a simple one car system employs multiplexer
units having a 32 word capacity such that the car unit, termed
multiplexer unit A in FIG. 4, transmits a signal cycle of 32 words
of true or false signals each of four pulse lengths in the
sequence:
door open manual switch
safe edge switch
door protection switch
door limit, open
door limit, closed
leveling switch up
leveling switch down
notching switch up
notching switch down
first floor car call
second floor car call
third floor car call
fourth floor car call
any car call
The receiver of the multiplexer unit at the controller, termed
multiplexer unit B, is sequenced to actuate counterpart controls at
the controller for the above signals in the order set forth.
Conversely, the transmitter of multiplexer unit B has a
predetermined sequence of signals for which the receiver of
multiplexer unit A is correspondingly sequenced. In the example,
the controller-to-car signals are sequenced for the individual car
call register lights as the first five words, then a blank or spare
word, then the five position indicator light signals for car
position, then seven spare words, then door open signal, door close
signal, position indicator up direction, and position indicator
down direction. These signals are directed in the sequence of their
receipt to actuate controls for call registration indicators,
position indicators and door controls to open and close the car
doors, all of which are on the car.
An initial portion of a car-to-controller signal issued by the
transmitter of multiplexer unit A is illustrated in FIG. 4 wherein
the first bit has a long pulse indicating the door open pushbutton,
DO, in the car is not operated during that signal sequence. The
safe edge switch SE signal is also represented by a long pulse
indicating no safe edge operation. An obstruction in the door path
operated the door protection switch, for example a safe ray (not
shown) which senses interruption of a beam of radiant energy across
the door path, to produce a true signal or short pulse, SR. At the
moment represented, the door is partially closed since the door
open limit, the "A limit," is true, and it has not fully closed
since the door close limit, the "B limit," also is true. The
remainder of the sequenced signals for the car-to-controller
transmitter cycle has not been shown.
FIGS. 5 and 6 are schematic representations of the transmitter
section 111 and receiver section 112 of FIG. 2. In FIG. 5, 141
represents an inverter which converts a logic "1" at its input to a
logic "0" or a logic "0" at its input to a logic "1". Element 142
is typical of a NAND gate which has a "0" output when both inputs
are at "1" and a "1" output for any other combination of inputs.
Element 137 illustrates the symbol for a NAND gate in negative
logic.
Element 158 is typical of a NOR gate which has a "1" output when
both inputs are "0" and a "0" output for any other combination of
inputs. Element 161 is typical of the symbol for a NOR gate in
negative logic.
Element 169 is a NOR flip flop comprised of two NOR's each with the
output coupled to an input of the other. When both inputs 1 and 2,
are at "1" and both outputs, 3 and 4, are at "0". When the inputs
are of opposite signals then output 3 will be at the same as input
1. If both inputs are at "0," one output will be "1" and the other
will be "0" depending on which input switched to "0" first. When
input 1 switches to "0" first output 3 will be "1."
Element 131 is a typical multiplexer section which has eight input
lines 1 through 8, three count input lines A, B and C, and enable
input 9 and an output 10. When enable 9 is at "0" the signal on
output 10 is the opposite of the one selected input signal on lines
1 through 8. A combination of signals on the three count input
lines selects one of the inputs to be represented at the output.
For example, if all three count input lines A, B and C are at "0"
then input line 1 is selected and a "0" on line 1 will produce a
"1" at output 10. By providing a binary count of zero to seven in
sequence at the count input lines A, B and C input lines 1 to 8
will be read in sequence.
Element 143 is a typical 4-bit binary up counter with four output
lines A, B, C and D. Line 1 is a parallel enable input which when
provided with a "1" input produces a one bit count on the output
lines for each "1" pulse at the input shown connected to line 129.
A "0" on line 129 enables the counter and a "1" transfers the data
to the output lines. Leads 2 and 3 are a count enable which enables
the counter when they have a "1" input. Lead 4 produces a "1" only
if lead 3 is a "1" and all outputs are at "1". This allows the
counters to be used in series. A master reset input is connected to
line 128 and a "0" will clear all the outputs.
Element 153 is a binary to decimal decoder. A "0" on input line D
enables one of the four output lines 1 through 4. For example, if
lines A, B and C are at "0" output line 1 will be at "0" and the
other output lines will be at "1". If line A is changed to "1",
output line 2 is at "0" and all others are at "1". With inputs C
and D grounded, the binary signal on lines A and B determines which
output is enabled and thus which of multiplexer sections 131, 132,
133 or 134 is enabled.
Line driver 121 is utilized to transmit the coded signals of FIG.
4. Element 157 is a NAND gate and when all inputs are at "1" output
4 is at "0". A "0" on any input will produce a "1" at output 4.
Output 5 is an inverting output which will have the opposite signal
from that of output 4. Elements 166 and 167 are amplifiers to
maintain the proper signal level for transmission on data lines
113. Line 113-A is connected to the noninverting output of the line
driver and is supplied with a positive bias from a power source
through a resistor. Line 113-B is connected to the inverting output
of the line driver and is grounded through a resistor. These
resistors permit the line drivers of the local and remote
multiplexer to be connected to the same transmission line 113 and
to function as wired ORs as independent inputs to a common
output.
In FIG. 6 line receivers 122 receives the coded signals from data
lines 113. Element 199 is an amplifier which produces a "1" for a
"1" signal on the "+" input and a "0" signal on the "-" input and a
"0" for a "0" signal on the "+" input and a "1" signal on the "-"
input.
Element 204 is an 8-bit addressable latch. A combination of signals
on the inputs connected to lines 227, 228 and 229 select one of
eight output lines 126. If a "0" is present on the enable input E
the decoded signal from the line driver 122 will be stored on the
selected output line 126 corresponding to an input line to the then
effective multiplexer section and a line of the transmitter.
Element 211 is a NAND flip flop which has a "1" on each output when
the inputs are at "0". When the inputs have opposite signals output
3 will be the same as input 2 and output 4 will be the same as
input 1. When both inputs are at "1" one output will be at "1" and
the other at "0" depending on which input switched to "1" first.
When input 1 switches to "1" first output 3 will be "0".
Element 193 is a monostable multivibrator consisting of an OR gate,
a flip flop and a timing network. The OR gate has a regular input 1
and an inverting input 2 and its output is the input to the flip
flop. By placing a "1" on the clock input CD the signal at the OR
output will determine the Q and Q outputs for a time period
determined by the timing network of resistor 194 and capacitor 195.
A "0" from the OR output produces a "0" at Q and a "1" from the OR
output produces a "1" at Q.
In FIGS. 5 and 6 the terminals of various devices have been
numbered or lettered and each device has a reference number. When
referring to a device terminal it will be set forth as a suffix to
the reference number separated therefrom by a dash, such as
terminal 1 of NAND 137 in FIG. 5 designated as 137-1.
The general scheme of operation of the transmitter section 111 as
shown in FIG. 5 is to sequentially consider or read each input 114
through sections 131 to 134 of the multiplexer 115 using the C and
D outputs of counter section 143 and the A output of counter
section 144 to enable, by binary code to the A, B and C inputs of
multiplexer sections 131 to 134, a corresponding one of each of the
inputs 1 to 8 of the multiplexer sections 131 to 134. Counter
section 144 also individually enables the multiplexer sections 131
to 134 by binary coded signals from its B and C outputs to the A
and B inputs of binary-to-decimal decoder 153. The A and B outputs
of counter section 143 control the logic which generates a wide
pulse for a "false" state at the then effective input lead 114 and
a narrow pulse for a "true" state.
Counter 117 is reset when the receiver section 112 of its
multiplexer station has received a full multiplex signal cycle
train of signal words. This is indicated as a master reset signal
on lead 147 from the receiver section 112. The clock 116 driving
counter 117 is free running until inhibited by an indication of the
completion of a multiplex signal cycle transmission to satisfy gate
135. When gate 135 is satisfied it also enables the multiplexer
receiver section of its multiplex station by signals on leads 173
and 174.
A multiplexer signal cycle is transmitted as thirty-two words each
comprising four pulse intervals of clock 116. A true word is made
up of contiguous pulses of logic 0-1-0-0 while a false word is
contiguous pulses of logic 0-1-1-0. These words are transmitted to
transmission line 113 from line driver 121 and are encoded by NAND
163 for a "true" word and NAND 165 for a "false" word. Flip flop
169 is set irrevocably during the initial read portion of a word
interval by the then current "true" or "false" state on the input
lead 114 being read by the multiplexer 115. This enables NAND 163
and disables NAND 165 for a "true" signal, and enables NAND 165 and
disables NAND 163 for a "false" signal. NAND 163 can be gated only
during the second counter pulse interval of each word interval by
gating NOR 161 when counter section 143 issues a "1" on its A
output and a "0" on its B output. NAND 165 can be gated only during
the second and third counter pulses. During the first pulse NOR 158
receives "0" from both the A and B counter outputs and inhibits
NAND 165. During the fourth pulse NAND 159 receives a "1" from both
the A and B counter outputs and inhibits NAND 165. During the
second and third pulses outputs A and B of counter 143 are in
opposite states to enable NAND 165 from NOR 158 and NAND 159.
Flip flop 169 is set at the beginning of each word interval during
the period the counter section 143 outputs A and B are both "0" as
signified by NOR 158 to NOR 171 to make NOR 171 responsive to the
signal from NAND 156 and thus the state of the effective
multiplexer input 114. It is reset at the time a "0" appears from
NAND 159 when both the A and B outputs of counter section 143 are
at "1". Any change of the signal at input 114 to NAND 156 has no
effect after the first clock pulse interval of the word interval
since NOR 171 is inhibited and cannot change the state of flip flop
169.
FIG. 5 is a schematic representation of transmitter section 111 of
FIG. 2 for each multiplex unit. Inputs from various control devices
appear on input lines 114 in the form of a "1" or a "0". A start
signal on line 118 enables ring counter 117 to receive a train of
pulses from clock 116. The number of pulses counted is presented in
binary form to word coder 158, 159 and 161, the reader-multiplexer
sections 131, 132, 133 and 134, and the binary to decimal decoder
119. Decoder 119 enables each of the multiplexer sections 131 to
134 of 115 in order. As each multiplexer section is enabled the
binary count enables each input line 114 in sequence. The signals
on the input lines as to an A unit are read and are coded and
transmitted over date lines 113 by line driver 121 to the receiver
section of another multiplex unit, the B unit. After the last input
signal has been sent by the A unit, signals on lines 173 and 174
activate receiver sections 112 of its multiplexer unit, the A unit,
to receive signals from the transmitter of the other multiplex
unit, the B unit. When receiver section 112 of the A unit has
completed receiving, it produces a signal on line 147 to enable the
transmitter section 111 of its multiplexer unit, the A unit. Lines
128 and 129 allow external resetting of all ring counter outputs
and injection of clock pulses for test purposes.
The input lines 114 are separated into four groups of eight lines
each which are the inputs to multiplexer sections 131, 132, 133 and
134. The particular multiplexer section is selected by the binary
to decimal decoder 119 while the line is selected by a signal from
the ring counter 117.
The clock 116 consists of NAND 136, NAND 137, resistor 138 and
capacitor 139. During the counting cycle of ring counter 117 at
least one of the inputs to NAND 135 will be "0" until the maximum
count is reached. This means that the output of NAND 135 is "1"
until all inputs become "1." The output "1" is changed to "0" by
inverter 141 and appears as the input at lead 137-1 of the clock
116. This "0" produces a "1" on output lead 137-3 of NAND 137 and
since the input leads 136-1, 2, 3, 4 of NAND 136 are tied together,
the output lead 136-5 is at "0." This output is fed back to the
input of NAND 136 by resistor 138 with a time delay caused by
capacitor 139.
With output lead 136-5 at "0" capacitor 139 discharges through
resistor 138 since output 137-3 cannot provide enough current to
keep it from doing so. Output 136-5 then changes to "1" and
capacitor 139 charges up again. The cycle repeats itself providing
a pulse train at a rate determined by the values of the resistor
138 and the capacitor 139.
The pulse train appears at input lead 142-2 of NAND 142 which in
turn provides the input to the clock pulse lead of 4-bit binary up
counters 143 and 144 which comprise ring counter 117. Line 118
provides a "1" on input lead 142-1 through resistor 145 and the
positive power supply. If the input to line 118 is grounded, for
example through an external relay, the resultant "0" signal on
input lead 142-1 will cause the output 142-3 to always be "1."
Therefore, the pulse train from the clock 116 will not be passed to
the ring counter 117. When the ground is removed, the output will
be "1" when lead 142-2 is "0" and "0" when lead 142-2 is "1."
During the time a "0" is present at the clock pulse inputs for
counters 143 and 144, data can enter and it is transferred to the
outputs when the clock pulse goes to "0". Leads 143-1 and 144-1 are
the parallel enable inputs and when they are connected to the
positive power supply as shown there will be a one bit shift in the
counter output for each clock pulse input.
The counters 143 and 144 also have a count enable which permits the
clock pulse to activate the counter only if leads 2 and 3 are both
at "1." On counter 143 the leads 143-2 and 143-3 are both connected
to the positive power supply so counter 143 will be counting all
the time. Counter 144 however has leads 144-2 and 144-3 connected
to lead 143-4. Lead 143-4 is only "1" when lead 143-3 is "1" and
all output leads A, B, C and D are "1." Therefore, counter 144 will
not count until counter 143 has registered 15 counts. The next
count changes the front output of counter 144 to "1" and sets all
the outputs of counter 143 to "0". This puts a "0" on lead 143-4
and counter 144 will not register another count until counter 143
has registered 15 more counts. When 127 pulses have been registered
all the counter outputs will be at "1" and the output NAND 135 will
change from "1" to "0". The input 137-1 will be "1" and the "1"
from output 136-5 is the input to 137-2 producing a "0" at 137-3
and stopping the clock. The clock will only start when the ring
counter 117 is reset.
Line 118 is also connected to input lead 146-1 of NAND 146 which
provides the master reset signal to the counters 143 and 144. A "0"
at the master reset clears all the outputs of the counters. Again,
if line 118 is grounded NAND 146 can only provide a "1" so the
removal of the ground enables NAND 146. The signal to reset the
counters is applied to line 147 from the receiver section 112 as a
"0" and is changed to a "1" by inverter 148. Now input leads 146-1
and 146-2 both are at "1" which produces a "0" output on lead 146-3
to reset the counters. This reset occurs when the receiver section
112 has completed receiving its data and the transmitter section
111 is ready to begin a transmission.
Lines 149, 151 and 152 are the "4", "8" and "16" count outputs from
the counters 143 and 144. These outputs are used to control the
selection of input lines 114, eight of which go to each multiplexer
section. Using multiplexer section 131 as representative of the
four shown, it has inputs 131-1 through 131-8, enable input 131-9
and output 131-10. When the enable input 131-9 is at "0" the output
131-10 represents the inverse of the input signal on the lead 114
selected for reading by the combination of signals on output lines
149, 151 and 152. For example, when the output lines 153-1 to 153-4
are all at "0", output 131-10 is "1" if the input line 114 selected
is "0."
The ring counter 117 changes output when a "1" from 142-3 or 129
appears at the clock pulse input. Since the output of clock 116 is
"1" when the ring counter is reset the ring counter will not record
a count until the second "1" is produced by the clock. Therefore,
during the four pulses of each word interval as the counter goes
from binary zero to a binary three lines 149, 151 and 152 remain at
"0." This combination of inputs to the A, B and C terminals of the
multiplexer sections selects the first input line for each
multiplexer section. During the next four pulses line 149 and the A
inputs are "1" and the second line in each multiplexer section is
selected for reading. As the ring counter progresses, each input
line is selected in turn and is held for four counts until 32 word
intervals have been generated. Therefore, during the 128 clock
pulses required for one cycle of the ring counter, the input lines
can be selected four times. However, each multiplexer section has
an enable input that receives signals from a binary to decimal
decoder 153. The sequencing of the decoder limits each line to one
reading during a ring counter cycle.
The "32" and "64" count outputs from the ring counter are inputs
153-A and 153-B. Inputs 153-C and 153-D of the decoder are tied to
ground so that a "0" is present. During the first thirty-two pulses
all the inputs to decoder 153 are at "0" which puts a "0" on enable
input 131-9 and a "1" on all the others. Therefore, multiplexer
section 131 reads all of its input lines in order. During the next
32 counts, input 153-A is at "1" while the others remain at "0"
which puts a "0" on enable input 132-9 and a "1" on all the other
enable inputs. After 128 pulses all four multiplexer sections have
read each of their eight input lines one time.
The outputs of the multiplexer sections are the inputs to NAND 156.
As long as one of the inputs is "0" the output is held at "1" and
it only goes to "0" when all inputs are "1". Since the output of a
multiplexer section is "1" when it is not enabled three of the
inputs to NAND 156 will always be "1." The fourth input will be the
output of the multiplexer section that is enabled which is the
inverse of the input line 114 that is selected for reading at that
moment. Therefore, if during the first four clock pulses input line
131-1 is at "1," output 131-10 will be at "0" making the output of
NAND 156 "1". Thus the signal on the selected one of input lines
114 will appear at the output of NAND 156.
The line driver 121 has three inputs which are connected to NAND
157. Input 157-3 receives the output from NAND 135 which is "0"
only after the last pulse in the ring counter cycle thus the line
driver is enabled during a transmission cycle and inhibited upon
termination of that cycle until the next transmission cycle. The
other two inputs receive signals from the signal word encoding or
defining logic network which combines the output signal from NAND
156 and the word defining "1" and "2" count outputs from the ring
counter. The "1" and "2" count outputs are the inputs to NOR 158,
NAND 159 and NOR 161. Before the first pulse in the ring counter
cycle, all ring counter outputs are at "1." A reset pulse on line
147 at the beginning of a transmission resets the ring counter
outputs to "0". This is the "zero" pulse interval which puts leads
158-1, 158-2, 159-1, 159-2, 161-1 at "0" and lead 161-2 at "1"
since the "0" is changed by inverter 162.
Each word interval of four counts is defined by a first clock
interval in which the A and B outputs of counter 143 are logic "0",
a second interval in which A is at "1" and B is at "0", a third
interval in which A is at "0" and "B" is at 1 and a fourth interval
in which A and B are both "1." Thus the first word in a transmitted
signal sequence is encoded during binary count zero through three,
the second word during binary count four through seven, the third
word is encoded during binary count eight through eleven, etc.
The initial logic "0" of each encoded word is developed on the
non-inverting output, the A line of the transmission line 113, by
coincident "1"s to the input of NAND 157. With 143-A and 143-B both
"0", the "1" and "0" input to NOR 161 produces a "0" output on lead
161-3 which is the input lead 163-2 of NAND 163. The "0" at NAND
163 makes output lead 163-3 go to "1" which is the input at lead
157-2 of the line driver. The "0" inputs to NOR 158 produce a "1"
output which is changed to a "0" by inverter 164 and is the input
for lead 165-1 of NAND 165. This produces a "1" output at 165-4
which is input 157-1. Therefore, all inputs to the line driver are
a "1" producing a "1" from inverting output 157-5 to lead 113-B and
a "0" from output 157-4 through amplifiers 167 and 166 thereby
transmitting a "0" on data line 113-A.
In order to avoid transmission of signal transistions which occur
during the transmission of a word, transmitter 11 is provided with
a latch for the signal from the active input lead 114 which is set
during the initial clock pulse interval of each word is maintained
through the second and third pulses, and is reset in the fourth
clock pulse interval of that word. Flip flop 169 provides that
latch by being set to issue a "1" at 169-4 and a "0" at 169-3 for a
"true" input at the lead 114 being read and being set to issue a
"1" at 169-3 and a "0" at 169-4 for a "false" input.
In the set state flip flop 169 has 169-1 at "1" and 169-2 at "0" so
that 169-3 is "0" and 169-4 is "1". The initial pulse interval of
each word imposes "0" on 158-1, 158-2, 159-1 and 159-2 so that
158-3 and 159-3 are "1." Inverter 168 makes 169-1 "0" so that the
set flip flop is enabled for transfer of state if a "1" is applied
at 169-2. Inverter 164 makes 171-2 "0" so that NOR 171 is
responsive to invert the signal from NAND 156 and the active input
114. If during the initial pulse interval NAND 156 issues a "1" for
a "true" signal, 169-2 remains "0" and the latch holds 169-4 "1"
and 169-3 "0." If NAND 156 issues a "0" for a "false" signal 171-3
and 169-2 transfer to a "1" and the latch changes 169-4 to "0" and
169-3 to "1."
During the second and third pulse intervals of the word encoding
period NOR 158 is inhibited by a "1" on lead 158-2 and 158-1
respectively, so that 158-3 holds a "0" to hold 171-2 "1" to hold
169-2 "0" in the face of any change on 171-1. Thus flip flop 169
retains the state established during the initial interval over the
second and third intervals.
Reset of the flip flop during the fourth pulse interval of each
word encoding period is accomplished through NAND 159 and inverter
168. At the time 143-A and 143-B are "1", 159-3 is "0" and 169-1 is
"1". 158-3 is "0" so that 171-2 is"1"and 171-3 to 169-2 is "0".This
insures 169-3 is "0" and 169-4 is "1."
Assuming that input line 114 to 131-1 has a "0" input, the output
of NAND 156 will be "0" during the time the ring counter counts the
"zero" pulse interval of the word cycle. The "0" output from
inverter 164 to input 171-2 enables NOR 171 and the "0" on input
171-1 produces a "1" at output 171-3. When the "one" pulse interval
is counted, input 158-2 becomes "1" changing outputs 158-3 to "0"
and changing input 171-2 to "1". The "1" on input 171-2 will
produce a "0" at output 171-3. The change of state of output 171-3
is delayed by capacitor 172. Therefore, the input signal on input
line 131-1 sets flip flop 169 during the "one" pulse interval. Any
change in the input signal on line 131-1 after the "one" pulse
interval is counted will not be transmitted until the next
transmission cycle of transmitter section 111 is initiated.
The "one" pulse interval also changes input 165-1 to "1". Although
input 159-2 changes to "1", the output 159-3 remains at "1" which
is the input at 165-2. This "1" is changed to "0" by inverter 168
which supplies the signal to lead 169-1 of flip flop 169. The "1"
output from 171-3 changes to "0", but is delayed by capacitor 172.
With a "0" on lead 169-1 and a "1" on lead 169-2, output lead 169-3
is at "1" and lead 169-4 is at "0." The change on lead 169-2 does
not produce a change in either output of flip flop 169.
The "1" on lead 169-3 is the input on lead 165-3 making all inputs
to 165 "1" and the output 165-4 a "0". This produces a "0" on
output 157-5 and a "1" on output 157-4. Therefore, at pulse two a
"1" pulse appears on data line 113-A.
At pulse three the input leads to NOR 158, NAND 159 and NOR 161
reverse polarity which does not change their outputs and
consequently the "1" pulse remains on data lines 113 during the
binary two count. On pulse four both inputs to NAND 159 are at "1"
so output lead 159-3 become "0" changing the output of NAND 165 to
"1". Inputs 157-2 and 157-3 remain at "1" so the output lead 157-5
changes to "1" and output lead 157-4 changes to "0" putting a "0"
on data lines 113. During the four count period, pulses one through
four, the data lines were "0" for pulse one, "1" for two pulses,
and "0" for the last pulse producing a signal representing a "0" on
the input line.
The "0" on output lead 159-3 during the fourth pulse interval is
changed to a "1" by inverter 168. The "1" and "0" inputs to 169-1
and 169-2 produce a change of state in flip flop 169 whereby output
lead 169-3 is at "0" and output lead 169-4 is at "0". This is the
reset of flip flop 169.
On pulse five (binary count four) input line 114 at terminal 131-2
is selected. Assuming a "1" signal is present, the output of NAND
156 is "1" which is the input to NOR 171. During pulses five to
eight the inputs to NOR 158,NAND 159 and NOR 161, will change as
was detailed above. The outputs of flip flop 69 will remain at "0"
for 169-3 and at "1" for 169-4. However, at pulse six (the second
pulse interval of this word and binary count five) when input lead
163-2 is in "1" the input lead 163-1 is also "1" producing a "0"
output at lead 163-3 which changes output lead 157-5 to "0" and
output lead 157-4 to "1." On pulse seven lead 163-2 changes back to
"0", output lead 163-3 goes to "1" and the outputs of NAND 157
switch placing a "0" on data lines 113 which remains there during
pulse eight. Therefore, during the four count word encoding period,
pulses five through eight, the data lines were "0" for one count,
"1" for one count and the "0" for two counts producing a signal
representing a "1" on the input line and the ring counter has a
binary seven output.
FIG. 6 is a schematic representation of the receiver section 112.
Coded signals from a transmitter section are received on data lines
113 by line receiver 122. Ring counter 123 produces a binary count
which is utilized by binary to decimal decoder 124 to select 8-bit
latch sections 204, 205, 206 and 207 of latch 125 in order. The
binary count also enables each output line of latch 125 in sequence
corresponding to the reading sequence of inputs 114 at the opposite
station so that the coded signals are stored on the output lines
126 as the same signals on input lines 114.
Each word transmitted to the line receivers 122 clocks the ring
counter 123 to selectively enable the latches or signal storage
means and establish the decoded signal on its individual output
terminal 126. Decoding is accomplished by time synchronism of the
state of the word signal as high or low during the third pulse
interval defined by the clock 116 of the transmitter 111 from which
signals are being received. A timer enables the latches 204, 205,
206 and 207 by means of a signal imposed on the enable input E from
gates 222, 223, 224 and 225 which are gated only during the third
pulse interval of each word. This selective gating is accomplished
by a timer 212 defining an interval greater than one pulse interval
and less than two pulse intervals of the transmitter clock 116 of
the remote multiplex transmitter. Such interval is initiated on the
rising signal of the second pulse interval of the word so that it
expires during the third pulse interval. When it expires it issues
a clocking signal to counter 123 and an enabling signal to the
latches to permit the active latch to respond to the then high or
low signal representing respectively a "false" or "true" signal as
decoded. Thus counter 123 is responsive to thirty-two steps in each
cycle as imposed by the thirty-two word intervals of a multiplex
signal sequence from the transmitter.
Receiver 112 of FIG. 6 responds to a train of words transmitted
from a remote station transmitter corresponding to transmitter
section 111 of the multiplexer unit discussed above. When the
transmitter section 111 of the local station has transmitted a full
multiplex signal cycle train of signal words, a master reset signal
on line 174 resets the counter sections 183 and 184. Each word of
the signal cycle being received begins with a "0" pulse which
produces a "1" from NAND 203. The "1" sets flip flop 211, which in
turn resets monostable multivibrator 212. Monostable multivibrator
212 is then set by the second pulse of each word which is always a
"1" and a timing interval one and one-half of the pulse interval of
the transmitter clock 116 of the remote station is produced. At the
end of the timing interval, the Q output returns to "0" which
enables NAND gates 222 to 225. The D output of counter section 183
and the A output of counter section 184 enable, by binary code to
the A and B inputs of binary to decimal decoder 231, the latch
sections 204 to 207. The A, B and C outputs of counter section 183
enable, by binary code on lines 227, 228 and 229,a corresponding
one of each of the outputs 1 to 8 of the latch sections 204 to 207.
The signal applied to the selected output is that present during
the third transmitter clock pulse interval of each word from lines
113 as indicated by NAND 203.
Completion of the reception of a multiplexer signal cycle gates
NAND 185 to inhibit further reception of signals in latch 125 by
changing the state of NAND 203 and through NAND 192 resets failure
timer 193 while gating NOR 186. This indicates reception is
complete to reset the local multiplexer transmitter section 111 on
line 147.
While normal operation involves the alternate advance of a local
transmitter 111 through its predetermined order of reading
functions to send a multiplexed signal sequence to the remote
receiver to which it is coupled by transmission line 133, followed
immediately by a signal reception sequence by the local receiver
112 from the remote transmitter,it is possible, particularly during
start up of the system,that the transmitter is out of synchronism
with the receiver to which it is sending signals. Such absence of
synchronism causes the system to lock up since the failure to
produce a coincidence of an indication of a completed local
transmission utilizing one hundred twenty-eight pulses through gate
135 of FIG. 5 and the indication of completion of local reception
of 32 word periods through gate 185 of FIG. 6 fails to gate NOR 186
to issue a transmitter reset signal on lead 147. In case of a
failure to reset a resynchronizing sequence is provided.
Resynchronization is instituted by failure timer 193 which
initiates a timing interval at the beginning of a receiving
sequence and is reset upon completion of the receiving sequence. If
timer 193 is not reset it ultimately times out and starts a new
transmission sequence. In general, the two station multiplex system
of this invention employs like transmitters and receivers at each
station. However, in the case of a failure timer only one timer is
required. Hence, the failure controls 200 within the dashed
boundries of FIG. 6 need be included in only one receiver, as at
the controller station 39, and the car top station 37 can be
considered to have each of switches 235, 236 and 237 open and each
of switches 238 and 239 transferred from their illustrated position
to the alternative position to couple inverter 188 directly to
reset lead 147 through lead 240.
When all the output lines on ring counter 117 of transmitter
section 111 are at "1", the output of NAND 135 is changed from "1"
to "0" which is inverted to a "1" on lead 174 by inverter 141 and
is again inverted to a "0" by inverter 182 and resets counter 123
of the local receiver. The switch in signals on line 173 produces a
"1" from inverter 141 on line 174. Capacitor 181 passes a short "1"
pulse which is converted to a "0" pulse by inverter 182. This "0"
pulse is transmitted to the master reset input of the 4-bit binary
up counters 183 and 184 comprising ring counter 123. The ring
counter is reset with all outputs becoming "0." The outputs of the
ring counter are also inputs to NAND 185 which produces a "1". That
"1" initiates failure timer 193 timing interval as will be
described. If the counter 123 reaches a count of thirty-two within
the interval of timer 193, completion of a signal reception
sequence is indicated by transfer to a "0" from NAND 185 to NAND
192 to reset timer 193 and the application of a "0" to NOR 186 at
186-1 which causes a reset of the transmitter counter to begin a
new transmission sequence. Lead 186-2 has a "0" signal from line
173 as its input producing "0" output until 186-1 goes "0." Since
line 186-1 has been at "1" a "0" on output lead 186-3 had no
resetting effect until 181-1 changing "0" made 181-3 "1." This
signal shift makes capacitor 187 and the inputs to NAND 188 "1".
The output of NAND 188 is "0." If failure circuit 200 is
disconnected, the "0" is applied directly to lead 147 as a reset
signal. With failure circuit effective the "0" is changed to "1" by
inverter 189 and is the input to lead 191-2 of NOR 191 to develop a
"0" at output 191-3 which resets the counters in the transmitter
section 111 through line 147.
The "1" from NAND 185 is also present at input 192-2 of NAND 192.
The other input 192-1 is connected to line 174 and carries the
inverse of the signal on line 173, a "1". The "1" inputs produce a
"0" output at 192-3 which is applied to the inverting input 193-2
of monostable multivibrator 193.
While the "0" is imposed on 193-2 timer 193 times an interval
determined by the time constant of the resistor 194 and capacitor
195, chosen to be in excess of a multiplex signal sequence interval
from the transmitter 111. If a full signal sequence is received to
transfer 192-2 to "0", the "1" at 193-2 enables input 193-1 to
become effective as a reset for failure timer 193. Input 193-1 is
connected to a clock formed from resistor 196, capacitor 197 and
NAND 198 which generates a pulse train at a frequency greater than
the timing period of monostable multivibrator 193 that resets the
multivibrator to prevent it from timing out.
The "1" on line 174 also enables the line receiver 122 to generate
pulses which correspond to those transmitted on data lines 113 from
the remote transmitter 111. A "1" from amplifier 199 on input 201-2
of NAND 201 and the "1" on input 201-1 produces a "0" as the input
to inverter 202. Therefore, the output of the inverter is the same
as the input to the line receiver 122 at non-inverting lead 113-A.
The "1" from NAND 185 indicating the reception sequence is
incomplete enables NAND 203 so that its output corresponds to the
output of the line receiver. The four pulse false signal word on
data line 113 which consisted of a "0" pulse, two "1" pulses and a
"0" pulse is now a "1" pulse, two "0" pulses and a "1" pulse at
output 203-3. This signal is the to the 8-bit addressable latch
sections 204, 205, 206 and 207.
Using the false signal as an example, the first "1" pulse is
changed to a "0" by inverter 208 and is the input at 209-1 of NAND
209. This produces a "1" at input 211-1 of NAND flip flop 211.
Output lead 211-4 will be at "1" if input lead 211-2 is at "0" or
it will not have changed from its previous state if 211-2 is at
"1". Assuming for the moment that input 211-2 is at "1" and the
previous state of output 211-4 was "1", monostable multivibrator
212 has a pulse train at input 212-2 of a frequency which prevents
it from timing out and keeps the Q output at "1". This "1" is the
input to inverters 213 and 214 which produce a "0" output from NAND
215. NAND 216 has all its inputs tied together so there is a "0" at
input 217-2 of NAND 217. This produces a "1" at input 211-2 which
supports the first part of the above assumption.
Pulse two from NAND 203 is a "0" which is changed to a "1" by
inverter 208 placing a "1" on both inputs to NAND 209. The output
of NAND 209 changes to "0". Input 211-2 remains at "1" so output
211-4 becomes "0." This "0" at inverting input 212-1 starts the
timing of the multivibrator 212 which is completed in the middle of
the third pulse. At that time the Q output switches from "1" to
"0". This "0" is applied at 218-1 of NOR 218. The output of NOR 218
is "0" unless both inputs are "0". The "0" is changed to a "1" by
inverter 219 but is delayed by capacitor 21 so that momentarily
both inputs are "0" and a "1" pulse results. This pulse enables
NAND 222, 223, 224 and 225 so that the correct latch is addressed
and the third pulse is read.
If the signal is high on line 113-A during the third pulse interval
of the word currently being transmitted, the signal 203-3 to the
latches 204 to 207 is low and conversely if it is low at 113-A the
signal to the latches is high at 203-3. The latches store the
signal so that the memory and its output 126 addressed at the
moment is set in a low state representing the "false" signal at the
then active transmitter input 114 or in a high state representing
the "true" state at active input 114 if that be the case. Thus, as
shown in FIG. 4 if the door open signal DO is the transmitted word
and is "false",the high during the third pulse interval results in
a low on the DO output 126, which is 204-1 in the example.
Similarly, a "true" safe ray signal SR has a low third pulse
interval for its word as shown in FIG. 4 and would cause its output
lead 126, 204-3, to be high.
The change of output Q of 212 to a "0" also is applied to inverters
213 and 214. Capacitor 226 provides a delay. After the delay, both
inputs of NAND 215 are "1" and produce a "0" causing the output of
NAND 216 to change to "1". This "1" provides the clock pulse on
lead 180 to counters 183 and 184 of ring counter 123. Initially
outputs A, B, C and D of 183 and A of 184 are all "0". The first
clock pulse on 180 produces a binary "1" count as a "1" on output
183-A and lead 227, while leads 228, the "2" lead, and 229, the "4"
lead, remain at "0". These leads provide the address to the latch
sections. The "1" on lead 227 is delayed until after the third
pulse is read and stored at output 204-1 while the address lines
are at "0". The delay is provided by capacitor 220 which prevents
NAND 216 from changing state for a predetermined time. When the
delay is over lead 227 goes to "1" and output line 204-2 is
selected for storage of the second bit of information. Thus, the
latch is addressed prior to being enabled from gate 222, 223, 224
or 225 and for subsequent words in the multiplex signal sequence
that address is established during the terminal portion of the
preceding word period.
The "8" and "16" count outputs from the ring counter 123 are inputs
231-A and 231-B of binary to decimal decoder 231. Inputs 231-C and
231-D are tied to ground so that they are always "0." During the
first eight pulses all the inputs to decoder 231 are at "0" and the
zero count output puts a "0" on inverter 234 to produce a "1" at
input 222-1 of NAND 222. All other count outputs of decoder 231 are
at "1" thereby inhibiting gates 223, 224 and 225. Since NAND 222 is
enabled by a "1" on input 222-2 a "0" is applied to the E input of
204 which enables latch section 204. As a result, the "0" which was
the third pulse from the transmitter is placed on the first output
line of latch 204. In this way the latches are set in the same
order as the input signals on lines 114 were processed by the
transmitter.
The fourth and last pulse in the group comprising the signal word
in the multiplex signal cycle is a "0" which is a "1" at 203-3.
This "1" is changed to a "0" by inverter 208 which produces a "1"
output from NAND 209. Since the Q output of multivibrator 212 is
still "0", input 217-2 remains at "1" and, with the "1" on input
217-1, produces a "0" on output 217-3. The "1" and "0" inputs to
NAND flip flop 211 change output 211-4 to "1." This allows the
pulse train at input 212-2 to change the Q output to "1" where it
will remain until changed by the next group of four pulses.
The "1" at Q of 212 for the reset timer is the input to inverters
213 and 214 and produces a "0" at input 215-1 changing the output
to "1". The output of NAND 216 becomes "0" which produces a "1"
from NAND 217 holding NAND flip flop 211 with a "1" at output 211-4
which supports the second part of the previous assumption.
The next group of four pulses will advance ring counter 123 and the
information will be stored on the second output line of latch
section 204. When the last group of four pulses is received all the
outputs of the ring counter will be "1" changing the output of NAND
185 to "0" and producing a "0" on line 147 through NOR 186
inverters 188 and 189 and NOR 191 to reset the local multiplexer
transmitter and start its clock. Failure timer 193 is reset by the
"0" at 192-2 to issue a resetting "1" to 193-2 so that Q remains
"0" to 191-1. If the receiver fails to respond to its full
multiplexer signal sequence by failing to advance its counter 123
through a count of thirty-two, NAND gate 185 would not be satisfied
and would continue to issue a "1" to NAND 192 at 192-2. This would
maintain 192 gated and continue the timing of timer 193. At the end
of the timer interval output Q of timer 193 would shift to "1"
causing NOR 191 to issue a "0" at 191-3 to lead 147 thereby
restarting the local transmitter.
Synchronization of the transmitter of each station with the
receiver of its opposite station is normally maintained by starting
transmission from transmitter A to receiver B simultaneously with
the start of reception by receiver B. At the end of transmitter A's
transmission it starts receiver A by resetting counter 123,
enabling line receiver 122, starting timer 193 through NAND 192 and
enabling its reset NOR 186. If at that time receiver B has
completed its reception it gates its NOR 186 to start transmitter B
by resetting its counter 117 to enable its line driver 121 and
clock 116. This alternate transmission and reception at each
station continues if the termination of transmission from one
station coincides with the termination of reception by the
other.
At times the transmission and reception can be out of
synchronization. That is a door open signal DO might be sent as a
first word and received as a safe edge signal SE, the second word
of the multiplex signal cycle. Such loss of synchronization is
corrected by the interlocks which start local reception when a full
word count of local transmission is completed and which prevent
local transmission until a full word count of local reception or
until expiration of a delay sufficient to assure that the remote
station transmission has been completed. This delay may be several
times a normal multiplex signal sequence cycle, the thirty-two
words in the example.
Assume for illustration that on starting the system both
transmitters begin to transmit and that multiplexer 39 (the unit
having failure timer 193) is ahead of the other unit, unit 37. When
39 completes transmission it starts its receiver which receives the
residue of the signal from 37. Receiver 39 continues to receive as
transmitter 37 completes its transmission. Receiver 37 is set to
receive but transmitter 39 is not transmitting. Since transmitter
37 has stopped transmitting and receiver 39 received only the
terminal portion of its transmission the system is stalled. Timer
193 times out and starts 39 transmitting. At this time receiver 37
has been conditioned to receive and, therefore, starts receiving in
synchronism with transmitter 39. Thereafter, synchronism is
maintained since transmitter 39 and receiver 37 complete their
cycles simultaneously and start their receiver and transmitter
respectively at the same time.
As another illustration,assume that both receivers started
partially through a receiving cycle. Neither transmitter would
transmit and timer 193 would time out in due course. Transmitter 39
would be started and would fill receiver 37 so that as transmitter
39 continued transmitting, transmitter 37 would start. We thus
would have the conditions first mentioned and that sequence of
events would proceed until a second timing out of failure timer 193
would place the stations in synchronism.
Other conditions which might exist where the stations were out of
synchronism include both transmitting with transmitter 37 ahead of
transmitter 39; transmitter 39 ahead of receiver 37; transmitter 39
behind receiver 37; receiver 39 ahead of transmitter 37; and
receiver 39 behind transmitter 37. In each instance the sequences
run to a time out of the failure timer and then run through the
preceding sequences to achieve synchronization.
In order to be compatible with existing elevator circuitry it may
be necessary to provide a buffer consisting of a voltage divider
and capacitor for each input line 114 to reduce the input voltage
from the signal applying switch associated therewith. Also, each
output line 126 may require a driver to raise the output voltage to
a level compatible with the circuits to be controlled by the output
signal. These are well-known techniques and do not form part of the
invention.
While specific circuit arrangements have been employed to
illustrate this invention, it is to be appreciated that other
circuits are within the skill of the art for achieving the
functions and interrelationships of this invention. For example,
the high and low signals transmitted could be high frequency and
low frequency signal bursts sequenced in the manner disclosed and
be decoded by high and low pass filters. Accordingly, the above
disclosure is to be read as illustrative and not in a limiting
sense.
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