U.S. patent number 3,766,559 [Application Number 05/190,843] was granted by the patent office on 1973-10-16 for adaptive processor for an rf antenna.
This patent grant is currently assigned to Harris-Intertype Corporation. Invention is credited to Wade E. Butcher, Jr., Robert J. Sims.
United States Patent |
3,766,559 |
Butcher, Jr. , et
al. |
October 16, 1973 |
**Please see images for:
( Certificate of Correction ) ** |
ADAPTIVE PROCESSOR FOR AN RF ANTENNA
Abstract
The elements of an RF antenna array are individually connected
to mixer circuits to produce a plurality of distinct IF signals.
Each signal is fed to a multi-tapped delay line which makes
available an increasingly delayed IF signal at subsequent points
therealong. The delayed signals are independently converted from an
analog to digital form so that they may be accepted by subfrequency
sampling input lines of a digital computer. A pilot signal can also
communicate with the computer or be generated internally to produce
a control signal for varying weights that control the amplitudes of
the IF signals transmitted from the tapped delay line. The weighted
signals are fed to a summing circuit which sums these signals to
form a system output. The system output is employed for achieving
null steering of the array by controlling system gain in the "look
direction" and rejecting noise.
Inventors: |
Butcher, Jr.; Wade E.
(Indialantic, FL), Sims; Robert J. (Red Bank, NJ) |
Assignee: |
Harris-Intertype Corporation
(Cleveland, OH)
|
Family
ID: |
22703024 |
Appl.
No.: |
05/190,843 |
Filed: |
October 20, 1971 |
Current U.S.
Class: |
342/368 |
Current CPC
Class: |
H04B
7/0845 (20130101); H04B 7/0891 (20130101) |
Current International
Class: |
H04B
7/08 (20060101); H04b 007/00 () |
Field of
Search: |
;343/1SA,1LE,854 |
References Cited
[Referenced By]
U.S. Patent Documents
Other References
R Widrow et al., Proc. of IEEE, Vol. 55, No. 12, Dec. 1967, pp.
2143-2159..
|
Primary Examiner: Borchelt; Benjamin A.
Assistant Examiner: Buczinski; S. C.
Claims
What is claimed is:
1. An adaptive processor for an antenna array comprising input
means for transmitting antenna signals between the array and the
processor, frequency translating means for translating the signals
to information in a subfrequency band, adjustable filter means for
filtering noise from the information, means for converting
unfiltered information to digital data and digital computer means
responsive to the data for generating control signals which adjust
the filter means to discriminate against noise whereby a least mean
square error of the filtered information is realized.
2. The circuitry set forth in claim 1 wherein the array includes a
plurality of antenna elements, and further wherein the adjustable
filter means comprises tapped delay means connected to an
information path associated with each element, tap off points
accessible at each delay means, adjustable weighting means
controlled by the controlled signals and respectively connected to
receive an information signal from each tap off point for adjusting
the amplitude of the respective information signal, and combiner
means receiving weighted information signals from said weighting
means for combining the signals to produce a filtered system output
signal.
3. The circuitry defined in claim 2 wherein the means for
converting the unfiltered information to digital data comprises an
analog to digital converter and means for connecting the converter
to sampled input terminals of the computer means.
4. The circuitry of claim 3 wherein the computer means includes
means for generating a software pilot signal having a frequency and
representing a direction, said pilot signal being combined by the
computer means with samples of data received at the input terminals
of the computer means to effect artifical insertion of the pilot
signal, and wherein said computer means further includes means for
constraining the array to have a main beam in the pilot signal
direction at a frequency corresponding to the pilot signal
frequency.
5. The circuitry of claim 4 wherein the computer means generates
the control signals in response to addition to the pilot signal to
the data samples, and wherein the circuitry further comprises means
for enabling the control signals to adjust the state of the
weighting means at an adjustment rate governed by the computer
means.
6. The circuitry defined in claim 5 wherein a plurality of the
weighting means are associated with each antenna element, the
plurality having output terminals connected to a first summing
means, and further wherein output terminals from all first summing
means associated with respective elements are connected to a second
summing means to generate a system output.
7. An antenna array adaptive processor for improving
signal-to-noise ratio in an unknown electromagnetic environment
comprising analog means for carrying a plurality of antenna element
signals along a plurality of preselected paths, filter means
interposed along each path for minimizing the mean square error of
the array signal as compared with a noiseless signal in a selected
look direction, and digital means responsive to the array signal
for adjusting the filter means in a manner effecting the minimizing
of the mean square error, said filter means comprising means for
delaying each antenna element signal a plurality of amounts to
produce a like plurality of delayed signals, amplitude adjustment
means respectively connected for adjusting the amplitude of each
delayed signal in response to said digital means and thereby
adjusting said filter means, and means for combining the outputs of
said amplitude adjustment means to produce the array signal.
8. The circuitry of claim 7 wherein means are provided along the
path for translating the frequency of the signal at array elements
to a subfrequency for permitting the digital means to operate
effectively at a subfrequency.
9. The circuitry set forth in claim 8 wherein the digital means
include means for converting the translated signal to a digital
form which is sampled at a subfrequency rate by the digital means,
the rate being governed by the digital means.
10. The circuitry as set forth in claim 9 wherein a pilot signal is
generated by the digital means, the digital means further including
means for linearly adding the pilot signal to the sampled signal to
constrain the array to have a main beam in the pilot direction and
at the pilot frequency.
11. An adaptive processor for an array of a plurality of element
antennas having a first electrical signal at each element antenna,
comprising a like plurality of input circuits respectively
receiving said first electrical signals and outputting respective
second signals accordingly; a like plurality of delay means each
receiving a respective one of said second signals as an input, each
of said delay means including circuit means having a plurality of
delay outputs for producing at each of said delay outputs a
differently delayed signal; a plurality of weighting means each
receiving a respective one of said delayed signals from a
respective one of said delay outputs for producing a weighted
signal, each of said weighting means being individually adjustable
by a control signal to change the amplitude of said weighted signal
compared with the amplitude of its corresponding delayed signal;
summing mean for adding together the weighted signals from the
weighting means to produce a final output signal; and control means
for producing said control signals including digital computer means
for independently simulating the effects upon said delayed signals
due to said weighting means and due to said summing means and
producing affected data accordingly, an input of said control means
being connected with said delay outputs of said delay means for
receiving input data depending upon said delayed signals.
12. An adaptive processor as defined in claim 11 and wherein each
of said circuit means comprises a plurality of delay devices
connected together in cascade for accumulating delays, the outputs
of each of said delay devices comprising said delay outputs.
13. An adaptive processor as defined in claim 11 and wherein said
affected data comprises data simulating said final output data and
said control means further comprises means for generating pilot
signal data representing the frequency and direction of a desired
signal that is expected to be received by the array, and wherein
said digital computer means comprises means utilizing said pilot
signal data and the simulated output data for computing and
producing said control signals.
14. An adaptive processor as defined in claim 13 and wherein said
means utilizing said pilot signal data comprises computation means
for computing values of said control signals to achieve least mean
square error between said pilot signal data and the simulated
output data.
15. An adaptive processor as defined in claim 13 and wherein said
means for generating pilot signal data comprises a digital computer
and software.
16. An adaptive processor as defined in claim 13 and wherein each
of said input circuits comprises a frequency down-converter for
producing said second signals at a lower frequency than said first
signals in response to said first signals.
17. An adaptive processor for an array of a plurality of element
antennas having a first electrical signal at each element antenna,
comprising a like plurality of input circuits respectively
receiving said first electrical signals and outputting respective
second signals accordingly; a like plurality of delay means each
receiving a respective one of said second signals as an input, each
of said delay means including circuit means having a plurality of
delay outputs for producing at each of said delay outputs a
differently delayed signal; a plurality of weighting means each
receiving a respective one of said delayed signals from a
respective one of said delay outputs for producing a weighted
signal, each of said weighting means being individually adjustable
by a control signal to establish an amplitude of said weighted
signal relative to amplitude of its corresponding delayed signal;
summing means for adding together the weighted signals from the
weighting means to produce a final output signal; and control means
receiving data at its input depending upon said second signals for
producing said control signals including digital means for
receiving and storing software data specifying a direction from
which a desired signal is to be received by the array, said digital
computer means further comprising algorithm computation means for
establishing values of said control signals to produce a final
output signal favoring signals received from said direction and
discriminating against signals received from other directions.
18. An adaptive processor as defined in claim 17 and wherein said
digital means further comprises means for receiving and storing
software data specifying a frequency of said desired signal to be
received by the array.
19. An adaptive processor as defined in claim 17 and wherein said
algorithm computation means comprises least mean square computation
means for establishing values of said control signals to produce a
final output signal whose mean square error for signals received
from said direction is minimum.
20. An adaptive processor as defined in claim 17 and wherein each
of said input circuits comprises a frequency down-converter for
producing said second signals at a lower frequency than said first
signals in response to said first signals.
21. An adaptive processor as defined in claim 17 and wherein said
control means is connected with said delay outputs of said delay
means for receiving input data depending upon said delayed
signals.
22. An adaptive processor as defined in claim 17 and wherein said
control means further includes digital computation means for
independently simulating the effects upon said delayed signals due
to said weighting means and due to said summing means and producing
data simulating said final output signal accordingly.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the elimination of interference in
an RF antenna array. More particularly, the invention is directed
to utilization of a digital computer in an adaptive processor that
controls the adaptation rate at a subfrequency below RF.
2. The Prior Art
Adaptive null steering methods for application to low frequency
signals are well known in the art. Typically, applications include
seismic and sonar information. The basic method includes an antenna
array with a transversal filter associated with each element of the
array. A transversal filter performs amplitude weighting of element
information that has been converted to the IF frequency band. By
adjusting the filter weights, desired interference rejection can be
obtained thereby maximizing the signal to noise ratio of an antenna
system. The basic problem with prior art systems for RF application
is that processing of signals is accomplished by analog techniques.
Although several authors have recognized the potential of using a
digital computer for adaptive processing, there has been a failure
by those skilled in the art to design a system where processing can
be accomplished by subfrequency sampling at frequencies lower than
RF, the sampling rate being computer controlled.
SUMMARY OF THE INVENTION
With the presently disclosed invention, the adaptation rate for
processing is independent of the signal frequencies and can be at
any arbitrarily slow rate, a fact which allows digital
implementation for RF signals. Thus, with the present invention,
subfrequency sampling can be used to perform adaptive processing of
antenna RF signals. Adaptive null steering for RF systems using
digital adaptation offers flexibility not herebefore obtainable
with an analog implementation.
Accordingly, a primary object of the present invention is to
achieve subfrequency sampling of antenna RF systems by an
adaptation rate much slower than the RF signal frequencies thus
permitting the use of a digital computer in the signal processing
loop.
A further object of the invention is to realize software generation
of a pilot signal that is employed in the computation of an output
control signal, derived from the computer, which sets the weight of
filter constraints in a processing loop. This software generation
and insertion into an array model allows the system to be trained
in the desired look direction while achieving interference
rejection. This approach does not disturb the actual system output
as would be the case of hardware insertion of a pilot signal. Thus,
there is provided a workable solution when the target frequency
estimate is in error. Such errors are likely in practice,
especially if the target is uncooperative.
A still further object of the invention is to ahcieve proper
control of the pilot signal amplitude and/or formation of an
initial beam rather than an initial isotropic pattern so that the
array gain can be constrained in the desired look direction, after
adaptation, to be close to the theoretical maximum.
The above-mentioned objects and advantages of the present invention
will be more clearly understood when considered in conjunction with
the accompanying drawings, in which:
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of the present system including a digital
computer serving as data processor for the system.
FIG. 2 - 5 illustrate array patterns for elements having various
filter configurations connected between the elements and a summing
circuit.
FIG. 6 is a block diagram of a basic adaptive element
configuration.
FIG. 7 is a block diagram of an adaptive element configuration
using a tapped delay line structure.
FIG. 8 is a block diagram of an adaptive element configuration
having automatic weight adjusting means.
PREFERRED EMBODIMENTS OF THE INVENTION
At the outset, it is appropriate to define what is meant by
adaptive signal processing in the context of the present invention.
An adaptive signal processor is a system that continually adjusts
its own parameters in the course of time to meet a particular
performance criterion. The present invention is most concerned with
the performance criterion of maximization of signal-to-interference
ratio. Inasmuch as interference is normally time-varying, some
adaptive mechanism is required to continually update filter
weights, employed in the present system, to meet the changing
interference pattern. In essence, the present system senses the
interference and automatically adjusts these filter weights to
their proper value through feedback loops.
The basic principles of design for an adaptive antenna system are
disclosed in an article by Widrow, et al. in the Proceedings of the
IEEE, vol. 55, No. 12, Dec., 1967. In the basic system disclosed in
this article, a scheme is presented for obtaining desired array
processing improvement in real time. The performance criterion used
is minimum mean square error. Statistics regarding the information
signal are assumed but there is no requirement of prior knowledge
or direct measurement of the noise field. The system is
automatically adjusted to perform an adaptive function according to
a simple iterative algorithm, and the procedure does not directly
involve the computation of any correlation coefficients or the
inversion of matrices, as was previously required by other systems.
The system of Widrow makes use of antenna input signals just once,
as they occur, in the adaptation process. Accordingly, no need
exists to store past input data; but there is a need to store the
processor adjustment values referred hereinafter as weights.
Reference is made to FIGS. 2 - 6 to demonstrate this basic system.
Referring particularly to FIG. 2 an example of a linear-array
receiving antenna is generally denoted by reference numeral 10. The
antenna consists of seven isotropic elements 12. These elements are
spaced along a straight line at equal distances of one-half wave
length where the wave length is a center frequency of the array.
The received signals are summed through equal length transmission
lines by an appropriate circuit 14 to produce an array output
signal 16. The directivity pattern 18 illustrates the relative
sensitivity of response to signals from various directions, and the
pattern illustrated in the figure is plotted in a plane over an
angular range of 180.degree.. It will be noticed that the pattern
is symmetric about the vertical zero angle line 20. The main lobe
22 of the pattern is centered about this vertical line. The largest
amplitude side lobe 24 has a maximum sensitivity which is typically
12.5 dB below the maximum main-lobe sensitivity. The pattern would
be different if it were plotted for a different frequency.
A similar array configuration is illustrated in FIG. 3. This
configuration is generally indicated by reference numeral 26 and as
will be noted, the output of each element 12 is delayed by an
associated suitable delay 28 which, for example, may be a strip of
transmission cable. Each delay is series connected between an
element and a common summing circuit 14. As a result, the
directivity pattern now has its main lobe 32 at an angle indicated
by 30.
The sensitivity of this configuration is maximum at the angle
indicated by 30 because signals received from a plane wave source
incident at this angle, and delayed by delays 28, are in phase with
one another and produce the maximum output signal.
Many different types of configuration for phased arrays exist.
Referring to FIG. 4, one such configuration 34 is shown where each
of the antenna element outputs is weighted by two weights 36 and 38
that are of equal magnitude.
The weight 38 of each element is preceded by a time delay of a
quarter cycle at the center frequency, which is equivalent to a
90.degree. phase shift. The output signal 40 is the sum of all the
weighted signals, and inasmuch as all weights are of equal
magnitude, the directivity pattern at the center frequency is the
same as that shown in FIG. 2 because of symmetry.
With continued reference to FIG. 4, an interferring sinusoidal
"noise" at the center frequency is indicated by 42. The angle of
incidence of this noise is such that it would be received on one of
the side lobes of the directivity pattern with a characteristic
sensitivity of only 17 dB less than that of the main lobe at an
angle of 0.degree..
The configuration shown in FIG. 5 is generally indicated by
reference numeral 44. In this configuration, the weights 36 and 38
associated with each element are of different value. Thus, all the
weights shown in configuration 44 have different values. The
resultant directivity pattern at the center frequency becomes as
shown in the figure. As will be noted, the main lobe 46 is almost
unchanged from that shown in FIG. 2 and FIG. 4. However, the side
lobe 45 (FIG. 4) which previously intercepted the sinusoidal noise
has been shifted so that a null is now positioned in the direction
of that noise. Typically, the sensitivity in the noise direction is
below the main lobe sensitivity, improving noise rejection by 20 -
30 dB when compared with the sensitivity associated with the
configuration of FIG. 4.
To illustrate the existence and calculation of a set of weights
that will cause noise rejection as just discussed, consider the
illustration of FIG. 6. The signal arriving from the desired
direction 48 at 0.degree. will be referred to as the "pilot"
signal, while the "noise" is incident to the array along direction
50. Both the pilot signal and the noise signal are assumed, for
this example, to be at the same frequency. At a spatial point
midway between the antenna array elements 12, the signal and the
noise are assumed to be in phase. In the example illustrated, two
identical omnidirectional array elements are spaced one-half wave
length apart. The signals received by the left element 12 are fed
to two variable weights 52 and 54, the weight 54 being preceded by
a series connected quarter wave length delay. A similar structure
exists between the right element 12 and weights 60, 62. As a result
of the configuration shown in FIG. 6, the four weighted signals are
summed by a summing circuit 56 to form the array output signal at
58. The determination of a set of weights 52, 54, 60 and 62 which
will accept the pilot signal along direction 48 and reject the
noise signal along direction 50 can be solved in accordance with
the mathematical expressions presented in the aforementioned
article by Widrow, et al. Suffice it to say that the solution to
this problem presents a set of weights so that the array will have
the desired properties, in that it will accept a signal from the
desired direction 48 while rejecting noise from direction 50, even
if the noise is at the same frequency as the pilot signal due to
the fact that the noise comes from a different direction than does
the signal.
The aforementioned discussion serves as a proper explanation of the
principles involved in the present invention. However, the
calculation of weights by this method is impractical. This is due
to the fact that the method is only useable when there are a small
number of extremely directional noise sources, when the noises are
at one frequency, and when the directions of the noises are
predetermined. In a practical process, it should not be required to
have detailed information regarding the nature and number of the
noise sources.
Before discussing more practical methods of adaptive filtering and
signal processing to be used in an adaptive array, the
configuration shown in FIG. 7 will be discussed. By way of example,
two identical system sections 64 and 66 are illustrated, although
as will be appreciated, a greater number will usually be used.
Referring to section 64, a plurality of delays 68 are series
connected with an associated antenna element 70. Individual weights
72 are connected at the junction between adjacent delays and the
input of a summing circuit 74. In a similar manner, a weight 76 is
connected between the antenna 70 and the summing circuit 74.
Likewise, a final weight 78 is connected between the output of the
last delay and the summing circuit 74. The various delays 68 may be
replaced by a tapped delay line which is discussed hereinafter with
particular reference to the present invention. The tapped delay
line permits adjustment of gain and phase as desired at a number of
frequencies over the band of interest. If the tap spacing is
sufficiently close, this network approximates an ideal filter which
would allow complete control of the gain and phase at each
frequency in the passband.
With continued reference to FIG. 7, the next step in the
consideration of an adaptive signal processor is to develop an
adaptation procedure which can be used to automatically adjust the
multiplying weights 72, 76 and 78 to achieve the desired spacial
and frequency filtering. The procedure should produce a given array
gain in the specified look direction while simultaneously nulling
out interfering noise sources.
FIG. 8 illustrates a basic adaptive element generally denoted by 80
which cooperates with the configuration of FIG. 7. The indicated
input terminals to this element are connected to respective
junction points at the input of the multiplying weights shown in
FIG. 7. Thus, the indicated multiplying weights 82 and 84 in FIG. 8
correspond to two of the multiplying weights shown in FIG. 7. The
dots 86 and 88 serve to indicate where the remaining multiplying
weights of FIG. 7 would be inserted in the element 80. As indicated
in FIG. 8, the element operates upon the input signals with
appropriate automatic circuits 90 that accomplish weight
adjustment. This adjustment is indicated by control lines 92 and
94. The summing circuit 74 generates an output along line 96. A
shunt lead 98 applies a portion of the output from line 96 to a
second summing circuit 100. A desired response signal is applied to
a second input 102 of the summing circuit 100 to generate an error
signal 104 which is in turn fed back to the automatic circuits
90.
Accordingly, the adaptive element shown in FIG. 8 constitutes a
closed loop feedback system which operates upon the automatic
circuits 90 in a manner adjusting the multiplying weights to
produce a given array gain in a specified look direction while
simultaneously nulling out interfering noise sources.
In order that adaptation or weight changing take place, a "desired
response" signal must be applied to the element 80. A method for
obtaining this signal is discussed in the Widrow et al article,
supra. Suffice it to say at this point, that the variable weights
of the element can automatically be adjusted by an adaptive
technique based on the least-mean-square (LMS) algorithm. However,
it must be stressed that other algorithms may be employed with
different results as to accuracy and computational time
requirements.
FIG. 1 shows the adaptive system which forms the present invention.
The desired response signal is provided through the use of an
artifically injected signal, referred to as a "pilot" signal, which
is completely known at the receiver because it can be generated by
computer software at the receiver. The pilot signal is constructed
to have spectral and directional characteristics similar to those
of the incoming signal of interest. These characteristics generally
represent estimates of the parameters of the signal of interest.
Adaptation with the pilot signal will cause reduced array response
(nulling) in the direction of directional noises impinging upon the
array.
With continued reference to FIG. 1, a system block diagram of the
present invention is shown. In essence, the invention is a
refinement and improvement over the basic systems aforementioned.
The principal objective is to include digital adaptation for RF
applications. The actual frequency range for which the present
invention is suited does not have restrictive limitations because
adaptation occurs at IF. A plurality of identical, spaced antenna
elements 106, 108 and 110 are connected to respective RF circuits.
For purposes of convenience, only the circuitry connected with
antenna element 106 will be discussed. The antenna element 106
feeds an RF amplifier 112. The amplifier drives an input to mixer
114, which can be any conventional first detector. A second input
116 is driven by a local oscillator 118 to produce a signal of
intermediate frequency (IF) along lead 120. This signal is
amplified by the IF amplifier 122 then is passed through the
transverse filter 124 that has its output appearing along lead 126.
As indicated in the figure, IF signals at 128 and 130 are
associated with antenna 108 and 110, respectively. The IF signals
at 128 and 130 drive their respective transverse filters (not
shown) and the outputs of these respective filters drive a summing
circuit 132 along with the driving input of the IF signal at 126.
Although three antenna elements 106, 108 and 110 have been shown,
the points 111 represent the location of other elements in the
array.
Considering the structure of each transverse filter, reference is
made to transverse filter 124 which includes a tapped delay line
134 similar to the interconnected delays 68 shown in FIG. 7 and
discussed hereinbefore. The IF signal from the IF amplifier 122 is
fed to the tapped delay line at input terminal 136. The outputs
from the tapped delay line 134 are separately connected to
sample-and-hold circuits 138. However, for convenience, only the
first and last output terminals 142 and 144 are shown. To each
output of the delay line 134 is connected a conventional amplitude
weighting circuit. In the case of delay line output 142, the
amplitude weighting circuit is denoted 146 while the delay line
output 144 is connected to a similar amplitude weighting circuit
indicated by 148. All the outputs from the amplitude weighting
circuits are connected in parallel with a conventional summing
circuit 150. The output from the summing circuit 150 carries the
summed signal.
Up to this point, we have dealt only with analog signals.
Therefore, if digital implementation is to take place, an analog to
digital conversion must be made. This conversion is implemented by
an A/D device of known design.
A digital processor (computer) 154 makes the adaptive processing
for RF antenna signals possible. Tap point samples from the A/D
converter 152 are made available at input terminals 156, 158 and
160. However, a greater number of tap off sample lines can be
present as indicated by the dots 161 adjacent the designated tap
points. Tap point samples can be delivered sequentially or in
parallel to the digital processor 154. It is to be stressed that
the adaptation rate is controlled by the processor speed, not by
the RF frequencies.
Other inputs required by the processor are some knowledge of the
target signal, such as its center frequency and direction, and
possibly samples from a pilot signal generator 162. However, as
discussed hereinafter in greater detail, the pilot signal can also
be software generated. Communication between the pilot signal
generator and the computer 154 is indicated by lines 164 and 166.
The computer 154 governs timing control and generates control
signals for varying the amplitude weighting circuits 146 and 148 so
as to achieve desired interference rejection. As will be
appreciated, the system of FIG. 1 is a hybrid system, inasmuch as
the information path is analog, but the adaptation is performed
digitally. The number of weights per filter must be determined by
the particular application. However, interference rejection is
achieved by iteratively adjusting the weight according to a
gradient search criterion that is built into the computer software.
At each iteration, the adaptive processor receives samples of all
the tap point signals, then makes the necessary computations
according to preselected algorithms, and commands the adjustment of
the filter weights 146, 148. The sample and hold circuits 138, at
all tap points in the systems, are strobed essentially
simultaneously. Thus, at each iteration, the processor "sees" more
than a single instantaneous sample of the RF environment. It must
be stressed once again that the actual sampling rate is controlled
by the processor speed, and not by the incoming RF signal
frequencies.
To complete the closed feedback loop of each transverse filter 124,
control signals are generated at output lines 168 and 170. For
brevity, only the closed loop associated with output line 168 will
be discussed. The control signal appearing at line 168 drives a
conventional weight control circuit 172 which produces a command
signal along output line 174 forming a second input to the
amplitude weighting circuit 146. The command signal causes the
amplitude weighting circuit to change or adapt. In this manner, a
closed feedback loop is created with the digital computer 154
forming a very important part of the loop.
Concentrating on the matter of pilot signal generation at 162, a
distinct advantage occurs if the generation is by software. The
advantage arises in the case when the estimate of the target center
frequency is in error, or the target has no appreciable carrier.
This situation requires artifically inserting the pilot signal into
the system. Such a manipulation is easily accomplished in the
software itself. However, this would be very difficult to
accomplish with hardware, and would perturb the array output.
To clarify the meaning of software insertion of a pilot signal,
consider the following: Having knowledge of the array geometry and
pilot frequency, as well as the direction of arrival, the relative
phase of the pilot at each antenna element may be computed as
though the pilot were actually a signal incident to the array. Then
at each sampling instance, these relative phase angles can be used
to compute pilot samples which would appear at each tap point in
the system if the pilot signal were part of the environment. These
pilot samples are linearly added to the actual tap point signals in
the software to accomplish artifical insertion. This insertion
constrains the array to have a main beam in the pilot direction and
frequency since the pilot is considered the desired signal when the
error signal is formed. Any signals present in the environment
which differ substantially from the pilot in frequency and/or
direction will be "nulled" by the adaptive system. The amount of
difference allowable is dependent upon the physical configuration
of the array. The computations at each sampling instant can be
minimized by using a table look-up to obtain the required pilot
samples. Pre-computed address differences for the various tap
points are used to obtain the appropriate pilot samples for each
point.
The block diagram of FIG. 1 illustrates an A/D converter at each
tap point as indicated by 156. This allows all the tap point
samples to be delivered to the computer in parallel. One
alternative would be use of only one A/D converter to service all
the sample and hold circuits and thus sequentially feed the data to
the computer.
Interference rejection will occur even after the interference
environment has been assumed unknown. Any prior knowledge of the
interference could be used by computer 154 to improve
rejection.
It should be borne in mind that the same techniques as discussed
hereinbefore can also provide null steering for a transmitting
array. Both of these are achieved by software insertion of the
nulling signal, nulling the transmitted signal noise in frequency
and direction.
It should be understood that the invention is not limited to the
exact details of construction shown and described herein for
obvious modifications will occur to persons skilled in the art.
* * * * *