Electronic Combination Lock

Abstract

An electronic combination lock includes an entry bank comprising a plurality of multistage registers interconnected with a plurality of pushbutton switches so that a combination number entered by actuation of the switches is progressively shifted through the various registers. Certain stages of the registers are interconnected through logic gate means so that if the combination is properly entered a controlled device such as a door unlocking solenoid is energized. In another embodiment a memory bank comprising second plurality of multistage registers are interconnected with the pushbutton switches and permit through actuation of memory/entry switch means the programming of the memory bank for a particular combination. The output of the respective ones of the shift registers in the memory bank are compared with respective ones of the shift registers in the entry bank and if, after the entry of the combination code number, registers of the entry and memory bank are identical, the controlled device is energized.

Description

This invention relates to electronic combination locks.

It is an object of the present invention to provide an improved electronic combination lock employing a plurality of static shift registers and which can be economically manufactured using medium or large scale integration techniques.

It is another object of the present invention to provide an electronic combination lock as aforementioned which is readily programmable to a new combination once the locked device has been unlocked.

In accordance with the present invention the electronic combination lock includes a plurality of pushbutton switches bearing indicia representing respective digits used in the combination lock number. Each of the switches is interconnected with respective shift registers and each of the shift registers is clocked each time any of the pushbutton switches are actuated. Logic means are connected with the output of certain stages of each of the registers depending on the length of the combination and the sequence of the digits in the combination. When the proper combination is entered by actuation of the pushbutton switches the output of the logic means energizes a controlled device which may be a lock solenoid or other device being controlled. In accordance with another embodiment of the invention a second plurality of shift registers is provided into which the operator may enter a combination code number of his own choosing.

Other objects and advantages of the present invention will be more apparent from the following detailed description which should be taken in conjunction with the drawings in which:

FIG. 1 is an embodiment of a preprogrammed electronic combination lock in accordance with the present invention;

FIG. 2 is a schematic diagram of a programmable electronic combination lock in accordance with the present invention.

Referring now to the drawings and initially to FIG. 1, the electronic combination lock of the present invention comprises five pushbutton actuated switches designated 1, 2, 3, 4 and 5 corresponding to the digits in the combination code. One side of each of the switches 1 through 5 is connected with a source of direct current potential designated V+. The other side of each of the switches 1 through 5 is connected with conventional switch bounce elimination circuitry generally designated 10a through 10e. Each of the circuits 10a through 10e are identical and only the circuit designated 10a will be described. The circuit 10a comprises a NAND gate 12 having its inputs connected to ground through a pull-down resistor 14 and its output connected to the inputs of a NAND gate 16. The output of the gate 16 is connected to the input of the gate 12 through a feedback resistor 18. The hysteresis of the gates 12 and 16 prevent changes in the output of the circuit 10 which might otherwise result from contact bounce during closure of the switch 1. The outputs of the circuits 10a to 10e are connected with the clock input of eight bit shift registers 20a to 20e through OR function performing logic generally designated 22. The logic 22 comprises a NOR gate 24 connected with the output of the circuits 10a, 10b, 10c and a NOR gate 26 connected with the outputs of the circuits 10d and 10e. The output of the gates 24 and 26 provide inputs to a NAND gate 28 the output of which is connected with the clock inputs of the shift registers 20a through 20e. The output of the circuits 10a to 10e are also connected with the D inputs of respective shift registers 20a through 20e. Each of the shift registers 20a to 20e contain eight interconnected D type flip-flops with leads designated S1 through S8 extending from the Q output of each of the flip-flops. Certain stages of the registers 20a to 20e are connected with the input of AND function performing logic means generally designated 30 depending on the number of digits in the combination and their sequence. In the example shown in combination which is programmed is 1353142. Thus, stages S3 and S7 of the registers 20a, stage S1 of the register 20b, stages S4 and S6 of register 20c, stage S2 of the register 20d, and stage S5 of the register 20e are connected with the logic 30. The logic 30 comprises a pair of NAND gates 32 and 34 having their outputs connected as inputs to a NOR gate 36. The output of the NOR gate 36 is connected with a transistor driver generally designated 38 through a resistor 40. The driver 38 comprises a pair of transistors 42 and 44 interconnected in a Darlington configuration. The driver 38 completes the circuit through a doorlock solenoid 46 whenever the transistors 42 and 44 are rendered conductive.

The operation of the circuit shown in FIG. 1 will now be described in connection with the entry of the aforementioned combination number 1353142. Initially with all pushbutton switches 1 through 5 deactuated, logic "0's" appear at the output of the circuits 10a through 10e. This places a logic "1" at the output of NOR gates 24 and 26 and accordingly, a logic "0" at the output of the NAND gate 28. Depression of pushbutton 1 places a logic "1" at the D input of the first stage of register 20a which is clocked to the Q output of stage S1 thereafter from the output of the OR logic 22. When pushbutton 3 is depressed a logic "1" appears at the output of stage S1 of register 20c and the logic "1" previously appearing at the output of stage S1 of register 20a is shifted to the output of stage S2 of register 20a. As the remaining digits 5, 3, 1, 4 and 2 are entered a logic "1" is shifted into stage S1 of the registers 20e, 20c, 20a, 20d, and 20b in that sequence. Accordingly, upon depression of pushbutton 2 entering the last digit of the combination; stage S1 of register 20b, stage S2 of register 20d, stages S3 and S7 of register 20a, stages S4 and S6 of register 20c, and stage S5 of register 20e will all be logic "1's." Therefore, the output of gates 32 and 34 switch to a logic "0" and the output of gate 36 switches to a logic "1" to render the transistors 42 and 44 conductive and energize the unlocking solenoid 46. By depressing one of the pushbuttons 1 through 5 the data in the registers 20a to 20e will be shifted one stage and the solenoid 46 will be deenergized. If the combination entered through the pushbuttons 1 through 5 is incorrect, at least one of the inputs to the gate 32 and 34 will be low so that the solenoid 46 will not be energized. In order to program registers 20a through 20e for the particular combination code number either of two approaches may be taken. Either the seven output leads may be brought out from the integrated chip pre-connected to the various stages indicating during the manufacture of the chip which would necessarily involve a different mask for each combination, or all leads from each of the registers 20a to 20e may be brought out and the inputs to the AND logic 30 hard wired to terminations of the desired stages.

Referring now to FIG. 2, a second embodiment of the electronic combination lock of the present invention is shown. Circuitry of FIG. 2 permits the combination number to be programmed into the circuit by the operator and changed at any time using the same pushbutton keys which open the lock. Not only does this allow the user to determine his own combination easily with no wiring changes but it also eliminates the need to bring out all of the shift register outputs to external terminals thus permitting more economical manufacturing of the circuit using medium or large scale integration techniques. Referring now to FIG. 2, the pushbuttons designated 1 through 5 have one side connected to V+ and the other side connected with bounce elimination circuitry generally designated 48a to 48e which may be the same as the circuits 10a to 10e of FIG. 1. The outputs of the circuits 48a to 48e are connected with the D input of 8 bit shift registers 50a to 50e respectively, through AND gates 52a to 52e respectively. The registers 50a to 50e form an entry bank generally designated 50. The outputs of the AND gates 52a to 52e are also connected with the clock inputs of each of the registers 50a to 50e through an OR gate 54. The output of the circuits 48a to 48e are also connected with the D inputs of eight bit shift registers 56a to 56e through AND gates 58a to 58e respectively. The outputs of the gates 58a to 58e are also connected with the clock inputs of the registers 56a to 56e respectively, through an OR gate 60. The registers 56a to 56e form a memory bank generally designated 56. A memory/entry switch 62 has one side connected to V+ and the other side connected as one input to each of the AND gates 58a to 58e and to ground through a pull-down resistor 64. The other side of the switch 62 is also connected as one input to each of the AND gates 52a to 52e through an inverter 66. Consequently, when the switch 62 is in the entry position as shown the output of the inverter 66 is a logic "1" so that each of the gates 52a to 52e are open while one input to each of the gates 58a to 58e is a logic "0" so that these gates are closed. When a switch 62 is placed in a closed or memory position logic "1's" appear at each of the inputs to the gates 58a to 58e so that these gates are open while a logic "0" appears at the output of the inverter 66 closing the gates 52a to 52e.

The output of the eight stages of the shift registers 50a and 56a provide inputs to an eight bit comparator 68a. Similarly, the outputs of the shift registers 50b, 56b; 50c, 56c; 50d, 56d; and 50e, 56e provide inputs to respective 8 bit comparators 68b to 68e. The outputs of the comparators 68a to 68e provide inputs to an AND gate 70 the output of which controls current flow to a control device such as the door opening solenoid 46 of FIG. 1.

The operation of the circuit of FIG. 2 is as follows. Actuation of the switch 62 to the memory position opens the gates 58a to 58e and permits the entering of a desired combination number into the registers 56a to 56e in the memory bank 56. Actuation of the switch 62 from the memory position to the entry position as shown closes the gates 58a to 58e, opens the gates 52a to 52e, and consequently, the number entered by actuation of the pushbuttons 1, 2, 3, 4 and 5 after the switch 62 is moved to the entry position will cause the number to be entered into the entry bank 50. If the number entered into the entry bank 50 is the same as that previously stored in the memory bank 56, the inputs to the comparators 68a to 68e will be identical and the outputs of the comparators will all be logic "1's" causing the output of the gate 70 to be a logic "1" and thereby unlock the door lock solenoid 46.

It is contemplated by this invention that the switch 62 will be located in an accessible location. For example, the keyboard containing the pushbuttons 1 through 5 may be located on the outside of the vehicle door and the switch 62 may be located on the inside of the vehicle. Consequently, in order to change the combination of the lock one must first insert the predetermined code number in order to gain access to the switch 62. Alternatively, where the combination lock is used to control starting of the vehicle, in which case the output of the lock circuitry would be used to provide a circuit completing closure in the starter circuit, the switch 62 may be responsive to operation of the vehicle engine so that the switch 62 is only in the memory position while the vehicle is running. In other words, only after the vehicle has been started by inserting the combination lock number can the combination lock number be changed.

The circuit of FIG. 2 is particularly advantageous from a manufacturing standpoint since very few outside terminations are required for this circuit. The only terminations required are those for the pushbutton key inputs, one for the memory entry switch input and for the output of the gate 70 and one each for input power and ground.

Claims

Having thus described my invention what I claim is:

1. An electronic combination lock circuit for actuating a control device in response to operator entry of a predetermined combination code number comprising:

a plurality of manually actuable switch means connected in parallel with each other and to a source of direct current potential, each of said switch means bearing indicia corresponding to a different digit,

a plurality of shift register means,

means connecting respective ones of said switch means with the data input of respective ones of said shift register means,

Or function performing gate means interconnecting each of said switch means with the clock input of each of said shift register means whereby each of said shift register means is toggled in response to actuation of any of said switch means,

And function performing means having a number of inputs corresponding to the number of digits in said combination code number, respective ones of said inputs connected with the output of particular stages of said shift registers depending on the length and sequence of said combination code number, said AND function performing means developing a control signal for actuating said controlled device only when said switch means are actuated in sequence corresponding to said combination code number.

2. An electronic combination lock circuit for actuating a control device in response to operator entry of an operator assigned combination code comprising:

a plurality of manually actuable switch means connected in parallel with each other and to a source of direct current potential,

an entry bank and a memory bank comprising a first and second plurality of shift register means respectively,

first gate means connecting each of said switch means to the clock input of each of said first plurality of shift register means and connecting respective ones of said switch means to the data input of respective ones of said first plurality of shift register means,

second gate means connecting each of said switch means to the clock input of each of said second plurality of shift register means and connecting respective ones of said switch means to the data input of respective ones of said second plurality of shift register means,

memory/entry switch means connected with each of said first and second gate means, said memory/entry switch means being actuable from an entry position opening said first gate means and closing said second gate means to a memory position closing said first gate means and opening said second gate means,

comparator means for comparing the output of respective ones of said first plurality of shift register means with the respective ones of said second plurality of shift register means and for developing a control signal for actuating said control device only when the outputs of said first and second shift register means are identical.

3. An electronic combination lock circuit for actuating a control device in response to operator entry of an operator assigned combination code comprising:

a plurality of pushbutton switch means connected in parallel with each other and to a source of direct current potential, each of said pushbutton switch means bearing an identifiable digit,

a memory bank comprising a plurality of shift registers,

an entry bank comprising a plurality of shift registers,

And function performing gate means connecting respective ones of said switch means with the data input of respective ones of said shift register means in said memory bank,

second AND function performing gate means connecting respective ones of said switch means with the data input of respective ones of said shift registers in said entry bank,

first OR function performing gate means connecting the output of each of said first AND function performing means with the clock input of each shift register means in said memory bank,

second OR function performing gate means connecting the output of each of said second AND function performing means with the clock input of each shift register means in said entry bank,

memory/entry switch means actuable from an entry position closing said first AND function performing gate means and opening said second AND function performing gate means, to a memory position opening said first AND function performing gate means and closing said second AND function performing gate means,

a plurality of comparator means for comparing the output of respective ones of said shift registers in said entry bank with respective ones of said shift registers in said memory bank and for developing a control signal for actuating said control device only when the outputs of respective shift registers in said entry bank are identical with the outputs of respective registers in said memory bank.