Electronic Locking System

Abstract

An electronic locking system utilizes a circuit to compare read-only-memories. Identical read-only-memories constitute a portable "key" and a fixed "lock" which are instantaneously compared electronically so that a determination of identity will initiate a locking or unlocking operation.

Description

BACKGROUND OF THE INVENTION

This invention relates to an electronic n-dimensional logic generation and comparision system for rapidly identifying an unknown logic function source and, more particularly, relates to an electronic logic generation and comparison system for use as an electronic locking system.

Conventional mechanical locks and locking systems are by and large based on the use of spring loaded pins and tumblers which control the operation of bolt locks. Concentric cylindrical tumblers have a series of pins passing through them so that inner tumblers can revolve within outer tumblers only if the pins are lined up to a depth at which they do not engage an adjacent tumbler. A key with a series of varying indentations is inserted within the innermost tumbler to line the pins up so the inner tumblers can revolve to open the bolt lock. An inherent problem with mechanical pin-and-tumbler locks is that an experienced locksmith can "pick" them by lining the pins up one by one or a universal pick can be used by an amateur to open any lock. Or, wax impressions can be obtained of the key way and an appropriate bogus key can be fabricated. Furthermore, once a lock is set it is costly and difficult to reset them. And large locking systems have master key and grandmaster keys which are capable of opening the locks, thereby creating a greater number of pin settings which permit the locks to open so the locks may be more readily picked.

It would be desirable, then, to utilize electrical or electronic principles in implementing an electrical or electronic locking or identification system. Attempts have been made to construct electrically controlled locks. See for example U. S. Pat. No. 3,529,454 in which a solenoid-operated bolt lock is controlled by a remote electromechanical code device. Such electromechanical locking mechanisms require hardware components which take up considerable space. Furthermore, the size of such remote control devices varies in direct proportion to the complexity of the potential code, so that extremely complex codes cannot be employed. Furthermore, many of the devices require the user to be familiar with the proper code to operate the control mechanism, a feature which renders the systems less suitable for large scale transient locking operations such as hotel door locks, industrial gate locks, automobile locks, and the like.

Electronic switching and comparison circuits which are capable of correlating the output from an unknown circuit with a reference circuit are well-known. See, for example, Marcus, M. P., "Switching Circuits for Engineers", 2nd ed. Comparison circuits which can accommodate a rapid succession of time spaced electrical signals are also known and have been widely used in data processing applications. The development of integrated circuits has made it possible to reduce the size of these circuits. Integrated circuits contain numerous components such as resistors, diodes, and capacitors, and are fabricated by the deposition of successive layers or by the selective diffusion of resistive materials, conductive materials and dopants such as boron and phosphorus onto semiconductor materials. Such circuits are nonvolatile so they do not require continuous power to be supplied. The more complex the circuit the lower the yield but once a circuit has been successfully fabricated and tested it will perform with a high reliability rating.

Up to the present no one has applied miniature switching circutiry techniques directly to portable large scale locking and identification systems. Such circuitry has been considered to be not portable enough to be utilized in such applications. Furthermore, the cost of such a system has been considered highly prohibitive. In addition no one has proposed a suitable electronic logic function generation and comparison circuit for such an application.

It is accordingly an object of this invention to provide electronically a logic function generation and comparison circuit wherein logic functions of a high order complexity are generated by a portable and lightweight source (i.e. a key) and are compared nearly instantaneously with the logic functions generated by a known logic function source (i.e. a lock) to permit rapid and reliable identification of the unknown source so that an unlocking or locking operation may be performed.

It is a further object of this invention to provide electronically an n-dimensional logic function generation and comparison circuit which has a nearly infinitesimal chance of mis-identifying an unknown logic function source.

It is another object of this invention to provide a portable electronic logic function generation source which is matable with a fixed electronic logic function identification circuit and which is capable of withstanding intermittent mechanical shocks up to 30,000 g's. without malfunctioning.

It is another object of this invention to provide a portable electronic n-dimensional logic function generation and comparison circuit wherein a plurality of master key logic function sources can be employed in alternation with a tenant key logic function source to complete a comparison circuit to activate a locking system.

A further object of this invention is the provision of an electronic push button combination locking system wherein an m'th and n'th state logic encoder is used to generate a series of test logic functions which are compared with a fixed logic function source so that the presentation of the proper combination initiates a locking or unlocking operation.

It is a still further object of this invention to provide electronically a logic function generation and comparison system which will trigger an alarm system if a given number of improper logic function sources are presented for identification to the locking system.

It is a final object of this invention to provide electronically a logic function generation and comparison system which will require resetting by presentation of the proper unknown logic function source once a given number of logic function sources have been presented for identification and an alarm system has been triggered.

SUMMARY OF THE INVENTION

An identical set of integrated circuit logic function sources such as read-only-memories (hereinafter described as ROMs) is fabricated. These logic function sources will be small in physical size even though they both contain a large number of addresses each of which is capable of storing a multi-bit word or byte of information. One or more of the ROMs serve as a reference or lock logic function source and the remaining ROMs serve as unknown or key logic function sources.

The input leads of the reference ROM are connected to the output of an n-dimensional counter and the output leads of the reference ROM are connected to an n-dimensional comparator. This reference ROM serves as a reference logic function generation source. As the counter ranges through all number permutations possible in an n-dimensional logic system with the given number of inputs for the reference ROM and transmits these numbers in electrical impulse form to the reference ROM a series of logic functions (in n-dimensional logic) is produced by the reference ROM; there is a one to one correspondence between each logic function generated and each number transmitted to the reference ROM. The logic function and their sequence is unique and depends upon the bytes stored at the individual addresses of the reference ROM. The logic functions are transmitted in electrical impulse form to the inputs of the comparator.

An unknown portable ROM is carried by the individual or object which seeks identification to activate the locking system. The unknown ROM is inserted into a socket-like device which provides electrical connections for the inputs and outputs of the unknown ROM. The input leads to the socket are connected to the same n-dimensional counter as the first ROM so that the numbers in electrical impulse form are presented to the reference and unknown ROMs simultaneously. The logic functions generated by the unknown ROM are transmitted through the output connections of the socket to the comparator. The logic functions generated by the reference and unknown ROMs will then be compared by the n-dimensional comparator. The comparator ascertains if they are identical in a stepwise fashion, i.e. ascertains if each bit of each byte is identical. If they are exactly identical the comparator will emit an electrical signal which will activate an electrically responsive instrumentality such as a solenoid operated lock. If they are not, the comparator emits an electrical signal which can be used to indicate a mismatch or can prevent the instrumentality from being activated.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating the components of the electronic locking system of the present invention in combination with a trial counter, and alarm network and maximum voltage sensor.

FIG. 2 is a block diagram of the components included in a master-tenant embodiment of the electronic locking system of the present invention.

FIG. 3 is a side cross-sectional view of an unknown portable logic function generation device.

FIG. 4 is a pictorial view of a portable logic function generation device illustrating an external key-way nub.

FIG. 5 is a schematic circuit diagram of the basic logic function generation and comparison circuit of this invention in combination with a trial counter alarm system.

FIG. 6 is a block diagram illustrating the components of the circuit of the present invention in combination with a key recording system, a standby power supply, and a trial counter and alarm network.

FIG. 7 is a schematic diagram of an embodiment of the present invention employing an octal to binary state logic encoder for the unknown logic function.

DESCRIPTION OF PREFERRED EMBODIMENT

Before describing the preferred embodiment in detail it is instructive to set forth the mathematical and electronic precepts on which it is grounded. An n-dimensional logic system is one in which n discrete states are capable of combination in any manner and sequence to form logic functions. For example, the decimal system has ten discrete states, i.e. the numbers 0 through 9, which can be used to generate a multitude of logic functions, e.g. sums, or powers of the ten basic numbers. The binary system has two discrete states, 0 and 1; the tertiary system has three discrete states, 0, 1 and 2, and so on. Any of these logic systems, i.e. an n-dimensional logic system, can be used to form logic functions.

The discrete states of an n-dimensional logic system are typically represented in electronic form as fixed voltage levels (although theoretically they could be represented by fixed impedances, currents or the like). The two states of the binary system are often represented in electronic form as a more positive fixed voltage for a 1 and a less positive voltage for 0 (so-called positive logic) or a less positive voltage for a 1 and a more positive voltage for 0 (so-called negative logic). A tertiary system could be handled in electronic form, for example, by assigning a zero voltage for 0, a positive fixed voltage for 1 and a higher positive fixed voltage for 2. Throughout the following description of the preferred and ancillary embodiments a binary system is used for purposes of example only and it is to be understood that any n-dimensional logic may be used with the reference and unknown logic function sources. The invention is premised on the application of miniature circuitry to prepare exceedingly complex logic function sources for use as comparison components in an electronic locking system and higher order logic systems have higher inherent complexity.

Referring now to the block diagram of FIG. 1 it can be seen that start switch 111 controls the energization of trial counter 105, binary counter 107 and oscillator 108, and binary comparator 103. The combination of oscillator 108 and binary counter 107 comprises an address generation subcircuit 109 which can generate rapidly in sequence all possible binary permutations for a given number of inputs to a reference logic function source 102 and an unknown logic function source 101. The binary numbers are generated in electrical impulse form and may be generated by any binary counter, e.g. TEXAS INSTRUMENTS 54/74160 or 54/74193, SIGNETICS 8284 or 8281, driven by an oscillator. Such subcircuits can generate well in excess of 10.sup.8 numbers/seconds.

The binary coded electrical impulses received by the reference logic function source 102 and the unknown logic function source 101 will cause the generation of respective logic functions which consist of binary numbers in electrical impulse form and which are then transmitted to parallel inputs of binary comparator 103. Binary comparator 103 examines each of the binary bits of the side-by-side functions to determine if they are identical. Such binary comparators are built around well known logic circuitry. For example, see Ryder, John D., "Electronic Fundamentals and Applications," pp. 521, et. seq. Binary comparators currently available on the market include: Fairchild model numbers 9324 and 93L24; Signetics model number 8242; and Texas Instruments model numbers 5486, 7486, 54L86, and 74L86. Binary comparator 103 will produce a first electrical signal if all inputs are identical. If there is at least one mismatch between the logic functions received then a second electrical impulse is emitted. The output of binary comparator 103 can be keyed to a variety of electro-mechanical instrumentalities 104 so that the instrumentality is energized or de-energized only if the first electrical signal is received. As an adjunct to the basic circuit of the present invention a trial counter 105 receives an input from lead 110 by which it can monitor the number of times that an unknown logic source is presented for identification. The trial counter may be any electro-mechanical or electronic counter, although the electronic counter circuit 117 of FIG. 5 is the preferred embodiment. The trial counter may be pre-set to trigger alarm 106 when a given number of improper unknown logic function sources have been presented. Additionally, the trial counter can be reset to zero by input 112 whenever electro-mechanical instrumentality 104 is energized or de-energized. Any suitable alarm system 106 may be employed.

To implement the present invention it is necessary to utilize logic function sources which are non-volatile and which are embodied in miniature circuitry. To obtain this feature it is necessary that the individual elements of the logic function circuits be at least temporarily fixed or programmed to represent a series of unique logic functions at specific addresses. It is also desirable that the logic function sources may later be changed, i.e. reprogrammed, so that the "lock" may be changed. These requirements are satisfied by a number of read-only-memories including mask programmed read-only-memories (ROMs), fusible ROMs or FROMs, MOS ROMs fabricated with MOS technology, amorphous semiconductor ROMs and avalanche induced electromigration ROMs.

Read-only-memories, commonly denoted ROMs, consist of a complex interlayering of diodes and other components, i.e. fuses and amorphous demiconductors, which are connected together to form an array of specific addresses each of which is capable of inherently storing a given number of bits or bytes of information. If a binary logic system is employed, a bit of information, i.e. a 1/0 or a 0/1, is represented respectively by a functioning diode link or a fused diode link (a diode which has been rendered inoperative by a surge of electrical current so that an open circuit exists). Mask programmed ROMs have a fixed arrangement of diodes and open circuits and can never be reprogrammed. Fusible ROMs or FROMs have an arrangement of diodes and fuses which can be altered by blowing additional fuses by surges of current. This process is, however, irreversible so that, eventually, the fusible ROM would approach the situation where all diode links were fused. Some MOS ROMs may be reprogrammed at will and are especially desirable for their low power consumption characteristics. Amorphous semiconductor ROMs and avalanche induced electromigration ROMs are also field programmable.

ROMs are defined in terms of the input and output leads as 2.sup.M .times. N where M is the number of input leads (determining the binary input combinations) and N is the number of output leads (determining the complexity of the logic functions produced). Such ROMs as are currently available include: Mask programmed ROMs -- Signetics model numbers 8224 and 8228; fusible ROMs -- Harris semiconductor model number HROM 0512 (64 by 8), HROM - 1256 (256 by 1); Monolithic Memories model numbers 6305 and 5305; Motorola model number MC 10139, and Signetics model number 8223; MOS ROMS -- INTEL model numbers 1601 and 1701; amorphous semiconductor ROMs -- Ovionics model number RM - 256; and avalanche induced electromigration ROMs -- INTERSIL model number 5600C.

The preferred and ancillary embodiments of this invention may be fabricated by incorporating the listed commercially available integrated circuit components or a custom designed integrated circuit incorporating the oscillator, binary counter, programmable or fusible ROMs, binary comparator, trial counter and alarm may be fabricated. The latter alternative is a more desirable approach for successful large scale commercial or consumer applications. Whether commercial components or a custom designed integrated circuit are utilized the comparison circuit will have highly desirable reliability and thermal shock characteristics and will be able to withstand intermittent physical shocks up to 30,000 g's. See Madland, et. al., "Integrated Circuit Technology," pp. 344-347. To add greater reliability various portions of the comparison circuit may be made redundant.

An advantage of the present invention is that astronomically large numbers of unique logic functions can be generated in extremely short periods of time. Logic functions containing 10.sup.8 bits of information can be processed by the system of the present invention in one second. Additionally, microcircuitry renders the present invention applicable to countless commercial and consumer situations. A list of the many possible applications includes personnel identification, the opening of doors, the identification of a person for purposes of advancing consumer credit, the establishment of a permanent record of one's presence at a particular place at a particular time, etc.

The circuit represented schematically in FIG. 5 is used to illustrate, by way of example only, a particular application of the system of the present invention. The output of binary counter 124 is transmitted to the inputs of a reference or lock ROM 122 and the ROM socket 121. Since the number of address related output leads of binary counter 124 is equal to the number of input leads to the lock ROM 122 and the ROM socket 121, the binary counter will present in electrical impulse form every binary combination possible to lock ROM 122 and ROM socket 121 and thence to unknown or key ROM 123 which is insertable within ROM socket 121.

The outputs from lock ROM 122 are connected to the input of binary comparator 120. The equal number of outputs from ROM socket 121 (with key ROM 123 inserted therein) are also connected to the input of binary comparator 120. Binary comparator 120 is programmed to compare the respective values for the outputs of lock ROM 122 and socket 121 to determine identity. If all binary bits of all logic functions are identical a uniform voltage, representing the binary number 1, is emitted from binary comparator 120.

In order to render the system crack proof it is necessary to prevent someone from ascertaining the logic functions which are stored at indivdual addresses. Since the addresses are externally accessible through socket 121 an unauthorized person can present all possible binary functions through the output pins of socket 121 and, if the system is designed to shut off at the first mismatch, the unauthorized person will eventually ascertain the logic functions at each address so long as he does not conduct successive unsuccessful matching attempts in excess of the number which will trigger the alarm. Thus, it is highly desirable that the system will be rendered inoperative only after the complete sequence of logic functions have been generated with the occurrence of one or more mismatches.

The operation of the electronic locking system is initiated by operating pushbutton 152. The energization of the set input of flip-flop 136 causes the output Q, initially 0, to go from zero to 1. The change of the Q output of flip-flop 136 from 0 to 1 initiates a pair of pulses from the pulse generator 137. The Q output of pulse generator 137 goes from 1 to 0 to 1 while the Q output goes from 0 to 1 to 0. One shot pulse generators which are available commercially include Fairchild model numbers 9601 and 9602, Signetics model number 8162 and Texas Instruments model numbers 54121, 54122, and 54123. The Q pulse resets the individual outputs a.sub.1, a.sub.2, . . . a.sub.n.sub.+1 of binary counter 124 to 0s. Once a.sub.n.sub.+1 goes to 0 the inhibition control of oscillator 125 is lifted so that oscillator 125 begins to oscillate and drive binary counter 124. Meanwhile, the Q pulse of pulse generator 137 sets flip-flop 153 so that the output of the flip-flop becomes 1. As oscillator 125 increments the outputs a.sub.1, a.sub.2. . . a.sub.n from all 0s to all 1s the comparison process described above takes place.

If there is a single mismatch between a single bit of a word at the same address of the lock ROM and the key ROM the appropriate Q.sub.i will go from 1 to 0 and the output of inverter 141 will go from 0 to 1. The 1 output of inverter 141 will reset the flip-flop 153 so that its output will go from 1 to 0. As soon as a single mismatch occurs the output of flip-flop 153 will go to 0 and will remain at 0 for the duration of the complete cycle of operation. In effect, flip-flop 154 remembers that a mismatch has occurred so that the system does not have to be shut down before the complete cycle has been run. If no mismatch has occurred during the complete cycle the output Q of flip-flop 153 is one. Since the output of NAND gate 143 is one unless both inputs are one in which case the output is 0 solenoid 144 will only be activated when the cycle has run (i.e. a.sub.n.sub.+1 becomes 1) and no mismatch has occurred.

In order to prevent an unauthorized person from continuously attempting to present logic functions for comparison, it is desirable to use a trial counter and alarm system powered by a separate power supply V.sub.cc2 which is always on to insure a record of the number of trials in the event the comparison circuit power supply is cut off. In the embodiment of FIG. 5 two toggle flip-flops are used in conjunction with a NAND gate and a solenoid. The truth table of the toggle flip-flop is shown below. ##SPC1##

Where: Q.sub.n is the state before the clock pulse, and Q.sub.n.sub.+1 is the state after the clock pulse. When the output of NAND gate 143 goes from 1 to 0, i.e. when the locking system is energized or de-energized, trial counter 117 is reset by the individual resetting of toggle flip-flops 132 and 133. When an additional trial is attempted the output of flip-flop 136 goes from 0 to 1. Since the T input of flip-flop 132 is connected to a separate trial counter power supply V.sub.cc2 through a resistor T is always 1 so that the output Q of toggle flip-flop 132 goes from 0 to 1. When the output of flip-flop 135 arrives at toggle flip-flop 132 the output of toggle flip-flop 132 was still 0. Therefore, the output Q of toggle flip-flop 133 does not change since its T input is 0; this will present inputs of 1, 0 to NAND gate 127. If this trial fails the next trial will toggle both toggle flip-flops 132 and 133 so the inputs to NAND gate 127 will be 0, 1. If the third trial fails, the inputs of the NAND gate 127 will read 1,1. Thus, a 0 will result at NAND gate 127's output. The trial counter will be held at 1, 1 through the set inputs to the toggle flip-flops 132 and 133 which override the clock pulse. The 0 at the output of NAND gate 127 will activate solenoid 147 and turn on an alarm system. The alarm will continue to operate until the proper key is used to make the output of NAND gate 143 go to 0 so that the reset inputs to toggle flip-flop 132 and 133 can override the set inputs so that the alarm will be turned off.

The block diagram of FIG. 6 illustrates several additional features which are added to the embodiment of the invention illustrated in FIG. 1. A reserve power supply 119 such as a long life dry cell may be added to the system to allow the system to operate in event of a power failure. The circuitry included in the system of the present invention requires little current so that only a small battery or reserve power supply network is required. Also, a key recorder 118 has been added to work in conjunction with the key logic function source. A fixed portion of the addresses in the key logic function source or the overall pattern of the key logic function can be used to indicate the identification of the key (and therefore the identification of the authorized key holder) which can be recorded in conjunction with the place at which the key was used (information which can be obtained from the lock logic function source) as well as the time and date. A maximum voltage sensor 121 serves as an additional safeguard in the event that a burglar attempted to break down the system by forcing large currents through it. If a surge of current were detected by the maximum voltage sensor 121 the whole system would shut down, the alarm would be triggered and the locking system could not be reactivated until a person with the proper key arrived.

For large scale portable applications of the system of the present invention it is necessary that a key logic function source be fabricated in a form that is highly portable as well as secure from mechanical shock. One embodiment using a portable ROM as a key is illustrated in the cross-sectional view of FIG. 3. Pins 71 of packaged integrated circuit ROM 70 are mounted on the straight through pin socket 77, and the composite of 70 and 77 is then affixed to the interior of cylindrical form 73. Cylindrical form 73 may also serve as an electromagnetic shield for the packaged integrated circuit. Pin socket 77 is open at the bottom end so that when key form 73 is inserted into a key channel, socket 77 will make electrical contact with interlocking electrical contacts which are in electrical communication with the identification circuit. A sealant 72 protects ROM 70 from the corrosive effect of external exposure and from mechanical shock. Access to ROM 70 is obtained by removal of plug 76 which is attached to key handle 75 and by removal of sealant 72.

FIG. 4 shows key-way nub 74 to be mounted externally on cylindrical form 73. Nub 74 serves as a guide that will ride in a key-way adjacent to the key channel. A key way with a particular configuration and a particular pin-socket configuration add two more threshold tests to the identification scheme of the present invention. For example, the key-way may require the key to be inserted and twisted so the electrical contacts within the key way line up with the electrical connectors in ROM socket 77.

If the identification system of the present invention is applied to a locking system a great advantage is obtained over conventional locks or electro-mechanical locks in that a high degree of security is achieved. A binary ROM with M inputs and N outputs (a 2.sup.M .times. N ROM) has a probability of 1/2.sup.M.sup.+N that a randomly programmed 2.sup.M .times. N ROM can match the logical function stored at a given address and a probability of 1/(2.sup.N).sup.2 ) that each and every address will be matched. Thus, for example, a ROM that has three inputs and four outputs has 1/c24).sup.2 = 1/(16).sup.8 .apprxeq. 10.sup.-.sup.10 probability that a randomly programmed 2.sup.3 .times. 4 ROM will contain identical information at each and every address. The degree of security that is achieved by utilizing ROMs in a locking system surpasses the security which is currently obtainable, especially for commercial applications such as hotels or building locks.

When the electronic locking system of the present invention is applied to large scale locking systems it is highly desirable to include an override or bypass scheme so that a hotel or building management can have master or grandmaster logic function sources to trigger locks without having immediate access to all individual logic function sources. This bypass may be accomplished, as indicated in FIG. 2, by a switching means 166 which is activated by the key 161. The switching means 166 serves to select the proper reference logic function source 165, i.e. selects either master reference ROM 163 or tenant reference ROM 164, for comprison with the key ROM. The switching means may be an electro-mechanical relay which is thrown by the presence or absence of an additional connector pin on the key. Or the switching means may be electronic and may be included as logic functions located at preliminary addresses in the key which activate a multiplexing unit in the stationary portion of the identification circuit. The multiplexing unit will then permit comparisons to be made only between the appropriate (master, grandmaster, etc.) reference logic function source 165 and the key logic function source 161. If the unknown logic function source is a tenant key 161 it will be compared with the tenant reference logic function source 164 so the tenant keys will operate as described above. With large scale applications it is further desirable to be able to readily rotate or change locks or to expand the system by adding additional or larger ROMs. Miniature circuit logic function sources can be readily replaced or rotated and additional or larger ROMs can be added. In fact new matched pairs can be employed if a key logic function source is lost. And, as described supra, the logic functions contained in fusible ROMs can be altered by fusing further links while MOS programmable ROMs can be reprogrammed at will.

For certain high security applications such as bank vaults and for applications in which portable keys are inconvenient combination locks are desirable. The use of an m'th to n'th state logic encoder can serve as the unknown logic function source. For example, in FIG. 7 an octal to binary encoder, shown as circuit 140 (obtainable by using eight of the 10 input leads and three of the four output leads of Harris Bipolar Keyboard Encoder HD-0165) is used to generate the unknown logic function source. The presentation of the right eight digit number (the approximate size of a phone number) to the eight address, three bit word encoder results in a probability of 1/2.sup.24 .apprxeq. 10 .sup.-.sup.8 that a random number would open the lock. The encoder as well as the other components of the circuit can be fabricated in an integrated circuit so the largest component by far in physical size would be an 8 digit push button panel for the encoder. And, for fire security, the encoder and reference ROM can be located remote from the vault.

In operation, reset button 90 is depressed to reset the output of binary counter 91 to 0, 0, 0 and to set the output of flip-flop 92 to 1. The first number button is depressed thereby presenting the first unknown logic function to binary comparator 93. The logic function stored at the first address of the lock logic function source is presented to binary comparator 93 simultaneously with the first unknown logic function source. If a match occurs between all corresponding bits of the two logic functions the output of NOR gate 95 remains 0 so that the Q of flip-flop 92 remains 1. When the first push button is released the binary counter is advanced to the next number because the clock input goes from 0 to 1. The process is repeated and when all logic functions have been compared (the output of the binary counter is 1, 1, 1) and if all logic functions match, the output of flip-flop 92 will remain 1 so the output of NAND gate 97 will be 0 and solenoid 98 will be activated. Every unsuccessful attempted comparison will be recorded by the tabulation of eight address comparisons without a reset by trial counter 99. If more than a preset number of unsuccessful attempted comparisons occurs then an alarm 100 will be triggered via NAND gate 101.

While a number of specific embodiments of the preent ikvention have been set forth in this specification, they are intended to be representative only and the scope of this application for Letters Patent is intended to be limited only by the scope and spirit of the appended claims.

Claims

We claim:

1. An n-dimensional logic function generation and comparison system for use as an electronic locking system comprising,

An n-dimensional counter capable of generating in electrical impulse form all numbers of a n-dimensional logic system;

A reference logic function source having a unique logic function stored at a plurality discrete addresses therein, each of said addresses having a one-to-one correspondence with a number in said n-dimensional logic system, said reference logic function source generating in electrical impulse form the logic function stored at a specific address upon receipt in electrical impulse form of said number corresponding to said address;

An unknown logic function source having a unique logic function stored at a plurality of discrete addresses, each of said addresses having a one-to-one correspondence with a number in said n-dimensional logic system, said unknown logic function source generating in electrical impulse form the logic function stored at a specific address upon receipt in electrical impulse form of said number corresponding to said address;

A comparator adapted to receive simultaneously said unique logic functions in electrical impulse form from said reference logic function source and said unknown logic function source, said comparator comparing said simultaneously received logic functions in stepwise progression, said comparator emitting a first electrical signal if all logic functions match and emitting a second and different electrical signal if at least one bit of one pair of said logic functions does not match; and

An electrically responsive instrumentality adapted to be energized or de-energized upon receipt of said first electrical signal.

2. The electronic locking system of claim 1 in combination with a trial counter and alarm circuit to monitor the number of attempted comparisons between the unknown logic function source and the reference logic function source and to register an alarm when more than a predetermined number of unsuccessful attempted comparisons have been made and a maximum voltage sensor to deactivate the locking system if a surge of current above a predetermined level is surged through the system.

3. The electronic locking system of claim 2 wherein said unknown logic function source is an m'th state to n'th state logic encoder.

4. The electronic locking system of claim 3 wherein said m'th state to nth state logic encoder is a decimal to binary encoder.

5. The electronic locking system of claim 2 wherein said n-dimensional system is the binary system, said counter is an oscillator driven binary counter and said reference and unknown logic function sources are read-only-memories and said unknown read-only-memory is detachably attachable with a socket having an array of electrical connectors therein to establish temporary electrical communication between the inputs of said unknown ROM and said binary counter and between the outputs of said unknown ROM and said binary comparator.

6. The electronic locking system of claim 5 wherein said read-only-memories are MOS devices.

7. The electronic locking system of claim 5 wherein said read-only-memories are fusible read-only-memories.

8. The electronic locking system of claim 5 wherein said read-only-memories are amorphous semiconductor read-only-memories.

9. The electronic locking system of claim 5 wherein said read-only-memories are avalanche induced electromigration read-only-memories.

10. The electronic locking system of claim 5 wherein said electrically responsive instrumentality is a solenoid-operated lock and wherein said first electrical signal from said comparator serves to energize said solenoid to open said lock.

11. The electronic locking system of claim 10 in combination with a recording means to record the time and place said unknown read-only-memory is presented for comparison and to record the identity of the authorized holder of the unknown read-only-memory.

12. An n-dimensional logic function generation and comparison system for use as a transient electronic locking system, comprising:

An n-dimensional counter capable of generating in electrical impulse form al numbers of an n-dimensional logic system;

At least one master reference logic function source having a unique logic function stored at a plurality of discrete addresses therein, each of said addresses having a one-to-one correspondence wtih a number in said n-dimensional logic system, said reference logic function source generating in electrical impulse form the logic function stored at a specific address upon receipt in electrical impulse form of said number corresponding to said address;

A tenant reference logic function source having a unique logic function stored at a plurality of discrete addresses therein, each of said addresses having a one-to-one correspondence with a number in said n-dimensional logic system, said reference logic function source generating in electrical impulse form the logic function stored at a specific address upon receipt in electrical impulse form of said number corresponding to said address;

An unknown logic function source having a unique logic function stored at a plurality of discrete addresses, each of said addresses having a one-to-one correspondence with a number in said n-dimensional logic system, said unknown logic function source generating in electrical impulse form the logic function stored at a specific address upon receipt in electrical impulse form of said number corresponding to said address, and said unknown logic function source having an indicator means to indicate whether said unknown source is an unknown tenant or a particular unknown master logic function source;

A comparator adapted to receive simultaneously said unique logic functions in electrical impulse form from the appropriate reference logic function source and said unknown logic function source, said comparator comparing said simultaneously received logic functions in stepwise progression, said comparator emitting a first electrical signal if all logic functions match and emitting a second and different electrical signal if at least one bit of one pair of said logic functions does not match; and

An electrically responsive instrumentatlity adapted to be energized or de-enerigzed upon receipt of said first electrical signal.

13. The transient electronic locking system of claim 12 wherein said n-dimensional system is the binary system, said reference and unknown logic function sources are read-only-memories, wherein said unknown read-only-memory is detachably attachable with a socket having an array of electrical connectors therein to establish temporary electrical communication between the inputs of said unknown read-only-memory and said binary counter and between the outputs of said unknown read-only-memory and said binary comparator, wherein said electrically responsive instrumentality is a solenoid-operated lock and wherein said first electrical signal emitted by said comparator energizes said solenoid to open said lock.

14. The transient electronic locking system of claim 13 in combination with a trial counter to monitor the number of attempts to compare said unknown logic function source with the appropriate reference logic function source, an alarm circuit to register an alarm and to deactivate said solenoid when more than a predetermined number of unsuccessful comparison attempts have been made, a maximum voltage sensor to deactivate said solenoid when a surge of current above a predetermined level is passed through the system, and a recording means to record the time and place said unknown logic function source is presented for comparison and to record the identity of the authorized holder of the unknown logic function source.

15. The transient electronic locking system of claim 14 wherien said read-only-memories are MOS devices.

16. The transient electronic locking system of claim 14 wherein said read-only-memories are fusible read-only-memories.

17. The transient electronic locking system of claim 14 wherein said read-only-memories are amorphous semiconductor read-only-memories.

18. The transient electronic locking system of claim 14 wherein said read-only-memories are avalanche induced electro-migration read-only-memories.