Synchronization Of Multiple Ink Jets

Abstract

A method is described for sequentially determining if drop formation for each jet in an array of ink jets is occurring at the proper time.

Description

PATENT APPLICATION OF INTEREST

U. S. Patent application Ser. No. 266,790 filed June 27, 1972, entitled "Ink Jet Synchronization and Failure Detection System," and having James D. Hill, et al., as inventors.

BACKGROUND OF THE INVENTION AND PRIOR ART

A multitude of systems have been proposed in the prior art utilizing ink jet printing techniques. Many of these devices have a plurality of ink jet heads arranged in an array or side by side with either simultaneous or sequential operation of the heads. In any ink jet system, synchronization is of prime importance. This relates to the fact that drops formed for printing need to be formed at a proper and synchronized time particularly with respect to charging potentials used in the system for deflection purposes.

SUMMARY OF THE INVENTION

In a preferred embodiment of the invention, a plurality of ink jet printing heads are monitored and controlled in a manner to obtain accurate synchronization of drops propelled from the heads.

OBJECTS

A paramount object of the present invention is to provide a system for synchronizing ink jet drop formation and propulsion in order to insure high quality and accurate printing.

The foregoing and other objects, features, and advantages of the invention will be apparent from the following more particular description of the preferred embodiment of the invention as illustrated in the accompanying drawings.

DRAWINGS

In the Drawings

FIG. 1 represents an ink jet system including a character generator and three ink jet nozzles or head assemblies with associated synchronizing circuitry.

FIG. 2 is an electronic switch circuit that is useful in the circuit of FIG. 1.

FIG. 3a illustrates the fundamentals of detector circuit while FIG. 3b illustrates the preferred embodiment of the detector circuit. The switching circuit of FIG. 2 is ultimately derived from the circuit of FIG. 3b.

FIG. 4 illustrates various timing relationships during a single drop interval in the system of FIG. 1.

DETAILED DESCRIPTION

The system of FIG. 1 includes a number of ink jet nozzle assemblies 1, 2, and 3 for forming and propelling drops of ink toward a record medium, not shown. The respective nozzle assemblies 1, 2, and 3 include crystals 6-8, charge electrodes 10-12, deflection electrodes 14-16, and sensor gutters 18-20. Each nozzle has a respectively associated charge electrode driver, designated 22-24. The charge electrode drivers 22-24 are controlled by the synchronization pulse generator 26 as well as a character generator 28. Initial control of the circuits is from master clock 30 and control logic 31.

As is known in the art, drops are formed by the respective nozzle assemblies in the form of streams of drops designated 33-35. During synchronization, a sequence of drops which, numerically, can be in a wide range as from only several drops to a hundred drops are directed to the respective gutters 18-20. Drops passing in the gutters 18-20 develop signals on lines 37-39 that are applied to the electronic switch circuit 40. Associated with switch circuit 40 is a detector amplifier circuit 41, the output of which is returned by line 42 to control logic 31.

Synchronization of the individual streams of drops formed by the nozzle assemblies 1-3 may be formed in a sequential fashion. That is, all of the synchronizing efforts for one nozzle assembly may be completed prior to initiation of efforts for any of the other nozzle assemblies. However, it is preferable to synchronize the respective nozzle assemblies in what might be characterized as a semi-parallel fashion.

With a semi-parallel arrangement, control signals are directed to the individual nozzle assemblies 1-3 in such a way that sequences of drops are propelled from the respective nozzle assemblies in rotation during drop synchronization procedures with signals developed from each assembly and corrective action taken with all assemblies, if and as required.

As is known, synchronization, may be achieved by varying the phase of the crystals with respect to the charging potentials applied to the respective charge electrodes 10-12. In the semi-parallel mode, all crystals are driven with the same phase signal initially. To start synchronization, a sequence of drops 33a, such as three drops, is formed and propelled, charged in nozzle assembly 1 and directed to gutter 18. This results in a signal on line 37 to switch circuit 40. Shortly thereafter separated by a few drops perhaps, a sequence of drops 34a is formed, propelled, and charged in nozzle assembly 2 and directed to gutter 19 to develop a signal. The signal is applied by line 31 to switch circuit 40. Shortly after that, and after a short interval of several drops, as before, another sequence of drops 35a is formed, propelled and charged in nozzle assembly 3 and directed to gutter 20 in order to develop a signal on line 39 for application to switch circuit 40. In this manner only a slight interval exists between the checking of each nozzle assembly and while a determination is made by control logic 31 as to the correction required to achieve synchronization for any particular nozzle, signals are developed for the other nozzles as well to at least initiate corrective action.

The charging of drops for synchronization purposes is customarily carried out in a manner similar to regular printing of characters and as described in the Hill, et al, application referred to previously.

Some of the relationships during a typical drop interval are illustrated in FIG. 4. One drop time is assumed to be 10 micro-seconds with a first portion of 2.5 micro-seconds constituting a forbidden time interval when drops should not be formed. Synchronization of drop formation with respect to charging preferably occurs in a 3 micro-second interval in the latter portion of the 10 micro-second drop interval. The forbidden time interval corresponds to the time when the charge electrode voltage is changing and thus drop formation should not occur at this time. If a drop is formed during the synchronization time illustrated then formation will occur in a correct relationship with respect to the charge electrode voltage and at a stable time.

In operation, if drops landing in the gutters 18-20 create no output, as an example, then the drops were formed outside of the synchronization time, that is improperly. Corrective action can then be taken by control logic 31 to change drop formation by either shifting the phase of the crystal device frequency for crystals 6-8 or changing the amplitude of the voltages applied to crystals 6-8, or by changing the phase of the voltage pulse (applied to the charge electrode) with respect to the crystal.

Comparable corrective action is required of course in the event of relatively low signals developed from gutters 18-20 and applied through switch circuit 40 and detector circuit 41 to logic 31. If a sufficient number of properly charged drops pass into gutter 18-20, then signal levels are developed that are of sufficient magnitude to indicate proper synchronization of drop formation and charging by charge electrodes 10-12. Thus, under such circumstances, no corrective action is required.

Some of the switching logic useful in the circuit of FIG. 1 and particularly in the switch circuit 40 is illustrated in FIGS. 2, 3a, and 3b.

The basic circuit of FIG. 3a uses an operational amplifier 45 with an FET (Field Effect Transistor) input which draws a negligible current, less than 0.5NA (nanoamperes) at 55.degree.C. Resistor 46 (R1) is a high value resistor such as 50 m.OMEGA. .+-. 5 percent carbon. Resistors 47 and 48 (R2 and R3) serve to increase the apparent feedback resistance as seen by amplifier A1. The voltage applied across R1 is determined by the ratio of R2 and R3 (minus input of amplifier 45 is at virtual ground). If R2 is 300.OMEGA. and R3 is 2.7k.OMEGA., 10 percent of the op-amp's output voltage is fed back to R1. The effective feedback resistance R.sub.FB is thus given by Equation 1:

R.sub.FB = R1 (R2 + R3/R2 ) (1)

as an example, if gutter current I.sub.G = 4NA and resistor R1 = 50m.OMEGA., V1 is virtual ground, then, neglecting bias current into amplifier 45, all the gutter current flows through R1. V2 = 50m.OMEGA. .times. 4NA = 0.2V if R2 = 300.OMEGA. and R3 = 2.7k.OMEGA., V3 must be as follows:

V3 = (.2V/R2) (R2 + R3)

= .2 (300 + 2700)/300 = 2.0 volts (2)

Capacitors 50 and 51 (C1 and C2) are chosen so that the gain of amplifier 45 tapers off at an appropriate frequency.

The circuit of FIG. 3b operates on the same basic principle as that in FIG. 3a except that a non-FET input, less expensive, amplifier 53 is used. A matched pair of junction Field Effect Transistors 55 and 56 provides a high input impedence buffer for amplifier 53. The matched pair of transistors is needed because of the wide variation of FET characteristics with currently available manufacturing procedures.

The method of synchronization is extended to synchronize "N" ink jets by using the circuits of FIG. 3b and "N" analog switches, as shown in FIG. 2. Using the principles of the circuits of FIGS. 3a and 3b, electronic logic determines if drop formation is occurring at the proper time. If it is not, the magnitude or the phase of the signal applied to the respective crystals 6-8, FIG. 1, is changed to shift drop formation to the desired point in time. Inputs on lines 37-39 are derived from FIG. 1 for the circuit of FIG. 2. The circuit of FIG. 2 includes matched pairs 60-62 of Field Effect Transistors, designated Q11 and Q21, Q12 and Q22, and Q13 and Q23, respectively, each pair having a respectively associated resistor 63-65 and a switch circuit 66-68.

The outputs of the switch circuits 66-68 are directed to the detector amplifier circuit 41. Resistors 63-65 correspond to resistor R1 designated 57 in FIG. 3b. The matched pairs 60-62 of Field Effect Transistors serve as high impedence buffers between the high impedence sensor inputs 37-39 (sensing gutters) and the lower impedence input to operational amplifier 70 on line 72. Switches 66-68, which are analog switches, serve to isolate the Field Effect Transistor pair 60-62 from one another. Switches 66-68 are operated by control logic 31 on line 44 representative of a cable operable in a timed sequence at inputs 44a, 44b and 44c, respectively. Preferably, only one switch 66-68 is coupled to amplifier 70 at any given time, the other switches being opened. By appropriate sequential closure of switches 66-68, the signals developed in gutters 18-20 reflected on lines 37-39 are sequentially scanned in order to determine what corrective action is required for synchronizing the ink jet strams of drops from the respective nozzle assemblies.

While not shown, it may be feasible to operate several ink jets from one crystal. One ink jet in a group attached to a single crystal could be used for synchronization. Then sufficient crystal assemblies could be used to provide the required number of jets. By combining the multiple jet per crystal technique with the sequential synchronizing cricuitry described above a significant reduction in the cost of multi-jet synchronization appears feasible.

Although the methods shown herein utilize the technique of sensing the stream current by means of a DC measurement, the same basic approach used here could work utilizing a non-contacting sensor. This would result in an AC measurement. The detector senses the sequence of charged drops passing by a small electrically isolated sensor near the gutter. This method has the advantage of not requiring direct sensor contact with the ink. Thus it is not as subject to contamination.

While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood skilled in the art that various changes in form and detail may be made without departure from the spirit and scope of the invention.

Claims

What is claimed is:

1. An ink jet synchronization system particularly suitable for apparatus utilizing a plurality of ink jets, comprising:

a plurality of nozzle assemblies for forming and propelling ink drops in respectively associated ink jet streams, each of said nozzle assemblies incorporating driving crystals, charge electrodes, and deflection electrodes,

means for driving said respective crystals at a predetermined frequency in order to form streams of drops for propulsion from said respective nozzle assemblies;

individual charge driving circuits interconnected with said charge electrodes, respectively, for producing a charge potential on drops passing therethrough, when required;

gutter-sensor means respectively associated with each of said nozzle assemblies, said gutter-sensor means being positioned for reception of drops propelled from said assemblies when said drops carry a particular predetermined charge level and said gutter-sensor means developing signals representative of charge levels on drops passing therethrough;

a detector circuit responsive to signal levels developed in said gutter-sensor means to provide a corrective signal in said system for insuring proper relationship of said crystal driving circuits and said charge driving circuits; and

switch circuit means interconnected for reception of signals from each of said gutter-sensor means and operable to supply signals from one and one only of said gutter-sensor means to said detector circuit during each of a number of succeeding synchronization testing intervals.

2. The apparatus of claim 1, further comprising:

control logic in said system for sequentially gating each of said charge driving circuits in order to develop a sequence of charged drops from each of said nozzle assemblies, each of the sequences of drops from the respective nozzle assemblies being separated by an inactive charge time interval;

means in said system for synchronously activating said switch circuit to receive developed signals from said gutter-sensor means during any time interval when charged drops are being received by said respective gutter-sensor means; and

means responsive to output signals from said detector circuit means for correcting the crystal drive or charge drive, as appropriate, to insure proper synchronization of drop formation and charging in the respective nozzle assemblies.

3. The apparatus of claim 2, wherein said switching means comprises individual Field Effect Transistor pairs and associated switch circuits operable in timed sequence:

a common operational amplifier; and

means interconnecting the respective switch circuits to the input of said operational amplifier in timed sequence during synchronization activities.

4. The apparatus of claim 1, further comprising:

control logic in said system for activating the crystal drive and charge electrode drive circuits associated with each of said respective nozzle assemblies and for applying corrective potentials as required for each of said nozzle assemblies, in turn, in order to complete the synchronization process for each respective nozzle assembly in turn prior to any synchronization activities with respect to the other nozzle assemblies.

5. The apparatus of claim 1, wherein individual drops are formed in successive drop intervals comprising a finite time interval, and further comprising:

control logic in said system for activating said charge driving circuits during an early portion of said drop time interval and for activating said crystal driving circuits during a later portion of said drop interval thereby achieving synchronization.