U.S. patent number 3,745,528 [Application Number 05/212,544] was granted by the patent office on 1973-07-10 for error correction for two tracks in a multi-track system.
This patent grant is currently assigned to International Business Machines Corporation. Invention is credited to Arvind Motibhai Patel.
United States Patent |
3,745,528 |
Patel |
July 10, 1973 |
ERROR CORRECTION FOR TWO TRACKS IN A MULTI-TRACK SYSTEM
Abstract
A system for correcting two tracks in error in a multi-track
data arrangement is provided. The message data Z.sub.1, Z.sub.2, .
. . Z.sub.k is encoded by adding two check bytes C.sub.1 and
C.sub.2 thereto which are generated from the message data which is
arranged in blocks of k bytes, where each byte has f bits of data
arranged in a cross track direction, where f = b .times. m and m
and b are integers >1 and k is an integer 2<k<2.sup.b. The
check bytes are generated in accordance with the equations: C.sub.1
= Z.sub.1 .sym. Z.sub.2 .sym. Z.sub.3 . . . .sym. Z.sub.k And
C.sub.2 = T.sup..lambda. Z.sub.1 .sym. T.sup.2.sup..lambda. Z.sub.2
.sym. . . . .sym. T.sup.k.sup..lambda. Z.sub.k Where T is the
companion matrix of a binary primitive polynomial g (x) of degree f
and .lambda. is an integer given by the expression: t(2.sup.f
-1)/(2.sup.b -1) In which t is any positive integer prime to
2.sup.b -1. The encoded message is decoded after usage (indicated
by the ' symbol) by first and second shift registers which generate
first and second syndromes from the encoded data in accordance with
the equations: S.sub.1 = C.sub.1 ' .sym. Z.sub.1 ' .sym. Z.sub.2 '
.sym. . . . .sym. Z.sub.k ' S.sub.2 = C.sub.2 ' .sym.
T.sup..lambda. Z.sub.1 ' .sym. T.sup.2.sup..lambda. Z.sub.2 ' .sym.
. . . .sym. T.sup.k.sup..lambda. Z.sub.k ' Error pointers are
provided for indicating the tracks in error and the bytes in error
in the indicated tracks are corrected in accordance with the error
patterns generated by processing the syndromes.
Inventors: |
Patel; Arvind Motibhai
(Wappingers Falls, NY) |
Assignee: |
International Business Machines
Corporation (Armonk, NY)
|
Family
ID: |
22791464 |
Appl.
No.: |
05/212,544 |
Filed: |
December 27, 1971 |
Current U.S.
Class: |
714/755;
G9B/20.053; 714/765 |
Current CPC
Class: |
G11B
20/1833 (20130101) |
Current International
Class: |
G11B
20/18 (20060101); G06f 011/12 () |
Field of
Search: |
;340/146.1AL,146.1AV,146.1AQ,172.5 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Atkinson; Charles E.
Claims
What is claimed is:
1. A system for correcting two tracks in error in a multi-track
data arrangement, comprising:
means for providing message data Z.sub.1, Z.sub.2, Z.sub.3, . . .
Z.sub.k arranged in blocks having k bytes arranged in a cross track
direction, each byte having f bits of data where f = b .times. m
where b and m are integers >1 and k is an integer
2<k<2.sup.b ;
means connected to said means for providing message data for
generating two check bytes from said message data in accordance
with the equations:
C.sub.1 = Z.sub.1 .sym. Z.sub.2 .sym. Z.sub.3 . . . .sym.
Z.sub.k
and
C.sub.2 = T.sup..lambda. Z.sub.1 .sym. T.sup.2.sup..lambda. Z.sub.2
.sym. . . . .sym. T.sup.k.sup..lambda. Z.sub.k
where T is the companion matrix of a binary primitive polynomial
g(x) of degree f and .lambda. is any integer given by the
expression t(2.sup.b -1)/(2.sup.b -1) in which t is any positive
integer prime to 2.sup.b -1;
means connected to said means for providing message data and to
said means for generating two check bytes for appending said two
check bytes to said message data to form an encoded message;
means connected to said means for appending said two check bytes to
said message data for utilizing said encoded message;
means connected to said utilization means for decoding said encoded
message denoted by Z.sub.1 ', Z.sub.2 ', . . . Z.sub.k ', C.sub.1
', C.sub.2 '; said decoding means including first and second shift
registers for generating first and second syndromes S.sub.1 and
S.sub.2 from said encoded message in accordance with the
equations:
S.sub.1 = C.sub.1 ' .sym. Z.sub.1 ' Z.sub.2 ' .sym. . . . .sym.
Z.sub.k '
and
S.sub.2 = C.sub.2 ' .sym. T.sup..lambda. Z.sub.1 ' .sym.
T.sup.2.sup..lambda. Z.sub.2 ' .sym. . . . .sym.
T.sup.k.sup..lambda. Z.sub.k '
means for providing error track pointer signals as inputs to said
decoder which identify the tracks in error;
error track parameters signal generating means connected to said
means for providing error track pointer signals for providing fixed
signals in accordance with the tracks indicated to be in error;
means connected to said error track parameters signal generating
means for generating control signals for the operation of said
decoder; and
error correcting means connected to said first and second shift
registers, to said means for providing identifying signals, to said
means for providing control signals, and to said utilization means
for providing error correction of the erroneous bytes in any two
indicated tracks in error.
2. A system according to claim 1, wherein said means for generating
said two check bytes includes a data distributor and first and
second feedback shift registers connected to said data distributor,
said first shift register providing modulo 2 addition of the
information bytes successively applied thereto from said data
distributor and said second shift register providing the product of
the contents thereof and the incoming byte from said data
distributor and the modulo 2 addition thereof with the product of
the contents thereof and the next input byte.
3. A system according to claim 2, wherein said second feedback
shift register has f data stages and a modulo 2 summing circuit at
the input to each stage, the feedback connections of each of said
stages of said feedback shift register are determined in accordance
with the digital "1" contents of the corresponding column of the
matrix T.sub.f .sup..lambda., the positions of the 1's in the
column determining feedback connections to the modulo 2 summing
circuits at the inputs of the shift register stages having
corresponding numerical positions in said feedback shift
register.
4. A system according to claim 1, wherein said error track
parameters signal generating means receives error track pointer
signals P.sub.1, P.sub.2, . . . P.sub.k, P.sub.k.sub.+1,
P.sub.k.sub.+2 from said means for providing error track pointer
signals and generates parameters x and y as binary numbers, new
pointers I.sub.1, I.sub.2, . . . I.sub.k identifying the first
erroneous data track, and the signals N.sub.0, N.sub.1 and N.sub.3
indicating respectively, 0, 1 and more than 2 tracks in error.
5. A system according to claim 4, wherein said error track
parameters signal generating means includes a plurality of logical
AND and NOT circuits having as inputs thereto the track in error
pointer signals P.sub.1, P.sub.2, . . . P.sub.k from said means for
providing pointer signals arranged in groups of increasing order by
a pointer value of 1 starting with P.sub.1, P.sub.1 P.sub.2,
P.sub.1 P.sub.2 P.sub.3, . . . P.sub.1 P.sub.2 P.sub.3 . . .
P.sub.k, all the pointer signals except the additional pointer
signal in each group being connected through one of said NOT
circuits so that an output I.sub.i is obtained from the AND circuit
in which the additional pointer signal has a "1" input thereby
identifying the first data track in error.
6. A system according to claim 5, wherein said error track
parameters signal generating means further includes a first
plurality of OR circuits, said I.sub.i signals identifying the
first track in error are grouped as inputs to said first plurality
of OR circuits, the grouping is predetermined in accordance with a
table wherein the output y parameter is obtained as a predetermined
b-bit binary number.
7. A system according to claim 4, wherein said error track
parameters signal generating means, further includes a second
plurality of AND circuits and a second and third plurality of OR
circuits said second plurality of AND circuits having error track
pointer signals as inputs thereto arranged in groups of pairs, said
pairs of said first group being all possible adjacent pairs, said
pairs of said second group being all possible pairs separated by
one error track pointer signal input, said pairs of said third
group being all possible pairs separated by two error track pointer
signal inputs, said pairs of said k.sup.th group being all possible
pairs separated by k-1 error track pointer signal inputs, the
outputs of each of said groups of second plurality of AND circuits
are connected to respective ones of said second plurality of OR
circuits whose outputs correspond to the j-i = 1 to the j-i = k-1
value; each of the j-i value outputs being connected as inputs to
said third plurality of OR circuits, the connections being
determined in accordance with a predetermined table giving said x
parameter as a b-bit binary number.
8. A system in accordance with claim 4, wherein said error track
parameters signal generating means further includes a combination
of a plurality of NOT circuits connected to an AND circuit, a `one
and only one` circuit, and a threshold circuit, each of said
circuits having the error track parameters signals from said error
track parameters signal generating means as inputs thereto and
having said signals N.sub.0, N.sub.1 and N.sub.3 as outputs
therefrom, respectively, representing 0, 1 and more than two tracks
in error.
9. A system in accordance with claim 4, wherein said means for
generating control signals includes counting means which are
energized to count down simultaneously with the shift signal for
said shift registers SR1 and SR2;
means for setting said counting means to the binary value of x
generated by said error track parameters signal generating means
and counting down to 0 in synchronism with the shifting of SR1 and
SR2 to introduce the parameter y into the error pattern e.sub.j
computation which is computed from the syndromes S.sub.1 and
S.sub.2 according to:
e.sub.j = T.sup.x.sup..lambda. [S.sub.1 .sym. T.sup.y.sup..lambda.
S.sub.2 ].
10. A system according to claim 9, wherein inhibiting means are
provided connected to the output of shift register SR2 for
inhibiting the e.sub.j output when j = k+2 and pointer
P.sub.k.sub.+2 is on indicating the k+2 track is in error.
11. A system according to claim 10, wherein said error correcting
means includes means for adding (modulo 2) error pattern e.sub.j,
erroneous read bytes Z.sub.1 ', Z.sub.2 ', . . . Z.sub.k ' and
syndrome S.sub.1 to obtain the corrected bytes Z.sub.1, Z.sub.2, .
. . Z.sub.k.
12. A system according to claim 4, wherein said decoding means
further includes an uncorrectable error indicating circuit
connected to said error track parameters signal generating means
which provides said N.sub.0, N.sub.1, and N.sub.3 signals, and to
said shift registers SR1 and SR2 which provide syndrome S.sub.1 and
error pattern e.sub.j signals, respectively; said N.sub.3 signal
indicating that more than two tracks are in error, and said N.sub.1
signal indicating that only one track is in error and that e.sub.j
is not 0 in all bit positions, and said N.sub.0 signal indicating
that no track is in error when e.sub.j or S.sub.1 is not 0 in all
bit positions.
Description
BACKGROUND OF THE INVENTION
This invention relates to error detection and correction and, more
particularly, to an improved error correcting code and system for
detecting and correcting two tracks in error in a multi-track data
arrangement.
In data communication systems as well as computers, the information
can be coded by adding redundant bits to the data message in such a
way that the message can be decoded with a practical amount of
apparatus to obtain the original information corrected in the event
an error has been introduced. Parallel data arrangements, that is,
arrangements where the information is contained in parallel bytes
arranged in a block of data, are used in computers and are well
known especially in multi-channel recording apparatus. In
co-pending application, Ser. No. 10,847, filed on Feb. 12, 1970,
now U.S. Pat. No. 3,629,824, encoding and decoding apparatus are
disclosed in which the redundant or check bits are associated with
the data in a cross byte or cross track direction. This co-pending
application sets forth a code capable of correcting one or more
errors within a single, multiple bit byte of data. The data is
divided into blocks which consist of k bytes of data (each of b
bits), plus two check bytes, each of b bits. The decoder is
effective in recovering the data without error when not more than a
single byte of the received message is in error no matter how many
bits may be in error in the single byte. In U. S. Pat. No.
3,319,223, filed Mar. 31, 1964, an error correcting code is
disclosed in which the check characters generated from the
information are added serially to the message block. The coding and
decoding is implemented by means of shift register circuits.
Another co-pending application, Ser. No. 99,490, filed Dec. 18,
1970, now U.S. Pat. No. 3,697,948 utilizes the above-identified
code but extends the capabilities thereof by combining therewith
pointer signals which extend the error correcting capability of the
arrangement to two bytes in error regardless of the number of bits
in error in each byte.
It is an object of the present invention to provide an improved
error control system in parallel data systems such as computer tape
recording systems and similar multi-channel recording
apparatus.
It is another object of the present invention to provide an error
detection and correction system based on a new code which can be
mechanized to provide two channel correction as well as detection
of a large percentage of other errors without increasing the
redundancy.
It is a further object of the present invention to provide an error
detection and correction system in which larger size characters or
bytes can be utilized without substantially increasing the encoding
and decoding time and hardware.
It is a further object of the present invention to provide an error
detection and correction code capable of providing correction for
two tracks in error in a multi-channel system when pointers for the
tracks in error are provided.
It is another object of the present invention to provide an error
detection and correction system in which all the necessary error
correction functions can be realized by means of the same pair of
shift registers.
The system for correcting two tracks in error in a multi-track data
arrangement consists of an encoding means for generating two check
bytes C.sub.1 and C.sub.2 for the message data Z.sub.1, Z.sub.2, .
. . Z.sub.k which is arranged in blocks having k bytes where each
byte has f bits of data extending in a cross track direction where
f = b .times. m where b and m are integers >1 and k is an
integer 2<k<2.sup.b. The check bytes are generated in
accordance with the equations:
C.sub.1 = Z.sub.1 .sym. Z.sub.2 .sym. Z.sub.3 . . . .sym.
Z.sub.k
and
C.sub.2 = T.sup..lambda. Z.sub.1 .sym. T.sup.2.sup..lambda. Z.sub.2
.sym. . . . .sym. T.sup.k.sup..lambda. Z.sub.k
where T is the companion matrix of a binary primitive polynomial
g(x) of degree f and .lambda. is any integer given by the
expression t(2.sup.f -1)/(2.sup.b -1) in which t is any positive
integer prime to 2.sup.b -1. The check bytes are appended to the
incoming message data to obtain the encoded data for use in a
multi-track data system. The encoded data is decoded after usage
(indicated by the ' symbol) by means of first and second shift
registers which generate first and second syndromes from the
encoded data in accordance with the equations:
S.sub.1 = C.sub.1 ' + Z.sub.1 ' .sym. Z.sub.2 ' .sym. . . . Z.sub.k
'
and
S.sub.2 = C.sub.2 ' .sym. T.sup..lambda. Z.sub.1 ' .sym. T.sup.2
.sup..lambda. Z.sub.2 ' .sym. . . . .sym. T.sup.k.sup..lambda.
Z.sub.k '
Error pointers are provided which indicate the tracks in error and
means are provided which locate the bytes in error in the tracks in
error which can then be corrected in accordance wIth the errors
indicated by the syndromes.
The foregoing and other objects, features and advantages of the
invention, will be apparent from the following more particular
description of a preferred embodiment of the invention, as
illustrated in the accompanying drawings.
FIG. 1 is a schematic diagram showing the data arrangement in a
multi-track data system.
FIG. 2 shows a block diagram for carrying out the encoding of the
present invention.
FIG. 3 is a schematic diagram showing the decoder arrangement for
the present invention.
FIG. 4 is a schematic diagram showing the organization of the first
shift register of the pair of shift registers used for encoding and
decoding in the error correction system of the invention.
FIG. 5 is a further schematic diagram showing the second shift
register of the pair of shift registers.
FIG. 6 shows the error track parameter generator used in the
decoder which includes the FIGS. 6a, 6b, 6c and 6d in its overall
arrangement.
FIG. 6a is a schematic diagram showing the logic network
connections for generating the i pointers.
FIG. 6b is a schematic logic diagram showing the generation of the
Y parameter.
FIG. 6c is a schematic logic diagram showing the generation of the
X parameter.
FIG. 6d is a schematic logic diagram for generating the control
signals N.sub.0, N.sub.1 and N.sub.3.
FIG. 7 is a schematic diagram showing the error corrector circuit
of the decoder.
FIG. 8 is a schematic logic diagram showing the arrangement for the
detection of a large percentage of uncorrectable errors.
It will be appreciated by those skilled in the art that this
invention can be applied to Information Handling Systems of various
capacities. The invention will, therefore, be first described in
algebraic terms which are applicable to any size system and
subsequently in terms of a specific system.
Data is processed by the system in blocks consisting of k bytes,
each byte having f bits of data where f = b .times. m. Here and
throughout, b and m designate integers >1 and k is an integer
2< k<2.sup.b. The values of f and k are to be considered
invariant for a particular embodiment, but are variously chosen for
embodiments of various capacities. A block of data is accordingly
designated Z.sub.1, Z.sub.2, . . . Z.sub.k wherein Z.sub.1
represents the first byte in the block, Z.sub.2 the second byte,
and so on to Z.sub.k which represents the k.sup.th and last byte.
The encoder calculates from the block of incoming data two check
bytes, (designated C.sub.1 and C.sub.2) each of f bits and appends
the check bytes to the k data bytes to generate the sent message of
k+2 bytes. The data format arrangement is shown in FIG. 1. The
check bytes are added in separate tracks, parallel and adjacent to
the tracks carrying the data bytes. Each byte Z.sub.i and C.sub.1
and C.sub.2 are f bit column vectors in the mathematical equations
throughout and can be explicitly written as: ##SPC1##
The check bytes C.sub.1 and C.sub.2 are computed from the
information bytes Z.sub.1, Z.sub.2, . . . Z.sub.k using the
following matrix equations:
C.sub.1 = Z.sub.1 .sym. Z.sub.2 .sym. . . . .sym. Z.sub.k (1)
C.sub.2 = T.sup..lambda. Z.sub.1 .sym. T.sup.2.sup..l ambda.
Z.sub.2 .sym. . . . .sym. T.sup.k.sup..l ambda. Z.sub.k (2)
wherein:
.sym. denotes the modulo 2 vector sum;
T is the companion matrix of a binary primitive polynomial g(x) of
degree f which will be developed further as equation (3). For every
f, there exists at least one primitive polynomial of degree f. For
a list of primitive polynomials, see W. W. Petersen, Error
Correcting Codes, M.I.T. Press, 1961.
T.sup.i is the i.sup.th power of the matrix T. (Computed using
modulo 2 operations).
.lambda. is any integer given by the expression:
t(2.sup.f -1)/(2.sup.b -1) in which t is any positive integer prime
to 2.sup.b -1. Since f = b .times. m, the above expression always
results in a positive integer. The use of .lambda. in this code has
particular significance, which will become apparent from the
discussion with respect to the preferred embodiment to follow.
In order to more clearly explain the invention, a specific value f
= 8 has been chosen. The polynomial g(x) of degree 8 can be
explicitly written as:
g(x) = g.sub.0 + g.sub.1 x g.sub.2 x.sup.2 + . . . g.sub.7 x.sup.7
+ g.sub.8 x.sup.8
where:
g.sub.0 = g.sub.8 = 1 and g.sub.i is either 0 or 1 for:
i = 1, 2, . . . 7
The companion matrix T of the polynomial g(x) is defined as:
##SPC2##
As was mentioned previously in the Background of the Invention,
co-pending application, Ser. No. 99,490, filed Dec. 18, 1970, now
U.S. Pat. No. 3,697,948 discloses a multi-track error correction
system having k data tracks and two check byte tracks. Two b-digit
check bytes are generated from k b-digit information bytes where
2<k<2.sup.b. It will be appreciated that in this prior art
system, the byte size b can be increased. However, the encoding and
decoding hardware increases considerably with the increase in size
of the bytes participating in the computation. Accordingly, these
prior art arrangements have attempted to keep the byte size as
small as possible while still satisfying the relation
2<k<2.sup.b.
There are a number of situations where an increase in the byte size
participating in the code word computation is desirable. For
example, in computer tape recording systems, dividing binary data
tracks into 8-bit bytes is preferred because of the 8-bit byte
organization of the main processor. Thus, an 8-bit byte error
correction arrangement would be preferred to the 4-bit byte
arrangement shown in the co-pending application.
The code generated in this invention is actually a shortened code
which possesses an added capability of detecting a certain
percentage of errors which cannot be corrected. The percentage R
can be estimated as:
R% = (1-shortened length/full length) .times. 100%
The full length is defined as 2.sup.b +1 and the shortened length
is defined as k+2, i.e., the maximum number of tracks on which the
code can be used versus the actual number of tracks. For example,
when k = 8, using a 4-bit byte gives a detection capability
estimated as 53 percent of the other errors as opposed to an
estimated 97 percent with an 8-bit byte arrangement.
Although the code generated in this invention is actually a
shortened form of a longer code, the encoding and decoding
apparatus required is equivalent to that required for the shortened
code rather than the longer code. Apparatus is also described for
encoding and decoding this special code by means of which two
tracks in error can be corrected when track pointers are provided.
The actual code generated as a result of this invention can best be
described through an example using 8-bit bytes. This arrangement
will also be contrasted with the 4-bit byte arrangement of the
prior art so that the advantages thereof can better be appreciated.
The binary form of the parity check matrix for the 4-bit byte code
in its full length is given by: ##SPC3##
where 0.sub.4 and I.sub.4 are 4 .times. 4 "zero" and "identity"
matrices and T.sub.4 is the companion matrix of a degree 4
primitive polynomial. One such polynomial is 1 + x.sup.3 + x.sup.4.
Accordingly, T.sup.4 is given by: ##SPC4##
Similarly, the parity check matrix for the 8-bit byte code in its
full length is given by: ##SPC5##
where 0.sub.8 and I.sub.8 are 8 .times. 8 "zero" and "identity"
matrices and T.sub.8 is the companion matrix of the primitive
polynomial 1 + x + x.sup.3 + x.sup.5 + x.sup.8. ##SPC6##
Note that T.sub.4.sup.i are elements of the Galois Field
GF(2.sup.4) and T.sub.8.sup.i are elements of the Galois Field
GF(2.sup.8). These elements have the properties that T.sub.4,
T.sub.4.sup.2, . . . , T.sub.4.sup.15 are all distinct and
T.sub.4.sup.15 equals I.sub.4 and T.sub.8, T.sub.8.sup.2, . . . ,
T.sub.8.sup.255 are all distinct and T.sub.8.sup.15 equals I.sub.8.
The Galois Field GF(2.sup.8) contains a subfield which is
isomorphic to GF(2.sup.4). The elements of this subfield are given
by:
T.sub.8 .sup..lambda., T.sub.8.sup.2 .sup..lambda., . . .
T.sub.8.sup.15.sup..lambda.
where:
.lambda. = t(2.sup.8 -1)/(2.sup.4 -1)
for any t prime to (2.sup.4 -1). One such .lambda. is 68. These
subfield elements have the property:
T.sub.8 .sup..lambda., T.sub.8.sup.2 .sup..lambda., . . .
T.sub.8.sup.15.sup..lambda.
are all distinct T.sub.8.sup.15.sup..lambda. = I.sub.8.
Furthermore, T.sub.8.sup.i.sup..lambda. and T.sub.4.sup.i possess a
one-to-one relationship in that the two sets are isomorphic in the
"Sum" and "Product" operations of the corresponding Galois Field.
Referring to the 8-bit byte code given by the following parity
check matrix: ##SPC7##
It is apparent that this code possesses the same mathematical
structure as that of the 4-bit byte code given by the parity check
matrix of equation (4). All the columns in the matrix of equation
(8) have an equivalent column in the matrix of equation (6). For
example, with:
.lambda. = 68, T.sub.8.sup.5 .sup..lambda. = T.sub.8.sup.340 =
T.sub.8.sup.255 . T.sub.8.sup.85 = T.sup.85
Thus, it can be seen that the fifth column in equation (8) is
equivalent to the 85th column in equation (6). It can be seen from
the above, that the code constructed using the subfield elements
T.sup.i .sup..lambda. is a shortened form of the code given by
equation (6). The code can be further shortened in the usual
manner. For example, the 8-track arrangement can be encoded using
the parity check matrix: ##SPC8##
Accordingly, for .lambda. = 68, the T.sub.8 .sup..lambda. is given
by: ##SPC9##
The preferred embodiment of this invention will be illustrated
using the code defined in matrix (9) in an 8-track arrangement with
8-bit bytes. Accordingly, the two check bytes C.sub.1 and C.sub.2
are computed from the information bytes Z.sub.1, Z.sub.2, Z.sub.3,
Z.sub.4, Z.sub.5, Z.sub.6 using the following equations:
C.sub.1 = I.sub.8 Z.sub.1 .sym. I.sub.8 Z.sub.2 .sym. . . . .sym.
I.sub.8 Z.sub.6 (11) C.sub.2 = T.sub.8 .sup..lambda. Z.sub.1 .sym.
T.sub.8.sup.2 .sup..lambda. Z.sub.2 .sym. . . . .sym. T.sub.8.sup.6
.sup..lambda. Z.sub.6 (12)
after the message has been encoded and utilized at the recorder,
the read message bytes are transmitted or conveyed to the decoder.
The message is distributed by a read message distributor which
sends the encoded message in parallel to a pair of shift registers
SR1 and SR2. The decoder computes two expressions known as the
syndrome S.sub.1 and S.sub.2 defined as:
S.sub.1 = C.sub.1 ' .sym. Z.sub.1 ' .sym. Z.sub.2 ' .sym. . . .
.sym. Z.sub.k ' (13) S.sub.2 = C.sub.2 ' .sym. T.sup..lambda.
Z.sub.1 ' .sym. T.sup.2 .sup..lambda. Z.sub.2 ' .sym. . . . .sym.
T.sup.k .sup..lambda. Z.sub.k ' (14)
The received message byte Z.sub.1 ', Z.sub.2 ', . . . Z.sub.k ',
C.sub.1 ', C.sub.2 ' are the read message bytes corresponding to
the recorded bytes Z.sub.1, Z.sub.2, . . . Z.sub.k, C.sub.1,
C.sub.2, respectively. As was previously mentioned, there may be
errors in up to two tracks causing errors in the corresponding
bytes. These erroneous tracks are designated by track numbers i and
j and are identified by pointer signals P.sub.i and P.sub.j in the
form of logical "1." For convenience, it is required that i
.ltoreq. j, 1 .ltoreq. i .ltoreq. k and 1 .ltoreq. j .ltoreq. k +
2. The case, where two indicated erroneous tracks are the check
tracks, is ignored.
The "pointer" signals are derived from the system in which the
error correction is taking place. Of course, there are various
means of generating "pointer" signals such as is set forth in
corresponding U. S. Pat. application, Ser. No. 40,836, filed May
26, 1970, entitled, "Enhanced Error Detection and Correction For
Data Systems." In this application, the quality of the record/read
back operations on a real time basis is used as pointers to
possible error conditions.
The syndromes generated from the encoded data bytes and check bytes
contain the error patterns. These error pattern bytes e.sub.i and
e.sub.j in the bytes corresponding to the tracks i and j (when i =
j, we assume e.sub.j = 0). S.sub.1 and S.sub.2 have the algebraic
equivalent:
e.sub.i .sym. e.sub.j if i < j < k + 2 S.sub.1 = (15) e.sub.i
if j = i or k + 2
T.sup.i .sup..lambda. e.sub.i .sym. T.sup.j .sup..lambda. e.sub.j
if i<j<k+1 S.sub.2 =T.sup.i.sup..lambda. e.sub.i if j=i or
k+l (16) T.sup.i.sup..lambda. e.sub.i .sym. e.sub.j if j=k+2
These expressions can be solved for e.sub.i and e.sub.j as
follows:
e.sub.j =T.sup.x.sup..lambda. [S.sub.1 .sym. T.sup.y.sup..lambda.
S.sub.2 ] if j.noteq.k+2 (17) S.sub.1 .sym. e.sub.j if j.noteq.k+2
e.sub.i = (18) S.sub.1 if j = k + 2
wherein:
[T.sup.(j.sup.-i).sup..lambda. .sym. I].sup.-.sup.1 if
i<j<k+1 T.sup.x.sup..lambda. = (19) I if j=i or k+1
and:
y = -i modulo 2.sup.b -1 (20)
For each value j-i, the values of parameter x and for each value of
i, the parameter y are fixed. These parameters can be computed
algebraically. For example, in the preferred embodiment where
T.sup..lambda. = T.sub.8.sup.68 as given in equation (10), the
values of x and y are tabulated in Tables 1 and 2. ##SPC10##
Using the above computed values of x and y, the errror pattern
e.sub.j is computed from the syndromes S.sub.1 and S.sub.2
according to equation (17). The erroneous bytes Z.sub.i ' and
Z.sub.j ' can then be corrected using the error pattern e.sub.j and
the syndrome S.sub.1 to produce the corrected bytes Z.sub.i and
Z.sub.j since:
Z.sub.i ' .sym. S.sub.1 .sym. e.sub.j if j .noteq.k + 2 Z.sub.i =
(21) Z.sub.i ' .sym. S.sub.1 if j = k + 2
Z.sub.j =Z.sub.j ' .sym. e.sub.j (22)
In summary, the decoding process consists of:
1. Computing the syndromes S.sub.1 and S.sub.2 from the received
message bytes Z.sub.1 ', Z.sub.2 ', . . . Z.sub.k ', C.sub.1 ',
C.sub.2 ' according to equations (3) and (4).
2. Computing the error pattern e.sub.j from the syndromes S.sub.1
and S.sub.2 according to equation (17) with proper values of
parameters x and y from precalculated tables.
3. Correcting the erroneous bytes with the error pattern e.sub.j
and the syndrome S.sub.1 according to equations (21) and (22).
4. Detection of the uncorrectable errors according to the
following:
4a. When more than two tracks are indicated as being in error, the
code cannot provide reliable error correction.
4b. When two tracks are indicated as being in error, the error
pattern bytes e.sub.i and e.sub.j have unique values.
4c. When exactly one track is indicated as being in error (the case
where i is equal to j), then the error pattern byte e.sub.j must be
0 in all bit positions. If the computed e.sub.j is not 0 in all bit
positions, then this is interpreted as detection of some other
errors.
4d. When no track is indicated as being in error, then the
syndromes S.sub.1 and S.sub.2 and, consequently, the error pattern
bytes e.sub.i and e.sub.j must be 0 in all bit positions. If not,
this is interpreted as detection of errors.
Utilizing the previous example of 8-bit bytes, it can be seen from
FIG. 2, that the data Z.sub.1, Z.sub.2, . . . Z.sub.k in forms of
blocks of equal size bytes is received at the input 9 of the
encoder 10. The received data is distributed by a data distributor
to shift registers SR1 and SR2. The distributor 12 applies the
incoming data to these shift registers in parallel. The shift
registers SR1, SR2 perform the computations previously described to
generate the check bytes C.sub.1 and C.sub.2. These check bytes are
appended to the message data at the output 14 of the encoder 10.
This encoded data is sent to the multi-track recorder or
transmitter for utilization. FIGS. 4 and 5 show the shift registers
SR1 and SR2, respectively. Each shift register contains 8 binary
storage elements (0) . . . (7) with appropriate feedback
connections and modulo 2 summing networks at each input stage. It
is implied that with a time control signal, the shift register
shifts the contents while simultaneously receiving the new input.
Shift register devices of this type are widely known and given the
feedback connection, it can be physically constructed from
available logic hardware in many different ways.
Referring to FIG. 4, each input bit Z(0) . . . Z(7) of the 8-bit
byte is applied to a separate modulo 2 summing circuit 16 at the
input to each of the eight separate shift register storage elements
18. The output 20 of each binary storage element 18 is fed back via
a feedback connection 22 to the modulo 2 adding circuit 16 at the
input thereto along with the new input.
In FIG. 5, each of the 8-bits Z(0) . . . Z(7) of an 8-bit byte are
shown as inputs to the modulo 2 adder circuits 20 - 27 at the input
to each storage element of the shift register. The outputs 30 - 37
of each of the binary storage elements (0) . . . (7) are connected
to certain ones of the modulo 2 adder circuits 20 - 27 in
accordance with the columns of the matrix T.sub.8.sup.68 which is
given in equation (10). For example, the output 30 of the 0.sup.th
storage element is connected back to the modulo 2 adder circuits 21
and 24 at the inputs of the first and fourth stages of the shift
register. These connections are made in accordance with the
0.sup.th column of T.sub.8.sup.68 which has 1's in the first and
fourth positions. The new 8-bit vector input is entered into the
register via the modulo 2 adding circuits 20 - 27 simultaneously
with the feedback mentioned. If an 8-digit byte X represents the
present contents of shift register SR1 and shift register SR2 and Y
representing the input is entered with a shifting operation; then
the next contents in shift register SR1 is Y .sym. X and in shift
register SR2 is Y .sym. T.sub.8.sup.68. X.
The information is entered into the shift registers SR1 and SR2 in
reverse order, that is, Z.sub.k is entered first and Z.sub.1 is
entered last. After the last byte Z.sub.1 has entered, the
registers are shifted one more time with a 0 input.
The contents of shift register SR1 will be Z.sub.1 .sym. Z.sub.2
.sym. . . . .sym. Z.sub.k which represents the first check byte.
The contents of shift register SR2 will be T.sup..lambda. Z.sub.1
.sym. T.sup.2.sup..lambda. Z.sub.2 .sym. . . . .sym.
T.sup.k.sup..lambda. Z.sub.k which is the second check byte. At the
start time of the encoder 10, t.sub.0, the binary counter 40 is set
to k + 1. The counter counts down in synchronism with the timing
control signal. At count 0, the last shift of shift register SR1
and SR2 generates the respective check bytes. The count 0 signal
obtained from the counter 40 closes the switches SW1 and SW2 after
a unit time delay (during the next timing signal).
Referring to FIG. 3, the decoder 42 receives the encoded read or
utilized message bytes Z.sub.1 ', Z.sub.2 ', . . . Z.sub.k ',
C.sub.1 ', C.sub.2 ' and the pointers P.sub.1, P.sub.2, . . .
P.sub.k, P.sub.k.sub.+1, P.sub.k.sub.+2 which indicate the tracks
in error. The decoder 42 computes from these inputs the corrected
data bytes Z.sub.1, Z.sub.2, . . . Z.sub.k or generates an
uncorrectable error signal E. The symbol represents the corrected
data.
The decoder 42 first computes the syndromes S.sub.1 and S.sub.2 in
shift registers SR1 and SR2, as shown in FIGS. 4 and 5 from the
read or received encoded message bytes Z.sub.1 ', Z.sub.2 ', . . .
Z.sub.k ', C.sub.1 ', C.sub.2 ' according to equations (3) and (4).
The message bytes Z.sub.k ', Z.sub.k.sub.-1 ' . . . Z.sub.1 ' are
applied to the shift registers SR1 and SR2 in that order by the
read message distributor 44. Of course, the decoding is being
performed to correct any errors that may have been introduced to
the message as a result of the utilization thereof, either in the
recorder or in the transmission with respect thereto. As each byte
of the input message is received at the shift registers SR1 and
SR2, the registers are simultaneously shifted by means of a time
control signal. After the byte Z.sub.1 ' has entered, the byte
C.sub.1 ' is entered into shift register SR1 and the byte C.sub.2 '
is entered into shift register SR2 while shifting the registers
once. The contents of shift register SR1 is now C.sub.1 ' .sym.
Z.sub.1 ' .sym. Z.sub.2 ' .sym. . . . .sym. Z.sub.k ' which is the
syndrome S.sub.1. The contents of shift register SR2 is now C.sub.2
' .sym. T.sup..lambda. Z.sub.1 ' T.sup.2.sup..lambda. Z.sub.2 '
.sym. . . . .sym. T.sup.k.sup..lambda. Z.sub.k ' which is the
syndrome S.sub.2. The syndrome generation is controlled by the
timing control signal. The binary counter B.sub.1 is set to k + 1
at time t.sub.0 (starting time for the decoder) and counts down in
synchronism with the timing control signals. At count 0, the last
shift of shift registers SR1 and SR2 results in S.sub.1 as the
contents of the shift register SR1 and S.sub.2 as the contents of
shift register SR2.
The count 0 signal from the counter B.sub.1 starts counter B.sub.2
after a unit time delay, that is, with the next timing control
signal. B.sub.2 is set to the binary value y at time t.sub.0.
Counter B.sub.2 counts down in synchronism with the timing control
signal which continuously shifts registers SR1 and SR2 also. At the
count 0, in the counter B.sub.2, the switch SW1 is closed. This
causes the contents of shift register SR1 which is S.sub.1 to enter
shift register SR2. Accordingly, the contents of shift register SR2
is S.sub.1 .sym. T.sup.y.sup..lambda. S.sub.2 and the contents of
shift register SR1 remains S.sub.1.
The count 0 signal generated by counter B.sub.2 initiates B.sub.3
after a unit time delay, that is, with the next timing control
signal. Counter B.sub.3 is set to the binary value x at time
t.sub.0. Counter B.sub.3 counts down in synchronism with the timing
control signal which continuously shifts registers SR1 and SR2. At
the count 0 in the counter B.sub.3, the last shift of SR1 and SR2
produces T.sup.x.sup..lambda. (S.sub.1 .sym. T.sup.y.sup..lambda.
S.sub.2) as the contents of SR2 while the contents of shift
register SR1 remains S.sub.1.
The count 0 signal from the counter B.sub.3 closes the switches SW2
and SW3 after a unit time delay (with the next timing control
signal). The switch SW3 is also controlled by the pointer signal
P.sub.k.sub.+2 as described later in connection with the error
corrector circuit.
FIG. 6 shows schematically the error track parameters generator 46
which generates the parameters x and y as binary numbers from the
input pointer signals P.sub.1, P.sub.2, . . . P.sub.k,
P.sub.k.sub.+1, P.sub.k.sub.+2. The error track parameters
generator 46 also generates the new pointers I.sub.1, I.sub.2, . .
. I.sub.k identifying the first erroneous data track which is
called the Ith track. It also generates the signals N.sub.0,
N.sub.1, N.sub.3, indicating respectively, 0, 1 and more than 2
tracks in error. The error track parameters generator 46 of FIG. 6
indicates that the logic circuits 6a, 6b, 6c and 6d are included in
order to obtain the above-noted outputs.
Referring to FIG. 6a, there is shown the logic network connections
for generating the I pointers I.sub.1 . . . I.sub.6 which
identifies the first erroneous data track called the Ith track.
Combinations of the pointer signals P.sub.1 . . . P.sub.6 are
utilized as inputs to AND circuits 50. The combinations are
arranged in successively increasing order of 1. For example, the
grouping is P.sub.1, then P.sub.1, P.sub.2 followed by P.sub.1,
P.sub.2, P.sub.3, etc. It should be observed that all of the inputs
except the additional input in each of the combinations is inverted
in a NOT circuit at the inputs to the respective AND circuits 50.
It can be seen that as long as all the pointer inputs are 0, there
will be no output from any of the AND circuits. However, the first
non-zero pointer signal will be indicated by an output from its
corresponding AND circuit. That is, the AND circuit 50 having that
pointer as the additional pointer input.
FIG. 6b has as inputs the I pointers generated in FIG. 6a. This
circuit generates the y parameters as a b-bit binary number
y.sub.3, y.sub.2, y.sub.1, y.sub.0. The input combinations of the I
pointers is determined according to Table 3. The logic connections
can be determined by retabulating y as a b-bit binary number with
the corresponding I pointers as shown in Table 3.
Table 3. Parameter y as a binary member
y as binary number i Indicated by y y.sub.3 y.sub.2 y.sub.1 y.sub.0
1 I.sub.1 14 1 1 1 0 2 I.sub.2 13 1 1 0 1 3 I.sub.3 12 1 1 0 0 4
I.sub.4 11 1 0 1 1 5 I.sub.5 10 1 0 1 0 6 I.sub.6 9 1 0 0 1
therefore, the signals y.sub.3, y.sub.2, y.sub.1 and y.sub.0 are
generated from I.sub.1 , I.sub.2, . . . I.sub.6. The input I
pointer signals are combined into three groups of three and then a
group of all six. These are inputted to OR circuits 52 which
produce the y parameter outputs. It will be appreciated that
y.sub.3 is always a logical one when any of the I signals is
logical 1. y.sub.2 is a logical 1 when I.sub.1 or I.sub.2 or
I.sub.3 is a logical 1. y.sub.0 is a logical 1 when I.sub.2 or
I.sub.4 or I.sub.6 is a logical 1.
FIG. 6c shows a logic circuit diagram which generates the x
parameter as a b-bit binary number x.sub.3, x.sub.2, x.sub.1,
x.sub.0 from the P pointers. Before the x parameter can be
generated, the (j-i) values must be generated from the track
pointers P.sub.1, P.sub.2, . . . P.sub.6. This is accomplished by
combining the P pointers into pairs of inputs to separate AND
circuits 56. It can be seen that the input paired arrangement of
pointers has the first group of pairs separated by the value 1,
while the second group of pairs is separated by the value 2, the
third group by the value 3, the fourth group by the value 4 and the
last pair by the value 5. Each of these P pointer pairs is fed to
respective AND circuits 56 whose outputs are inputted to
appropriate OR circuits 58 to obtain the appropriate j-i value. For
example, j-i = 1 is obtained from the OR circuit 58 connected to
the AND circuits 56 having as inputs thereto the pairs separated by
1. Similarly, the other OR circuits 58 have connections thereto
based on similar properties. For example, the second OR circuit 58
has an output value j-i = 2, while the third has a value j-i = 3
and the fourth has a value j-i = 4. Each of these j-i values are
connected to the appropriate OR circuits 60. The connections for
the associated functions are determined by means of Table 4 which
is derived from Table 1. The procedure is similar to that in
generating the connections for the previous parameter. The
parameter x then is obtained as a b-bit binary number with signals
x.sub.3, x.sub.2, x.sub.1, x.sub.0.
Table 4. Parameter x as a binary number
x as a binary number j-i Function x x.sub.3 x.sub.2 x.sub.1 x 0 or
j=7 N.sub.1 +P.sub.7 0 0 0 0 0 1 P.sub.1 P.sub.2 +P.sub.2 P.sub.3
+P.sub.3 P.sub.4 +P.sub.4 P.sub.5 +P.sub.5 P.sub.6 3 0 0 1 1 2
P.sub.1 P.sub.3 +P.sub.2 P.sub.4 +P.sub.3 P.sub.5 +P.sub.4 p.sub.6
6 0 1 1 0 3 P.sub.1 P.sub.4 +P.sub.2 P.sub.5 +P.sub.3 p.sub.6 11 1
0 1 1 4 P.sub.1 P.sub.5 +P.sub.2 P.sub.6 12 1 1 0 0 5 P.sub.1
P.sub.6 5 0 1 0 1
note that P.sub.k.sub.+2 does not participate in the determination
of the values j-i. Also, j-i = 0 or j = k+2 does not generate
logical 1 on any of the x.sub.0, x.sub.1, x.sub.2, x.sub.3 signal
outputs.
FIG. 6d shows the circuit arrangement for generating the control
signals N.sub.0, N.sub.1 and N.sub.3. N.sub.0 indicates that none
of the track pointers P.sub.1, P.sub.2, . . . P.sub.k.sub.+2 are
on. N.sub.1 indicates only 1 is on. N.sub.3 indicates that more
than two track pointers are on. The N.sub.0 signal is generated as
an output from an AND circuit 62 having the 8 pointer signals
P.sub.1 . . . P.sub.8 as inputs thereto. It can be seen that any
one of the pointer inputs being on will cause no output from the
AND circuit 62. Thus, the absence of N.sub.0 indicates that there
is an energized track pointer. The N.sub.1 output is obtained from
a `one and only one` circuit 64 which likewise has the pointers
P.sub.1 through P.sub.8 as inputs thereto. The output N.sub.1 will
only by obtained from circuit 64 when only one of the pointer
inputs thereto is energized. The output N.sub.3 is obtained from a
threshold network 66 which provides a logical one output when more
than two of the inputs have logical 1's.
Referring to FIG. 7, there is shown the error corrector circuit 68
which produces the corrected data bytes Z.sub.1, Z.sub.2, . . .
Z.sub.k by combining the read data bytes Z.sub.1 ', Z.sub.2 ', . .
. Z.sub.k ', the error pattern byte e.sub.j and the pointer signals
I.sub.1, . . . I.sub.k and P.sub.1 . . . P.sub.k. The combining is
done in accordance with the equations (21) and (22). These two
equations are interpreted as follows.
If j = k + 2, i.e., the pointer P.sub.k.sub.+2 is on, then e.sub.j
the output of SR2 should be inhibited. The inhibiting is done by
AND gates (switch SW3) as shown in FIG. 3. Otherwise, e.sub.j is
added (modulo 2) to the erroneous read bytes and S.sub.1 is added
to the first erroneous read byte. This is accomplished by a set of
8 modulo 2 summing networks 70 and 2 sets of 8 AND gates 72,74 for
each data byte Z.sub.1 ', Z.sub.2 ', Z.sub.3 ', Z.sub.4 ', Z.sub.5
', Z.sub.6 ' as shown in FIG. 7. The first set of 8 AND gates 72
acts like a normally closed gate controlled by the corresponding
track pointer signal and passes the e.sub.j byte only when that
track pointer is on. The second set of 8 AND gates 74 are
controlled by the corresponding I signal and pass syndrome S.sub.1
only when that I pointer is on. The set of 8 modulo 2 summing
networks 70 combine the input signals Z.sub.i ', e.sub.j and
S.sub.1 to produce the corrected byte Z.sub.i.
to FIG. 8, there is shown the uncorrectable error indicator logic
circuit 80 for detection of a large percentage of uncorrectable
errors. This circuit generates an error indicator signal E when one
of the following happens:
1. N.sub.3 is on indicating more than two tracks are in error. This
can be seen from the N.sub.3 input to the last OR circuit 81.
2. N.sub.1 is on indicating that only one track is in error and
that e.sub.j, the output of SR2, is not 0 in all bit positions.
This is accomplished by having N.sub.1 and e.sub.j .noteq.0 signals
as inputs to an AND circuit 82, the output of which forms one of
the inputs to the OR circuit 81. The e.sub.j .noteq. 0 signal is
generated by an OR circuit 83 which receives all of the e.sub.j
bits as its input.
3. N.sub.0 is on indicating that no track is in error when e.sub.j,
the output of SR2, or S.sub.1, the output of SR1, is not 0 in all
bit positions. This is accomplished by deriving an S.sub.1 .noteq.
0 signal from OR circuit 85 which has all the bits of S.sub.1 as
inputs thereto. The S.sub.1 .noteq. 0 signal is applied as an input
to AND circuit 84 along with the N.sub.0 input. The AND circuit 84
output is connected to OR circuit 81. The e.sub.j .noteq. 0 signal
and the N.sub.0 signal are connected as inputs to an AND circuit 86
whose output forms another input connection to OR circuit 81. Thus,
any one of the inputs N.sub.0, N.sub.1 and N.sub.3, under the
conditions enumerated above, produces an output signal E from OR
circuit 81 indicating detection of uncorrectable errors.
While the invention has been particularly shown and described with
reference to a preferred embodiment thereof, it will be understood
by those skilled in the art that the foregoing and other changes in
form and detail may be made therein without departing from the
spirit and scope of the invention.
* * * * *