Integrated Current Supply Circuit

Abstract

DC biasing currents for a monolithic integrated circuit are obtained from a single regulated current reference source supplying current through first and second series connected diodes to establish points of reference potential. Some of the current source transistors which are referenced to this regulated current source have the base-emitter junctions thereof connected across the first diode, and the emitter current of these current source transistors is collected and added to the current from the regulated current source and supplied through the second diode. This second diode, with a larger regulated current flowing therethrough, is used to reference additional current source transistors for substantially larger currents without necessitating the use of high ratio area scaling of the emitter areas of these current source transistors.

Parent Case Text

This is a continuation, of application Ser. No. 186,269, filed Oct. 4, 1971, now abandoned.

Description

BACKGROUND OF THE INVENTION

In monolithic integrated circuits, several DC biasing currents from different current sources normally are required. The different biasing currents on a single monolithic integrated circuit chip can range in value over a considerable range, for example, from 10 microamps to a milliamp or more. Often all of these biasing currents are derived from a single regulated current reference, which is utilized to conserve the area of the chip consumed by the reference current circuit portions, and which is regulated to be independent of voltage and temperature variations.

The current provided by the regulated current source normally is supplied through a reference diode to establish a point of reference potential, and the base-emitter junctions of the current source transistors which supply the various biasing currents are connected directly across this diode. As a result, the biasing currents exhibit the same stability as the reference current. Usually, the emitter area of the reference diode is some multiple (greater or less than one) of the emitter area of the current source transistors and thus allows the regulated currents to be approximately ratioed to the regulated reference current. Optimally, the emitter area of the reference diode is selected to utilize the smallest possible die area to provide the current source transistors with both the largest and smallest currents required by the circuit. Even with such a selection, however, a high ratio of emitter area scaling often is necessary, with the area of the largest emitter for a current source transistor being many times the area of the emitter of the reference diode (as much as 100 times). Area scaling of this magnitude consumes a large area of the chip and is undesirable from an economical standpoint.

Another technique has been to use resistors in series with the emitters of the reference diode and current source transistors. The ratio of the values of the emitter resistors determines the relative ratios or magnitudes of the currents supplied by the various current source transistors. These currents are referenced to the regulated current through the emitter resistor of the reference diode. Once again, however, if large current ratios are required in the circuit, a high ratio of the values of the emitter resistors also is necessary. This also results in undesirable consumption of large areas of the integrated circuit chip. In addition, such resistors result in the unnecessary consumption of power.

SUMMARY OF THE INVENTION

Accordingly, it is an object of this invention to provide an improved integrated current supply circuit.

It is another object of this invention to provide an improved integrated current supply circuit which supplies the same range of biasing currents but with lower emitter area ratios of the various current source transistors to the reference diode than heretofore required.

It is a further object of this invention to combine currents from some biasing current sources in an integrated circuit with the current from the common reference current source to provide an additional higher reference current through a reference diode to control other biasing current sources.

In accordance with a preferred embodiment of this invention: an integrated current supply circuit includes a reference current source connected in series with first and second diodes, in the order named, between a pair of voltage supply terminals. The diodes are poled to conduct current in their forward direction from the current source to one of the supply terminals. First and second utilization circuits are provided, each of which is supplied with a biasing current from corresponding first and second current source transistors, respectively. The base-emitter path of the first current source transistor is connected across the first one of the diodes to provide the biasing current for the first utilization circuit. The base-emitter path of the second current source transistor is connected across the second diode. This diode has a higher current flowing through it than that which flows through the first diode since it receives current from both the first diode and the first current source transistor. As a result, the second current source transistor is biased with a higher current than is the first current source transistor.

BRIEF DESCRIPTION OF THE DRAWING

The sole FIGURE of the drawing is a schematic diagram, partially in block form, of a preferred embodiment of the invention.

DETAILED DESCRIPTION

Referring now to the drawing, there is shown enclosed within the dotted lines a typical integrated circuit, which preferably is a monolithic integrated circuit in which a number of different utilization circuits performing different circuit operations are provided with regulated biasing currents from corresponding current source transistors. These utilization circuits are identified as circuits A through N' in the drawing and may take any suitable form, such as amplifying circuits, comparator circuits, and the like. Since the particular configuration of the circuit elements and the function of these utilization circuits is unimportant to an understanding of the operation of the bias current supply circuit, the details of the utilization circuits are not shown to avoid unnecessary cluttering of the drawing.

The various utilization circuits A, B, C, D, . . . N', however, may require operating or biasing currents of different values, with these biasing currents preferably being voltage and temperature regulated to stabilize the operation of the utilization circuits A through N'. Each of the various biasing currents, of course, could be obtained from an independent voltage and temperature regulated source; but this would be wasteful of chip area and would unnecessarily complicate the circuitry on the chip.

A single regulated reference current source circuit 10 is provided to establish a regulated reference current which is relatively independent of variations with junction temperature and supply voltage. The current source 10 may be in the form of a number of different configurations, the circuit shown merely being illustrative of a typical suitable regulated current source. The reference current is supplied by an NPN current source transistor 11, the collector of which is connected through a voltage dropping resistor 12 to a bonding pad 13 and the emitter of which is connected through a resistor 14 and a pair of NPN transistor diodes 15 and 16 to a grounded bonding pad 18. A suitable source of B+ operating potential (not shown) is applied to the bonding pad 13, so that the regulated current flows from the bonding pad 13 through the collector-emitter path of the transistor 11, the resistor 14 and the NPN transistor diodes 15 and 16 to the grounded bonding pad 18.

A stabilized source of operating potential for the reference current source transistor 11 is provided by a lateral PNP current source transistor 20, the emitter of which is connected to the bonding pad 13 through a resistor 21. The transistor 20 supplies current to a zener diode 22 coupled between the collector of the transistor 20 and the bonding pad 18. The base of the transistor 11 is connected at the junction of the cathode of the zener diode 22, the collector of the PNP current source transistor 20, and the resistor 26. The potential drop across the zener diode 22 constitutes a constant reference voltage for driving the current source transistor 11.

The base-emitter junction of the transistor 11 and the diodes 15 and 16 all have negative temperature coefficients which are chosen to partially offset the positive temperature coefficient of the zener diode 22. The change in voltage across the resistor 14 due to changes in temperature is offset by corresponding changes in resistance of the resistor 14. Thus, the current flowing through the current source transistor 11 and the diodes 15 and 16 has a zero temperature coefficient. An NPN transistor 24 is connected across the emitter-base junction of the transistor 20 to compensate for beta variations of the lateral PNP transistor 20. The base of the transistor 24 is connected to the junction of the resistor 12 with the collector of the transistor 11.

To insure that the circuit 10 operates upon the application of the operating potential to it, resistor 26 of relatively high value is connected from the bonding pad 13 to the collector of the current source transistor 20 to provide a small leakage current from the positive input bonding pad 13 through the zener diode 22 to the grounded bonding pad 18. Sufficient current initially flows through this resistor 26 and the zener diode 22 to initiate operation of the circuit. The temperature and voltage regulated current supplied by the current source transistor 11 constitutes the master reference current for the biasing current source transistors used to supply operating or bias current to the utilization circuits A through N'.

It is known that by connecting the base-emitter junction of a biasing current source transistor across the junction of a transistor diode supplied with current from a regulated current source, the current flowing through the biasing current source transistor also is regulated. The magnitude of the biasing current is determined by the ratio of the area of the emitter of the biasing current source transistor to the area of the emitter of the transistor diode. Normally all of the emitters of the biasing current source transistor are returned to a point of reference potential or a supply terminal in common with the current flowing through the current source transistor diode.

In the circuit shown in the drawing, however, four such biasing current source transistors 30, 31, 32 and 33 in the form of NPN transistors, are connected with the base-emitter junctions thereof in parallel across the transistor diode 15. Thus, the current flowing from the emitters of the current source transistors 30, 31, 32 and 33 does not flow directly to ground but instead is added to the original reference current and caused to flow through the transistor diode 16 to the grounded bonding pad 18. The collectors of the transistors 30, 31, 32 and 33 are connected through utilization circuits B, C, D and N' to the source of positive potential applied to the bonding pad 13 from which the additional biasing current is obtained.

In the circuit shown in the drawing, the emitter area of the transistors 30 and 31 is indicated as area "A" which is equal to the emitter area of the transistor diode 15. A unit current "I," which is the magnitude of the reference current supplied by the transistor 11 in the current source 10, flows through the transistor diode 15 (neglecting base current loading at the node X by the current source transistors. As is well known, with equal emitter areas, the current flowing through the current source transistors 30 and 31 also is equal to "I" since the emitter area of these transistors is identical to the emitter area of the diode 15.

As indicated in the drawing, the emitter area of the transistor 32 is selected to be A/2 so that the area scaling of the emitter of this transistor relative to the emitter area of the diode 15 is such as to cause the current flowing through the biasing current source transistor 32 to be I/2. The emitter area of the transistor 33 is indicated as NA (where N is a positive integer or a fraction thereof). The transistor 33 represents a single transistor or several transistors with a total emitter area NA, supplying a total current NI to one or more utilization circuits N' (where N' is a positive integer).

Thus far, the circuit operation which has been described is similar to the operation generally employed to derive a number of different valued biasing currents from a single regulated current supply. All of the currents flowing out of the emitters of the transistors 30, 31, 32 and 33, however, are combined with the original reference current "I" flowing through the diode 15 and this combined current flows through the diode 16 to the grounded bonding pad 18. In the example shown in the drawing, this results in a total current of (31/2 + N) I flowing through the diode 16. This (31/2 + N) I current still is independent of the supply voltage and junction temperature. Since this current is regulated, it may be used as a reference current for biasing one or more additional current source transistors which must supply substantially higher biasing currents to utilization circuits than are supplied by the current source transistors 30, 31, 32 and 33.

If the emitter area of the diode 16 also is unit area "A," as is the emitter area of the diode 15, connection of the base-emiter junction of a biasing current source transistor having the same emitter area across the diode 16 results in a current drawn by such a biasing current source transistor in the amount of (31/2 + N) I. This is a significant current scaling or multiplication of the initial reference current "I" without an increase of the emitter area of such a biasing current source transistor over the area of the emitter of the diode 16. As shown in the drawing, however, a biasing current source transistor 40 having an emitter area of PA is controlled by the current flowing through the diode 16. The base of the transistor 40 is connected to the junction of the diodes 15 and 16, and the emitter of the transistor 40 is connected to the grounded bonding pad 18. The bias current transistor 40 then supplies a current of P (31/2 + N) I to the utilization circuit A, and this current is independent of junction temperature variations and supply voltage variations. Thus, it is a regulated current based upon the original regulated reference current "I" supplied by the transistor 11 in the reference current source 10.

To illustrate the manner in which the circuit which has been described conserves chip area, assume N=21/2 and P=3. As a result, the total current flowing through the diode 16 is 6I, and the emitter current through the transistor 40 is 18I. If it is assumed that the utilization circuits B, C, D, and N required the current source transistors 30, 31, 32 and 33, then to achieve this current of 18I, the total additional emitter area required is 4A (A for the diode 16 and 3A for the transistor 40).

If the technique shown in the drawing was not employed, the diode 16 would be eliminated and the emitters of the diode 15 and the transistors 30, 31, 32 and 33 would be connected to the grounded bonding pad 18. The base of the transistor 40 then would be connected to node X and the emitter of the transistor 40 would be connected to the bonding pad 18. To achieve an emitter current of 18I with this conventional circuit, the emitter area of the transistor 40 would need to be 18 times that of the diode 15 (18A). This is 4.5 times more emitter area than is required to obtain the same current using the circuit shown in the drawing and described above.

Other biasing current source transistors (indicated in dotted lines) also could be connected across the diode 16 for supplying currents to additional utilization circuits if desired. The value of the current supplied by such other current source transistors would be dependent on the emitter area scaling or ratio to the area of the emitter of the diode 16.

By using the circuit shown in the drawing, with the reference current "I" supplied by the reference current source 10, a substantial saving in the chip area is accomplished while achieving the desired current ratios. The circuit could be iterated, and more than the two diodes 15 and 16 could be employed in series circuit between the resistor 14 and the grounded or reference bonding pad 18. Combining of various currents from other current sources referenced across diodes higher in the series string then could be used to provide increasingly greater reference currents for the diodes lower in the series string. This would permit even greater current scaling without significant emitter area scaling.

Claims

I claim: 1An integrated current supply circuit including in combination:

first and second voltage supply terminals;

first and second diode means;

reference current source means connected in series circuit with said first and second diode means, in the order named, between said first and second voltage supply terminals, said first and second diode means poled to conduct current in the forward direction between said reference current source means and said second voltage supply terminal;

at least first and second utilization circuits;

at least one first current source transistor means having collector, base, and emitter electrodes, the collector thereof connected with said first utilization circuit to provide biasing current therefor, the base and emitter connected in parallel circuit with said first diode means; and

second current source transistor means having collector, base and emitter electrodes, the collector electrode thereof connected with said second utilization circuit to provide biasing current therefor, and the base and emitter thereof connected in parallel circuit with said second diode

means. 2. The combination according to claim 1 wherein said reference current source means comprises a regulated current source, substantially

independent of variations in supply voltage and junction temperature. 3. The combination according to claim 1 wherein said first utilization circuit comprises a plurality of first utilization circuits and said first current source transistor means comprises a plurality of first current source transistors, each having collector, base, and emitter electrodes, the collectors of which are each connected with a different one of said first utilization circuits and the bases and emitters of which all are

connected in parallel circuit with said first diode means. 4. The combination according to claim 1 wherein said second utilization circuit comprises a plurality of second utilization circuits and said second current source transistor means comprises a plurality of second current source transistors, each having collector, base, and emitter electrodes, the collectors of which are each connected with a different one of said second utilization circuits and the bases and emitters of which all are

connected in parallel circuit with said second diode means. 5. The combination according to claim 1 wherein the base-emitter circuit of said first current source transistor means is connected to be forward biased by current flowing through said first diode means, and the base-emitter circuit of said second current source transistor means is connected to be

forward biased by current flowing through said second diode means. 6. The combination according to claim 5 wherein said first and second diode means each comprise transistor diode means having a shorted collector-base junction, with said transistor diode means and said first and second

current source transistor means being of the same conductivity type. 7. The combination according to claim 6 wherein said first and second transistor diode means and said first and second current source transistor means all are NPN transistors and said second voltage supply terminal is coupled with a point of reference potential.