Electronic Voting Machine

Abstract

An electronic voting machine is disclosed which accommodates for selection of one, and only one, candidate from each of two office groups. Electronic logic circuitry is used throughout. The logic features redundant interlocks to assure (1) that overvoting in either office group cannot occur and (2) that a vote cannot be counted unless a selection has been made in both office groups. The interlocks feature redundancy while minimizing the components needed to accommodate for large numbers of candidates in both office groups, and also a combined cancelafter vote reset arrangement which both prevents overvoting and causes reset after vote completion. Another feature of the system is the use of parallel tallying devices each capable of printing out its tally, one such device being the electromechanical counters usually associated with a voting machine and which tally the votes for the individual candidates, and the other such device being an electronic accumulator which likewise counts or tallies the votes for the individual candidates. At the end of a voting day, a print-out of the electromechanical tally and the accumulator tally is made. The accumulator tally print-out is made sequentially much in the fashion of an adding machine, while the print-out of the electromechanical counters is made in one pass of a movable platen. The accumulator has the capability of providing a digital read-out of the voting at all times so that, if desired, the accumulator may be connected, along with a great number of others at different voting sites, to a central computor which may then give an instantaneous tally of the vote for an entire district, state or nation. Both print-outs produce a tally sheet having type which may be be optically scanned to produce a digital output which, from a central location receiving a number of such tally sheets, may forward this digital information to a central computer, as before, at the end of a voting day. Other flexibilities are also presented by the parallel electromechanicalelectronic accumulator system.

Parent Case Text

CROSS REFERENCE TO RELATED APPLICATION

This application is a continuation-in-part of copending application Ser. No. 204,506, filed Dec. 3, 1971, now abandoned.

Description

BACKGROUND OF THE INVENTION

Known electronic voting machines have been proposed wherein provision for automatic cancellation of previously selected candidates is made in response to overvoting within the party category within which votes are being cast and thus there has been provided a rudimentary interlock for overvoting. Further, such machines have also utilized a separate resetting circuitry for insuring that the machine is cleared prior to the next voter utilization of the machines. These arrangements of the prior art have been cumbersome, have required a great many interlocking components or elements to effect a single interlock system and have, for the most part been lacking in such multiplicity of interlock relationships as absolutely insures against error.

BRIEF SUMMARY OF THE INVENTION

It is therefore of primary concern in connection with the present invention to provide an improved form of electronic voting machine wherein a single resetting or clearing circuit is utilized not only to assure that reset or clear is effected after each voter has cast his vote, but also to provide for clearing a candidate selection system or candidate category in the case of overvoting within that candidate selection, and, as well, to provide for a great many further interlocks within the system absolutely to assure that no error is made.

A further concern of the present invention is to provide great flexibility in the tally system for an electronic voting machine. To this end, the usual electromechanical counters of the machine which tally the votes for the individual candidates when the voter "exits" from the machine, are paralleled by an electronic accumulator system which electronically tallies or counts the votes for the individual candidates. By this arrangement, an electronic read-out of the tally is available at all times during the vote day, which allows for continuous or periodic electronic read-out of the tally during the day which may be forwarded, together with corresponding read-outs from a great many other voting sites, to a central computer. Various other set-ups or arrangements are also possible due to the parallel electronic accumulator.

Additionally, this invention utilizes a printer in conjunction with the electromechanical counters whose type format is such as may be optically scanned to provide a digital output of the tally at the end of a voting day. Thus, the record or tally sheet which is printed at the end of a voting day may be forwarded to one of a number of central locations, together with other tally sheets from other voting sites, for transmission of all such tallies to a central computer whose function is to record and provide a total vote for, say a particular district, state or the entire country.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

In the drawings, FIG. 1 is a simplified block diagram illustrating certain principles according to the present invention;

FIG. 2 is a circuit diagram of one of the candidate module circuits;

FIG. 3 is a circuit diagram showing one of the interlock circuits;

FIG. 4A is a circuit diagram showing a portion of the lockout expander circuitry;

FIG. 4B is a circuit diagram showing another portion of the lockout expander;

FIG. 5 is a circuit diagram showing the exit card circuit;

FIG. 6A is a circuit diagram showing a portion of the security interlock system;

FIG. 6B is a circuit diagram showing a further portion of the interlock system;

FIG. 7 is a circuit diagram showing the remainder of the security interlock system;

FIG. 8 is a circuit diagram of the control logic circuitry;

FIG. 9 is a circuit diagram of the remote control circuit;

FIG. 10 is a circuit diagram showing an arrangement for detection of error in the electromechanical counters;

FIG. 11 is a circuit diagram illustrating a portion of the accumulator circuitry;

FIG. 12 is a circuit diagram showing a portion of the multiplexer circuitry;

FIG. 13 is a circuit diagram illustrating the remainder of the multiplexer circuitry;

FIG. 14 is a circuit diagram showing the digit sequencer;

FIG. 15 is a circuit diagram illustrating the register sequencer;

FIG. 16 is a circuit diagram showing the printer driver;

FIG. 17 is a circuit diagram illustrating certain portions of the printer;

FIG. 18 is a circuit diagram showing the printer interface logic circuit;

FIG. 19 is a circuit diagram illustrating the identification counter;

FIG. 20 is a block diagram illustrating certain principles of the data section;

FIG. 21 is a circuit diagram of a modified form of candidate module;

FIG. 22 is a circuit diagram of a modified interlock system;

FIG. 23 is a circuit diagram of a modified control card system; and

FIG. 24 is a circuit diagram of a modified form of instruction and totalizer system.

DETAILED DESCRIPTION OF THE INVENTION

With reference now to FIG. 1, certain principles and arrangements according to the present invention will be clear therefrom although it is to be understood that the entirety of the logic circuitry and connections are not illustrated in FIG. 1 for the purpose of clarity. As shown, the system includes a remote control logic circuitry indicated generally by the reference character 10, the main purpose of which is to permit an election official, through the control of a switch, to provide a signal at the output conductor 12 which allows a voter to make his selections. This signal is applied to the control logic circuitry 14 which produces, under proper conditions, an enabling output at the conductor 16 which is applied to each of a plurality of candidate module circuits. For the purpose of the present invention, the description which follows applies to an arrangement wherein one vote in each of two candidate categories is to be made, the candidate categories being a congressional candidate and a presidential candidate. Further there will be a total of 20 selections within the congressional candidate selection and eight candidates in the presidential candidate selection. Thus, there will be a total of 28 candidates and each of the candidate modules hereinafter described is constructed to accommodate for two candidates so that there will be a total of 14 candidate modules, 10 of them associated with the congressional selection and four of them will be associated with the presidential selection.

Associated with eight of the dual candidate modules for the congressional selection is the interlock circuitry indicated by the reference character 18 whereas for the four dual candidate module circuits associated with the presidential selection, there is an interlock circuitry 20. Thus, for the eight candidate modules associated with 16 of the congressional candidate selections arranged in cooperation with interlock circuitry 18, the first and eight of which are indicated at 22 and 24, each has two candidate selection outputs 26 and 28 applied to the interlock circuit 18, making a total of 16 candidate selection outputs from these eight candidate modules to the interlock circuit 18. To accommodate for the total of 20 congressional candidates, two additional candidate modules 30 and 32 are provided each having a pair of outputs as at 34 and 36 which are applied to a combining and security interlock circuitry indicated generally by the reference character 38. The main purpose of the interlock circuitry 18 is to provide a signal at the output conductor 40 thereof which is applied to the combining and security interlock circuitry 38 when one and only one selection has been made out of the 16 congressional candidates associated with the interlock circuitry 18. The input from the two modules 30 and 32 are combined with the input at 40 in the circuitry 38 to provide a one to 20 signal output at the conductor 42 or a two of 20 output at the conductor 44, the former being the correct signal output and the latter being the incorrect signal output indicating an overvote in the congressional candidate selection.

Similarly, each of the candidate modules associated with the interlock circuitry 20 for the presidential office, of which only the first and fourth 46 and 48 are shown, have a pair of outputs 50 and 52 associated with the two different candidates accommodated by each modules. These eight outputs are applied to the interlock circuitry 20 which has a one of eight output conductor 54 and a two of eight output conductor 56 both of which are applied to the lockout expander circuitry 58 similarly to the two signals 42 and 44 previously described as possible outputs from the combining and security interlock circuitry 38.

Assuming a voter has been given entrance and has chosen both a congressional and presidential candidate, and no overvoting or other errors or disabling signals are present, an exit enabling signal will appear at the output 60 of the lockout expander circuitry 58 which is applied to the control logic circuitry 14. When the voter operates an exit switch in the circuitry 62, an exit pulse appears at the output conductor 64 which is also applied to the control logic circuitry 14. This causes a register signal to be applied at the conductor 66 as an output of the control logic circuitry 14, this register signal being applied as shown to all candidate modules, causing those which have been selected to apply signals from their corresponding output conductors such as those shown at 68 and 70 to an electromechanical counter system indicated generally by the reference character 72. The individual conductors from the various candidate modules are shown as a single conductor 74 in FIG. 1 for the purpose of clarity. At the same time, count enable outputs 81 from the candidate modules and a register output at conductor 80 from the lockout expander circuitry 58 are provided as inputs to the electronic accumulator 82, so that electronic signals corresponding to the electromechanical count are stored and accumulated in the circuitry 82 to establish a vote tally identical with that of the electromechanical counters in the circuitry 72.

After the register signal has been applied and the electromechanical counters have been actuated in the circuitry 72, a delayed clear signal appears at the output conductor 76 of the control logic circuitry 14 which is applied to the lockout expander circuitry 58 and from there over the output conductor 78 back to all of the candidate modules to clear or reset them to the initial position and to make the system ready for the next voter. At the same time, a vote complete signal is applied at the conductor 61 to the exit logic circuitry 62 which energizes a signal lamp apprising the voter that he has completed his vote.

Again, for the sake of clarity, only a few conductors are shown in the electronic accumulator and subsequent circuitry. However, associated with each candidate, making a total of 28 candidates as noted before, there is a decade counter for units, tens, hundreds and thousands the outputs of which ultimately appear sequentially at the output conductors 84, 86, 88 and 90 of the multiplexing circuitry 92 when print-out by the ADDO-X printer portion of the printer mechanism indicated generally by the reference character 94A is actuated at, for example, the end of the day after the polls have closed. The circuitry 10 under control by the election officials provides a print out signal at the conductor 96A to allow operation of the printer. The printing operation provides sequential stepping signals which appear at the output conductor 100 which, when applied to the sequencer 102 control not only the electronic accumulator 82 and multiplexing circuitry 92, but also the decoding circuitry 104, and, ultimately, shuts down the printing operation by the provision of an output signal at the conductor 106 of the sequencer 102.

The printer 94A in the specific embodiment according to the present embodiment is an ADDO-X printer. This device receives sequential data one digit at a time. The most significant digit (extreme left-hand digit) enters the extreme right-hand position and is subsequently moved to the left as additional digits enter sequentially. The first two digits of data entered represent an identifying symbol for the candidate whose count will follow on that same line of print out. The identification and totals for a candidate are printed and the paper roll is indexed. This process is repeated until all totals have been printed.

Alternatively, when the accumulator data is shifted out, the output conductor 108 may be utilized to feed the information to a centralized computer receiving such information from a great many voting machines scattered over a wide area, as for example an entire country.

The circuitry 10 under control of the election officials also provides a signal at conductor 96 to allow operation of the printer 94. This printer is a motor driven platen which moves across the electromechanical counters and by means of hard rubber rollers, presses a pack of several sheets of carbonized paper against the raised numerals on the counters. At the beginning of the day, the platen is run from left to right printing the total on all counters before voting has taken place, which if the machine is properly setup, will be zero in each position. At the end of its travel, the pack is indexed and this indexing allows the official to remove the part of the pack called the proof sheet showing the number on each counter before voting.

At the end of the day, after all voting is complete, the platen is again energized by the official. This time the platen moves from right to left recording the total votes on each counter. At the end of its travel the pack is released and comes out a chute to the election official. It will be noted that this provides a permanent record of the count both before and after voting and is accomplished without the official having physical access to the counters. Also, the act of taking this final print out at the closing of the polls provides a signal at output conductor 98 to prevent further voting.

Both the ADDO-X tape record sheet and the record pack printed on the electromechanical counters will be understood to be of form such as to be scanned optically and provided, as digital information, to a central computer arrangement as for example over telephone lines. The advantage of this latter procedure is that a number of record sheets may be accumulated from various precincts or locations and brought simultaneously to a more centralized location which represents one of only a few of such centralized locations for optical scanning and sending the results over telephone lines to a centralized computer. The advantage of this latter procedure is that in a procedure where digital information is fed from the accumulators 82 of a great many machines, the demand made upon the telephone equipment is likely to be much too great for the normal telephone equipment capability.

Referring now to FIG. 2 wherein one of the candidate modules is shown, it will be noted first of all that the circuit is divided into two parts, each having a candidate selection switch 110 or 112 associated therewith. The respective cross-coupled NAND gate flip-flop circuits 114 and 116 are associated with the respective switches 110 and 112. The flip-flop 114 comprises the two NAND gates 118 and 120 having their output conductors 122 and 124 cross-coupled as shown. The gate 118 is connected such that its input conductor 126 is normally high and the output of the gate 120 also is normally high so that the output of the gate 118 at the conductor 122 normally is low. When the candidate modules are enabled, the signal at the input conductor 128 to the NOR gate 130 is high and the output at the conductor 132 is low so that when the switch 110 is closed, the signal at the conductor 126 goes low and the output at 122 will go high, thus producing a high input at the cross-coupled conductor 134 to the gate 120, causing its output at the conductor 124 to go low, since the input at the conductor 136 normally is high. The low output at the conductor 124 will maintain the output of the gate 118 high after the switch 110 is released and the flip-flop 114 will thus remain in its changed state until a low output appears at the output conductor 136 from the NOR gate 138.

The two NAND gates 140 and 142 are connected as inverters so that after the switch 110 is operated, the normally high outputs of the two gates 140 and 142 will go low. After a slight delay as occasioned by discharge of the capacitor 144, the transistor 146 will be driven to saturation so as to switch on the filament of the light or bulb 148 which indicates to the voter that he has selected the candidate associated with the switch 110. The normally high output of the gate 142 at the conductor 150 goes low and this low signal is applied at the conductor 152 as a blocking input to the NAND gate 154 associated with the candidate related to the switch 112. Since the NAND gate 154 and the corresponding NAND 156 associated with the switch 110 control the counter drive transistors 158 and 160, vote selection of the candidate associated with the switch 110 blocks any counter drive output signal at the conductor 162 associated with the transistor 160 and, conversely, selection caused by actuation of the switch 112 blocks the NAND gate 156 which controls the transistor 158 to produce the counter drive signal at the conductor 164. The winding 163 shown connected to the switch 160 represents the armature winding of the electromechanical counter associated with the candidate corresponding to the selection switch 112. It will be understood that another counter is similarly connected to the switch 158 and that one such counter winding is similarly connected to each candidate selection circuit, for as many such circuits as are provided.

Although one input to the NAND gate 156 is enabled by virtue of the now high output at the conductor 122 from the flip-flop 114, two other inputs to the gate 156, namely at the conductors 166 and 168 still are in the low state so that no change of state from the normally high output at the conductor 170 occurs and the transistor 158 remains non-conductive. The corresponding conductors for the NAND gate 154 are at the inputs 172 and 174 thereof. The signals for the inputs 166 and 174 normally are low to block the gates 154 and 156 and are applied to the circuits at the input terminal 176. The signal at the input terminal 178 which provides the inputs at 168 and 172 to the gates 154 and 156 normally is high until a signal appears from the interlock circuitry hereinafter described to indicate an overvote condition and the signal at the input terminal 176 does not go high until a register signal also as hereinafter described appears but when both of these signals are high and, as previously described, the switch 110 has been activated, all inputs to the gate 156 will be high so that its output goes low to drive the transistor 158 into saturation so as to record the vote for the candidate associated with the switch 110 by grounding the conductor 164 through the transistor switch 158 to step the counter associated with the candidate selected to the next highest digit, thus effecting the final drive to the electromechanical counter system associated with each of the candidates. The capacitor 175 normally is charged and discharges through the gate 156 when same is actuated; and when the gate 156 is returned to its normal condition, the capacitor charges through the diode 177 and resistor 179. The arrangement is such as to smooth the action of the transistor switch.

Similarly, the candidate selection switch 112 controls the flip-flop 116 whose output at the conductor 180 normally is low due to the high input at the conductor 182 and the cross-coupled conductor 184 to the NAND gate 186. The NAND gate 188, on the other hand, has the normally high input at the conductor 190 and the normally low input at the cross-coupled conductor input 192 so that its output at the cross-coupled conductor 184 normally is high. The NOR gate 194 like the NOR gate 138, has a normally low input pair as provided for by the normally low output at the conductor 196 from the NOR gate 198. The CLEAR signal input at the conductor 200 normally is high, but when it goes low as hereinafter described, the output of the two NOR gates 138 and 194 also go low to clear or reset the flip-flops 116 and 114. However, if this clearing action occurs by virtue of overvoting (i.e., voting for a second congressional candidate as for example if the actuation of switch 110 constituted the second selection for a congressional candidate) the normally high CLEAR signal at the conductor 200 which goes low in response to this second congressional selection will go high again to remove the reset signal from the NOR gate 138 before the manually actuated switch 110 can be released, as hereinafter described.

The transistor 202 associated with the light 204 corresponds to the transistor 146 previously described but of course is actuated only in response to manipulation of the candidate selection switch 112. The NAND gates 206 and 208 correspond to the NAND gates 140 and 142 previously described, the output from the NAND gate 208 at the conductor 210 providing the SELECT signal associated with the candidate corresponding to the switch 112 and also being connected over the conductor 212 to the gate 156 to block same as was described previously in connection with a blocking signal to the gate 154 as provided at the input 152 thereto. The several conductors 214, 216, 217, 218 and 220 shown in FIG. 2 are provided for test purposes. However, the output signals at the conductors 222 and 224 are the count enable signals corresponding to individual candidates and which all are applied to the electronic accumulator circuitry as described later.

As noted hereinbefore, there are 20 congressional candidates accommodated for in total and 16 of these are associated with the interlock circuitry 18 (FIG. 1), such interlock circuitry being illustrated in FIG. 3. It will be noted that the SELECT outputs from the various candidate modules (at 150 and 210 in FIG. 2) are connected as certain inputs to the gates at the left hand side of the FIG. 3, thus the two SELECT signals outputs 150 and 210 from the candidate modules as described in FIG. 2 are connected to the NAND gate 225, the SELECT signals from another candidate module at the conductors 222 and 224 are connected to the NAND gates 226; another pair of SELECT output signals from a further candidate module at the conductors 228 and 230 are connected as inputs to the NAND gate 232; another pair of SELECT output signals from a further candidate module at the conductors 234 and 236 are connected to the NAND gate 238; and so on for the SELECT pairs 240 and 242, 244 and 246, 248 and 250, 252 and 254 for the respective NAND gates 256, 258, 260 and 262. For each pair of NAND gates 225 and 226, 232 and 238, 256 and 258 and 260 and 262, there is a further pair of NAND gates 264 and 266, 268 and 270, 272 and 274, and 276 and 278, respectively. As will now be described for the uppermost left hand group of NAND gates in FIG. 3, whereas pairs of SELECT outputs from the same candidate module are connected to respective NAND gates 225 and 226, one each of these outputs is also connected as an input to one of the NAND gates 264 and 266. Since all of the SELECT outputs are normally high and go low only when a vote selector switch is actuated, it will be evident that if both SELECT signals from a single candidate module are sequentially caused to appear, either will cause the associated gate to which both are connected to produce a high output which will be ineffective in itself to cause a change of state of output of the circuitry of FIG. 3. To illustrate, if both the SELECT signals at the conductor 150 and 210 go low, all that will happen insofar as gate 225 is concerned is that its output will go high but the gate 280 will retain its normally high output at the conductor 282 since the input thereto which is the output from the gate 226 will not have changed and will still be low. However, the low output at the conductor 150 also provides a low output at the input conductor 284 of the gate 266 so that its normally low output at the conductor 286 will now go high causing one high input to the NAND gate 288, whereas the now low input at the conductor 210 will also be applied over the input conductor 290 to the NAND gate 264 so that its normally low output at the conductor 292 will also go high so that, now, both inputs to the NAND gate 288 have gone high so as to cause its normally high output at the conductor 294 to go low. Thus, even though the output of the gate 280 remains high, the output at the conductor 294 which is the other input to the NAND gate 296, will go low causing the output at the conductor 298 to go high which, as inverted by the NAND gate 300 connected as shown, produces a low output at the conductor 302 which extends to the NAND gate 304, which, due to the fact that all of the remaining inputs thereto are high as will hereinafter be described, causes its output at the conductor 306 to go high.

Similarly, any pair of SELECT signal outputs from the same candidate module in the other groups will cause the normally high outputs of the respective NAND gates 308, 310 or 312 to go low thus causing corresponding high outputs from the NAND gates 314, 316 or 318 which, as inverted by the NAND gates 320, 322 or 324, will cause a normally high output therefrom to go low and thus produce a high output at the conductor 306 which, in every instance, indicates that two candidates of the 16 described have been selected.

On the other hand, if any two SELECT signals not originating from the same candidate module but from two different candidate modules associated with each group of NAND gates corresponding to those indicated by reference character 225, 226, 264 and 266 are caused to go low, both inputs to the NAND gate 280 will go high so that its normally high output at conductor 282 will go low causing the normally low output of the gate 296 to go high which, after inversion at 300, goes low and produces a high output at the conductor 306 from the gate 304.

On the other hand, if for example, SELECT signals appear at the conductors 150 and 230, for example, the two NOR gates 326 and 328 will operate to cause a low output at the input conductor 330 to the gate 304, correspondingly to produce a high output at the conductor 306. The manner in which this occurs will now be explained. Since any one SELECT signal of those which are grouped together, as for example the conductors 150, 210, 222 and 224 is caused to produce a low SELECT signal, either the gate 264 or the gate 266 will produce a high output and since the outputs of these gates, being normally low are connected as the input conductors 332 and 334 to the NOR gate 326, either one of them going high will produce a change of state of the output at the conductor 336, same normally being high and going low when either one of the inputs 332 or 334 goes high. This signal, now low, is applied at the conductor 340 as one input to the NAND gate 342 and also, at the conductor 344 as one input to the NAND gate 346. Thus, the normally low outputs of both gates 342 and 344, at the output conductors 348 and 350 will go high but no low signal will appear at the conductor 330 to gate 304 because the other inputs to the two gates 352 and 354 normally are low. However, the normally high output from the NOR gate 328 will also go low because, as previously described the input at the conductor 230 has gone low which causes the output from the gate 268 to go high which, as shown, is connected to the input conductor 360 of the NOR gate 328. Thus, the now low output at the conductor 362 from the NOR gate 328 is applied as an input at the conductor 364 to the NAND gate 342 and also as an input to the NAND gate 368. Thus, the outputs at the conductor 350 and 370 have now both gone high causing the output at the output at the conductor 372 from the gate 354 to go low and, since both inputs to the gate 374 normally are high, the low input at the conductor 376 goes high which, after inversion by the NAND gate 378 connected as shown, appears as a low signal at the conductor 330 as previously described.

The NOR gates 380 and 382 operate in conjunction with each other or in any combination of two of the NOR gates 326, 328, 380 and 382 to produce a low output at the conductor 330 leading as an input to the gate 304, as previously described.

Also, it will be seen that the outputs at the conductors 336, 362, 384 and 386 from the respective NOR gates 326, 328, 380 and 382 all are connected as inputs to the NAND gate 390 so that when any one of them goes low, the normally low output of the gate 390 at the conductor 392 goes high to provide a ONE output signal.

Thus, it will be seen that when any one of the 16 SELECT inputs is applied to the circuitry of FIG. 3, a ONE output signal appears at the output conductor 392 and this signal remains high even though, subsequently, a second candidate of the 16 is selected and a TWO output signal appears at the conductor 306.

Referring now to FIG. 7, the manner in which the other four of the congressional candidates is accommodated for in addition to the 16 described in conjunction with FIG. 3 will now be made clear. As will be seen in FIG. 7, the signals which go high when either one or two congressional candidates have been selected from the 16 associated with the circuitry of FIG. 3 are at the corresponding conductors 392 and 306 extending to the circuitry of FIG. 7. These signals, respectively, are inverted by the NOR gates 400 and 402 connected as shown so that their normally high outputs at their respective conductors 404 and 406 will now go low. The conductor 404 provides one input for the NAND gate 408 and if one of the 16 candidates associated with the circuitry of FIG. 3 has been selected, the low output at the conductor 404 will cause the normally low output of the gate 408 at the conductor 410 to go high and thereby provide a one of 20 output signal at such conductor 410. If, now, only one of the congressional candidates associated with the circuitry of FIG. 3 has been selected, but now one of the four remaining congressional candidates is selected, the interlock circuitry of FIG. 7 will come into play as will be described.

In FIG. 7, the two conductors 412 and 414 are provided from one remaining candidate module while the conductors 416 and 418 are provided from the other remaining candidate module. These several conductors are connected as the SELECT outputs corresponding to the conductors 150 and 210 of FIG. 2. The signals thereat normally are high and go low when a corresponding candidate module selection switch is activated. The two conductors 412 and 414 are connected as the inputs to the NAND gate 420 and also as one each of the inputs to the NAND gates 422 and 424 whereas the two conductors 416 and 418 are connected as the two inputs to the NAND gate 426 and, as well, as the other inputs to the two gates 422 and 424. Remembering that the condition now being described is one in which a selection had been made from the one of the candidate selection switches associated with the circuitry of FIG. 3 so that a high output appears at the conductor 392, it will be readily apparent that when any one of the conductors 412, 414, 416 or 418 is energized to produce a low output signal, a high output will appear at one or the other of the conductors 432 or 434 which are connected as inputs to the NOR gate 436 from the conductors 428 and 430. Consequently, the normally high output at the conductor 438 from the gate 436 will go low, thus producing a low output signal on the conductor 440 to the gate 408. This will not, of course, change the state of the output of the gate 408 since its output is already high due to the input at 404 which was previously low. However, the now low output at the conductor 442 which is connected to the inverting NOR gate 444 causes the output at the conductor 446 to go high as one of the inputs to the NAND gate 448. However, the signal at the conductor 392 which is connected through the conductor 450 as the other input to the NAND gate 448 is also high due to the one of 16 signal at the conductor 392 so that, now, the output of the NAND gate 448, at its output conductor 452 goes low. This causes the NAND gate 454 to produce a high output on its normally low output conductor 456 which provides the two of 20 output signal as utilized hereinafter.

The other two inputs to the gate 454, namely at the conductor 406 and at the conductor 458, normally are high. That is to say, that at the conductor 406 normally is high provided the two of 16 signal has not appeared at the conductor 306 and that at the conductor 458 is high if the signal output of the inverting NAND gate 460 has not been changed as will now be described.

The purpose of the NAND gate 460 is to accommodate for a situation in which two votes are selected at any pair of the conductors 412, 414, 416, 418 when no signals appear at either of the conductors 392 or 306. As before, if two signals appear from the same candidate module, for example, from the conductors 416 and 418, the logic circuitry is through the two gates 422 and 424 whose normally low outputs now both go high at the conductors 428 and 430 causing the normally high output at the conductor 470 from the NAND gate 472 to go low which causes the normally low output from the NAND gate 474, at the conductor 476, to go high which, after inversion at 460, causes a low output signal at the conductor 458 and, correspondingly a high output signal at the two of 20 output conductor 456. Of course, both of these signals are the conductors 416 and 418 or, more accurately, either one of them, will have caused the NOR gate 436 to respond and, at the conductor 440, to cause the gate 408 to produce a high output at the conductor 410. If, on the other hand, the two conductors 414 and 416, for example, have outputs which go low, the two gates 420 and 426 will both produce low outputs at the conductors 480 and 482 which will cause the normally high output of the gate 484 at the conductor 486 to go low, thus acitvating the gate 474 and causing its output, at the conductor 476 and through the inverter 460 to produce a low output signal at the conductor 458 and correspondingly, the high output at the conductor 456.

It should be remembered that the circuitry of FIG. 3 as combined with the circuitry of FIG. 7 constitutes the full interlock logic associated with the congressional candidate selection to assure that only one out of 20 selections is made for a congressional candidate. Insofar as the presidential candidate is concerned, it will be remembered that there are eight possible selections and, again, it is mandatory that only one out of these eight be selected. The interlock 20 of FIG. 1 accommodates for this by providing a one of 8 output at the conductor 54 when any one presidential candidate has been selected and presenting a two of eight output at the conductor 56 when two presidential candidates have been selected. Although the specific interlock circuitry associated with the block 20 of FIG. 1 is not shown, it will be appreciated that same constitutes an arrangement embodying the lower half of the arrangement of FIG. 3, thereby to provide a one of eight output signal from a two-input NAND gate corresponding to the gate 390 in FIG. 3 but embodying four gates associated directly with the NOR gates corresponding to those indicated at 380 and 382 in FIG. 3, ultimately to provide either a one of eight output signal alone or that in combination with a two of eight output signal, as will be evident.

Thus, referring to FIG. 4A, one of eight presidential candidate selections will appear as a high output at the input conductor 500 whereas two of these eight presidential candidate selections will appear as a high input at the conductor 502. The one of 20 congressional candidate signal appears at the previously described conductor 410 and, the two of 20 congressional candidates signal appears at the previously described conductor 456, as shown in FIG. 4A. It will be appreciated that FIG. 4A is the lockout expander circuitry 58 shown in FIG. 1, certain logic functions being performed thereby as will now be described. The circuitry of FIG. 4A has a number of output conductors identified by the reference characters 504, 506, 508, 510, 512, 514, 516, 518, 520 and 522. Correct output signals from the circuitry of FIG. 4A occur when one and only one presidential candidate selection has been made and one and only one congressional candidate selection has been made, as is evidenced by high inputs at the conductors 500 and 410. Both of these signals are inverted by the inverting NAND gate 546 and 548 such that the normally high inputs thereof at the conductors 550 and 552 go low, either one of which will cause the normally low output of the NAND gate 554 to go high and produce a NONE output signal at the conductor 506. These two low signals at the conductors 550 and 552 will cause corresponding low outputs at the conductors 504 and 508 which are, respectively, the ONE presidential selection and ONE congressional candidate selection. Additionally, these two output signals at the conductors 500 and 410 will cause the normally high output of the gate 556 to go low which, as inverted by the NAND gate 558, produces then a high output at the conductor 560. The conductor 560 provides one input to the NAND gate 562 and, as will hereinafter appear, the other input at the conductor 564 thereto normally is high so that the change of state at the conductor 560 will cause the normally high output from the gate 562 at the conductor 566 to go low which, when inverted by the gate 568 causes a high output at the conductor 510 which is the exit enable signal hereinafter described with more particularlity.

If either of the conductors 502 or 456 have a high output signal, indicating either that two presidential candidate selections or two congressional candidate selections have been made, the corresponding high signals thereof are inverted by the respective NAND gates 570 and 572 to produce low output signals at the conductors 574 and 576, either one of which will cause the normally low output of the NAND gate 578, at the output conductor 580, to go high which, after inversion by the NAND gate 582, produces a blocking low signal at the input conductor 564 to the gate 562 and thus prevents the exit enable high signal to appear at the conductor 510.

At the same time, a high input at the conductor 502, producing the low input at the conductor 584 providing one input to the NAND gate 586, will cause its normally low output at the conductor 588 to go high which, after inversion by the parallel NAND gates 590 and 592 will produce low output signals at the conductors 512 and 514. These are the clear signals for the presidental candidate modules. It will be evident, of course, that the other input to the gate 586, at the conductor 598 normally is high as produced by the inverting NAND gate 600 which has, as its inputs, the signal at the conductor 602 which is the after vote reset signal hereinafter described. This normally high signal at the conductor 598 is also applied by the conductor 604 as one input to the NAND gate 608 which has, as its other input at the conductor 610, the normally high output of the NAND inverting gate 572 at the conductor 576. If the signal at the conductor 456 is high indicating that two congressional candidate selections have been made, the now low output at the input conductor 610 to the NAND gate 608 will cause its normally low output to go high at the conductor 612 which, after inversion by the parallel series of NAND gates connected as inverters as shown and indicated by reference characters 618, 620, 622, and 624 to provide the respective now low output signals at the conductors 516, 518, 520 and 522. These signals are the clear outputs for the congressional modules. Thus, in case a high input appears at the two presidential candidate selection conductor 502, low outputs will appear at the conductors 512 and 514 which will clear the presidential candidate modules. Likewise, if a high output appears at the two congressional candidate selection input 456, low outputs will appear at the conductors 516, 518, 520 and 522 to clear the congressional candidate modules. The only purpose served by the plurality of gates 590 and 592, 618, 620, 622 and 624 is to provide sufficient power for the large number of modules involved.

Similarly, as will hereinafter be described in detail, an after vote reset signal which is a high output appearing at the conductor 602 will affect not only the gate 586 but also the gate 608 so that both sets of clear signals will appear at the conductors 512, 514, 516, 518, 520 and 522.

The lockout expander circuitry of FIG. 4B provides a register signal and count pulses for the accumulator circuitry hereinafter described and, for this purpose, a register pulse input is applied at the conductor 778 as shown and a pair of inverting NAND gates 626 and 628 invert this signal in parallel and apply it in parallel to the gate 630, 632, 634, 636, 638, 640, 642, 644, 646, 648 and 650 to provide the outputs at the several output conductors 524-544. Of these, one at the conductor 524 is applied to the remote control circuitry as hereinafter described while the rest are applied to the electronic accumulator circuitry, again, the large number of gates 632-650 being for the purpose of providing sufficient power to drive the various circuits.

Referring now more particularly to FIG. 8 wherein the control logic card is shown, the after vote resetting circuit is shown as well as an initial reset circuitry. The initial reset circuitry includes a grounded inverter 700 connected through a resistor 702 and an integrating capacitor 704 to a further inverter 706. When the power is first turned on, the signal at the conductor 708 tends to go high and the capacitor 704 is charging through the resistor 702 delays the low output signal at the conductor 710 from the inverter 706, which signal is applied over the conductor 712 to the security interlock circuitry of FIG. 6 and is also inverted at 714 providing a delayed positive going voltage step at the conductor 715 which assures resetting of the flip-flop 716 and, as well of the flip-flop 718, assuring that the output of the flip-flop 718 at the conductor 720 is high.

The signal at the conductors 722 normally is low as will hereinafter be descirbed and the exit enable signal at the conductor 510 (from FIG. 4A) is also normally low so that the output from the NAND gate 726 normally is high at the conductor 728. Further, the ONE signal at the conductor 508 normally is high as has been previously described (FIG. 4A) and the signal at the conductor 730 normally is low so that the output of the NAND gate 732 at the conductor 734 normally is high. The ouput from the NAND gate 736, at the conductor 738 is, therefore, normally low while that output from the NAND gate 740 at the conductor 720 is, as previously described, normally high.

The normally low input at the conductor 506 normally provides a high output at the output conductor 742 and the NAND gate 744 and correspondingly, a normally low output at the conductor 746 at the output of the NAND gate 748.

Speaking generally, the flip-flop 718 changes state when the voter, having properly completed his selections, actuates the exit switch. As a result of this change of state of the flip-flop 718, the ouput at the conductor 758 from the gate 756 momentarily goes low and this performs the following functions:

1. the driving coil 802 of a voter totalizer of counter is energized;

2. count or register pulses appear at the conductors 770-778 to step the appropriate electromechanical counters and to affect the electronic accumulator;

3. a VOTE COMPLETE step function signal appears at the conductor 818 to energize the vote complete light of FIG. 5B;

4. the SWITCH ENABLE signals go low at the conductors 820-826 to disable the switches 110 and 112 of the candidate modules, FIG. 2;

5. the output of the gate 782 goes low to produce a high AFTER VOTE RESET signal at the conductor 602;

6. the signal at 506 goes low when all selections are cleared and the flip-flop 716 is reset turning off the after vote reset signal.

The above noted change of state of the flip-flop 718 is effected by the proper signals at the conductors 510 and 722. The purpose of the gate 732 is to reset the flip-flop 718 and thereby condition the machine for operation by the next voter. This is called giving "entrance" to the machine for the voter. Note that the entrance cannot be given unless the ONE signal at the conductor 508 is high which will occur only if no selection has been made. Thus, if a voter is in the process of voting or if, for some reason, a voter has left the machine after having made a selection but before completing his vote, entrance to the machine cannot be given to another voter because of the blocking input at the input 508 to the gate 732.

Also conductor 1144 must be high indicating switch 1142 of FIG. 6A is closed and the platen is in the right-hand position. Therefore, entrance can not be given before the proof sheet is printed by the platen in the morning or after the final return sheet is printed at the end of the voting day.

Note also that the gate 782 is blocked by the input thereto from the flip-flop 716 until such flip-flop has changed state in response to both a selection having been made which places a high signal at the conductor 506, and an exit occurring producing a low pulse at 780.

Assuming that the machine is in proper condition for giving entrance to a voter, under control of the election official, the entrance signal at the input conductor 730 momentarily goes high assuring reset of the flip-flop 718 prior to the entrance by a voter by producing momentarily a low output pulse at the conductor 734. As soon as a candidate selection is made, the signal at the conductor 506 corresponding to the NONE signal goes high but does not as yet affect the state of flip-flop 716. At the same time, the ONE signal at the conductor 508 goes low which disables the gate 732 as mentioned above. When the voter completes his selections, the exit enable signal at the conductor 510 goes high and then when he pushes the exit button, the signal at the conductor 722 goes high which causes the output at the conductor 728 to go low thus to change the state of the flip-flop 718 to perform the function set forth above.

The output of the conductor 720 goes high and that at the conductor 738 goes low and because the capacitor 750 takes some time to discharge through the resistor 752 and gate 736, the input conductor 754 to the NAND gate 756 momentarily remains high while the two other inputs thereto are also high, giving rise to a momentary output signal at the conductor 758 which, through the inverter 760, 762, 764, 766 and 768, provide the register signals at the conductors 770, 772, 774, 776 and 778. The signals at the conductors 770-776 are applied to three each of the candidate modules for the congressional and presidential candidates whereas the signal at the conductor 778 goes to the lockout expander module in FIG. 4B as well as to the two remaining candidate modules.

The trailing edge of the momentary low output pulse at the conductor 758 produces the after vote reset signal at the conductor 602. When the signal at the conductor 758 goes low, the flip-flop 716 is triggered so that its output at the conductor 746 goes high so that the output from the NAND gate 782 does not change at this time. However, when the REGISTER signal at the conductor 758 goes high again (trailing edge), both inputs to the gate 782 will be high so that its normally high output at the conductor 784 will go low. This signal is inverted by the NAND gate 786 to provide the after vote high signal at the conductor 602. The high output at the conductor 602 is subsequently returned to a normal low signal by virtue of the fact that the NONE signal at the conductor 506 will now go low due to the reset and will reset the flip-flop 716 to its normal state in which the output conductor 742 is high and the output conductor 746 is low.

When valid selection is complete (510 high) and the exit switch is closed by the voter (722 high), the output state of the flip-flop 718 is changed. This change of state immediately causes all of the outputs 818, 820, 822, 824 and 826 to go low so that no further candidate selections can be made at the candidate modules (820, 822, 824 and 826 low) and the vote complete light goes on at the election official's console (818 low). At the same time, the leading edge of the register pulses at the outputs 770, 772, 774, 776 and 778 is generated, the duration of which pulse is determined by the time constant of the R C circuit 750, 752. The output state of the flip-flop 716 is changed at the leading edge of the REGISTER pulse (at 758) so that one input to the gate 782 goes high (from flip-flop 716) while the other goes low (from 758). Thus, no after vote reset pulse is generated as yet. However, when the REGISTER pulse goes high again (trailing edge of register pulse) both inputs to the gate 782 will be high, thereby generating the leading edge of the after vote reset pulse at 602. The trailing edge of the after vote reset pulse is generated when the NONE input at 506 goes low again (resetting flip-flop 716) due to the clear signals applied to the candidate modules.

REGISTER pulse at the output conductor 758 also is applied through the inverter 792 and the inverting NAND gate 794 to cause the output of the latter at the conductor 796 to go low so as to close the switch 798 and to ground the congressional candidate totalizer drive conductor 800 which is connected to the totalizer armature coil 802 as shown.

The output of the gate 736 when it went low provided a vote complete signal at the conductor 804 through the inverter 806 and is applied through a bank of inverters 808, 810, 812, 814 , 816 , whose output conductors 818, 820, 822, 824 and 826, provide the vote COMPLETE signal and four selection switch enabling signals as indicated. Thus, until resetting of the flip-flop 718 by a proper signal from the entrance conductor 730, the outputs at the conductors 820, 822, 824, 826 which provide the signals at the enabling conductors 128 of FIG. 2 will be such as disables these candidate modules. The purpose of the vote COMPLETE signal will be apparent hereinafter.

The exit card logic is shown in FIGS. 5A and 5B. First of all, when the vote COMPLETE signal at the conductor 818 of FIG. 8 provides a low output signal, the NAND gate 880 causes the junction 882 to go high so that the NAND gate 900 changes its normally high output at conductor 902 to a low output thus causing saturation of the transistor 904 which contains the vote complete light 906 in its emitter circuit and the voter is now apprised that he has completed his vote and that it has been recorded. However, in order to obtain this indication, he must first actuate the exit switch indicated generally by the reference character 908. When he does so, the normally high input at the conductor 910 to the NAND gate 912 of the flip-flop 914 goes low thereby to change the state of the flip-flop such that the output conductor 916 thereof goes high whereas the output conductor 918 of the NAND gate 920 goes low. Because the capacitor 922 takes a finite time to discharge through the resistor 924 and the gate 920, the input 926 to the NAND gate 928 remains high for a short time overlapping the high input from the conductor 916 so that the output at the conductor 930 momentarily goes low correspondingly to provide the inverted output at the exit conductor 722 from the NAND gate inverter 934 which momentarily goes high.

To summarize the description to this point, the selection of either one of the candidate selection switches from any candidate module places an enabling input to its associated gate 154 or 156 (FIG. 2) while simultaneously blocking the corresponding gate associated with the other candidate selection switch thus providing an interlock within each candidate module. The selection of a single candidate, assuming same to have been made in the congressional office selection, causes either one of the NOR gates 326, 328, 380 or 382 of FIG. 3 or the NOR gate 436 of FIG. 7 to change its output state thereby to cause a high signal at the output conductor 410, FIG. 7, indicating a selection of one out of twenty of the congressional candidates. If any other congressional candidate is thereafter selected before the vote is cast, either the NAND gate 304 of FIG. 3 or the NAND gate 448 of FIG. 7 will cause a high output to appear at the conductor 456 from the NAND gate 454 indicating that two out of 20 congressional candidates have been selected. If the second congressional candidate is selected, the lockout expander circuitry of FIG. 4A receives an input at the conductor 456 to the gate 472 which acts as an inverter which will cause the NAND gate 608 to produce an output which ultimately changes the states of the NAND 618-624 and places low clear signals at the conductors 516, 518, 520 and 522. As a result, this will produce a clearing signal at all congressional candidate modules thereby to cancel the first selected congressional candidate in sufficiently rapid fashion that the second-selected candidate selection switch will not be released before the cancellation of the first-selected candidate is effected and, correspondingly, the two candidate signal disappears from the conductor 456 of FIG. 4A to terminate the clear signal. Thus, the second-selected congressional candidate will be recorded for selection.

A similar situation prevails for the presidential selection only, in this case, the input at the conductor 500 of the presidential circuitry corresponding to FIG. 4A is high upon the first presidential election and a second presidential selection will cause a high input at the conductor 502, the latter signal causing the gate 586 to change its output state so that low signals appear at the conductors 512 and 514, cancelling the first-selected presidential candidate as described above in conjunction with the first-selected candidate selection for the congressional office.

Assuming now that the voter has made his two selections, one in the congressional office and one in the presidential office, he may now operate the exit switch 908 which produces the exit signal at the conductor 722 which, in conjunction with the exit enable signal at the output conductor 510 of FIG. 4A which is also supplied to the NAND gate 726 of FIG. 8, will trigger the flip-flop 718 such that the output at its conductor 720 goes high. As a result, not only will the totalizer relay winding 802 be energized to count the total of the voters which have voted, but also the register signals at the conductor 770, 772, 774, 776 and 778 will be applied to the card modules, FIG. 2, at the input terminals 176 thereof to provide the last enabling pulse to either the gate 154 or 156, as the case may be, correspondingly to actuate the transistor 158 or 160 and complete the electromechanical counter circuit associated with the particular candidate under consideration. Of course, a similar operation occurs for the presidential candidate modules.

The trailing edge of the REGISTER output pulse at the conductor 758 of FIG. 8, on the other hand, is utilized for the purpose of providing the delayed vote reset pulse, the flip-flop 716 NAND gate 784 and inverting NAND gate 786 being utilized for this purpose as previously described. The after vote reset pulse of course operates through the circuitry of FIG. 4A causing both NAND gates 586 and 608 to change their output states, ultimately to produce the clear signals at all of the conductors 512, 514, 516, 518, 520 and 522.

The flip-flop 718 also produces the vote COMPLETE output at the conductor 818 and the candidate module switches are disabled by the outputs at the conductors 820, 822, 824 and 826. Thus, as so far described, the electromechanical counters associated with the voting machine corresponding to one selected congressional candidate and one selected presidential candidate are stepped forward by a count of one after completion of the vote and the vote COMPLETE output at the conductor 818 thereby turns on the vote complete light 906 within sight of the voter so that he is sure that his vote has been completed and counted.

The control logic circuit under remote control of an election official is shown in FIG. 9 and will be seen to have as inputs thereto the register pulse at the conductor 524 from the circuitry of FIG. 4B; the vote COMPLETE input at the conductor 818 from the circuitry of FIG. 8; and the congress ONE and presidential ONE signals respectively at the conductors 508 and 504 from the circuitry of FIG. 4.

Assuming the machine is in the non-vote position, both conductor 818 and the input conductor to transistor switch 1024 will be in the low state. Therefore, transistor switch 1024 will be conducting, turning on the associated vote complete light. Also it will be noted, both conductor 508 and 504 will be high since none of the candidates has been chosen.

When entrance is given by the election official, conductor 818 goes high and not only does the vote complete light go out, but the input conductor 1034A goes high providing the second high input to gate 1036 changing its output conductor 1038 from a high to a low. This low input turns on switch 1026 and the associated ready light.

When the signal at the conductor 508 goes low indicating that one congressional candidate has been selected, the inverter 1000 produces a high output at its conductor 1002 which is inverted by the NAND gate 1004 connected as shown whereby to produce a low output at the conductor 1006 which closes the switch 1008 and energizes the light (not shown) associated with the conductor 1010 thereby to indicate to the election official that one congressional candidate has been selected. Similarly, when one presidential candidate has been selected, the ONE signal at the conductor 504 goes low which is inverted by the gate 1012 so that its ouput conductor 1014 goes high which, after inversion by the NAND gate 1016 causes the output conductor signal at 1018 to go low thereby causing the transistor 1020 to conduct thereby to energize the light 1022 indicating to the election official that one presidential candidate has been selected.

It should be noted that the transistor 1020 which energizes the one presidential lamp 1022 is the same arrangement used for the circuitry 1008 and, as well, for the circuitries 1024 and 1026.

When both of the signals appear at 504 and 508, the two inputs at the 1028 and 1030 to the NAND gate 1032 are high so that its output at 1034 goes low causing the output of the NAND gate 1036 at the conductor 1038 to go high thus extinguishing the ready light associated with the switch 1026.

When the exit switch is pushed by a voter, conductor 818 will go low in response to the change in state of flip-flop 718 of FIG. 8. The low signal at 818 will also cause the input conductor of transistor switch 1024 to go low, turning on the Vote Complete Light. Also, 818 being low provides a blocking input to gate 1036 insuring that the Ready Light remains off. The trailing edge of the register pulse as previously described, triggers an after vote reset which clears the voter's selections from the machine. The conductors 508 and 504 now go high as previously described and transistor switches 1008 and 1020 are turned off extinguishing the one presidential lamp and the one congressional lamp.

The remote control logic of FIG. 9 also includes a two key switch, a manually actuated ADDO-X dump switch 1080, and a manually actuated platen switch 1042, the purpose of which will be hereinafter apparent. In addition, a manually controlled entrance switch 1044 is also provided under control of the election official.

At the beginning of the voting day, with the switch 1040 closed, one of the first things the election official does is manually depress the dump switch 1080 which causes conductor 96A to go low while the button is depressed. This signal is called Addo Dump and is applied to the circuitry of FIG. 15 hereinafter described. The function of switch 1080 is to initiate a zero print out of the electronic accumulator via the ADDO-X printer. The second thing the election official does is manually to depress the platen switch 1042 which causes the conductor 1054 momentarily to go low which is inverted by the gate 1056 so that the signal at the output conductor 1058 goes low to high to low providing a high/low/high output from the gate 1060 due to the presence of the high input at the other conductor 1062 which is an input to the gate 1060. The PLATEN signal at the conductor 1062 is applied to the circuitry of FIG. 6B hereinafter described.

After the platen switch 1042 has been manipulated by the official, the two key switch 1040 is opened so that the output at 1050 of the gate 1048 goes low. Now, when entrance is to be given, the official depresses the switch 1044 thereby to ground the input conductor 1051 to the inverting gate 1052 so as to provide the requisite momentary high output signal at the ENTRANCE conductor 730.

At the end of the election day, the two key is closed and once again the platen switch 1042 is depressed. This sends the platen to the left-hand home position and the official now may take an ADDO-X printout. It will be noted that the platen can not be recycled and further voting is impossible.

One further function is performed by the remote control logic insofar as vote counting is concerned. Thus, the register pulse input at the conductor 524 is inverted by the NAND gate 1064 causing its output conductor 1066 to go low to close the transistor switch 1068 and energize the relay winding 1070 of a total vote counter which, it should be understood, counts the total number of voters which have successfully registered a vote.

With reference to FIG. 6B, it will be recalled that one of the first things the election official does at the beginning of the voting day is to depress the platen switch 1042 of FIG. 9 which produces the momentary low output on the PLATEN conductor 1062 which after inversion by the converter 1116 is applied over the conductor 1118 as inputs to both the gates 1106 and 1120 thereby causing the output from the gate 1106 momentarily to go low at the conductor 1122 so as to trigger the flip-flop 1124 whereby the previously low output at the conductor 1126 goes high and remains high so as to provide a signal at the output of the inverting gate 1128, which is low, at the conductor 1130, thereby causing the transistor switch 1132 to close and energize the relay 1134 and cause the two switch contacts 1136 and 1138 to engage the +12V and ground contacts thereby to energize the motor 1140 which drives the platen to the right-hand position. As soon as the platen leaves its left-hand home position, the switch 1108 is permitted to return to its normal position thereby setting the output of the flip-flop 1072 high at conductor 1110 thereby removing one of the enabling inputs to the gate 1106 and assuring that the output of the NAND gate 1106 is high, but as will be evident this will not affect the flip-flop 1124 and the motor 1140 will continue to drive the platen to the right-hand position. As soon as the platen has reached the right-hand position, the platen switch 1142 is moved from its position in FIG. 6A so that the state of the flip-flop 1076 is changed to provide a high output at the conductor 1144.

This signal is inverted at 1147 to produce a low output at the conductor 1148 which is applied to the NAND gate 1150 of the flip-flop 1124, thereby resetting the flip-flop 1124 and deenergizing the relay 1134, thereby to shut down the motor. In addition, as the platen reaches the right-hand position, switch 1040 of FIG. 6A is changed from the open position to the closed position. Thus, conductor 1100 which previously was low will go high. Switch 1040 is a toggle switch and once it is closed it will remain closed. Therefore, conductor 1104 will go low and remain low providing a permanent disabling signal to NAND gate 1106. Operation of the switch 1142 also produces an enabling input at the conductor 1152 to the NAND gate 1120 and an enabling input at the conductor 1144 as previously described in conjunction with FIG. 8 so that entrance to the machine is now possible while the platen is in the right-hand position. When the first vote is cast and recorded, the count pulse at 524 going high will produce a low output at the conductor 1154 from the inverter 1156 thereby to trigger the flip-flop 1158 producing a high output at its normally low output conductor 1160. It should be noted that this flip-flop 1158 will remain in this high state at the output 1160 all during the voting and will not reset until the machine is disconnected from its electrical supply and then reconnected, which will produce a reset pulse at the conductor 712 which, after inversion at the inverter 1162, will reset the NAND gate 1164 to provide the normally high output therefrom at 1166. Thus, the first vote registered after the platen has been sent to its right-hand position operates, in conjunction with the switch 1142 to provide two enabling inputs to the NAND gate 1120.

The third enabling input to the NAND gate 1120 which causes its normally high output at the conductor 1170 to go low thus triggering the flip-flop 1172, will not appear until the election official has manually depressed or actuated the platen switch 1042 at the end of a voting day which will cause the platen to move to the left and at that time to print out the record of the total votes recorded by the electromechanical counters and allows the record sheet so printed to be collected by the election official. The normally low output at the conductor 1174 of the flip-flop 1172 goes high in response to the PLATEN input at the conductor 1062 providing a momentary high input at the conductor 1118 whereby the signal which goes high at the conductor 1174, after inversion by the NAND gate 1176 produces a low output at its conductor 1178 thereby to turn on the transistor switch 1180 and energize the relay 1182 which actuates the movable switch contacts 1184 and 1186 to energize the motor 1140 to cause the platen to move back to the left and print out the vote record.

When the platen reaches the left-hand home position, switch 1108 of FIG. 6A is again closed producing a low input at conductor 1110. This signal is twice inverted by NAND gates 1112 and 1190 produces a low at conductor 1192 resetting flip-flop 1172 and turning off the associated transistor switch 1180. This turns off the platen motor 1140. It will be noted that conductor 1144 is now in the low state as a result of switch 1142 being open and the platen leaving the right-hand side of the machine.

It will be seen that conductor 1152 is in the low state and will block any signal to NAND gate 1120. Also, as previously described, conductor 1100 is in the high state and conductor 1104 as inverted by gate 1102 is in the low state. This provides a blocking signal to NAND gate 1106, and the platen can not again be energized since both gates 1106 and 1120 are blocked. Conductor 1110 is low and conductor 1188 is high, providing a high printout enable signal at conductor 1118. This enables the official to take an ADDO-X printout of the vote totals or if desired, send these totals over a data-phone to a central tabulation center.

The signal at the conductor 1188, when low, provides a print-out enable signal from the circuitry of FIG. 6 which is applied to the digit and register sequencer circuits hereinafter described.

Before proceeding with a detailed description of the data section of the system, reference is had at this time to FIG. 20 which is a generalized block diagram which will illustrate the general principles of the data section of the machine. In FIG. 20, one set of accumulating registers is indicated generally by the reference character 1200 of which the first register is that indicated by the reference character 1202 and the last is indicated by the reference character 1204. It will be understood that there are 28 such registers, only the two 1202 and 1204 being shown for the purpose of clarity, one each of these registers being associated with an individual candidate. In addition, there are two fixed registers 1206 and 1208 for the purpose of identifying the machine and its serial number and, further, there is one additional accumulating register 1210 which, as will be seen hereinafter, provides count numbers which identify the candidates at the print-out.

The inputs to the registers 1202 to 1204 are from the circuitry of FIG. 2 and consist at the outputs from the conductors 222 and 224. Although the output to the electromechanical counters 72 are not from the exact same source, they are nevertheless shown as such in FIG. 20 for the sake of clarity, in order to indicate that the voting operation simultaneously actuates the electromechanical counter 26 and, as well, the data accumulation system as depicted generally in FIG. 20. The signals designated as COUNT are from the circuitry of FIG. 4B inclusive of the outputs from the conductors 526-544.

The outputs of the various registers 1202-1204 are in the form of four bit binary words, the bits and words being shifted out in parallel from the registers. Thus, the conductor 1214 represents four separate conductors derived from a decade counter corresponding to the units; the conductor 1216 represents four conductors carrying the binary words derived from a decade counter and representing the tens unit; the conductor 1218 likewise represents four conductors carrying the four bit binary word representing the hundreds unit; and the conductor 1220 represents the four conductors carrying the parallel four bit binary word representing the thousands unit. All of these words are derived from decade counters.

The fixed registers 1206 and 1208 have no input and so do not effect a counting operation as do the registers 1202-1204. Rather, these two registers 1206 and 1208 are connected such that the binary words at their output 1222 and 1224 represent a fixed number which is a number representing the voting machine as to model and serial number. Otherwise the outputs at 1222 and 1224 are as described in conjunction with the registers 1202-1204.

The circuitry of FIG. 11 embodies a bank of accumulating counters indicated generally by the reference character 1300 and a corresponding bank of shift registers indicated generally by the reference character 1302 and, as well, a bank of multiplexing gates indicated generally by the reference characters 1304. In addition to the two inputs at 222 and 526 as shown, there is an input at the conductor 1306 from the register sequencer (FIG. 15) which is inverted at 1308 for connection in common at the conductor 1310 to one input of all of the multiplexing gates 1304. The signal at the conductor 1310 normally is low as occasioned by a high input at the conductor 1306, as will hereinafter be described, so that none of the gates are enabled. However, as soon as a signal appears at the conductors 1306 which goes low indicating that the assembly of FIG. 11 is to be produced as an output to the multiplexer 1246 of FIG. 20, the enabling signal at the conductor 1310 goes high, thus enabling all of the gates 1304. It will be understood that the registers 1300 correspond to one of these registers 1200-1204 of FIG. 20 and that each of the registers 1320, 1322, 1324 and 1326 are accumulating registers associated with the shift registers 1312, 1314, 1316 and 1318. It will be appreciated also that the output conductors 1328, 1330, 1332 and 1334 from the shift register 1312 correspond to one connection 1214 shown in FIG. 20; that the output conductors 1336, 1338, 1340 and 1342 of the shift register 1314 correspond to the signal output conductor 1216 of FIG. 20 and so on such that the four shift registers correspond to the units, tens, hundreds and thousands. The reduction of the shift registers is primarily to buffer data accumulated in registers 1300 to the multiplexers 1304. The modules may be interconnected such that signal 1321 of one counter assembly be applied to 1309 of the following counter assembly. Thus all 1302 shift registers would be connected in series making it possible to provide a serial dump of accumulated data. This feature is included in the voting machine to provide an extremely simple and straight forward means of transmitting and receiving data via a data link .

Correspondingly, the four outputs 1344, 1346, 1348 and 1350 from the associated gates 1304 correspond to the single connection shown at 1234 in FIG. 20; the output conductors 1352, 1354, 1356, and 1358 of the gates associated with the register 1314 correspond to the output of 1236 of FIG. 20; and so on for the output conductors 1238 and 1240, the latter corresponding to the output conductors 1360, 1362, 1364 and 1366 of FIG. 11. It will be recalled that the outputs at 1242 and 1244 of FIG. 20 correspond to outputs of the identification register 1210 hereinafter described.

Thus, when the proper signal is present at the conductor 1306 to the circuitry of FIG. 11, all of the outputs of gates 1304 are available to the multiplexer 1246.

The counters 1300 are serially connected such that the carry output 1370 of the counter 1320 is connected to the counter 1322 and so on, the carry output 1372 of the last counter 1326 being available for another serial connection should it be desirable to provide a higher count possibility. At the beginning of a voting procedure, a general reset pulse is applied at the conductor 1374 which resets all of counters 1300 to zero.

The counts are applied at the input conductor 1376 from the NAND gate 1378 and are applied to the first counter 1320. The counters 1300 record a count at the trailing edge of an input pulse at the conductor 1376 and shift same to the registers at the trailing edge of such pulse. The input to produce the counting pulse is from the count enable conductor 222 and the count input conductor 526 which were described respectively in conjunction with FIGS. 2 and 4B.

Lastly the registers 1210 and 1212 are connected together as indicated by the conductor 1226, to provide identification numbers for the candidates at their outputs 1228 and 1230.

The multiplexing circuitry 1232 is operated in the fashion hereinafter described more particularly, such that the outputs at 1214, 1216, 1218 and 1220 of the register 1202 first appear at the respective corresponding four wire outputs 1234, 1236, 1238 and 1240 of the multiplexer circuitry 1232, whereafter the next register outputs are present at these outputs 1234, 1236, 1238, 1240 and so on through the fixed register 1208. The output lines 1242 and 1244 are the outputs at 1228 and 1230 from the register 1210. These several outputs are applied to a multiplexer 1246 having a sequential output and each digit or word represented by 4 bits at 1248, 1250, 1252 and 1254 which are decoded in the decoder 1256, the output of which at 1258 is applied to the printer 94.

The general operation of the multiplexing circuit 1232 is such as successively to produce outputs at the conductors 1234-1244, each of which is the contents of one of the registers 1204-1208 plus the candidate identification number output of the register 1210. Each of the outputs 1234-1244 is a four-bit binary word and each output 1234-1244 successively is caused to appear at the output 1248-1254 of the multiplexing circuit 1246 for application to the decoder 1256.

The interrogation at the registers 1200 is accomplished in the following manner. When switch 1045 of FIG. 9 is depressed, a signal is generated which after proper interlocking appears at FIG. 20 as the DUMP signal. The DUMP signal causes two other signals to be generated namely 1268 and 1272. Signal 1268 is a series of enable signals which allows the multiplexer 1232 to observe the contents of the registers 1200, one at a time. Signal 1272 is the TRIG which allows the Digit Sequencer 1262 to initiate its operations by generating a DRIVE signal. The DRIVE signal permits data on lines 1248-1254 to be applied to the printer 94. Once a digit has been transmitted the sequencing action continues.

Referring now to FIG. 12, the group of input conductors 1414, 1416, 1418 and 1420 and which are associated with the group of NAND gates 1422 are of course the output conductors of the group of gates 1304 associated with the register group 1302 in FIG. 11. The logic shown in FIG. 13 is simply an extension of FIG. 12. An enabling input to each group of NAND gates in FIGS. 12 and 13 is provided, at the respective conductors 1424, 1426, 1428, 1430, 1432 and 1434, as shown. The signals derived at these enabing conductors are obtained from the digit sequencer logic 1262 of FIG. 20 and are represented in FIG. 20 by the reference character 1270. The outputs of each group of NAND gates of FIGS. 12 and 13 are tied together to provide the individual output conductors 1436, 1438, 1440 and 1442. For the purpose of clarity, these conductors being individually shown in each of FIGS. 12 and 13 but it will be understood that they are commonly connected for application to the decoder circuitry 1256 of FIG. 20. It will further be understood that the outputs at the conductors 1436, 1438, 1440 and 1442 represent by the signals thereon a binary number from zero to nine corresponding to the units, tens, hundreds or thousands output of a single register. The identification registers are read first, then 3 zeros are inserted by the digit sequencer and finally the 4 digits of the candidate register are read. The most significant digit is read first in every case.

The identification register 1210 of FIG. 20 is shown in FIG. 19. As illustrated, a pair of decade counters 1500 and 1502 are serially connected by the conductor 1504 which is the carry output of the counter 1500 and there is an enabling input 1506 to the counter 1500 and, as well, a clocking or counting input at the conductor 1508. The derivation of the signal at the conductor 1508 will be described hereinafter but suffice it to say at the present, that there is one count input at the conductor 1508 for each of the registers 1202-1208 counted sequentially, see FIG. 20.

Because a ground signal is applied to certain inputs of counters 1500 and 1502 and a +5V signal is applied to other inputs of the counter 1502, the identification counter is preset to the number 10 upon initiation by input signal 1506.

The multiplexing gates constituting the two groups 1510 and 1512 thereof associated with the two counters 1500 and 1502 each have a +5V enabling input to allow the outputs at the respective groups of conductors 1514, 1516, 1518, 1520 and 1522, 1524, 1526 and 1528. These of course are applied as the inputs to FIG. 16 as will be evident.

The enabling inputs at the conductors 1432 and 1434 of FIG. 13 are controlled in sequence as are the remainder of the corresponding inputs in FIGS. 12 and 13 for providing the proper output information at the conductors 1436, 1438, 1440 and 1442.

Thus, the total count for each candidate is followed immediately by identification output from the identification register of FIG. 19 and so on for each candidate in sequence and also for the registers 1206, 1208. This last operation, of course, provides identification for the machine.

The decoder and driver assembly is shown in FIG. 16 and the circuit 1256 identified in FIG. 16 accepts the four inputs 1436, 1438, 1440 and 1442 and has ten output conductors 1600, 1602, 1604, 1606, 1608, 1610, 1612, 1614, 1616 and 1618, one and only one of which is energized in response to the binary words represented at the input conductors 1436, 1438, 1440 and 1442. Thus only one of the outputs 1600-1618 will be energized at any particular time and whichever one is energized will be inverted by one of the inverters 1620 to produce a corresponding enabling output at the respective output conductor 1622, 1624, 1626, 1628, 1630, 1632, 1634, 1636, 1638 or 1640. Each of these enabling outputs is applied to a different AND gate 1642, 1644, 1646, 1648, 1650, 1652, 1654, 1656, 1658 and 1660. The primary enabling input to the gate 1642-1660 is derived from the drive input signal at the conductor 1662 hereinafter more particularly described, which signal is buffered by the parallel gates 1664 and 1666 as primary enabling inputs to the gates 1642-1660. Thus, when two inputs are present at any one of the gates 1642-1660, the output thereof turns on a corresponding transistor switch such as the transistor switch indicated generally by the reference character 1668 and the circuit completed thereby actuates the proper drive mechanism of the printer to cause the correct digit to be presented for subsequent print out when the digit sequence is completed.

Referring now more particularly to FIG. 17 wherein relevant portions of the ADDO-X printer mechanism are shown, the ten output lines of 1670, 1672, 1674, 1676, 1678, 1680, 1682, 1684, 1686 and 1688 from the transistor switches of FIG. 16 are connected to the inputs to the printer solenoid mechanisms designated generally by the reference character 1690, as shown. Each solenoid is responsible for effecting position of the associated print bar to the particular digit with which it is associated. It will be understood that the ADDO-X printer prints out in the fashion of an adding machine and is not operated in conjunction with the previously described platen which causes the print-out from the electromechanical counters, although both operate to print upon the same record. Thus, the two printers are side-by-side.

Each time a solenoid is actuated the digit switch is moved so as to apply a D.C. Common (Ground Signal) to pin 7 of the connector shown on FIG. 17. This ground signal acts upon the electronics of FIG. 18 in such a manner as to produce a drive signal (STEP and STEP) on the output pins 18 and 19 of FIG. 17. This drive signal indicates to the digit sequencer that the last digit transmitted has been received and the sequencer (FIG. 14) is commanded to advance to the next digit. After all nine digits (two identification digits, 3 spacing zeros and four data digits from the candidate accumulator) have been received by the ADDO-X printer, the final step and STEP signal causes the digit sequencer to initiate a PRINT command which appears at the conductor 1710 and energizes a relay to cause the printer motor to start. Once the printer motor mechanism is started, the HOME POSITION switch is moved so as to apply a D.C. common (Ground Signal) to pin 5 of the connector shown on FIG. 17. This ground signal acts upon the electronics of FIG. 18 in such a manner as to produce a drive signal (MOTION and MOTION) on the output pins 20 and 21 of FIG. 17. This drive signal indicates to the register sequencer (FIG. 15) that the contents of the last register and its identifier code have been printed and that the sequencer is commanded to advance to the next register. After the contents of all registers have been printed the ADDO-X printer stops. If it is desired to obtain additional records of the contents of the electronic accumulators, these can be obtained simply by generating another DUMP command.

Before proceeding further with a specific description of the various circuits involved, it should be noted first that a four digit counter and multiplexes logic circuit (FIG. 11) is associated with each of the 28 candidates, that two further such circuits are used for counting the total number of votes for all candidates, that two further such circuits are employed as fixed registers to identify the particular voting machine, and that a special candidate identification counter arrangement (FIG. 19) is also employed. Each of the circuits associated with the candidates provides four 4-BIT outputs which are the units, tens, hundreds and thousands units whereas the candidate identification counter (FIG. 19) employs only two 4-BIT outputs. Since the count for each candidate plus his identification number will be printed out by the ADDO-X printer, this means that these six digits must be sequenced into the ADDO-X for each candidate before the printer is actuated to print. As a practical matter (not specifically illustrated) it is preferred to insert three zeros between the vote tally count and the candidate identification number so as to avoid ambiguity in the print-out for each candidate. This makes a total of nine digits to be sequenced for each candidate. The didit sequencing is controlled by the circuit of FIG. 14.

After the nine digits of each register are sequenced, the next register is sequenced and this operation is controlled by the circuitry of FIG. 15. Generally speaking, by counting the nine digits for each register sequence, a signal is generated to print the tally and identification and a further signal is generated to step to the next register. Additionally, the digit sequence counter is reset for counting the next digit sequence.

The data for each digit is inserted into the ADDO-X by energizing one of the ten input lines (0-9) thereto in response to a DRIVE signal (conductor 1662 of FIG. 16) generated for this purpose. When all nine digits have been so inserted, a PRINT signal is generated whereafter the next register is sequenced into operation.

Referring now to FIG. 15, the register sequencing operation will be explained. This circuit includes a pair of counters 1800 and 1802, a predecoder 1804, a decoder 1806 and control circuitry including the NAND gates 1808, 1810, 1812 and the NOR gate 1814. There are three principal inputs to the circuitry of FIG. 15 according to the preferred embodiment of the invention, namely, the PRINT OUT ENABLE input at the conductor 1188 (From FIG. 6B), the DUMP input at the conductor 1818, the print out reset from the circuit of FIG. 8 and the RST input at the conductor 1915 which originates from the digit sequencer as hereinafter described. A signal appearing at conductor 1822, when the two conductors 1818 and 1188 are both high so as to provide a low output at the conductor 1822 from the NAND gate 1810, causes the normally low output at the conductor 1824 from the OR gate 1814 to go high so that the inversion thereof by the gate 1812 produces a low output TRIGGER pulse at the conductor 1826. This RST pulse combines with the print out reset in OR gate 1860 and causes a reset input (via conductor 1864) to the counter 1934 which is located on FIG. 14.

The DUMP signal at the conductor 1818 is generated externally, as by a manually controlled switch in the remote control logic, and provides one enabling input to the gate 1810. Another enabling input is provided by the PRINT OUT ENABLE signal at the conductor 1188 which will be present if the platen associated with the electromechanical counters is in its right-hand or home position.

An enabling ground output from the conductor 1842 allows the sequencing operation to start. The conductors 1836, 1838 and 1840 preferably control the machine identification output whereas the conductors 1828 to 1830 are the 28 candidate sequencing controls. The conductors 1832 and 1834 provide the total vote tally sequential controls. At the end of the complete sequence, a RESET signal appears at the conductor 1844 which is applied as a low input to the OR gate 1850 so that a low RST signal will cause the output of the gate 1850 as inverted at 1852 to reset the counter 1802 and provide a low input to the OR gate 1856. The inverter 1854 provides the other input to the gate 1856 so that both being low, the gate output will go high and, after inversion by the gate 1858, will reset the counter 1800. Each occurrence of an RST signal will produce a C4RST signal to appear at the conductor 1864 through the OR gate 1860 and inverter 1862, assuming of course that the normally high PUR signal (FIG. 8) is present at the conductor 712. At the end of the sequence, the reset signal which appears at the output conductor 1844 is also connected to produce the PRINT output at the conductor 1710 in FIG. 14 as hereinafter described.

The digit sequencer is shown in FIG. 14 and includes the counter 1934 and a decoder 1936, the former of which is clocked in response to STEP inputs at the conductor 1709 (from FIG. 18) which are produced by the ADDO-X Printer where a digit has been inserted thereinto. Thus, the counter 1934 advances one counter each time a digit is inserted. It will be recalled that nine digits are involved in all, but only those six signals 1424-1434 previously described plus the 9 signal are shown.

Upon receipt of a DUMP command, the register sequencer is caused to advance to the first register (the first three registers are used for machine identification). The signal which triggers the register sequencer is the TRIG signal identified as 1826. The TRIG signal is also applied to the Digit sequencer (FIG. 14) where it triggers the Drive timing circuit which consists of gates 1900, 1986, 1918, 1940, 1942 and 1941. Triggering this circuit causes a timed pulse on conductor 1662. The operation of this circuit is described below. The signal 1662 ultimately causes a digit to be entered into the ADDO-X printer which responds with a STEP as described above.

When the trailing edge of the STEP signal goes high, the output of the gate 1991 also goes high. As a result, the output of the inverting gate 1992 goes low so that the capacitor 1994 discharges through the resistor 1993 and the gate sufficiently slowly to hold a high input on the gate 1995 to produce a low output pulse therefrom as shown. At this time, both inputs to the OR gate 1996 will be low to produce the high output pulse therefrom, as shown, which is differentiated by the capacitor 1988 in conjunction with the diode 1990 and resistor 1989 so that at the trailing edge of this pulse, momentary ground input appears at the OR gate 1900. The output of the gate 1900 goes high at the conductor 1910 which, triggers a timing circuit similar to that described above. The negative pulse output at the conductor 1926 is inverted by the gate 1940 to produce the third high input to the NAND gate 1942. The gate 1942 thus produces a negative output pulse which is inverted by the gate 1941 to produce the positive DRIVE pulse at the conductor 1662. This DRIVE output is applied to the circuit of FIG. 16 so as to insert the value of the digit over the appropriate line 1670-1688.

When the next-to-last digit has been sequenced, the 8 output of the counter 1936 is inverted at 1982 to change the state of the flip-flop and provide one enabling high input to the NAND gate 1981. The, when the last digit is sequenced, the 9 output signal is inverted at 1987 to provide the other enabling input to the gate 1981. The now low inputs to the NAND gate 1950 cause its output to go high which in turn causes the gate 1956 to discharge the capacitor 1964 through the resistor 1966 which are connected to the output conductor 1958.

The output of the NAND gate 1962 at the conductor 1966 now goes low momentarily, resetting the flip-flop 1980 and, after inversion at 1970, produces a high input at the conductor 1972 which turns the transistor switch 1974 on to produce a negative PRINT pulse output at the conductor 1710. As a result, the sequence of digits is printed by the ADDO-X and, in response to cessation of movement thereof, a MOTION signal appears at the conductor 1706 (see also FIG. 18). The negative step function produced is inverted and processed at 1903, 1905 and 1907 to cause the output of the gate 1913, due to the capacitor and resistor combination 1909, 1911, to produce the RST output at the conductor 1915. Thus, the RST signal produced at the end of the digit sequence causes the register sequencer to operate at this time.

The circuitry of FIG. 10 is intended to be utilized with the electromechanical counters previously described and, as shown, there are a number of switches 2000 associated with the electromechanical counter drive ratchets for the presidential office and a plurality of similar switches 2002 associated with the congressional office. Each of the switches 2000 is associated with a flip-flop 2004 and each of the switches 2002 is associated with a flip-flop 2006, the former having outputs as indicated by reference character 2008 in parallel to the interlock circuitry 2010 whereas the latter have outputs at 2012 directed in parallel to the interlock circuitry 2014. The interlock circuits 2010 and 2014 are constructed as previously described and have one and two outputs at the respective conductors 2016 and 2018 and 2020 and 2022. These outputs are connected to respective pairs of NAND gates 2024, 2026 and 2028, 2030 whose respective outputs 2032, 2034, 2036 and 2038 are connected to control the transistor switching devices 2040, 2042, 2044 and 2046. There is an additional NAND gate 2048 controlling the transistor switching device 2050.

A register pulse input is provided at the conductor 2052 which controls the flip-flop 2054 having an output conductor 2056 extending to the NAND gate 2048. The operation of this circuit is such that the outputs at the conductors 2032, 2034, 2036, 2038 and at the conductor 2058 are normally high such that when anyone of them goes low, the associated transistor switching circuit will conduct current and cause the respective lamps 2060, 2062, 2064, 2066, or 2068 to be energized. The outputs of all of the flip-flops shown normally are high.

As soon as the register pulse appears at the conductor 2052, the state of the flip-flop 2054 is changed so that the output at the 2056 goes low, thus driving the output of the NAND gate 2048 low causing the switch 2050 to conduct and energize the lamp 2064 to apprise the election official that the vote has been completed, provided that the other inputs in the NAND gate 2048 are all high. Thus, if the presidential candidate electromechanical counter has been operated properly such that one and only one of the switches 2000 has been closed, there will be a high output at the conductor 2016 which, through the conductor 2070, provides a high input to the NAND gate 2048. Correspondingly, if one and only one congressional candidate selection has been made and the corresponding ratchet electromechanical counter drive switch 2002 has been closed, there will be a high output at the conductor 2020 providing, through the conductor 2072, a further high enabling input to the NAND gate 2048.

Further, if two of the switches 2000 have not been closed, there will be a low signal at the conductor 2018, which, as inverted at 2074, will provide a further high input to the NAND gate 2048 at the conductor 2076. Lastly, if two of the congressional candidate electromechanical counter switches 2002 have not been actuated, there will be a low signal at the conductor 2022, which, after inversion at 2078, will provide the last high enabling input to the gate 2048 at the conductor 2080 and, under these circumstances, only the vote complete lamp 2064 will be energized. However, if an undervoting condition exists at for example the presidential electromechanical counter, none of the switches 2000 will have been closed and the thereby low output at the conductor 2016 will provide a low output at the input 2070 to the NAND gate 2048 and prevent the register signal at the conductor 2052 from causing the vote complete lamp 2064 from being energized. However, since the output at the conductor 2016 remains low, the input at the conductor 2082 to the NAND gate will be high such that when the high signal appears at the conductor 2056, the other inputs to the gate 2024 will also be high to drive its output at 2032 low and thereby turn on the switch 2040 and energize the lamp 2060 which is marked undervote for presidential selection. A corresponding operation will occur in the congressional candidate area if none of these switches 2002 is closed.

If two of the switches 2000 or two of the switches 2002 are closed, one or the other of the overvote lamps 2062 or 2068 will be energized. The lamp 2066 is the undervote lamp associated with the congressional candidate vote.

To illustrate the overvoting condition, assuming that two of the switches 2000 have been closed, the signal at the conductor 2018 will be high so that when the register signal is provided to change the state of the flip-flop 2054, the high output at the conductor 2056 will cause the gate 2026 to produce a low output and cause conduction of the switch 2042 and energization of the lamp 2062.

To illustrate a somewhat modified form of the invention, reference is now had to FIGS. 21-24 wherein a modification of the vote selection portion of the machine is shown.

In FIG. 23, the entrance switch 100 is controlled by the election official, and when opened from its normally closed position, the signal at the conductor 2102 is inverted by the inverter 2104 to produce a low output at the conductor 2106. This signal resets the NAND gate 2108 of the voting switch enabling flip-flop 2110 and also resets the NAND gates 2112, 2114 and 2116 of the respective flip-flops 2118, 2120 and 2122 in FIG. 24 which control the total vote counter circuit 2124. These flip-flops also control the lamp circuits 2126 and 2128 as later described.

Assuming that a previous voter has cast and recorded his vote by operating the exit switch 2130 so that the flip-flop 2110 is set to the state in which the output of the NAND gate 2132 is high while that of the gate 2108 is low, operation of the switch 2100 will now cause the output conductor 2134 of the gate 2108 to go high to enable the voting switch circuits at the candidate modules.

At the candidate modules (FIG. 21) this enabling signal is inverted by the inverter 2136 of each pair of voting selection switches 2138 and 2140 which controls the inputs to the NAND gates 2142 and 2144 of the respective voting selections flip-flops 2146 and 2148. The two NAND gates 2140 and 2152 of these flip-flops normally have high outputs as the respective conductors 2154 and 2156 which are cross-coupled as inputs to the two gates 2142 and 2144. Thus, one input to each gate 2142 and 2144 is high while those at the inputs 2158 and 2160 from the respective selection switches 2138 and 2140 are low. Thus, if either switch is actuated, the other input to gate 2142 and 2144 goes high causing a low output from the gate to appear at one of the cunductors 2162 and 2164. These outputs are cross-coupled as inputs to the gates 2150 and 2152, the other inputs to which are from the respective output conductors 2166 and 2168 from the NOR gates 2170 and 2172, which normally are high. Thus a selection switch 2138 or 2140 will change the state of the output from the corresponding gate 2142 or 2144 and will also alter the normally high output from the gates 2150 and 2152.

Assuming that the switch 2138 has been actuated to change the normally low output of the gate 2142 to a high output, it will be seen that this high signal is used for several purposes as previously described in conjunction with FIG. 2. First, the signal is applied as one input to the NAND gate 2174 to prepare this gate later to pass a vote-counting signal. Secondly, this signal is inverted at 2176 causing the transistor 2178 to conduct, thereby to energize the lamp 2180 adjacent the chosen candidate's name. Thirdly, this signal is inverted at 2182 to provide a low SELECT signal at the conductor 2184 which is passed not only to the vote-count gate 2186 associated with the other selection switch 2140, but also to the interlock circuit 2188 of FIG. 23. Lastly, this signal is applied as an input to the NOR gate 2172.

Similarly, actuation of the switch 2140 will cause a high output at the conductor 2164 which is connected to the NOR gate 2170; is applied as one input to the NAND gate 2186; is inverted at 2190 and 2192 respectively to cause the transistor 2194 to conduct and energize the vote selection lamp 2196, and to provide the SELECT low output at the conductor 2198 which is applied as a blocking input to the gate 2174 and as an input to the interlock circuit 2188.

It will be understood that the modules consisting of a pair of switches and associated circuits as described are duplicated for as many candidates as are necessary, and it will also be understood that such groups of switch-pairs are provided for each office within which one and only one vote selection is to be made. For the modification shown, there are five pairs of switch modules to accommodate for one of 10 selections for the office of President, and ten pairs of switch modules to accommodate for one of 20 selections for a Congressional office. Other and different arrangements as previously described will be obvious.

One feature of the modified circuit of FIG. 21 is the use of additional interlocks within each switch module pair. Thus, if the candidate associated with the switch 2138 is chosen, the vote-counting gate 2186 is blocked, and similarly for the gate 2174 if the candidate associated with the switch 2140 is chosen. Further, if first one switch of the module pair is actuated, thus causing the output of the corresponding gates 2142, 2150 or 2144, 2152 to go high and low respectively, the gate 2150 or 2152, as the case may be, now has a cross-coupled high input and a high input from its corresponding NOR gate 2170 or 2172, thus sustaining the change of state when the selector switch is deactivated. The other NOR gate, however, now provides a low input to the corresponding gate 2150 or 2152. If, now, the other selection switch of the pair is actuated, the output state of its gate 2142 or 2144 will change (go high) but that of its gate 2150 or 2152 will remain high until the first-made selection is cancelled by reason of a low, clear signal being applied from its associated NOR gate 2170 or 2172. The clearing or cancellation of the first-selected candidate then allows the NOR gate output of the second-selected candidate to go high again so as to cuase the state of the gate 2150 or 2152 to change (go low) and thereby retain the second-selected candidate selection when the second-actuated switch is released.

This automatic cancellation feature applies only to the switch-pairs of each module and is a further interlock redundancy since, as will be seen presently, the selection of a second candidate causes a change of state of the clear signal at the conductor 2200 which, after inversion at 2202 , produces a high input at the conductor 2204 causing the NOR gates 2170 and 2172 (and those of all other switch modules) to apply low clear pulses to the gates 2150 and 2152. This interlock, like the automatic cancellation feature of each switch pair, cannot be "beaten" manually and the second-selected candidate will be selected.

A selected candidate, assuming only one has been selected in the corresponding office category, will have a vote registered for him when on subsequent manipulation of the machine causes the rest of the inputs to the gates 2174 and 2186 to go high. The outputs of the gates 2174 and 2186 at the conductors 2206 and 2208 normally are high so as to cut off the corresponding transistors 2210 and 2212 but when a low signal appears, one of these transistors will conduct and step a corresponding mechanical counter by energizing its relay 2214 or 2216. Correspondingly, a "count candidate A" or "count candidate B" pulse, suitably inverted, will be applied to the instruction and totalizer gate circuits 2218 or 2220.

As will be described hereinafter, when a candidate has been selected in each of the two candidate groups, the interlocked gate circuitry 2188 and the interlocked circuitry 2222 will respond to produce a high output at the respective conductors 2224 and 2226, both of which signals are applied as two of the inputs to the NAND gates 2228. At the same time, if more than one candidate has not been selected in each of the office categories, the output conductors 2230 and 2232 of the circuitries 2128 and 2222 will remain low and, as inverted at 2234 and 2236, will be applied as two ot;er inputs to the gate 2228. Thus, if proper selection has been made for both the presidential and congressional offices (i.e., only one selection in each) four of the five inputs to the gate 2228 will be high. The fifth input to this gate over the conductor 2238 under control of the exit switch 2130, such input normally being low.

At the same time the output at the conductor 2224 of the gate circuit 2188 is inverted at 2240 so that the output at the conductor 2242 now is low and this signal, inverted at 2244, now provides a high input at the conductor 2246 to the NAND gate 2248. Similarly, the now high output at the conductor 2226, inverted at 2250, appears as a low output at the conductor 2252 and after inversion again at 2254, now produces a high output at the other input conductor 2256 of the gate 2248. Thus, the output of the gate 2248 now goes low at the conductor 2258 allowing the transistor 2260 to conduct and energize the coil 2262 of the relay 2264, thus energizing the lamp 2266 which illuminates an instruction to the voter to operate the exit 2130.

At the same time, it will be seen that the outputs at the two conductors 2224 and 2226 are also applied to a control gate 2268 for the lamp circuit 2128 so that when both of these inputs are high, the output conductor 2270 of the gate 2268 goes low and thus causes the output of the NAND gate 2272 to go high. This cuts off the transistor 2274 and deenergizes the winding 2276 of the relay 2278 and deenergizes the lamp 2280. Normally, before voting, the input at the conductor 2270 to the gate 2272 is high and when the flip-flop 2122 is reset such that the output of the gate 2116 is high at the conductor 2282, the output of the gate 2272 is low, allowing the transistor 2274 to conduct and thus energize the lamp 2280. The lamp 2280 illuminates indicia indicating to the voter that he should make his selections in the two office categories and, as described, this lamp is extinguished after the selections are made.

When the normally closed exit switch is actuated, the normally low signal at the conductor 2284 goes high and is inverted at 2286 so that the signal at conductor 2288 goes low which signal is inverted again at 2290 and provides a high output at the conductor 2292 as one input to the NAND gate 2294. The capacitor 2296 holds the other input at 2298 high for a brief period of time so that under these circumstances there is a momentary condition in which both inputs to the gate 2294 are high so that its normally low output at the conductor 2306 goes high and the normally high output at the conductor 2134 goes low. The capacitor 2308, discharging through the resistor 2310, however, momentarily holds the input at the conductor 2310 to the NAND gate 2312 high, similar to the situation with respect to the capacitor 2296 for the gate 2294 and thus there is a momentary low output at the conductor 2314. This momentary low output causes the gate or inverter 2316 momentarily to produce a high output at its conductor 2318 which is applied as one of the additional inputs to the gates 2174 and 2186 of the voting switch modules. Now, assuming that the switch 2138 has been actuated to change the state of the flip-flop 2146, all of the inputs to the gate 2174 will be high, inclusive of a TWO signal obtained from the output of the inverter 2234 at the conductor 2320. Thus, the output of the gate 2174 momentarily goes low, enabling the transistor 2210 to conduct and actuate the counter winding 2214 and also to provide a count output at the conductor 2324. A similar conductor 2326 for the switch 2140 is shown and all of these corresponding count output conductors are provided as inputs to the gate circuits 2218 or 2220.

At the same time, the inverter 2328 processes the low-high-low signal at the conductor 2314 momentarily to produce a low output at the conductor 2330. The capacitor 2332 in combination with the resistor 2334 and the shunt diode 2336 causes a pulse input at the conductor 2338 to the inverter 2340 coinciding with the trailing edge of the momentarily low pulse at the conductor 2330 and this output, after inversion at 2342, appears as a timed low output pulse at the conductor 2344 thereby changing the state of the flip-flop 2346 so that its normally high output at the conductor 2348 goes low.

The momentary low output at the conductor 2344 is connected to the two NAND gates 2346 and 2348 of the respective flip-flops 2350 and 2352 and changes the normally high outputs at their output conductors 2354 and 2356 to a low. The outputs of the NAND gates 2358 and 2360 then go high and thereby trigger the respective cancelling or clearing oscillators 2362 and 2364. The timing circuits of these oscillators produce a series of high output pulses at the respective output conductors 2366 and 2368 thereof which are inverted at 2370 and 2372 to provide the clear signals at the conductors 2200 and 2374, and these oscillators continue to operate until the NAND gates 2376 and 2378 are reset.

With respect to this, it will be seen that with a candidate selected for each office, the one inputs to the gates 2376 and 2378 go low so that when the other inputs to these gates from the oscillators 2362 and 2364 are in the form of a series of high pulses, the outputs of the gates 2376 and 2378 remain unaffected and their output conductors 2380 and 2382 remain high. However, as soon as cancellation occurs due to the clear signals from the oscillators, the one signals go high and the next high pulses from the oscillators will then reset the flip-flops 2350 and 2352 by producing low inputs to the NAND gates 2384 and 2386 thereof. The oscillators are thus shut off and the system is ready for the next voter.

The main interlock features of the modified form of the invention involve the bank of NAND gates 2388, 2390, 2392, 2394, 2396, 2398, 2400, 2402 and 2404. As shown, the select signal outputs at the conductors 2184 and 2198 of one switch module pair are connected as inputs to the gate 2388, and the SELECT output conductor pairs 2406, 2408, 2410, 2412, 2414, 2416; and 2418, 2420 from the remaining modules for the presidential office selection are connected as the inputs to the gates 2390, 2396, 2398 and 2404. Thus, when any one switch of a module is actuated the signals at the corresponding output conductors 2422, 2424, 2426, 2428 or 2430 go high. The secondary NAND gates 2432 and 2434, however, will respond by changing their normally high outputs to a low output only if two switches from different modules have been actuated. Thus, to provide for a change of state of the outputs of the NAND gates 2436 and 2438 when any combination of two switches in corresponding modules are actuated, and also to produce a signal, with interlock, when any one switch of all available is actuated, the NAND gates 2392, 2394, 2400 and 2402 as well as the NOR gate 2440 are provided.

Thus, as soon as any switch of the first two modules has been actuated, one or the other of the gates 2394 or 2392 will produce a high output at one of the other of the conductors 2442 or 2444 and the normally high output of the NOR gate 2446 will go low. This low signal appears at the conductor 2448 and is applied to the NAND gates 2450, 2452 and 2454. The NAND gate 2454 changes its normally low output to a high at the conductor 2224 previously described while, at the same time, the changed outputs (now high) at the conductors 2456 and 2458 of the gates 2450 and 2452 will place one input of each of the NAND gates 2460 and 2462 as a high. The normally high outputs of the gates 2460 and 2462 will remain high, however, unless either the NOR gate 2464 responds to actuation of a second switch in either one of the second set of switch modules, causing its normally high output at the conductor 2466 to go low correspondingly to cause the signals at the output conductors 2468 and 2470 of the NAND gates 2472 and 2474 to go high, or the gate 2404 responds to closing of either one of the switches with which it is associated correspondingly to change the states of the gates 2452 and 2472. Thus, the bank of gates 2450, 2452, 2472 and 2474 is provided to respond to two different switch selections which are not made within corresponding module groups; the two banks of gates 2388, 2390, 2392, 2394 and 2396, 2398, 2400, 2402 are provided to respond to two different switch selections within corresponding module groups; and the NOR gate 2440 is provided to respond to selection of both switches of its associated switch-pair module.

A switch selection causing a low input at the conductor 2184, followed by a switch selection causing a low input at the conductor 2414 causes the outputs of both gates 2388 and 2394 to go high and the outputs of both gate 2398 and 2402 to go high. The high output from the gate 2388 does nothing since the output of the gate 2432 will remain high unless the output of the gate 2390 also goes high, which it does not. The high output of the gate 2394, however, causes the output of the NOR gate 2446 to go low and this accomplishes the following:

1. the ONE signal gate 2454 goes to high output

2. the signal at the conductor 2456 from the gate 2450 goes high

3. the signal at the conductor 2458 from the gate 2452 goes high.

The high output at the conductor 2428 from the gate 2398 likewise does nothing since the output of the gate 2434 will remain high unless the output of the gate 2396 also goes high, which it does not. The high output of the gate 2402, however, causes the output of the NOR gate 2464 to go low to accomplish the following:

1. the ONE signal gate 2454 is unaffected and remains at high output

2. the signal at the conductor 2468 from the gate 2472 goes high

3. the signal at the conductor 2470 from the gate 2474 goes high.

Thus, the outputs at all of the conductors 2456, 2468, 2458, and 2470 are high and the outputs of the two gates 2460 and 2462 at the conductors 2480 and 2482 both will go low, either one of which will cause the output of the NAND gate 2484 at the conductor 2486 to go high. This signal, inverted at 2488, now appears as a low signal input at the conductor 2490 to the NAND gate 2492 so that the normally low output at the conductor 2230 now goes high.

For a condition in which two selections are made in the same group of modules, assume the two switches selected produce successive low signals at the conductors 2184 and 2406. The condition resulting from the signal at the conductors 2184 have been discussed previously. The signal at the conductor 2406 causes the output of the gate 2390 at the conductor 2424 to go high so that now both inputs to the gate 2432 are high. The signal at the conductor 2406 also causes the output of the gate 2394 to go high so that now both inputs to the gate 2494 are also high. In consequence, the signals at the conductors 2496 and 2498 both go low, either one of which will cause the normally low output of the gate 2436 to go high which, after inversion at 2500, causes the gate 2492 to respond with a high output.

Other combinations will be obvious. Note, for example, that any double selection within the same module will also actuate the gate 2500, or the gate 2502, or the NOR gate 2440 to produce a high output from the gate 2492 even though the automatic cancellation feature within each module (as previously described) is provided.

At any time that a high output appears at the output conductor 2230 of the gate 2492, the oscillator control gate 2358 is caused to produce a low output at the conductor 2504 which triggers the input NAND gate 2506 of the oscillator 2362.

Claims

What is claimed is:

1. In an electronic voting machine, in combination:

a plurality of candidate selection means for accepting manual selection inputs and producing electrical selection output signals corresponding thereto;

a plurality of selection logic means for receiving said selection output signals and enabling a subsequent discrete counting output electrical signal for each of said selection inputs;

electromechanical counter means for receiving said discrete counting output signals and separately tallying the number of times each individual candidate is selected and voted;

interlock means for receiving said selection output signals and producing a vote enabling output signal in response to a certain and only said certain number of candidate selections;

control logic means for receiving said vote enabling output signal to enable a vote register output signal therefrom, said vote register output signal being connected to all of said selection logic means to produce said counting output signal from any thereof enabled by said selection output signals;

voter-controlled exit means for enabling said control logic means to produce said vote register output signal therefrom upon actuation of said exit means;

after vote reset means having said vote register output signal as an input for producing an after vote reset signal which is delayed in time with respect to said vote register output signal; and

clearing means for receiving said after vote reset signal to produce a clearing signal in response thereto, said clearing signal being connected to all of said candidate selection means to cancel any selection made thereon subsequent to tallying of the vote.

2. In an electronic voting machine as defined in claim 1 wherein said interlock means produces an overvote output signal in response to actuation of more than said certain number of candidate selections, said overvote output signal being connected to said clearing means to produce said clearing signal independently of said after vote reset signal.

3. In an electronic voting machine as defined in claim 2 wherein said interlock means produces a no selection output signal in the absence of any selection output signal thereto, said no selection output signal being connected to said after vote reset means to terminate said after vote reset signal.

4. In an electronic voting machine as defined in claim 1 wherein said interlock means produces a no selection output signal in the absence of any selection output signal thereto, said no selection output signal being connected to said after vote reset means to terminate said after vote reset signal.

5. In an electronic voting machine, in combination:

a plurality of candidate selection means for accepting manual selection inputs and producing electrical selection output signals corresponding thereto;

a plurality of selection logic means for receiving said selector output signals and enabling a subsequent discrete counting output electrical signal for each of said selection inputs;

electromechanical counter means for receiving said discrete counting output signals and separately tallying the number of times each individual candidate is selected and voted;

interlock means for receiving said selection output signals and producing a vote enabling output signal in response to a certain and only said certain number of candidate selections;

control logic means for receiving said vote enabling output signal to enable a vote register output therefrom, said vote register output signal being connected to all of said selection logic means to produce said counting output signal from any thereof enabled by said selection output signals; and

voter-controlled exit means for enabling said control logic means to produce said vote register output signal therefrom upon actuation of such exit means;

said candidate selection means being separated into two groups, one for each of two different offices;

said interlock means comprising a pair of principle interlock means for receiving the separate selection output signals of each group and expander interlock means controlled by said pair of principle interlock means, said expander interlock means having said vote enabling output signal therefrom.

6. In an electronic voting machine as defined in claim 5 including:

remote control means for accepting a voting official manual input and producing an entrance output signal therefrom, said entrance output signal being connected to said control logic means to reset same.

7. In an electronic voting machine, in combination:

a plurality of candidate selection means for accepting manual selection inputs and producing electrical selection output signals corresponding thereto;

a plurality of selection logic means for receiving said selection output signals and enabling a subsequent discrete counting output electrical signal for each of said selection inputs;

electromechanical counter means for receiving said discrete counting output signals and separately tallying the number of times each individual candidate is selected and voted;

interlock means for receiving said selection output signals and producing a vote enabling output signal in response to a certain and only said certain number of candidate selections;

control logic means for receiving said vote enabling output signal to enable a vote register output signal therefrom, said vote register output signal being connected to all of said selection logic means to produce said counting output signal from any thereof enabled by said selection output signals;

voter-controlled exit means for enabling said control logic means to produce said vote register output signal therefrom upon actuation of such exit means; and

remote control means for accepting a voting official manual input and producing an entrance output signal therefrom, said entrance output signal being connected to said control logic means to reset same.

8. In an electronic voting machine, in combination:

a plurality of candidate selection means for accepting manual selection inputs and producing electrical selection output signals corresponding thereto;

a plurality of selection logic means for receiving said selection output signals and enabling a subsequent discrete counting output electrical signal for each of said selection inputs;

electromechanical counter means for receiving said discrete counting output signals and separately tallying the number of times each individual candidate is selected and voted;

interlock means for receiving said selection output signals and producing a vote enabling output signal in response to a certain and only said certain number of candidate selections;

control logic means for receiving said vote enabling output signal to enable a vote register output signal therefrom, said vote register output signal being connected to all of said selection logic means to produce said counting output signal from any thereof enabled by said selection output signals; and

voter-controlled exit means for enabling said control logic means to produce said vote register output signal therefrom upon actuation of such exit means;

said interlock means including a first pair of logic gates in which each gate receives a pair of said selection output signals and a second pair of logic gates each receiving a pair of vote selection output signals which are inputs to two gates of said first pair, and a further logic gate having the outputs of said second pair as inputs thereto.

9. In an electronic voting machine as defined in claim 8 wherein there are additional pairs of first and second logic gates, each having a further logic gate connected to the outputs of an associated second pair;

a final pair of logic gates each having a pair of outputs from two of said further gates as inputs thereto, a second pair of logic gates each receiving a pair of outputs from a pair of further gates which are inputs to two gates of said final pair;

a first output logic gate receiving the outputs of said further logic gates as inputs thereto; and

a second output logic gate controlled by the outputs of all of said first pair of logic gates all of said second pair of logic gates, and said final pair of logic gates.

10. In an electronic voting machine, in combination:

a plurality of candidate selection means for accepting manual selection inputs and producing electrical selection output signals corresponding thereto;

a plurality of selection logic means for receiving said selection output signals and enabling a subsequent discrete counting output electrical signal for each of said selection inputs;

electromechanical counter means for receiving said discrete counting output signals and separately tallying the number of times each individual candidate is selected and voted;

interlock means for receiving said selection output signals and producing a vote enabling output signal in response to a certain and only said certain number of candidate selections;

control logic means for receiving said vote enabling output signal to enable a vote register output signal therefrom, said vote register output signal being connected to all of said selection logic means to produce said counting output signal from any thereof enabled by said selection output signals;

voter-controlled exit means for enabling said control logic means to produce said vote register output signal therefrom upon actuation of such exit means; and

electronic vote count accumulating means for receiving said selection output signals and said vote register output signals electronically to accumulate the votes cast for individual candidates.

11. In an electronic voting machine as defined in claim 10 including:

printer means for receiving and printing out the tally from said accumulator means.

12. In an electronic voting machine as defined in claim 11 including:

security interlock means controlled by an election official for operating said printer means.

13. In an electronic voting machine as defined in claim 11 including:

digit sequencer means controlled by said printer means for inserting vote count digits thereinto;

register sequencer means controlled by said digit sequencer means for shifting from one candidate tally to the next when all the digits of the tally of said one candidate have been inserted into said printer means.

14. In an electronic voting machine as defined in claim 13 wherein said accumulator means includes a counter having an input each time said register sequencer means is shifted, said digit sequencer means shifting the output of said counter into said printer means for each candidate tally, whereby each candidate tally in the printer means is identified.

15. In an electronic voting machine as defined in claim 14 including:

first multiplexing means controlled by said register sequencer means for shifting out the tally of individual candidates in sequence; and

second multiplexing means controlled by said digit sequencer means for inserting digits of each tally sequentially into said printer means.

16. In an electronic voting machine, in combination:

a plurality of candidate selection means for accepting manual selection inputs and effecting selection output electrical signals corresponding thereto;

logic means receiving said selection output signals for enabling a number of discrete counting output electrical signals corresponding to manual selection inputs which meet an allowable voting selection;

electromechanical counter means responsive to said counting output signals for separately tallying the number of times each individual candidate is selected and voted;

electronic accumulator means responsive to said counting output signals for accumulating the tally of votes cast for the individual candidates in duplication of the tallies made by said electromechanical counter means;

first printing means associated with said electromechanical counter means for printing out the tallies indicated thereby;

second printing means associated with said electronic accumulator means for printing out the tallies accumulated thereby;

voting official-controlled first means for actuating said first printing means at the beginning of a voting day to print out the tally on said electromechanical counter means and open the voting machine for subsequent voting and said voting official-controlled first means actuates said first printing means at the end of a voting day to print out the tally on said electromechanical counter means, and closes the voting machine to further voting;

voting official-controlled second means for actuating transfer the tally accumulated in said electronic accumulator means to said second printing means; and

voter-controlled means for connecting those counting output signals corresponding to his vote to said electromechanical counter means and to said electronic accumulator means.

17. In an electronic voting machine as defined in claim 16 including means disabling said voting official-controlled second means until at least one vote has been recorded by the machine.

18. In an electronic voting machine as defined in claim 16 wherein said voting official-controlled first means includes a mechanical switch actuated by said first printing means in response to actuation of said voting official-controlled first means.