Traffic Signal Control System

Abstract

An apparatus for centrally controlling traffic over a wide geographical area. A master controller collects traffic information from traffic signal stations throughout the area at predetermined intervals, and stores this information in its associated memory, along with various operating time parameters associated with the traffic signal operation at each traffic signal station. A central processor reads and evaluates the traffic information stored in the master controller and continuously updates the operating time parameters. The master controller controls the traffic signals on the basis of their operating time parameters.

Description

This invention relates to a traffic control system and, more particularly, to a system for centrally controlling traffic in a wide area.

There are known many types of systems for centrally controlling traffic in a wide area. Generally, such a system comprises a plurality of terminal or local stations provided at different spots over the wide area where traffic is to be controlled and a central station which centrally controls those local stations. The central station collects various data concerning traffic from the local stations and analyzes them to foretell and indicate the degree of traffic congestion and determines what control pattern is to be selected by each of the local stations.

The central station is provided with a processing unit including an electronic computer which performs various required operations. In the prior art the electronic computer samples various traffic information detected by the local stations, that is, the presence or absence of vehicles at each of the spots and the time during which any vehicle exists within the detection area, and calculates the traffic volume at each of the spots, time occupancy, the average vehicle speed, etc. from the sampled information. In addition to these operations, the computer must perform necessary calculations to select the control pattern in accordance with which the traffic signal at each of the spots is to be controlled and to provide signals to change the traffic signals in accordance with the selected pattern, and perform various other operations such as recording or indication of necessary traffic data. Therefore, in order to effect smooth and efficient traffic control, the computer must have a large capacity and be capable of high-speed operation.

Accordingly, the primary object of the invention is to provide a traffic control system which includes a central station provided with a processing unit capable of operation with a computer having a relatively small capacity.

Another object of the invention is to provide such a traffic control system as aforesaid, wherein the central processing unit itself does not collect the traffic information detected at various spots, which is collected by and stored in a separate master controller, so that the central processing unit samples the data stored in the master controller every predetermined period of time and processes them to provide required data to be used for control purposes.

Another object of the invention is provide such a traffic control system as aforesaid, wherein when the function of the central processing unit has become paralyzed for one cause or another, the traffic signals at the different spots are controlled on the basis of the traffic information stored in the master controller at that time.

The invention will become more apparent from the following description of a preferred embodiment thereof with reference to the accompanying drawings, therein;

FIG. 1 is a block diagram of one embodiment of the invention;

FIGS. 2 and 3 are block diagrams of portions of the master controller provided in the central station;

FIG. 4 is a detailed block diagram of the input-output (I/O) device provided in the central station; and

FIG. 5 is a block diagram of another portion of the master controller.

Referring now to FIG. 1, there is shown a road network comprising a plurality of roads R, with traffic signals installed at different spots where traffic flow is to be controlled. Local or terminal stations 1-1 to 1-n are provided each to control one of the traffic signals. The traffic information detected by each local station is generally transmitted to a central station by means of telephone circuits. The central station includes a MODEM 2, a detected traffic information collector 3, a master controller 4, a I/O device 5, a processing unit 6 and a control signal transmitter 7. The traffic information transmitted every moment from each local station is received by the MODEM 2 and collected by the collector 3 and then applied to the master controller 4 to be stored therein. The information or data stored in the master controller 4 are applied to the processing unit 6 every predetermined period of time under the control of the I/O device 5.

Thus, the processing unit 6 does not collect the data to be processed. Instead, upon passage of every predetermined unit period of time the unit 6 calls the master controller 4 to receive the data therefrom and performs necessary operation on the data. This means that the unit 6 need not always be operating and that at a high speed.

The master controller 4 stores various data for each local station, such as the time of each step of the traffic signals, offset and split (these will be referred to as the operating time data) and the time that has elapsed since the reference time (the elapsed time) and the steps (these will be referred to as the variable data). When the processing unit has processed the detected traffic information, on the basis of the result of the processing the operating time data stored in the master controller are changed so as to be most suitable for control of traffic about the spot at which the traffic information has been detected, and the master controller 4 controls each local station so that the latter in turn controls its traffic signals in accordance with the data thus provided. The data are transmitted by the device 7 to the local stations 1-1 to 1-n via the MODEM 2.

As will be apparent from the above description, the master controller 4 is operatively connected to the processing unit 6 through the I/O device 5. Most of the operations required for control of the traffic signals are performed by the master controller 4, so that the computer in the processing unit 6 may be of a relatively small capacity and have a relatively low operating speed. Since the master controller 4 stores the fixed data, if the processing unit 6 has made an error or its function has become paralyzed, the operating time data stored in the master controller 4 can be used for coordinated or fixed cycle control of the traffic signals as fail-safe operation of the system.

Now turning to FIGS. 2 and 3, the master controller 4 will be described in detail. FIG. 2 schematically shows that part of the master controller which controls the local stations on the basis of the fixed data. A memory device 100 comprising core memories stores the fixed data, the variable data and instruction data. A timing pulse generator 200 produces timing pulses to be applied to a controller 300, which transfers the pulses to the variable data stored in the memory device. As the pulses are added to the data, they are changed. The changed data are collated with the operating time data for comparison. Every time an agreement occurs between the changing variable data and the fixed data, a signal is produced to control the terminal stations 1-1 to 1-n. Thus, each of the traffic signals is changed in accordance with the operating time data stored in the memory device 100. It has already been mentioned that the fixed data are always being changed on the basis of the result of the operation of the processing unit 6. This means that the operating time data are always determined on the basis of the latest detected traffic information, so that the traffic signals are always controlled on the basis of the newest operating time data. In other words, each of the traffic signals is controlled in a manner most suitable for the present traffic condition at each spot.

In case the master controller 4 is controlling the traffic signal at a selected one of the spots so that the signal is changed at a fixed cycle, the pulse generator 200 produces one timing pulse per second to be applied to the controller 300, whereupon the controller 300 reads the data expressing the time that has elapsed since the reference time (that is, the time at which the step began) as stored in the memory device 100, and "1" is added to the data, which are again written in the memory device 100. This means that the data concerning the elapsed time have one second added thereto upon lapse of every 1 second. At the same time, the data concerning the step stored in the device 100 are read by the controller 300, and on the basis of that data the data concerning the duration time of the step at that time are read from the operating time data in the memory device 100. The data are compared with the data expressing the time that has elapsed since the reference time. When both data have come to agree, the time set for that step has now passed. Then, the elapsed time stored in the memory device is reset, and the data expressing that step are read by the controller 300 so that "1" is added to the data, and the new data are written in the memory device 100 as the data concerning the next step. At the same time, a control signal is applied to the terminal station so as to change the step of traffic signal to the next one.

Suppose that the master controller 4 is conducting traffic-actuated control of the traffic signals. In this case, whenever the pulse generator 200 produces a clock pulse, the data expressing the time that has elapsed since the reference time are read by the controller 300 from the memory device 100, and "1" is added to the data, which are then written in the memory 100. On the other hand, the data expressing the step are read by the controller 300, and on the basis of the data the data concerning the initial green time at that step is read from the memory device 100, and is compared with the data concerning the time that has elapsed since the reference time. When the data concerning the time that has elapsed since the reference time exceeds the data concerning the initial green time, the manner in which the traffic signal is controlled will depends on whether or not there is any vehicle on the spot. If there is no vehicle on the spot, a signal is applied to the corresponding terminal station to change from the present step to the next one, that is, the traffic signal is changed to yellow immediately upon lapse of the initial green time. On the contrary, if there is any vehicle on the spot, the green time is extended and the controller 300 reads from the memory device 100 the data concerning the time (the extension of the green time) that has passed since the end of the initial green time, and "1" is added to the read data, which are then written in the memory device. The controller 300 reads from the memory device 100 the data concerning the actual extension of the green time and the data concerning the unit extension of the green time, so that the two data are compared. If the two data are equal, it is again checked whether there is any vehicle on the spot at that time. If there is no vehicle there, a signal is applied to the terminal station to change the step of the traffic signal to next one. However, if there is any vehicle on the spot, the green time is again extended so that the above operation is repeated. As the green time is extended in this manner, the data concerning the extension, that is, the time that has elapsed since the end of the initial green time and the data concerning the maximum extension of the green time are read by the controller 300 from the memory device 100 and compared. If the former data have come to exceed the latter, the green time can no longer be extended, so that a signal is given to the corresponding terminal station to change the traffic signal at the spot to the next step, say, red.

In case the traffic signals are controlled in a coordinated manner, the pulse generator 200 produces 100 pulse per signal cycle to be applied to the controller 300. (The pulses will be referred to as the "percent" pulses.) Whenever one pulse is applied to the controller 300, one of the variable data stored in the device 100, for example, the data concerning the time that has passed since the reference time and which is expressed as a percent of one signal cycle, are read by the controller 300, and "1" is added to the data, which are then stored in the memory device 100. On the other hand, the operating time data concerning offset and split as stored in the memory device 100 are read by the controller 300 upon application of every one "percent" pulse thereto, so that these data are compared with the previously mentioned data to which "1" is added upon application of every one "percent" pulse to the controller 300. If the data expressing the time that has elapsed since the reference time has come to exceed the data expressing the offset, a signal is applied to the corresponding terminal or local station to start the green signal. If the above-mentioned data expressing the elapsed time has come to exceed the data expressing the split, a signal is applied to the corresponding terminal station to terminate the green signal. The operating time data stored in the memory device 100 are determined by the processing unit 6 on the basis of the traffic conditions detected at each of the spots.

Turning now to FIG. 3 which shows that portion of the master controller 4 which collects the traffic informations or data detected at the different spots, a plurality of vehicle detectors 1'-1 to 1'-n are provided at the spots where traffic is to be controlled. While each of the detectors is detecting a vehicle, it produces an output signal "1," which is transmitted through the MODEM 2 to the data collector 3. The memory device 100 has storage areas corresponding to the detectors 1'-1 to 1'-n, respectively. The pulse generator 200 produces a pulse every predetermined period of time, say, every 50 m. sec. This pulse signal causes an address register MAR included in the controller 300 to scan the coincidence circuits 310-1 to 310-n within 50 m.sec. and at the same time successively designate the addresses of the spots at which the detectors are installed. Suppose that the register MAR has designated the coincidence circuit 310-1. When the vehicle detector 1'-1 has detected a vehicle, the coincidence circuit 310-1 produces an output signal, which is applied to an OR circuit 320. Therefore, when the coincidence circuit 310-1 produces an output, the OR circuit 320 produces an output. On the other hand, when the address register MAR has designated the coincidence circuit 310-1, the data concerning the corresponding spot that are then stored in the memory device 100 are read therefrom. At this time, if there is an output from the coincidence circuit 310, the output from the OR circuit 320 causes the controller 300 to add "1" to that data, and the new data are again written in the memory device 100.

In this manner, while the vehicle detector 1'-1 is detecting a vehicle, "1" is added to the data in the corresponding address of the memory device 100 every 50 m. sec. Therefore, if the data are sampled every unit period of time, the time occupancy for the unit period of time at the spot can be obtained. Every time sampling is done, the data at the corresponding address in the memory device 100 are rewritten.

The traffic volume in the unit period of time at each of the spots can be obtained in the following manner. When the coincidence circuit 310-1 has been designated by the address resister MAR, the other corresponding address in the memory device 100 is designated. When a coincidence circuit 120 produces an output, "1" is added to the data in that other address, and the new data are written in the memory device. The data are read by the controller 300. If the data used to obtain the above-mentioned time occupancy comprise 16 bits, the last three bits are stored in the register 110 through the controller 300. If the first of the four bits input to the coincidence circuit 120 is "1," the second bit "0," the third bit "0" and the fourth bit "0," the circuit 120 produces an output signal. This condition occurs when the detector has detected one vehicle. When the detector 1'-1 is detecting a vehicle, the OR circuit 320 produces an output signal every time the coincidence circuit 310-1 is designated. Therefore, while the detector is detecting a vehicle, the coincidence circuit 120 produces an output when it has received the second of the pulses produced by the pulse generator 200 every 50 m. sec. after it received the first one, and thereafter the circuit 120 produces no output signal. Therefore, if the data stored in the address of the memory device 100 are sampled every unit period of time, the traffic volume per unit period of time at the corresponding spot can be obtained.

In the above manner, the traffic informations detected at the different spots are collected and stored in the corresponding areas in the memory device 100 included in the master controller 4. The informations are sent to the processing unit 6 through the I/O device 5 every unit period of time. The operating time data stored in the memory device 100 of the controller 4 are rewritten on the basis of the result of operation of the processing unit 6. The detected data stored in the memory device 100 are transfered to the processing unit 6 every unit period of time under the control of the I/O device 5. The transferring operation will be explained with reference to FIG. 4.

As shown in FIG. 4, the master controller 4, the I/O device 5 and the processing unit 6 are connected by means of data lines B1 to B4, and there are also provided control lines C1 to C4. In case the operating time data processed by the processing unit 6 and temporarily stored in the memory device of the unit are written as the operating time data in the memory device 100 of the master controller 4, and also in case the data detected at the spots are written in the memory device of the processing unit 6, the processing unit 6 designates the first of the addresses in the memory device of the processing unit 6, the first of the addresses in the memory device 100 of the master controller 4, the number of the words to be transferred and the instruction word.

An FNR register 8 stores the above-mentioned instruction word; an IMR register 9 stores the first address of the memory device 100 of the master controller 4; and MAC register 10 stores the first address of the memory device of the processing unit 6; and a TNR register 11 stores the number of the words to be transferred. There are also shown in FIG. 4 a clock pulse generator 12, a translating circuit 13 which receives the output pulses from the generator 12 to control the gates and registers to be described hereinafter, a TWR register 14, an adder 15 and a BUR register 16.

In this embodiment, the transfer of data between the controller 4 and the unit 6 is controlled by the asynchronous method that the transfer operation is interlocked by the request signal and the response signal. To put it in more details, when the clock pulse generator 12 produces a pulse to be applied to the translating circuit 13, the circuit 13 produces an output as the request signal, and after a response signal corresponding to the request signal has been produced, the circuit 13 receives the next clock pulse from the generator 12. In other words, the next clock pulse is not applied to the circuit 13 until the request signal is produced, so that the present condition is maintained until the next clock pulse is produced.

The control lines C1 include a line SLFN, which becomes energized or "on" when a code for instructing the data to be transferred and a code for designating the I/O device 5 have been applied to the information line B1, provided that there is no data transfer request signal from the devices connected to the processing unit 6. The line SLEN becomes deenergized or "off" when a line ACPT has become "on."

The control lines C2 further includes a line SRVI. In case the data are transferred from the master controller 4 to the processing unit 6, the line SRVI becomes "on" when the data to be transferred have been applied to the data line B1, and "off" when a line SRVO included in the control line C1 has become "on." In case the data are transferred from the processing unit 6 to the master controller 4, the line SRVI becomes "on" when the I/O device 5 has become ready to receive data, and "off" when the line SRVO has become "on" upon complection of transfer of the data.

In case the data are transferred from the master controller 4 to the processing unit 6, the line SRVO becomes "on" after the processing unit 6 has received the data on the data line B1, and "off" when the line SRVI of the control lines C2 has become "off." In case the data are transferred from the processing unit 6 to the master controller 4, the line SRVO becomes "on" when the line B1 has received the data to be transferred, and "off" when the control line SRVI has become "off."

The control lines C2 further include a line ADRI. In case the data are transferred from the master controller 4 to the processing unit 6, the line ADRI becomes "on" when the I/O device 5 has applied to the data line B1 the data concerning the address in the core memory of the processing unit 6 to which the data are to be transferred, and "off" when the line SRVO in the control lines C1 has become "on."

The line REQD included in the control lines C2 becomes "on" when the I/O device 5 has got ready to transfer one word of the data, and "off" when the line ACK included in the control lines C1 and then the line INTL included in the control lines C2 have become "on."

The line REQI included in the control lines C2 becomes "on" when the I/O device 5, or one of the other devices connected to the processing unit 6 has made a request for data transfer, and "off" when the line ACPT in the control lines becomes "on" after the line ACK in the control lines C1 became "on." The line ACK becomes "off" when either the line REQD or REQI has become "on," with the lines ACPT, INTL and DRCT being "off." The line INTL included in the control lines C2 becomes "on" when the I/O device 5 has received the signal on the line ACK, and "off" when the data transfer has been completed so that the line SRVO of the control lines C1 has become "off."

The line MARC of the control lines C3 becomes "on" when the address register MAR of the master controller 4 is set; the line RWCL becomes "on" when the memory device 100 is energized; the line RWGL becomes "on" when data are written into the memory device 100; and the line MBRG becomes "on" to set the memory register when the data in the memory device 100 are read.

The transfer of data between the master controller 4 and the I/O device 5 is performed so that every one word is transferred at one time. When transfer of one word has been finished, the control line ONEE becomes "on," and when transfer of all the data has been completed, the line ALLE becomes "on."

The line UERR included in the control lines C3 becomes "on" when the function of the processing unit has become paralyzed. When the master controller 4 receives the signal on the line UERR, it controls the terminal stations so that a coordinated traffic signal control is effected in accordance with the operating time data stored in the memory device 100.

The signals on the above-mentioned control lines C1 - C4 are used as the response or confirmation signals in the transfer of data between the processing unit 6 and the I/O device 5 and also between the master controller 4 and the device 5.

When the first clock pulse has been produced by the pulse generator 12, if the request signal lines ACPT, INTL and DRCT are "off," the first gate circuit 17 receives the signal from the translating circuit 13 so as to be opened. After that, when the response signal line SLFN becomes "on," the FNR register 8 is set, so that the instruction code and the data designating the I/O device 5 on the line B1 are stored in the FNR register 8, and then a second clock pulse is applied to the translating circuit 13.

When the second clock pulse has been produced, if the request signal line ACPT is "on" and the response signal line SLFN is "off," a third clock pulse is applied to the translating circuit 13. When the third clock pulse has been produced, if there is a request signal on the line SRVI, the first gate 17 is opened. After that, when the response signal line SRVO becomes "on," the MAC register 10 is set, so that the data on the line B1 is stored in the MAC register 10, and a fourth clock pulse is applied to the translating circuit 13. After the fourth clock pulse was produced, when the response signal line SRVO has become "off", the request signal line ACPT also becomes "off" and a fifth clock pulse is applied to the translating circuit 13. When the fifth clock pulse has been produced, the TWR register 14 is reset by the signal received from the translating circuit 13, and at the same time a request signal is produced on the line REQD. After that, when the response signal line ACK becomes "on," a sixth clock pulse is applied to the translating circuit 13, whereupon the request signal line INTL becomes "on." After that, when the response signal line ACK has become "off," the I/O device 5 retains the data line B1, and a seventh clock pulse is applied to the translating circuit 13. When the seventh pulse has been produced, the second, third and fourth gates 18, 19 and 20 are opened and at the same time, the request signal ADRI is produced, and the data stored in the MAC register 10 are applied to the data line B2 through the third gate 19. After that, when the response signal line SRVO becomes "on", the MAC register 10 is set, and an eighth clock pulse is applied to the translating circuit 13.

Meanwhile, the data stored in the MAC register 10 and applied to the line B2 are also applied to an adder 15, and since a fifth gate 21 is opened, "1" is added to the data, and the added data are applied through the second gate 18 to the MAC register 10 to be stored therein. After the eighth clock pulse was produced, when the response signal line SRVO becomes "off," a ninth clock pulse is applied to the translating circuit 13 and at the same time, "1" is added to the data stored in the TWR register 14.

When the ninth clock pulse has been produced, the first gate 17 is opened and at the same time the request signal SRVI is produced, and when the response signal SRVO is produced, the IMR and FNR registers 9 and 8 are set since the value in the TWR register 14 is 1, so that the data on the data line B1 are applied through the first gate 17 to the IMR and FNR registers 9 and 8 so that the first four bits of the data are stored in the FNR register 8, with the remaining 12 bits stored in the IRM register 9, and a 10th clock pulse is applied to the translating circuit 13.

When the 10th clock pulse has been produced, the second and sixth gates 18 and 22 are opened, but the fifth gate 21 is closed. After that, when the response signal line SRVO becomes "off," the next clock pulse is applied to the translating circuit 13 as equvalent to the seventh clock pulse, since the value in the TWR register 14 is "1" which is less than "2". At this time, if the value in the TWR register 14 is "2," the TNR register 11 is set, so that with the fifth gate being closed, the data stored in the TNR register 11 have -1 added thereto, and the result is again stored in the TNR register 11. Thus, the operations from the seventh to the 10th clock pulses are repeated three times from the time when the fifth clock pulse was produced to reset the TWR register 14 till the value in the TWR register 14 becomes "3." This will be explained below in detail.

When the request signal REQD is produced and the response signal line ACK becomes "on" after the production of the fifth clock pulse, there are stored in a predetermined area of the processing unit 6 the first of the addresses of the core memories of the unit 6 and the master controller 4 in which the transferred data are to be stored, the instruction word and the number of the words to be transferred. To put it in detail, the instruction word is stored in the first four bits of the first of the predetermined areas; the first address of the core memory of the master controller 4 is stored in the remaining 12 bits thereof; the number of the words in the data to be transferred is stored in the second of the areas; and the first address of the core memory of the processing unit 6 is stored in the third of the areas. Under the condition, when the ninth clock pulse has been produced, if the value in the TWR register 14 is "1" after the request signal SRVI is produced and the response signal SRVO becomes "on," the instruction word and the first address of the master controller 4 stored in the first of the predetermined areas of the processing unit 6 are applied to the data lines B1 and B3 so that the instruction word and the first address of the master controller 4 are stored in the FNR and IMR registers 8 and 9, respectively. When the value in the TWR register 14 becomes "2," the number of the words to be transferred are supplied form the second of the predeterimined areas in the processing unit 6 to the data lines B1 and B3 to be stored in the TNR register 11. When the value in the TWR register 14 becomes "3," the first address of the core memory of the processing unit 6 is supplied from the third of the predetermined areas of the processing unit 6 to the MAC register 10 to be stored therein. In this manner, the instruction word stored in the FNR register 8 is read by the translating circuit 13 so that it is determined whether the instruction word is the instruction to transfer the data in the processing unit 6 to the fixed data of the master controller 4, or the instruction to transfer the detected informations collected by the master controller 4 to the processing unit 6. Suppose that the instruction stored in the FNR register 8 is to transfer the data in the processing unit 6 to the operating time data in the master controller 4. Then, the lines MARC, RWGL and RWCL of the control lines C3 become "on" as will be described later.

When an 11th clock pulse has been produced, the request signal INTR is produced. After that, when the response signal STRL is prduced, a 12th clock pulse is applied to the translating circuit 13. When the 12th clock pulse has been produced, the fourth, third and second gates 20, 19 and 18 are opened and the request signal ADRI is produced. Therefore, the data stored in the MAC register 10 are applied to line B3 through the third gate 19. When the response signal line SRVO becomes "on," the MAC register 10 is set, so that the data in the MAC register 10 applied to the line B2 are applied to the adder 15, where 1 is added to the data and the resultant data are stored in the MAC register 10. Then, a 13th clock pulse is applied to the translating circuit 13.

When the 13th clock pulse has been produced, the seventh and eighth gates 23 and 24 are opened, so that the address of the memory device 100 of the master controller 4 stored in the IMR register is applied to the data line B4. When the response signal line SRVO becomes "off," the control line MARC becomes "on," so that the data applied to the line B4 are stored in the address register of the memory device 100 of the master controller 4, and a 14th clock pulse is applied to the translating circuit 13.

When the 14th pulse has been produced, the first gate 17 is opened and the request signal SRVI is produced. When the response signal SRVO is produced, the BUR register 16 is set, so that the data applied to the data line B1 are stored in the BUR register 16, and a 15th clock pulse is applied to the translating circuit 13.

When the 15th clock pulse is produced, the eighth and ninth gates 24 and 25 are opened and the control lines RWCL and RWGL become "on," so that the data stored in the BUR register 16 are applied to the data line B4 and are written in the core memory whose address was designated when the 13th clock pulse was produced. After that, when the response signal SRVO becomes "on," a 16th clock pulse is applied to the translating circuit 13.

When the sixteenth clock pulse has been produced, the six, fifth and second gates 22, 21 and 18 are opened and the TNR register 11 is set, so that -1 is added to the data stored in the TNR register 11. After that, a 17th pulse is applied to the translating circuit 13.

When the 17th clock pulse has been produced, the seventh and second gates 23 and 18 are opened, and if the data stored in the TNR register 11 are positive, the request signal ONEE is produced, while if the data are negative, the request signal ALLE is produced. When the response signal STPL becomes "off," the IMR register 9 is set so that 1 is added to the data stored in the IMR register and the resultant data are again stored in the IMR register 9. Then, an 18th clock pulse is applied to the translating circuit 13.

When the 18th pulse has been produced, if the data in the TNR register 11 are positive, the next clock pulse is applied to the translating circuit 13 as equivalent to the 11th clock pulse, so that the operations from the 11th to 18th clock pulses are repeated. If the data in the TNR register 11 are negative, however, the next clock pulse is applied to the translating as equivalent to the first clock pulse so that the operation of the system is completed. Thus, the data stored in the TNR register 11 express the number of the words of the data to be transferred, and every time the sixteenth pulse is applied to the translating circuit 13, -1 is added to the data, so that when the transfer of all the data has been completed, the data in the TNR register 11 become 0.

The case will now be described in which, after the production of the 11th clock pulse, the instruction word stored in the FNR register 8 is to transfer the detected data in the memory 100 of the master controller 4 to the memory device of the processing unit 6.

When the 11th clock pulse has been produced, the request signal INTR is produced. After that, when the response signal STPL becomes "on," a 12th clock pulse is applied to the translating circuit 13. When the 12th clock pulse has been produced, the third, second and fourth gates 19, 18 and 20 are opened, and the request signal ADRI is produced and the request signal DRCT becomes "on." After that, when the response signal SRVO becomes "on," 1 is added to the data stored in the MAC register 10, and a 13th clock pulse is applied to the translating circuit 13. When the 13th clock pulse has been produced, the seventh and eighth gates 23 and 24 are opened, so that the data expressing the address of the core memory 100 of the master 4 stored in the IMR register 9 are applied to the data line B4. After that, when the response signal SRVO disappears, the control line MARC is set so that the data on the line B4 are stored in the address register of the core memory 100 of the master controller 4, and then a 14th clock pulse is applied to the translating circuit 13. When the 14th clock pulse has been produced, the tenth gate 26 is opened and the control lines MBRG and RWCL are set and the request signal READ is produced. When the BUR register 16 is set, the data stored in the address of the core memory of the master controller 4 designated by the 13th clock pulse are stored in the BUR register 16, and then a 15th clock pulse is applied to the translating circuit 13. When the 15th clock pulse has been produced, the ninth and fourth gates 25 and 20 are are opened, and when reqiest signal SRVI is produced, the data in the BUR register 16 are applied to the data line B1. After that, when the response signal SRVO becomes "on", a 16th clock pulse is applied to the translating circuit 13.

When the 16th pulse has been produced, the sixth, fifth and second gates 22, 21 and 18 are opened, and the TNR register 11 is set, so that 1 is added to the data in the TNR register 11. After that, a 17th clock pulse is applied to the translating circuit 13.

When the 17th clock pulse has been produced, the seventh and second gates 23 and 18 are opened, and if the data stored in the TNR register 11 are positive, the request signal ONEE is produced, whereas if the data are negative, the request signal ALLE is prouced. When the response signal STPL becomes "off," the IMR register 9 is set, so that 1 is added to the data in the IMR register 9. After that, an eighteenth clock pulse is applied to the translating circuit 13.

When the 18th pulse has been produced, if the data stored in the TNR register 11 are positive, the next clock pulse is applied to the translating circuit 13 as equivalent to the 11th clock pulse, so that the operations from the 11th to 18th colck pulses will be repeated. If the data in the TNR register are negative, however, the next clock pulse is applied to the translating circuit 13 as the first clock pulse so that the operation of the system is completed.

In the above-mentioned operations of the master controller 4, the collecting of the detected traffic information or data, the operation of providing control signals for the traffic signals, and the transfer of the data between the controller 4 and the processing unit 6 are conducted in the order mentioned.

Turning to FIG. 5, there are shown AND circuits 27, 28, 29 and 30 to one input of which is applied the signal AKI. The signal AKI becomes "on" when the master controller 4 is to be operated, for example, when a timing pulse is produced for collection of the detected information, when a timing pulse is produced for operation of providing the control signals, or when a request for transfer of data between the master controller 4 and the processing unit 6 is made. The other input signal to the AND circuit 27 becomes "on" when a timing pulse for collection of the detected traffic information is produced; the other input signal to the AND circuit 28 becomes "on" when a timing pulse for operation of providing the control signals is produced; and the other input signal to the AND circuit 29 becomes "on" when a request is made for transfer of data between the master controller 4 and the processing unit 6. The output from each of the AND circuits 27, 28, 29 and 30 sets the corresponding one of the four bits of a register 31 to render its output "1," and when any one of the bits has been set, an OR circuit 32 produces an output signal to set a flip-flop 33.

The set output from the flip-flop 33 operates a counter IC1, while the reset output therefrom operates another counter IC0. The latter counter ICO controls the collection of the detected traffic data and the operation of providing control signals for the traffic signals in a predetermined order. The counter IC1 scans the outputs from the register 31 after the signal AKI has been produced. If during the scanning operation it detects any one of the outputs from the register 31, a signal CM is produced to reset the flip-flop 33.

Suppose that while the counter IC0 is controlling a certain operation of the system, a timing pulse for collection of the detected traffic informations coincides with the request for transfer of data between the master controller 4 and the processing unit 6. At this time, the signal AKI must be "1," so that the AND circuits 27 and 29 produce an output to set the first and third bits of the register 31. As a result, the output signal from the OR circuit 32 becomes "1" to set the flip-flop 33, so that the counter IC1 operates. This causes the reset output from the flip-flop 33 to become "0," so that the operation that has until then been performed by the counter IC0 is stopped. The counter IC1 scans the first to fourth outputs of the register 31. Since the first and third outputs are "1," the counter IC1 receives the first output to produce the output CM to reset the flip-flop 33. Then, on the basis of the first output, the counter IC0 controls the collecting operation of the detected information. After the collecting operation has been finished, the data transfer is yet to be conducted, so that the signal AKI is "1." Since there is no timing pulse for the operation of providing control signals for the traffic signals, the output from the third bit of the register 31 is scanned by the counter IC1 so that the transfer of data between the processing unit 6 and the master controller 4 is performed.

As previously mentioned, the master controller 4 performs the collection of the detected traffic data, the operation of providing control signals for change of the traffic signals, and the transfer of data between the controller 4 and the processing unit 6 in the order mentioned. While the data transfer is being conducted, if a timing pulse happens to be produced for the collection of the detected data or for the operation of providing the control signals, the data transfer is temporarily interrupted. Also, while the operation of providing the control signals is being performed, if a timing pulse is produced for the collection of the detected traffic informations, the operation is interrupted for collection of the detected informations.

Claims

What we claim is:

1. An apparatus for centrally controlling traffic signals at different locations within a wide geographical area comprising:

a first control means for controlling the condition of traffic signals, including means for communicating between said first control means and a plurality of signal terminal stations, each of said signal terminal stations having at least one associated traffic signal, the terminal stations collecting traffic information and communicating said traffic information to said first control means, said first control means further including means for storing data, said data being utilized by said first control means for controlling the condition of said traffic signals, said data including operating time data for each of said traffic signals, an elapsed time, and traffic information received from said traffic terminal stations, said first control means controlling the condition of said traffic signals on the basis of said stored operating time data;

means for processing said traffic information received from said signal terminal stations, said processing means including means for updating said operating time data stored in said storage means on the basis of said processed traffic information;

a second control means connected to said first control means and said processing means for controlling communication between said first control means and said processing means;

means connected to said first control means for generating timing signals;

means included in said first control means and actuated by said timing means for comparing said elapsed time data with said operating time data, and means actuated by said timing means for updating by one said elapsed time data at predetermined intervals.

2. An apparatus according to claim 1, wherein said detected traffic information stored in said master controller are applied to said processing unit every predetermined unit period of time, so that said processing unit processes said operating time data.

3. An apparatus according to claim 2, wherein said processing means includes means for actuating said comparing means at the conclusion of the most recent updating of said operating time data stored in said first control means by said processing means.