Alarm System

Abstract

This invention relates generally to alarm systems and, more particularly, to an alarm system using a two-way communication link between a monitoring station and a transponder station at a remote location the alarm status of which is being monitored, such system employing encoding techniques based on the generation of a truly random signal at the monitoring station.

Description

BACKGROUND OF THE INVENTION

Alarm system installations, particularly those which are used to protect relatively large industrial institutions having a highly valued inventory such as money or other valuable materials, as in banks, industrial plants, government installations housing classified documents, and the like, should be such that it is substantially impossible for an intruder to thwart the operation of such a system and, thus, enter the premises undetected.

In simple alarm systems in present use, intruders often are able to take appropriate action to prevent the annunciation of an alarm. Even in the more complicated of such systems using selective coding and communication techniques for informing a central monitor station of the alarm status of a station at a remote location, a sophisticated intruder may be able, for example, to "break" the system code using appropriate electronic techniques and thereby produce a simulated signal indicating an "all clear" status for insertion into the communication link between the stations and, accordingly, avoid detection.

Further, it is desirable that an alarm be able to detect and display other undesirable conditions which may exist in the system, as, for example, the presence of an open or short circuit in the communication link, or of other troubles which may arise in the system, such as malfunctions in the equipment being used or tempering with the system by an intruder.

DESCRIPTION OF THE PRIOR ART

Alarm systems of the prior art for installations which require a relatively high degree of protection usually utilize a one-way communication link for transmitting alarm information from a remote location to a central monitoring station. In such systems, for example, an appropriately encoded signal which contains the alarm status information is entirely generated at the remote location and is transmitted to the central monitor station where it is decoded and the alarm status information displayed in some appropriate audible or visual manner. Such systems may utilize either signals of a non-random nature which are suitably encoded at the remote station with the alarm status information, or, alternatively, they may utilize signals of a psuedo-random nature for encoding. The complementary decoding process utilized at the monitor station detects and identifies the alarm status information which is carried by the remotely generated signals.

Such systems, however, can often be defeated by an intruder through appropriate electronic techniques wherein the intruder, for example, can use his own equipment to produce a simulated signal corresponding to the coded signal which signifies a normal or "all-clear" condition and can insert such artificially produced signal onto the communications link in place of the signal generated by the system itself. In that way the monitor station is not alerted to the presence of the intruder and the true nature of the alarm status at the remote location remains undetected.

Thus, where the encoded signal is generated at a remote station, whether using a non-random signal or a pseudo-random signal in the encoding process, an intruder normally need only record the encoded signal in the "all clear" state and, by suitable statistical analysis thereof, fashion a correctly synchronized simulated signal having the same characteristics as the true encoded signal, without the need for a knowledge of the specific coding scheme which is being used therein.

Even in systems where the code scheme being used can be changed periodically, the number of different code schemes available is usually quite limited in the prior art systems and the capability of an intruder to reproduce the desired simulated "all clear" signal is still relatively high.

While more elaborate coding systems may be devised by the prior art to defeat intruders in certain applications, such as for extremely sensitive military security purposes where cost is often no object, the more complex equipment required for such purposes increases the costs thereof to a point where the use of such elaborate schemes in the applications in which the system of the invention is intended becomes prohibitive.

As discussed more fully below, the system of the invention is designed so that its costs are substantially the same as the costs of prior art systems for use in the same applications and are well below the cost of the more complex coding systems used in other highly sensitive security applications. However, despite the relatively low cost of the system of the invention, the system is much less susceptible to the recording and analysis techniques discussed above and the possibility that an intruder might defeat the system is considerably reduced in comparison with such possibility in connection with presently known systems of comparable cost.

DESCRIPTION OF THE INVENTION

The above discussed disadvantages of prior art systems are overcome by the system of the invention, which permits the use of an extremely large number of different code schemes for use therein. While the techniques used in the invention are somewhat more complex than those used in prior systems, the increase in complexity does not require an unwarranted increase in equipment costs while, at the same time, the ability of an intruder to "fool" the system is considerably reduced in comparison to present systems.

In this system of the invention, a two-way communication link is utilized between a central monitoring station and one or more remote locations which are to be protected. Further, the system utilizes a basic signal which is truly random in nature and which is generated at the monitor station for transmission to a transponder station at a remote location. The transponder appropriately encodes the random signal with alarm status information using a specifically selected code program network to form specific code words representing the different alarm status conditions. The random signal is simultaneously encoded at the monitor station so as to produce a plurality of code words representing a plurality of different anticipated alarm status conditions which may be present at the remote location, the monitor encoder using the same specifically selected code program network as that used at the transponder.

The encoded alarm status signal transmitted from the transponder to the monitor station uses, in a preferred embodiment, the same communication link as that used to transmit the random signal from the monitor to the transponder station, through appropriate time-multiplexing techniques. The encoded signal from the transponder is compared at the monitor with each of the plurality of encoded alarm status signals generated at the monitor. So long as the encoded word from the remote location matches the encoded "all clear" word of the monitor with which it is being compared, an "all clear" output signal is generated at the monitor. However, when the encoded word received from the remote location is the same as that of one of the plurality of encoded alarm signals generated at the monitor, an alarm output signal is produced to indicate the particular alarm status involved, such output signal being thereupon used to activate an audible and/or a visual display unit. As used herein the term "alarm status" is used to include an indication of an "all clear" status at the remote location.

Moreover, in the system of the invention, appropriate logic circuitry in the comparator unit at the monitor is used to detect and display the presence of a "line fault," that is, a fault occurring in the communication link itself, e.g., a transmission line which is either opened or short-circuited. Further, should any other abnormal condition occur, resulting from a malfunction of the equipment at the remote location, for example, or from an attempt by an intruder to substitute an incorrect bit stream on to the communication link, such a "trouble" condition is also appropriately detected and displayed at the monitor.

As mentioned above, the basic random signal is generated at the monitor station and is transmitted to the remote location for encoding and then retransmitted in encoded form to the monitor. The fundamental encoder/decoder design used in the invention permits an extremely large number of different codes to be used in the system in conjunction with the randomly generated signal. Such codes can be changed in a periodic, or non-periodic, manner known only to the user of the system. With such a large selection of codes available, even were an intruder somehow able successfully to analyze the signals in the system of the invention for one specific code scheme in order to simulate a counterfeit "all-clear" signal, a difficult enough task in itself, the fact that a user can readily change the code program greatly reduces the chances that an intruder can successfully insert the simulated signal without detection. Thus, the ability of an intruder to defeat the system becomes in a practical sense effectively negligible.

The detailed operation and configuration of the system of the invention can be described best with the help of the accompanying drawings, wherein:

FIG. 1 shows a block diagram of the overall system of a preferred embodiment of the invention;

FIG. 2 shows a more detailed block diagram of the system of FIG. 1;

FIG. 3 shows a more detailed block diagram of the random signal generator of FIGS. 1 and 2;

FIG. 3A shows a more detailed circuit and block diagram of the generator of FIG. 3;

FIG. 4 shows a more detailed block diagram of the monitor transmitter and receiver of FIGS. 1 and 2;

FIG. 4A shows a more detailed circuit and block diagram of the transmitter and receiver of FIG. 4;

FIG. 5 shows a more detailed block diagram of the monitor encoder of FIGS. 1 and 2;

FIG. 6 shows a chart illustrating the operation of a circuit configuration of FIG. 6A;

FIG. 6A shows a typical circuit configuration of a portion of the encoder of FIG. 5;

FIG. 7 shows a more detailed diagram of one form of the code control program unit of FIG. 5;

FIG. 8 shows a more detailed block diagram of a portion of the monitor system of FIGS. 1 and 2;

FIG. 9 shows a more detailed block diagram of the alarm and display units of FIGs. 1 and 2;

FIG. 9A depicts certain waveforms to illustrate the operation of the units of FIG. 9;

FIG. 9B shows a more detailed block diagram of the units of FIG. 9;

FIG. 10 shows a more detailed block diagram of the transponder of FIGS. 1 and 2;

FIG. 11 shows a more detailed block and circuit diagram of the transponder receiver of FIG. 10;

FIG. 11A depicts certain waveforms to illustrate the operation of the receiver of FIG. 11;

FIG. 12 shows a block diagram of the timing circuitry of FIG. 10;

FIG. 12A depicts certain waveforms to illustrate the operation of the timing circuitry of FIG. 12;

FIG. 13 shows a more detailed block diagram of a portion of the timing circuitry of FIG. 12;

FIG. 13A depicts certain waveforms to illustrate the operating of the circuitry of FIG. 13;

FIG. 14 shows a more detailed block diagram of the transponder encoder of FIG. 10;

FIG. 15 shows a more detailed block diagram of the transponder transmitter of FIG. 10; and

FIG. 15A shows a more detailed block and circuit diagram of the transmitter of FIG. 15.

FIG. 1 shows a simplified block diagram of the overall system of the invention wherein a centrally located monitor station 10 includes a random signal generator 11 which provides an output signal in digital form, such signal having a truly random nature, i.e., a signal having aperiodic characteristics. The random signal is fed to an appropriate transmitter 12 where it is supplied to a transmission link 13, which in a preferred embodiment may be a two-wire transmission line, for example. The output of random signal generator 11 is also simultaneously fed to an appropriate monitor encoder 14 which operates in accordance with a specifically selected code program 15 to produce a plurality of encoded signals, each one of which represents a different alarm status condition which may exist at a remote location which is being monitored.

The remote location is identified in FIG. 1 as including a transponder station 16 which utilizes an appropriate data receiver 17 for receiving the random signal transmitted by the monitor station from transmission link 13. The received signal is fed to a suitable transponder encoder 18 which functions in accordance with code program 19. Encoder 18 is adapted to be responsive to one or more different alarm input signals received from one or more sensors (not shown), one of which is activated in accordance with the alarm status of the remote location. Accordingly, the encoder 18 produces an encoded signal which represents the particular alarm status of the remote location, the encoded signal being thereupon transmitted back to monitor 10 via data transmitter 21 and transmission link 13.

At monitor 10 the encoded alarm signal transmitted from transponder 16 is received by receiver 22 and is thereupon fed to an input of an alarm comparator/decoder 23 which also has fed to it the encoded signals from monitor encoder 14. The received signal from receiver 22 is then compared in sequence with the plurality of encoded signals from encoder 14 and produces an output signal only when the two signals being compared represent code words which are identical. The output from decoder 23 is connected to a plurality of alarm output and display systems 24 which are used to display the alarm status of the remove location when an output signal indicating a matching of the coded characteristics of the input signals to the comparator/decoder occurs.

The operation of each of the above subsystems shown in the simplified overall block diagram of the invention is discussed in more detail below.

FIG. 2 shows a more detailed block diagram of the overall system shown in FIG. 1. The monitor 10 is typically located at a central alarm receiving facility, such as a central privately operated station, a police station, or the like. In general, the monitor station generates a digital signal of a truly random nature and transmits such signal to the remotely located transponder whose alarm status is to be monitored. The monitor further provides for the encoding of the digital random signal at the monitor to produce a plurality of encoded signals for comparison with the encoded alarm signal received from the transponder. Accordingly, the received alarm signal is compared sequentially to each of the encoded comparison signals generated at the monitor, the alarm status of the remote location being extracted as a result of the comparison. The monitor further provides for an audible and/or visual annunciation or display of the alarm status.

In FIG. 2 the digital random signal from generator 11, which is fed to transmitter 12 for transmittal to the remote transponder location, is simultaneously stored in a data storage unit 25 for subsequent use in encoder 14 in accordance with a timing signal from a timing circuit 26 which operates in response to a suitable clock 27. Timing and data storage units are required at various positions in the system because the processing of the data is performed sequentially and because the transmitted and received signals are carried on the same two-way transmission link at different times using known techniques for time division multiplexing.

The encoder 14 at monitor 10 utilizes a selected code which is determined by code control program unit 15 which is responsive to a plurality of simulated signals each representing a different anticipated alarm condition (including an "All Clear" condition) which may arise at the remote location which is being monitored. Encoder 14 thereby operates upon the random digital signal stored in data storage unit 25 and produces a plurality of encoded signals, each one of which represents a different encoded alarm signal or "All Clear" signal.

The transponder unit 16 receives the digital random signal transmitted from monitor 10 and stores the received signal in data storage unit 28. This received signal also includes appropriate synchronizing information in the form of a suitable timing pulse for actuating timing circuitry 29 in the transponder subsystem 16. Encoder 18 encodes the signal from data storage unit 28, at an appropriate time, in accordance with code control program unit 19 the code program of which is selected to be the same as that used for code control program unit 15 in the monitor 10. As discussed more fully below, an extremely large number of code programs may be selected for use in the system of the invention. In each case, the same code control program is selected and used in both the monitor and transponder units during operation at any one time.

One of a plurality of alarm signals which indicates the alarm status at the remote location where the transponder is positioned is suitably inserted into the signal which is encoded by encoder 18, so as to produce a coded alarm status information signal which again is appropriately stored in a data storage unit 31, the operation of which is suitably timed to produce an encoded alarm information output signal for transmission via transmitter 21 and transmission link 13 back to monitor 10.

The receiver unit 22 at monitor 10 then feeds such signal to data storage unit 32, the operation of which is appropriately timed so as to produce a signal for feeding to comparator/decoder unit 23 which also receives the signals from encoder unit 14. Decoder unit 23 thereupon compares the received encoded alarm information signal from data storage unit 32 with each of the plurality of encoded signals from encoder 14 in a sequential manner to determine which of the latter signals has the same characteristics as the coded alarm information signal from transponder 16.

The comparator/decoder 23 is connected to a plurality of alarm display subsystems 24. As discussed more fully below, decoder unit 23 produces an output when the signals being compared have matching characteristics and such output activates one of the alarm display subsystems at a time depending on the alarm status information contained in the encoded signal from the transponder 16. In addition the decoder 23 is also arranged to produce output signals for indicating an "All Clear" status, a "Line Fault.infin. status, or a "Trouble" status which represents a malfunction in the system which may have resulted from incorrectly operating, or non-operating, units of the system or from tampering with the system by an intruder. The operation of all of the above subsystems and units therein is described more fully with reference to the remaining figures.

Monitor Random Signal Generator

The purpose of random signal generator 11 is to produce a random sequence of digital bits (i.e., "ones" and "zeros") which are non-periodic in nature, so that the sequence has truly random characteristics. The random bits are then grouped in series to form random digital groups or "words" which form the basic message signal for communication between the monitor and the transponder subsystems. Although not limited thereto, the invention is described herein with reference to the use of 4-bit groups in each digital word for transmission from the monitor to the transponder and return.

FIG. 3 shows a functional block diagram of one embodiment of random signal generator 11 which includes a "noisy" oscillator 33 which is an oscillator designed to be relatively unstable so as to produce in effect a signal having a frequency f.sub.1 which is made up of a basic frequency f.sub.o and has superimposed thereon a relatively rapid frequency jitter of "noise," represented by.+-..DELTA.f(t) about the average or basic frequency f.sub.o. The frequency f.sub.o is designed to be substantially higher than the bit rate from the random signal generator 11 and is also statistically independent of the bit rate. The oscillator output (which by appropriate limiting means provides either a digital "one" or a digital "zero" oscillation) is sampled at a bit rate determined by stable clock 34 which produces a gating signal comprising bits with a width ".tau." at a frequency f.sub.2 where f.sub.1 >> f.sub.2 and .tau.<<1/f.sub.1. The gating signal is applied to an appropriate gated storage unit 35 which produces a random bit stream at the output thereof. The output random bit stream has essentially no bit-to-bit correlation and no message-to-message (i.e., bit group to bit group) correlation.

FIG. 3A illustrates a specific implementation of the system shown in FIG. 3. In that figure the oscillator comprises three digital inverters, 40, 41 and 42 interconnected as shown with a resistor 43 connected between inverters 40 and 41 and a resistor 44 connected between the input of the inverter 40 and the output of the inverter 42. A capacitor 45 is connected in parallel with inverter 40 and resistor 43 as shown. The values of resistors 43 and 44 and capacitor 45 determined the time constants of the circuitry and, accordingly, determine the oscillation frequency. The oscillation, however, is highly unstable in frequency so that the output signal effectively has an average frequency on which is superimposed a relatively rapid jitter, or noise, frequency signal, as discussed above. Relatively short strobe pulses at the desired bit rate (i.e., 1/f.sub.2) are supplied from stable clock pulse generator 34 to a well-known JK flip-flop circuit 36, the J and K input terminals of which are connected to the output of the unstable frequency oscillator and the timing strobe pulses being connected to input terminal t. The flip-flop circuit samples and stores the oscillator output and produces an output v.sub.t therefrom an output terminal Q which changes only when the strobe pulse occurs, such output representing the most recently sampled oscillator output state. Accordingly, the output of flip-flop circuit 36 is a sequence, or stream, of bits (i.e., "ones" or "zeros") which are truly randomly sequenced.

Monitor Line Transmitter and Receiver

A block diagram of the monitor transmitter receiver circuitry is shown in FIG. 4, the transmitter 12 (shown by dashed line 50) being in the form of a switchable current source connected amplifier having a power supply 51 producing a voltage V.sub.L as the power source therefor. Transmission of data bits on transmission link 13, which in a preferred embodiment is a two-wire transmission line, is achieved by the presence or absence of current flow I.sub.s in the transmission line. The current flow is controlled by the state of the logic input signal v.sub.t which is received from random signal generator 11, where v.sub.t is either a "zero" (v.sub.t = 0v) or a "one" (v.sub.t = +5v). THe magnitude of the current flow is controlled by a reference voltage v.sub.ref from a suitable reference source 52. The logic input signal v.sub.t and reference voltage signal v.sub.ref are fed to operational amplifier 53, the output of which is fed to a power amplifier 54 with a current feed back loop 55 producing a current dependent feed back voltage across a resistor 56, as shown. A specific circuit configuration for transmitter 12 is shown in FIG. 4A wherein the logic input voltage v.sub.t representing the random data to be transmitted is fed through a diode 57, to one input of amplifier 53 via input resistor 58, the voltage reference v.sub.ref being fed to the other input thereof. The output of amplifier 53 is fed via diode 59 to the base of a transistor 60 across resistor 61. Current feed back is supplied from the transistor 60 to the input of amplifier 53 across resistor 56.

If the logic input voltage v.sub.t is high (+5v), diode 57 conducts and the output of amplifier 53 is negative so that diode 59 is non-conducting and the base of transistor 60 is at ground potential. The transistor is thereby cut off with no collector current thereby inhibiting the flow of transmission line current.

If v.sub.t is low (0v.), diode 57 is off and the output of amplifier 53 rises so that diode 59 conducts and transistor 60 is turned on, thereby allowing the flow of transmission line current I.sub.s. Current I.sub.s flows through resistor 56 to produce a feed back voltage v.sub.fb proportional to I.sub.s, i.e., V.sub.fb =I.sub.s R.sub.56. The feed back control is such that I.sub.s = V.sub.fb /R.sub.56 = v.sub.ref /R.sub.56. A feature of the transmission line signaling system as shown in the FIGS. 4 and 4A is that the signal current will remain approximately constant (I.sub.s = v.sub.ref /R.sub.56) regardless of the transmission line length up to some maximum length. The transmission line, for example, offers a resistance R.sub.L which is proportional to its length. The maximum transmission line resistance R.sub.L, max for a given signal current I.sub.s and power supply source voltage V.sub.L is approximately V.sub.L /I.sub.s. While 59 is not essential to the operation of the circuit shown in FIG. 4A, its use prevents the reverse base-emitter voltage breakdown of transistor 60 from being exceeded and also protects amplifier 53 if the collector-base voltage breakdown of transistor 60 is exceeded as, for example, because of a spike of voltage noise on the transmission line.

THe monitor receiver circuitry 22 is also shown in FIGS. 4 and 4A as enclosed in dashed line 65 and includes a low pass filter circuit 61 having a received voltage signal, v.sub.r, supplied thereto across resistor 62, the output of the filter being supplied to one end of a voltage comparator circuit 63 via resistor 64. The other input of voltage comparator 63 is a voltage reference v'.sub.ref from a suitable reference source 66. THe signal to be detected is the presence of absence of current on the transmission line 13 as received from transponder 16. Resistor 62 is a current sensing resistor having a value R.sub.s in series with the transmission line so that v.sub.r = I.sub.s R.sub.s. When line current is flowing, v.sub. r is greater than v'.sub.ref and the comparator data output is a logic "zero" signal. When no line current is flowing, v'.sub.ref is greater than v.sub.r, the latter being approximately equal to zero, and the comparator data output is a logic "one" signal. In this way, the on-off signal current between the monitor and the transponder is converted to appropriate logic level signals by the monitor line receiver. The low pass filter 61 prevents noise spikes and other high-frequency noise typically encountered on long transmission lines, such as long wire lines, from causing false data to be supplied at the output of comparator 63.

Encoder

As mentioned above, identical encoders are used at the monitor and the transponder subsystems of the overall alarm system of the invention. At the transponder the encoder performs two functions. First, it modifies the received random bit stream sequences to produce a new random bit stream in accordance with a known code control program and, secondly, it inserts alarm status information into the modified or coded random bit sequences. At the monitor, the encoder is used as a "keying" network for decoding the alarm status information contained in the modified return signal received from the transponder. The stored sequence of bits from the most recently transmitted random signal from random signal generator 11 is processed through the encoder 14 at the monitor and compared with the most recently received encoded bit sequence from the transponder, the results of this comparison identifying the alarm status of the transponder.

The encoders used in the monitor and transponder of the alarm system of the invention are capable of generating a relatively large vocabulary of unique code relationships (or words), are relatively simple to implement, and are arranged so that it is relatively easy not only to program them by a selected code program, but also to change the selected program in accordance with an extremely large number of different programs.

The overall coding technique is described, first of all, with reference to FIG. 5 in which data store unit 25 of FIG. 2 is depicted in the form of a 4-bit shift register 65, the input data from random signal generator being fed serially thereto and the output data being supplied in parallel therefrom. Each bit storage element 66 of the 4-bit shift register is arranged to provide two outputs, namely, the storage data bits B.sub.1, B.sub.2, B.sub.3 and B.sub.4 and their complementary bits B.sub.1, B.sub.2, B.sub.3 and B.sub.4. The output bits therefrom are then fed through an appropriate control program unit 15 to four appropriately interconnected exclusive/or gate networks 68 having the same configurations as shown in detail with respect to two of them in the figure. Unit 15 is arranged to provide a selected interconnection of the outputs from storage unit 65 to encoder gating networks 68 and may be changed as desired, as discussed more fully below. Further, in the monitor unit the various alarm signal inputs, Alarm 1, Alarm 2 . . . , Alarm (N-1), are sequentially connected to the code control program unit 15 for selected interconnection with exclusive/or gate networks 68. Unit 15 thereby produces 16 gate interconnections represented by P.sub.1, P.sub.2, P.sub.3 . . . P.sub.16, which are used to interconnect the exclusive/or gate networks 68 so that the input bits B.sub.1, B.sub.2, B.sub.3 and B.sub.4, and their complementary bits, are encoded with the alarm inputs to form the output bits B'.sub.1, B'.sub.2, B'.sub.3 and B'.sub.4.

The operation of the exclusive/or gating networks can be described with reference to FIGS. 6 and 6A wherein FIG. 6 shows an appropriate table of the input-output relationships in conjunction with the typical network configuration of FIG. 6A. In the latter figure, a pair of exclusive/or gates 67A and 67B have three variable inputs, A, B, and D for producing two outputs C and E in accordance with the table of FIg. 6, E representing an output encoded message bit corresponding to an output bit B.sub.n ' of FIG. 5. Thus E = A X B X D, and C = A X B where the symbol X represents the operation of the exclusive/or gates shown. The input data from the shift register 65 is fed to the encoder networks 68 via a selected program of code control program unit 15 which produces the coded output in accordance with the selected interconnections thereof. Program unit 15 can be made in the form of a plug-in unit so that the configuration of the interconnections therein can be appropriately changed merely by substituting a different code plug unit, so long as the code plug used at the monitor has the same interconnection configuration as the code plug used at the transponder.

An example of one interconnection configuration of a code program plug is shown in FIG. 7 wherein terminals A and B of a first exlcusive/or gate network, for example, are supplied with data bit B.sub.1, from a first shift register element, and alarm signal A.sub. 1, respectively, terminal C thereof being left unconnected and terminal D thereof being connected to a terminal G of an adjacent exclusive/or gate network. Terminals E and F of the adjacent network are connected to the outputs B.sub.2 of a second storage register element and B.sub. 4 ' of a fourth storage register. Thus, the output B.sub.1 ' can be expressed as B.sub.1 ' = B.sub.1 X A.sub.1 X B.sub.2 X B.sub.4. The outputs B.sub.2 ', B.sub.3 ' B.sub.4 ' can be similarly expressed.

An extremely large number of code combinations can be generated by the use of a relatively small number of exclusive/or gates. Thus, if a basic 4-bit word unit is used in the system, (i.e., n / 4), a single output bit represented as B.sub.1 ' may be generated in 32 different ways, as shown in Table I shown below.

TABLE I

B.sub.1 ' = 1 0 B.sub.1 B.sub.1 B.sub.2 B.sub.2 B.sub.3 B.sub.3 B.sub.4 B.sub.4 B.sub.1 B.sub.2 B.sub.1 B.sub.2 B.sub.1 B.sub.3 B.sub.1 B.sub.3 B.sub.1 B.sub.4 B.sub.1 B.sub.4 B.sub.2 B.sub.3 B.sub.2 B.sub.3 B.sub.2 B.sub.4 B.sub.2 B.sub.4 B.sub.3 B.sub.4 B.sub.3 B.sub.4 B.sub.1 B.sub.2 B.sub.3 B.sub.1 B.sub.2 B.sub.3 B.sub.2 B.sub.3 B.sub.4 B.sub.2 B.sub.3 B.sub.4 B.sub.1 B.sub.3 B.sub.4 B.sub.1 B.sub.3 B.sub.4 B.sub.1 B.sub.2 B.sub.4 B.sub.1 B.sub.2 B.sub.4 B.sub.1 B.sub.2 B.sub.3 B.sub.4 B.sub.1 B.sub.2 B.sub.3 B.sub.4

Since each of the 4 output bits, B'.sub.1, B'.sub.2, B'.sub.3, and B'.sub.4 can be independently generated 32 different ways from the input bits B.sub.1, B.sub.2, B.sub.3, and B.sub.4, the total number of code combinations is 34.sup.4, or 1,048,320.

If the two conditions where B'.sub.1, B'.sub.2, B'.sub.3 and B'.sub.4 are either all "zeros" or all "ones" are eliminated from that total, then the total number of code combinations is reduced to 810,000. Accordingly, even with such an elimination an extremely large number different arrangements of the code control program unit is possible. The alarm signal inputs are then appropriately inserted via code plug 15 to provide the different alarm status output signals to correspond to those inserted at the transponder.

Unless the monitor and the transponder utilize identical code plug interconnection networks, correct communication between them in accordance with the system of the invention can not occur and an alarm condition indicating "Trouble," i.e., a condition wherein an unidentifiable message is present, will be annunciated at the monitor as an indication that some type of malfunction has occurred somewhere in the system. Thus, it can be seen that an intruder, attempting to reproduce the characteristics of the information which is being communicated between the central and remote stations, without any knowledge of the specific code plugs which are being used therein, will find it extremely difficult to determine the code program characteristics required for such reproduction. Accordingly, an intruder's capability for defeating the system becomes statistically negligible, particularly in comparison to an intruder's ability to defeat presently known systems of comparable cost.

Alarm Decoder

FIG. 8 illustrates the alarm/comparator decoder 23 used to extract the alarm status information which has been encoded onto the random signal at the transponder. The decoder is arranged to be capable of detecting not only specific alarm status information, but also transmission line faults or other malfunctions, including intentional attempts to simulate the system signals by an intruder. Identical encoder and code control program units are used at both the monitor and the transponder, as mentioned above. If it is assumed that a 4-bit digital message is used as the basic word unit, there are 16 possible information signals available (i.e., 2.sup.4) of which 15 can be used to identify different alarm status conditions and one can be used to identify a normal or "All Clear" condition.

The random bits B.sub.1, B.sub.2, B.sub.3, and B.sub.4 which are transmitted during each message frame are stored and encoded at the monitor to form the 4 encoded bits B'.sub.1, B'.sub.2, B'.sub.3 and B'.sub.4 as discussed above with reference to the alarm encoder system. By sequentially simulating each of the 15 possible alarm conditions at the encoder alarm input, the encoder output bits can be made sequentially to represent the 15 different encoded alarm status conditions which it is possible to receive from the transponder. The normal or "All Clear" condition can be generated, for example, when no alarm inputs are stimulated, i.e., all of the simulated alarm inputs are zero.

Each 4-bit simulated alarm status signal produced by encoder 14 is fed to the 4-bit comparator/decoder unit 23 which compares the encoded bits B'.sub.1, B'.sub.2, B'.sub.3 and B'.sub.4 of each such signal in sequence with the corresponding coded bits B*.sub.1, B*.sub.2, B*.sub.3 and B*.sub.4 of the received signal, on a bit-to-bit basis in accordance with well-known bit comparator circuitry. The comparator output represents either the presence or the absence of a correspondence between the transponder encoded alarm signal and the simulated monitor encoded signal with which it is being compared. If the characteristics of the signals compared are the same, an output signal is present from the comparator/decoder unit and is fed to its corresponding alarm and display subsystem via appropriate storage units 70 through the use of alarm select strobe signals from a strobe signal generator 71. The strobe pulses sequentially activate each alarm storage subsystem in accordance with the sequential comparison being performed in comparator/decoder 23. Each of the alarm status or "All Clear" indications are updated each message frame.

Two additional alarm conditions of importance to the overall alarm are also arranged to be detected by the comparator/decoder 23. The first condition which can be signified as a "Trouble" condition may represent, for example, a deliberate attempt on the part of an intruder to insert a simulated encoded signal representing a normal "All Clear" condition so as to defeat the system, or it may indicate that the equipment at the transponder, for example, is malfunctioning in some manner. A second condition which can be signified as a "Line Fault" condition is an indication that the transmission line has been either opened or short-circuited.

An open-circuited or short-circuited transmission line produces either all "ones" or all "zeros", respectively, for the received encoded bits B*.sub.1, B*.sub.2, B*.sub.3 and B*.sub.4 as supplied to the decoder from receiver 22. These conditions are easily detected by the "All Zeros or All Ones" detector 72, which produces an output signal only when its inputs are either all "ones" or all "zeros" for supply to an appropriate logic circuit 73, one output of which is stored in a "Line Fault" storage unit 74. Logic circuit 73, for example, may be in the form of appropriate gating circuitry which is gated off so as to produce no signal at either its "T" or its "LF" output, so long as a signal is supplied by "or" circuit 74 indicating that an alarm status signal has been detected by the comparator/decoder 23 and fed to one of the alarm storage units 70. If the detector 72 indicates an "All Zeros" or an "All Ones" condition and no valid alarm signal has been detected by the comparator/decoder 23 for feeding to one of the alarm storage units 70, a signal is supplied to logic circuit 73 from detector 72 but no signal is supplied by "or" circuit 75. Under such conditions the gating logic circuit 73 is arranged to produce a signal at its "LF" output only, which signal indicates a line fault condition and is stored in line fault storage unit 74 for ultimate display.

If no valid alarm signal is detected by comparator/detector 23 and no "All Zeros" or "All Ones" condition is detected by detector 72, then a "Trouble" situation is indicated. Under such conditions no signals are supplied from "or" circuit 75 or from detector 72 and logic circuit 73 is arranged to provide a signal only at its "T" output, which signal is supplied to a "Trouble" storage unit 76 for ultimate display.

In some cases it is possible that the transponder alarm status will be such that encoding of the input random signal thereto for a particular alarm status will result in a correctly encoded signal comprising all zeros or all ones. Although the monitor encoder will also generate an encoded signal for such alarm status comprising all zeros or all ones, the monitor will be unable to make a certain determination as to whether the consequent matching of signals at the comparator/decoder has resulted from the receipt of a correctly encoded signal or from the presence of a line fault. Because of such uncertainty and in order to avoid the displaying of a false alarm, the information obtained in that particular message frame from such comparison is effectively discarded without the loss of much information to the system. The discarding of such information is effected by the use of a second all zeros or all ones detector 77 which is responsive to the monitor encoded signal from encoder 14. If the input thereto is either all zeros or all ones, the gate 78 is placed in an off condition and the strobe pulses from the generator are prevented from activating the alarm storage units 70.

Alarm Output and Display

A block diagram of one of the plurality of alarm output and display units 24 used at monitor 10 is shown in FIG. 9. The purpose of each alarm output and display unit is to process the stored decoded signal representing each particular alarm status condition at the transponder and to average that information over a preset number of message transmissions thereupon to trigger a latching circuit if the particular alarm status condition is question persists. Operation of the latching circuit causes an audible and/or visual annunciation of the particular alarm status. Once the alarm has been so triggered, it cannot be reset until an appropriate manual reset is activated. As seen in FIG. 9, each alarm output and display unit has an alarm storage unit 70, as mentioned with reference to FIG. 8, which unit stores an alarm signal from the comparator/decoder 23 when the characteristics of the encoded signal from the transponder, representing a specific alarm status condition, matches one of the plurality of encoded signals sequentially supplied to the comparator/detector 23 from the encoder 18 at the monitor. The output of the storage circuit 70 is fed to an averaging circuit, such as integrator circuit 80, the output v.sub.a of which is fed to one input of a voltage comparator circuit 81, the other input of which has a reference threshold voltage v.sub.th applied thereto. The output of voltage comparator 81 is fed to a latching circuit 82, the latter, upon being triggered, applying such voltage to an appropriate audio circuit 83 for producing an audible alarm when triggering of latch 82 has occurred. The same signal can also be applied to an appropriate visual alarm display 84, such as a lamp which lights up when a signal from latching circuit 82 is present.

A useful modification to the visual alarm display is also shown in FIG. 9 wherein an appropriate alternating "blink" or "on-off" voltage signal (i.e., an alternating "one" (0v.) and "zero" (+5v.) signal) is supplied to one input of an "and" gate 85, the other input of which is supplied with the signal from voltage comparator 81 via latch 82. Gate 85 thereby causes an alarm signal to flash the lamp on and off in order to emphasize the visual effect.

Operation of the circuitry in FIG. 9 can be explained with the help of FIG. 9A which illustrates the pertinent timing and signal voltages which appear at critical points in the alarm output and display circuitry. A "message frame" may contain, for example, 11-bit intervals which can be identified as T.sub.0 through T.sub.10. The 5-bit time interval T.sub.5 through T.sub.10 of one message frame is shown in FIG. 9A. During bit times T.sub.5, T.sub.6, T.sub.7 and T.sub.8 data is being received by the monitor from the transponder, and alarm decoding starts at the beginning of bit time T.sub.9. The alarm signal from the decoder 23 is permitted to take any logic value at any time except at the intervals during T.sub.9 and T.sub.10. All the alarm output and display units associated with each particular alarm status condition are connected in parallel at the decoder output. The various alarm signals, if present, are supplied to the correct alarm storage unit by the use of the alarm strobe timing signal which "picks off" the sequentially decoded alarm signals. For instance, with respect to a first alarm output and display unit (Alarm 1) at the time of an Alarm 1 strobe signal the presence of an alarm signal from decoder 23 indicates that the remote location is in an "Alarm 1" status condition.

Such alarm data information as contained in the alarm storage unit 70 is updated once each message frame and the output of alarm storage unit 70 is continuously integrated, or averaged, over a selected number of message frames, with the results of the integration process being continuously compared to the reference threshold voltage v.sub.th at voltage comparator 81. At the instant an alarm condition is stored into the alarm storage unit 70, the alarm storage output falls to a logic "zero" state as shown in FIG. 9A at bit time T.sub.9. The output voltage signal, v.sub.a, from the integrator 80 being fed to comparator 81 gradually begins to fall in response to the logic "zero" at the input of integrator 80. The rate of fall of v.sub.a is a function of the integration time constant and is typically continued over several message frames. If the alarm status condition prevails from message frame to message frame over a selected number of frames, v.sub.a will eventually reach a level equal to the level of the comparator threshold voltage v.sub.th, at which time the comparator output is arranged to change from a logic "one" state, indicating the lack of an "Alarm 1" status, to a logic "zero" state, indicating the presence of an "Alarm 1" status. The alarm is then locked in by the latching circuit 82 and the alarm is annunciated audibly and/or visually, as discussed above.

After the alarm is latched in, removal of the alarm condition will not cause the alarm annunciation to cease until the latch is manually reset. Two independent adjustments are possible to set the length of time an alarm is integrated before annunciation occurs. First, the time constant of the integrator can be adjusted and, second, the level of the comparative threshold voltage v.sub.th can be adjusted. With a longer time constant, a greater number of messages are averaged before the threshold voltage is reached and, conversely, the lower the threshold voltage v.sub.th, the longer the time required for v.sub.a to decrease to v.sub.th.

One specific circuit implementation for the alarm storage unit and for the alarm output and display unit of FIG. 9 is shown in FIG. 9B. As depicted therein, the alarm data from the comparator/decoder 23 is fed to one input of a conventional flip-flop circuit 86 which is used as the storage element. A positive alarm strobe signal, which is illustrated in FIG. 9A, applied thereto will cause storage of any alarm data signal which is present at the input of the flip-flop circuit at the time of the strobe. A simple RC integrator 89, including resistor 87 and capacitor 88, is used for alarm data averaging. The comparator 81 can be of a well-known configuration such as a circuit made and sold as the ".mu.A710" circuit by Fairchild Semiconductor, Inc., Mountain View, Cal. The output of comparator circuit 81 is fed to a dual input "nand" gate latching circuit 90, the output of which is fed to "and" gate 85, the latter supplying a blinking visual indication via a circuit 91 comprising resistor 92, transistor 93 and lamp 94. The operation of latching circuitry 90, "and" gate 85 and the visual indicator circuit 91 are in themselves well known to those in the art.

Transponder

A block diagram of the transponder 16 is shown in FIG. 10 and includes an input data receiver 17, which includes a signal filter 95 and data detector 96 for providing an output signal which is supplied to input data storage unit 28 and to a synchronization detector 97 of timing circuitry 29. The output of synchronization detector 97 is used to actuate an appropriate clock oscillator 98 which in turn actuates a timing chain circuit 99, the purpose of which is to maintain the transponder counting operation in both bit time and frame time synchronization with the counting operation at the monitor and to control the time sequencing of the data processing functions in the transponder.

The input data storage unit 28 receives the data input serially and provides data output in parallel form to encoder 30 which is of the same type as described with reference to encoder 14 of the monitor and which accordingly utilizes an identical code control program unit 19 for encoding the received data signal. Alarm input signals from appropriate sensing elements (not shown) are fed to alarm latching circuit 100, each alarm signal representing a particular alarm status condition being thereby fed to encoder 30 for insertion of information concerning such alarm status onto the signal which is being encoded. The alarm latching circuit is similar to the latching circuit shown in the alarm output and display units of the monitor and must be similarly manually reset once an alarm signal has been provided by the latching operation. The encoded signal is then suitably fed in parallel form to output data storage unit 31 via an encoder gate unit 101. The input data storage unit 28, the encoder gate unit 101 and the output data storage unit 31 being placed into operation at the appropriately desired times by timing signals t.sub.d, t.sub.e, and t.sub.t, respectively, as obtained from timing chain circuit 99. The encoded output data signal containing the alarm status information is thereupon supplied in serial form to line transmitter unit 21 for transmission to monitor 10 via transmission line 13. The operation of the various transponder units shown in FIG. 10 are discussed in greater detail below.

Transponder Receiver

The transponder receiver 17 is shown and its operation discussed with reference to FIGS. 11 and 11A. Receiver 17 includes a receiver line current sensing resistor 102 connected across the transmission line 13 and the input of a noise filter circuit 95. The output of the filter is fed to one input of a detector 96 which comprises a voltage comparator circuit 103 the other input of which is supplied with an appropriate reference voltage v".sub.ref. Line current changes cause a corresponding variation in the voltage v.sub.s across resistor 102, and the noise filter 95 reduces unwanted line noise, cross talk and current spikes, etc., which may appear on the transmission line. The filtered signal, identified as signal v.sub.1, is applied to voltage comparator 103, the latter thereby generating an output signal v.sub.2 having one of two states, depending on the relative values of v.sub.1 and v".sub.ref.

In the first instance, when v.sub.1 is less than v".sub.ref, a logic "one" state is provided at the output of the comparator. When v.sub.1 is greater than v".sub.ref, a logic "zero" state occurs at the output thereof. It has been found that maximum noise immunity occurs if the comparative voltage reference v".sub.ref is adjusted to be approximately one-half of the maximum value of v.sub.1. The band width of the transmission line and the noise filter determine the rise time of v.sub.1 as a function of time and also determine the delay between the input data current signal i.sub.s through the receiver sensing resistor 102 and the output data voltage v.sub.2. Thus, the receiver extracts digital data in the form of current pulses flowing in the transmission line, the interference or noise which may frequently contaminate the input received signal being appropriately filtered so as to avoid the generation of false alarm signals.

Transponder Time Synchronizer

A simplified block diagram of the transponder synchronization or timing circuit 29 is shown in FIG. 12 with typical signal wave forms associate therewith being shown in FIG. 12A. The purpose of the synchronization circuitry is to synchronize the transponder operation in frame time, the local clock oscillator 98 having sufficient accuracy and stability to maintain bit synchronization within each frame. The frame synchronization signal is a "zero" pulse at bit time T.sub.0 which represents the beginning of each message frame. Bit times T.sub.9 and T.sub.10 are effectively at "rest," with neither the monitor nor the transponder transmitting along the transmission line 13. During bit times T.sub.9 and T.sub.10 the transmission line is maintained at a "one" state, that is, current is flowing therein. In addition near the end of bit time T.sub.10 the strobe output 104 from timing decoder 105 drops from a first level to a second level which causes the oscillator 98 to stop its operation and simultaneously enables the monostable multivibrator 106 of synchronous detector 97.

When multivibrator 106 is so enabled it can be appropriately triggered into operation by the presence of an output from Schmitt trigger circuit 108 which circuit is actuated by a change from a "one" to a "zero" at the receiver output which, under appropriately synchronized conditions is the synchronization pulse 107 occurring at time bit T.sub.0 representing the beginning of the next message frame. The presence of synchronization pulse 107 at the input of Schmitt trigger circuit 108 produces an output which actuates multivibrator 106 which in turn produces a sharp pulse 109 at the beginning of bit time T.sub.0 to reset the countdown timing chain of timing generator 99 to zero. The resetting of the countdown circuits causes the strobe output of timing decoder unit 105 to return to its first level and thereby enables the oscillator 98 and simultaneously inhibits the operation of the multivibrator 106. The oscillator remains enabled and the multivibrator remains inhibited until the countdown circuits again reach the state, detected by the timing decoder 105, which represents the last portion of bit time T.sub.10 whereupon the synchronizing operation is repeated for the next message frame.

An important feature of the synchronization circuitry is that the overall circuitry is self-starting and self-correcting so that acquisition of synchronization will occur automatically at system turn-on, or if synchronization is accidentally lost.

For example, if the transponder is turned on at bit time T.sub.2 in FIG. 12A instead of at bit time T.sub.10 then the data "zero" at bit time T.sub.3 would be accepted as representing a synchronization pulse and a transponder message frame would begin at T.sub.3 instead of at T.sub.0. Accordingly, the transponder message frame would be a full four time bits out of synchronization with the monitor message frame which begins at T.sub.0. The transponder timing generator would operate normally and complete its first timing cycle still four bits out of synchronization with the monitor frame. At the completion of the first transponder frame timing cycle, the multivibrator of the transponder synchronous detector is enabled in anticipation of an expected "zero" synchronization pulse at T.sub.0 which in the case in question is actually at T.sub.3 because the transponder is operating four time bits out of synchronization. If the new data at T.sub.3 is also a "zero," the previous cycle is repeated with the transponder frame maintaining its 4-bit synchronization error.

However, T.sub.3 is a data bit position with a 50-percent probability of either being a "zero" or a "one." If T.sub.3 is a "one" the synchronous detector remains enabled until bit time T.sub.4 which is also a data bit position with a 50-percent probability of being either a "zero" or a "one." Whenever a "one" is encountered the transponder frame synchronization steps one bit position. In this way the continuous stepping of the transponder synchronization "walks through" the frame bit-by-bit, until proper frame synchronization is achieved. Bit positions T.sub.5 through T.sub.9 are all "ones," as transmitted at the monitor, so that the resynchronization of the transponder operation requires a walking through of only four frames at the most before synchronization is achieved.

Transponder Timing Generator

FIG. 13 is a simplified diagram of the transponder timing generator 99 and includes a plurality of flip-flop countdown circuits 110 which count down the oscillator frequency in powers of 2, that is, it produces a plurality of oscillator output signals one of which is equal in frequency to the input oscillator frequency, another of which is at one-half the input oscillator frequency, another at one-fourth the oscillator frequency, etc. The different unique states of the countdown circuits are decoded by the timing decoder unit 111 so as to produce the three timing signal outputs t.sub.d, t.sub.3 and t.sub.t as shown in FIG. 13A. The timing output signal t.sub.d is supplied to the receiver data storage unit 28 so that such unit receives and stores input data only during bit times T.sub.1, T.sub.2, T.sub.3 and T.sub.4 which data is encoded for transmission by the operation of encoder 18 the output encoder gate 101 of which is actuated by the encode data timing output signal t.sub.e. The data which has been encoded is transmitted only during bit times T.sub.5, T.sub.6, T.sub.7 and T.sub.8 in accordance with the actuation of the encoder data transmitter unit 21 by timing output signal t.sub.t. Data clocked into the receiver storage unit 28 by t.sub.d pulses at bit times T.sub.5, T.sub.6, T.sub.7, T.sub.8, T.sub.9 and T.sub.10 are shifted out of such data storage unit and discarded without being encoded. The t.sub.t pulses at bit times T.sub.0, T.sub.1, T.sub.2, T.sub.3, T.sub.4, T.sub.9 and T.sub.10 merely shift out a constant "one" which is used to maintain the transponder transmitter in a passive state for uninhibited signal reception at the transponder receiver. Pulse shaping circuits in 111 of any appropriate and well-known configuration can be used to generate very narrow pulses representing the data timing pulse t.sub.d. These pulses precisely define the instants at which data is accepted and minimize the time in which the data gate is open, thus, effectively reducing the time in which the stored data can be contaminated by noise at the receiver input.

Transponder Data Processing

The transponder data processing units are discussed with reference to FIG. 14 wherein 4 data bits are clocked in a serial manner into the input data storage unit represented in the figure by 4-bit storage shift register 112, such clocking being actuated by the receiver data storage timing output signal t.sub.d. At the end of bit time T.sub.4, the 4 received data bits reside in the input data storage register corresponding to bit 1 at T.sub.1, bit 2 at T.sub.2, bit 3 at T.sub.3 and bit 4 at T.sub.4.

The encoder 18 is of the form described previously with reference to monitor encoder 14 and is programmed by an appropriate code control program unit 19 in a manner as also discussed with reference to the monitor encoding operation. For each four bits inserted at the input of encoder 30, a corresponding, but encoded, 4 bits appear at the output thereof. In general, each of the output bits is a function of all the input bits as well as a function of the alarm status condition at the transponder. A unique alarm signal representing such status is supplied to the encoder, the insertion of such alarm input signal under the control of the code control program unit thereby modifying the encoded signal in a manner the same as that discussed above with reference to the monitor encoding operation. At the end of bit time T.sub.4 the output of the encoder is an encoded version of the most recently received data bits B.sub.1, B.sub.2, B.sub.3 and B.sub.4 including information representing the alarm status condition of the transponder. At the beginning of bit time T.sub.5, encoder timing pulse t.sub.e occurs, which pulse activates an encode gate 113 causing a parallel transfer of encoded data into the output data storage unit 31 which is shown in the form of a shift register 114. Subsequent transmit timing pulses t.sub.t shift the stored encoded data out to the line transmitter unit 21. Only the four t.sub.t pulses at T.sub.5, T.sub.6, T.sub.7 and T.sub.8 shift out the encoded data, all other t.sub.t pulses at T.sub.9, T.sub.10, T.sub.0, T.sub.1, T.sub.2, T.sub.3 and T.sub.4 shift out a "one" which serves only to maintain the transmission line in the conduction state which allows line current flow and transmission of data signals from the monitor.

Transponder Line Transmitter

FIGS. 15 and 15A illustrate the transponder line transmitter, the former figure providing a simplified block diagram thereof and the latter figure illustrating a particular circuit embodiment thereof. The purpose of the transponder line transmitter is to transmit data from the transponder to the monitor at a high signal-to-noise ratio with minimum power drain at the transponder. The remotely located transponder must operate at low power even though in some applications it may have to signal over great distances of relatively lossy transmission links, such as telephone lines, for example. The power required to transmit at high signal-to-noise levels over miles of telephone lines can be several watts. However, the power required to interrupt a signal current on the line is minimal. Therefore, during that portion of the data message frame when the transponder is transmitting, i.e., at bit times T.sub.5, T.sub.6, T.sub.7 and T.sub.8, the monitor is arranged to maintain a constant line current and signals are transmitted to the monitor from the transponder merely by opening or closing a transponder line switch 115 according to the data which is to be transmitted. The current sensor of the monitor detects the presence or absence of current flow and converts this information into digital signals corresponding to the transponder data output, as discussed with reference to the operation of the receiver 22 of monitor 10 shown in FIGS. 4 and 4A. The only signalling power required at the transponder to transmit the data is the power required to operate the switch. The relatively high power necessary to drive the line current is produced at the monitor end of the transmission line and not at the transponder end so that minimal power is required at the latter location.

The operation of the transponder transmitter circuit in FIG. 15A is such that the digital data to be transmitted is either at +5v. (i.e., a "one") or 0v. (i.e., a "zero"). If a zero is to be transmitted, transistors 116 and 117 are cut off so that no collector current flows in transistor 117, such condition corresponding to an open line thereby preventing any line current from flowing thereon. If a "one" is to be transmitted transistor 116 conducts and transistor 117 is turned on to full saturation, with negligible voltage drop from the collector to the emitter, which condition corresponds to a closed circuit transmission line, allowing line signal current to flow.

In this manner, transponder data is transmitted by controlling the line current with negligible signalling power required at the transponder. At all bit times other than the transponder transmission periods during bit times T.sub.5, T.sub.6, T.sub.7 and T.sub.8, transistor 117 is maintained in the "on" condition to allow data transmission to the transponder receiver.

Claims

What is claimed is:

1. An alarm system for monitoring at a first station the alarm status of at least one second station, said system comprising

a monitor located at said first station, said monitor including

means for generating a random signal;

means for producing one or more simulated signals corresponding to one or more alarm status conditions at said second station;

monitor encoding means responsive to said random signal and to said one or more simulated signals for producing one or more encoded monitor signals, said latter signals being encoded with a selected code program;

monitor transmitter means for feeding said random signal to a transmission link means for transmission to said second station;

a transponder located at said second station, said transponder including

means for receiving said transmitted random signal;

transponder encoder means responsive to said received random signal and adapted to be responsive to a signal representing the alarm status of said second station for modifying said received random signal to produce an encoded transponder signal, said latter signal being encoded in accordance with said selected code program;

transponder transmitter means for feeding said encoded transponder signal to said transmission link means for transmission of said signal to said first station;

said monitor further including

means for receiving said transmitted encoded transponder signal;

means for comparing said encoded transponder signal with each of said encoded monitor signals to produce an alarm output signal when the characteristics of said encoded transponder signal are the same as the characteristics of at least one of said encoded monitor signals; and

display means responsive to said alarm output signal for annunciating the alarm status of said second station.

2. An alarm system in accordance with claim 1 further including timing means for timing the operation of said random signal generating means, said monitor encoding means, said transponder encoding means, said comparing means, and said display means whereby said monitor encoding means produces said one or more encoded monitor signals and said transponder encoding means produces said encoded transponder signal in response to the same random signal generated from said random signal generating means for comparison at said comparing means.

3. An alarm system in accordance with claim 2 wherein said monitor encoding means includes

first data storage means responsive to said random signal for feeding said random signal data to an encoder in parallel form;

second data storage means responsive to said encoded transponder signal for feeding said encoded transponder signal data to said comparing means in parallel form; and

said timing means includes means for timing the operation of said first and said second data storage means.

4. An alarm system in accordance with claim 2 wherein said transponder encoding means includes

first data storage means responsive to said transmitted random signal for feeding said random signal data to an encoder in parallel form;

second data storage means responsive to said encoded transponder signal for feeding said encoded transponder signal to said transponder transmitter means in series form; and

said transponder timing means controlling the operation of said first and said second transponder data storage means.

5. An alarm system in accordance with claim 1 wherein said display means includes means for audibly displaying said alarm status.

6. An alarm system in accordance with claim 1 wherein said display means includes means for visually displaying said alarm status.

7. An alarm system in accordance with claim 1 wherein said random signal generating means includes

an unstable oscillator for producing a plurality of pulses at a randomly varying frequency;

gated storage means for receiving said plurality of pulses; and

clock means for producing a series of gating pulses at a fixed frequency for actuating said gated storage means to produce an output stream of random bits.

8. An alarm system in accordance with claim 7 wherein said randomly varying frequency is f.sub.1 and is of the form f.sub.0 .+-. f(t), said fixed frequency is f.sub.2, and the width of said gating pulses is .tau., the frequency f.sub.1 being much greater than the frequency f.sub.2 and said pulse width .tau. is much less than 1/f.sub.1.

9. An alarm system in accordance with claim 1 wherein said monitor transmitter means includes

means for providing a reference voltage;

voltage comparator means responsive to said reference voltage and to the random signal from said random signal generator;

means responsive to the output of said voltage comparator means and connected at its output to said transmission link for producing a controlled current pulse on said transmission link when the value of said random signal exceeds that of said reference voltage and for producing a zero current on said transmission link when said random signal value is less than that of said reference voltage; and

power supply means for supplying power for transmitting said controlled current pulse on said transmission link.

10. An alarm system in accordance with claim 9 wherein

said transmission link is a transmission line; and

said current pulse is produced independently of the length of said transmission line.

11. An alarm system in accordance with claim 1 wherein said monitor receiving means includes

means responsive to received current pulses on said transmission link for producing a voltage pulse;

filter means responsive to said voltage pulse for producing a filtered voltage pulse;

means for providing a reference voltage;

voltage comparator means responsive to said filtered voltage pulse and to said reference voltage for producing an output pulse representing the received signal data on said transmission link.

12. An alarm system in accordance with claim 3 wherein said first data storage means is a shift register for storing said random signal input data in serial form and for providing said signal data at its output in parallel form;

a plurality of logic networks responsive to parallel signal data for producing encoded parallel signal data;

a code control program network interconnecting the inputs of said logic networks with said output signal data from said shift register and with simulated alarm status information signals in accordance with a selected interconnection program.

13. An alarm system in accordance with claim 12 wherein said logic networks include a plurality of exclusive/or gates.

14. An alarm system in accordance with claim 13 wherein each such logic network includes

a first exclusive/or gate having two inputs connected to said code control program network and an output connected to said code control program network;

a second exclusive/or gate having one input connected to the output of said first exclusive/or gate and a second input connected to said code control program network, the output of said second exclusive/or gate thereby providing an encoded data bit.

15. An alarm system in accordance with claim 1 wherein said display means includes

a plurality of display units, each being responsive to a different one of said alarm output signals and including

a plurality of storage means adapted to store said alarm output signals;

means for feeding said alarm output signals sequentially to each of said plurality of storage means.

16. An alarm system in accordance with claim 15 wherein said sequential feeding means includes

means for generating strobe pulses;

gating means for feeding said strobe pulse to said plurality of storage means for sequential operation of said storage means; and

means for actuating said gating means.

17. An alarm system in accordance with claim 16 wherein said gating actuating means includes

detector means responsive to said encoded monitor signal for producing an output signal if all the data bits in said encoded monitor signal are in either a zero or a one state, said output signal preventing the actuation of said gating means when present and permitting the actuation of said gating means when absent.

18. An alarm system in accordance with claim 15 and further including

alarm gate means connected to the outputs of said storage means for producing a gating output signal if any of said storage means has an alarm output signal stored therein and for producing a zero signal if none of said alarm storage means has an alarm output signal stored therein;

detector means responsive to said encoded transponder signal for producing an output signal if all of the data bits in said encoded transponder signal are in either a zero or a one state;

logic circuit means responsive to said further gate means and to said detector means for producing a first output signal when an output signal is present from said detector means and no output signal is present from said further gate means for producing a second output signal when no output signal is present from said detector means and no output signal is present from said or gate means;

first means for displaying the presence of said first output signal; and

second display means for displaying the presence of said second output signal.

19. An alarm system in accordance with claim 15 wherein each of said plurality of display units further includes

averaging means for producing an averaged voltage in response to a stored alarm output signal;

threshold reference means for producing a threshold reference voltage;

voltage comparator means responsive to said averaged voltage and to said threshold reference voltage for producing an output voltage when said averaged voltage is greater than said threshold voltage; and

latching circuit means responsive to the output voltage from said voltage comparator means for actuating a display device for displaying the presence of an alarm output signal.

20. An alarm system in accordance with claim 19 wherein said display device includes

a visual display unit;

a source for producing an on-off voltage;

an and gate responsive to the output of said latching circuit and to said on-off voltage for producing a display output signal when a voltage is present from said latching circuit and said on-off voltage is in the on state, said visual display unit being responsive to said display output signal from said "and" gate to produce a blinking visual effect.

21. An alarm system in accordance with claim 4 wherein said transponder receiving means includes

a signal filter means responsive to said received random signal to provide a filtered received signal;

detector means for detecting the presence and absence of a current pulse in said filtered signal and for feeding said detected pulses to said timing means and to said first transponder data storage means.

22. An alarm system in accordance with claim 21 wherein said timing means includes

a timing chain generator for producing a plurality of timing pulses for operating said first and said second transponder data storage means and said transponder encoder;

means for producing clock pulses for the actuation of said timing chain generator;

synchronous detector means responsive to said detected pulses and to a timing pulse from said timing chain generator for producing a reset signal to reset said timing chain generator to its initial condition at the end of each message frame of said received signal;

said timing chain generator producing a strobe output pulse at a selected time in said message frame for stopping the operation of said clock pulse producing means.

23. An alarm system in accordance with claim 22 wherein said synchronous detector includes

a monostable multivibrator means for producing said reset pulse in response to said strobe pulse from said timing chain generator; and

trigger circuit means responsive to said received detected pulses for triggering the operation of said monostable multivibrator.

24. An alarm system in accordance with claim 21 wherein said transponder receiving means further includes

means connected to said transmission link means for sensing the current in said transmission link means, said current sensing means being connected to the input of said filter means; and

said detector means includes

reference voltage source means; and

voltage comparator means having a first input connected to said reference voltage source means and a second input connected to the output of said filter means, said voltage comparator means producing said detected pulses, said pulses including said random signal transmitted from said monitor transmitter means and a synchronous pulse for actuating the timing means of said transponder.

25. An alarm system in accordance with claim 1 wherein said transponder transmitter means includes switching means responsive to said encoded transponder signal for interrupting a continuous current signal on said transmission link means in response to the encoded data of said transponder encoded signal.