U.S. patent number 3,701,971 [Application Number 05/079,563] was granted by the patent office on 1972-10-31 for terminal message monitor.
This patent grant is currently assigned to Burroughs Corporation, Detroit, MI (U.S. corp.). Invention is credited to Charles B. Hebeler, Gary L. Sanner.
United States Patent |
3,701,971 |
|
October 31, 1972 |
TERMINAL MESSAGE MONITOR
Abstract
A monitoring system to permit a first terminal computer on line
with a central processor to monitor message traffic from the
central processor to other terminals concatenated or in a multidrop
mode with the first. When messages are sent through a modem to a
plurality of terminal computers in a concatenated configuration a
verification of message traffic is provided. Logic circuitry is
provided for monitoring both transmitted and received information
and providing a printout of the communication line information. The
monitoring terminal, regardless of the address of the message, will
store the communication line information in its memory and print
out the stored information to provide a positive communication
system check.
Inventors: |
Gary L. Sanner (Detroit,
MI), Charles B. Hebeler (Farmington, MI) |
Assignee: |
Burroughs Corporation, Detroit, MI
(U.S. corp.) (N/A)
|
Family
ID: |
22151330 |
Appl.
No.: |
05/079,563 |
Filed: |
October 9, 1970 |
Current U.S.
Class: |
709/224; 710/15;
714/47.1 |
Current CPC
Class: |
G06F
13/22 (20130101); G06F 13/38 (20130101) |
Current International
Class: |
G06F
13/20 (20060101); G06F 13/38 (20060101); G06F
13/22 (20060101); G06f 003/00 (); G06f
009/18 () |
Field of
Search: |
;340/172.5 |
References Cited
[Referenced By]
U.S. Patent Documents
|
|
|
3336582 |
August 1967 |
Beausoleil et al. |
3454936 |
July 1969 |
Bridge et al. |
3456242 |
July 1969 |
Lubkin et al. |
3469243 |
September 1969 |
Willcox et al. |
3539998 |
November 1970 |
Belcher et al. |
3564509 |
February 1971 |
Perkins et al. |
|
Primary Examiner: Paul J. Henon
Assistant Examiner: Sydney R. Chirlin
Attorney, Agent or Firm: Kenneth L. Miller Charles S.
Hall
Claims
1. In a system wherein a central data source communicates messages
with a plurality of concatenated remote terminals, each of said
terminals normally comparing a received message address from said
central source with its terminal address to exclude messages to
other terminals, a method for temporarily utilizing one of said
terminals having memory means and display means for monitoring
terminals more remote from the central data source, comprising the
steps of: clearing a portion of said monitoring remote terminal
memory means for temporarily storing said messages received from
said central data source, suppressing said address comparison in
said monitoring terminal to allow all received messages, regardless
of their address, to enter said monitoring terminal, temporarily
storing said received messages in said cleared portion of said
terminal memory means, and displaying said temporarily stored
messages in response to an inquiry
2. The monitoring method according to claim 1 additionally
including the step of: gating messages transmitted by said more
remote terminals to said
3. The monitoring method according to claim 2 additionally
including the step of: selectively isolating the monitoring of
messages received from said central
4. The monitoring method according to claim 2 additionally
including the step of: registering the concurrent monitoring of
messages received from said control data source and messages
transmitted from said more remote
5. In a system wherein a central data source communicates with a
plurality of concatenated remote terminals, each of said terminals
having means for normally comparing the address of a message
received from said central source with its terminal address to
exclude messages to other terminals, apparatus for temporarily
converting one of said terminals having memory means and display
means to a monitor as to terminals more remote from said central
data source comprising: means for suppressing said comparison means
and for routing all messages received from said central data
source, regardless of address, to said memory of said monitoring
terminal, means for gating messages transmitted from said more
remote terminals to said monitoring terminal memory, and means for
selectively isolating said suppressing and routing means and
said
6. In a system wherein a central source communicates data through a
selected remote terminal, having memory means and display means,
and being serially connected to at least one other more remote
terminal, each terminal normally comparing the address of a
received message from said central source with its terminal address
to exclude messages to other terminals, a method for temporarily
utilizing said selected remote terminal for monitoring
communications between said central source and said more remote
terminal comprising the steps of: clearing a portion of said memory
means of said selected remote terminal for temporarily storing said
received message; suppressing said address comparison in said
selected remote terminal to allow all received messages, regardless
of their address, to enter said selected remote terminal; storing
said received message temporarily in said cleared portion of said
memory means; and displaying said temporarily stored message in
response to an inquiry command.
Description
This invention relates generally to a data processing system
wherein a series of terminal computers is on-line, through a modem,
with a central processor and more particularly to a method and
apparatus for monitoring message traffic between the central
processor and the terminals by utilizing an intermediate terminal
in a monitor mode.
In interfacing terminal computers with a central processor it is
essential to determine if each unit is receiving the correct
information in order to eliminate transmission inaccuracies as a
source of error. This is especially troublesome when new systems
are set up and when various types of terminals are added to an
existing system. In data processing systems information is usually
in the form of time-spaced electrical pulses arranged in a
pre-determined code representing numerals and characters. It is
always possible that, due to transient voltages, line malfunctions,
a failure of the equipment, or other means this data will be
transferred in error. Thus it is desirable to have checking or
monitoring apparatus available to trace malfunctions.
A typical on-line commercial computer application requires
continued access to a centrally located data file. Teleprinters on
line, at various locations, were previously used to display
information received and to provide a source of input, including
answers to inquires from a central processor. This process helped
to identify any transmission of errors to the central processor.
Central processors could work independently of these teletypewriter
terminals but the flow of received and transmitted information was
significantly impeded by the much slower printing operation. Since
the teletype printers had no memory they significantly hampered
time-sharing efforts.
An example of a system of this type would be a bank operation where
it is necessary to obtain or update certain account balances kept
in a file of bank accounts. Similarly insurance companies find it
is necessary to periodically update information in various files
such as the amount of insurance, the premium data and the extent of
insurance coverage for each insured person. High speed electronic
data processing systems are commonly used for storing files of
information for banks, insurance companies and the like. Further in
such businesses, it is often desirable to have a centrally located
data processing system including high speed electronic central
processor and peripheral equipment and to employ remote terminal
devices for entering and receiving information at any of a number
of remote points. Such remote terminals may be located, for
example, at branch offices of the banks or insurance companies.
When installing these systems and adding new terminals to existing
systems accurate checking and monitoring apparatus is necessary for
field engineering people to solve complex interface requirements. A
number of prior art techniques have proved to be expensive and
excessively time consuming when applied to the new sophisticated
terminals. A known method of verifying message traffic was to
insert test messages into the line and read these messages at a
distant point to determine accuracy of transmission. This system
required external connections and interrupted data flow
considerably. Also, the tests conducted were not under actual
conditions, since chosen test messages were inserted.
Another approach was to provide a permanent monitoring and checking
apparatus as a part of an installation. This was effective in
tracing errors and signalling an operator, but required expensive
permanent equipment and, obviously, increased the cost of the user.
More recently field "monitoring kits" have been provide wherein
known specifications are used as a standard, with lights or
counters indicating variations from the norm. These devices are
portable, but must be connected between the modem and a terminal
and left "on" for a period of time so that intermittent errors can
be recorded. The most recent development is a channel monitor which
is externally connected anterior to a terminal unit. This monitor
synchronizes, controls, and decodes monitored information for
printing, in code, format characters. Again, this is an external
system costing several thousands of dollars and requiring complex
interconnections.
It has been found that transmission errors occur mainly during
start-up operations and when interfacing foreign systems. Also,
terminal units have been most economically set up in series, or
concatenated, configuration utilizing a single modem.
It is, therefore, the primary object of this invention to provide
for an improved monitoring system for verifying message
traffic.
It is another object of this invention to utilize a concatenated
terminal computer as a monitor for sampling both transmitted and
received information.
It is another object to provide a printout of message traffic
without affecting terminal or central processor operation.
It is still another object of this invention to selectively use a
terminal computer as a monitor by simple and inexpensive means, so
that once an error is found and corrected the monitor can quickly
be converted back to a terminal unit.
BRIEF STATEMENT OF THE INVENTION
To accomplish the above objects, logic means is selectively
employed to utilize the memory and computational ability of a
terminal computer in a monitor mode. Gating circuitry is also
provided to place both transmitted and and received information on
the same line when in the monitoring mode. A terminal computer in
the concatenated mode is utilized as a monitor by non-destructively
storing communication line information from or to any other
terminal, by use of logic circuitry and the memory of the terminal,
and then printing out this information for visual review by a field
engineer for aberrations in the flow of signals. External
connections or systems are not required and an inexpensive
modification is used to utilize the existing internal micro-logic
of the terminal computer.
DESCRIPTION OF THE DRAWINGS
In the drawings:
FIG. 1 is a block diagram of a data processing system of the type
in which the invention may be utilized;
FIG. 2 is a symbolic block diagram of a remote terminal computer
utilizable in accordance with the principles of the invention;
FIG. 3 is a simplified functional block diagram of the remote
computer terminal of FIG. 2;
FIG. 4 is a flow diagram illustrating the steps performed in order
to monitor data on a terminal computer; and
FIG. 5 shows logic circuitry for handling received and transmitted
information through a monitoring terminal computer.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring to FIG. 1, there is illustrated a data processing system
capable of utilizing the present invention. A system of this type
may be found in a banking industry wherein a central processing
unit (CPU) 11 is located at a central or main bank headquarters.
Operatively connected to the CPU 11 is an on-site modem 13. This
modem is connected via a communications channel and customarily
over a telephone communications system to a central office bridge
15. The central office bridge 15 functions to connect the CPU modem
13 to one of a plurality of receiver modems 17 and 19 located at
receiver sites. A receiver site may be for example, an individual
branch bank. The receiver modems 17 and 19 are connected to the
central office bridge 15 by a four or two wire communication
channel. Operatively and electrically connected to the receiver
site modems 17 and 19, is a plurality of terminal computers (TC).
The first terminal in the line, 21 or 27, is followed by a
plurality of succeeding terminals 23, 25 and 29, respectively,
which are electrically connected in concatenation. In an actual
operation there may be a large number of receiver site modems, each
with many terminal computers.
In the banking industry, for example, each terminal computer may
represent a teller's window at a branch bank. Thus, from the modem
17, for example, the branch bank associcated therewith has three
terminal computers on the modem line, i.e., 21, 23, and 25.
Similarly, a branch bank having the modem 19 has terminal computers
in line therewith, but as is illustrated, this comprises only two
terminal computers, i.e., 27 and 29. As may be seen, a number of
terminal computers may be connected in concatenation with a modem
at a branch office. In operation, any instruction or request from
the CPU 11 will contain an address representing one of the terminal
computers at a particular branch bank. Actually, a two character
address is provided which indicates which terminal computer in the
system is being addressed. When a particular terminal computer at a
teller window is addressed, it then has the responsibility to reply
to the CPU.
Referring now to FIG. 2, there is shown a simplified block diagram
of a remote terminal in which the principles of the present
invention may be incorporated. A typical remote terminal such as 21
may be described as comprising three major sections: a main
processor 33, utilizing a main memory 35 and an input/output
keyboard 37; a line discipline processor 41, with its message
memory 43 and terminal address control logic 45; and a terminal
buffer storage 47. The output of the buffer storage 47 is coupled
by modem 17 to the input of a communication line 22. The discussion
of the preferred embodiment will deal only with those terminals in
line with the modem 17. However, it is apparent that the
explanation is applicable to the modem 19, as well, or to any group
of terminal computers in concatenation with an on-line modem. The
structure and operational interrelationship of the sections of the
terminal 21 is discussed in detail hereinafter in conjunction with
FIGS. 3, 4 and 5 with similar reference numerals being used to
designate the respective sections of the terminal 21.
Now referring to FIGS. 1 and 2 in conjunction with Table I below,
the format and function of the various portions of inquiry and
response messages transmitted between the central processor and the
remote terminals may be
understood.----------------------------------------------
-----------------------------TABLE 1 A. POLL, TRANSMISSION,
ACKNOWLEDGEMENT AND SIGNOFF CENTRAL DATA POLL PROCESSOR ACK. e a a
p e a o d d o n c t 1 2 l q message k line discipline s a a x s e b
e processor o d d m t t e x t t c o h 1 2# x x c t b. poll with no
message central data poll signoff processor e a a p e o d d o n t 1
2 l q line discipline e processor o t c. selection, acceptance,
message receipt and acknowledgement central data select message
processor e a a s e s ae bx s o d d e n ack o dt cm t t e x t ack t
1 2 l q h 1x c x a a line discipline c c processor k k d. selection
with no acceptance central data select processor e a a s e o d d e
n neg. t 1 2 l q ack. line discipline n processor a k legend
function message format 1 2 3 . . . . .
_________________________________________________________________________
_ .
entries A through D of Table I illustrate typical examples of
messages exchanged between the remote terminal such as 21 or 23 and
the central processor 11. A remote terminal is capable of operating
in either an off-line or an on-line mode. In the off-line mode,
processing tasks are accomplished by the main processor 33 in
accordance with program and object data stored in its memory 35. In
the on-line mode, the main processor 33 preferably operating in a
poll or select mode, relies upon communications with the central
processor 11 over the communication line for at least a portion of
its operation.
A poll inquiry message is defined as a message by which the central
data processor 11 interrogates one of a plurality of the addressed
remote terminals and inquires whether the addressed remote terminal
has a message ready for transmission to the central processor. A
select inquiry message is defined as a message by which the central
data processor interrogates one of a plurality of the addressed
remote terminals in the communication net informing the addressed
remote terminal that the central processor has a message ready for
transmission to the addressed remote terminal.
In either the poll or select inquiry mode, if an addressed remote
terminal is not ready to receive a message, i.e., it is either
being operated off-line or it is otherwise not ready to receive or
transmit a message in response to the received inquiry message
addressed to it, the line discipline processor 41 automatically
responds with an appropriate "not ready" message to the central
processor 11. As shown in entries B and D of Table I, the line
discipline processor 41 responds to a poll with an EOT (End of
Transmission) and to a select with a NAK to indicate that it is not
ready to transmit or receive a message, respectively. Upon
receiving a negative acknowledgement from the addressed remote
processor, the central processor either retransmits its message,
which may have been garbled in the transmission channel, or it may
continue on its poll or select sequence to the next remote terminal
in the normal addressing sequence.
Referring to entries A through D of Table I, the function or
explanation of the message is written above the signal indicating
waveform-type line and the message format is indicated below the
line. The message format includes, reading left to right,
characters 1, 2, 3 . . . N. The respective characters indicated are
those of the United States of America Standard Code for Information
Interchange (USASCII).
Entry A of Table I illustrates a message exchange for a typical
poll operation. The first character in the message transmitted by
the central data processor 11 comprises an end of transmission
character EOT. All transmissions may begin with this EOT character
or another suitable character. Following the EOT character are two
address characters AD1 and AD2. In a typical multi-terminal line
environment each remote terminal, be it 21, 23, or 25, would have
assigned to it a plurality of addresses indicating characters which
are, for example, stored in an expected message portion of the
memory of the line discipline processor 41. Following the address
characters are the POL (poll) and ENQ (inquiry) characters. Entries
C and D of Table I show a similar message from the central data
processor 11 as assembled and transmitted for the selection-type
inquiry message with the SEL (select) character replacing the POL
character of the poll message format illustrated in entries A and
B.
Referring again to FIGS. 1 and 2 it may be seen that each terminal
21, 23 or 25 through its line discipline processor 41 responds only
to the messages specifically addressed to that terminal even though
the communication network is in a multi-drop mode. In the
multi-drop mode each terminal 21, 23, or 25 receives all messages
transmitted by the central processor. Each terminal is in effect a
slave to the central processor which establishes the poll and
select routing and the frequency with which each respective
terminal 21, 23, or 25 in the net will receive a poll or select
message addressed to it.
The terminal address control logic 45, which may comprise a shift
register or other memory store and logic gating for storing an
address generated either by the arithmetic unit of the main
processor 33 or of line discipline processor 41, expands the
capabilities of the remote terminal by permitting either the
terminal operator or the central processor to determine in advance
the address of the terminal. This in turn determines which
subsequently received messages the remote terminal will respond to
by determining when the present, i.e., altered, address of the
remote terminal corresponds with the message address characters of
the inquiry message transmitted from the central processor. As
hereinafter is more fully explained in conjunction with FIGS. 3, 4,
and 5, by selectively changing a remote terminal, such as terminal
21, into a message monitor, any comparison with an expected message
store is bypassed so that all data coming through the modem 17 will
appear to be addressed to the terminal 21 but also be acted on by
the addressed terminal.
Referring now to FIG. 3, there is illustrated a logic block diagram
of the remote computer terminal 21 capable of modification to a
monitor. As hereinabove described the remote terminal 21 comprises
three major sections: a main processor 33, a line discipline
processor 41 and a terminal buffer storage 47.
The main processor 33 preferably comprises a stored program machine
in which object data is manipulated in an arithmetic unit 51 in
accordance with a sequence of micro-logic instructions stored in
and withdrawn from the main memory 35 in a predetermined sequence.
The input channel 36 and the keyboard 37 are arranged to
selectively enter programs and object data into the processor 33
via an input buffer register 39. The main memory 35 may comprise,
for example, a rotatable magnetic disk having a plurality of
read/write heads for accessing an unrestricted general memory
section and a plurality of read only heads for accessing a
restricted stored program portion of the memory. The information
and object data stored in the main memory is processed in the
arithmetic unit 51 which may include, for example, a full adder and
appropriate input gating selection networks, not shown. A memory
address register (MAR) 53 is operatively associated with the memory
select matrix 35 via gates 55 and 57 to access an appropriate
portion of the memory data in response to an address loaded in the
MAR by an instruction decoder 59.
In operation of the main processor in accomplishing its tasks as
designated by a given program being run, the memory address
register 53 periodically addresses and interrogates the main memory
35 and withdraws therefrom an appropriate program instruction
indicated by the address located by the instruction decoder 59 into
the memory address register 53. The micro-logic instructions
withdrawn from the read only portion of memory 35 are sequentially
loaded into the instruction decoder 59. The output of the
instruction decoder 59 enables appropriate control logic for
controlling various gating functions in the main processor in
accordance with the contents of the instruction decoder 59. The
instruction decoder, in response to withdrawn program instructions,
controls a state machine 61 via a gate 63. The state machine 61,
which may comprise a counter, generates a sequence of timed machine
state levels or timing pulses for controlling the various logic
functions of the main processor including, for example, the
operation of an adder or the exchange of information between the
memory, the main processor, the instruction decoder or a printer
65. As shown, either the arithmetic unit 51 or the memory 35 of the
terminal processor in conjunction with the instruction decoder 59
may directly actuate the printer 65 via gates 67 and 69,
respectively, thus providing a hard copy of the results of the
arithmetic units computation.
As in a normal stored program machine, after each instruction is
decoded by the instruction decoder 59 and executed by the memory 35
and state machine 61, the processor, for example through its adder
logic, generates an advance signal to increment, for example, a
counter associated with the instruction decoder thereby advancing
the instruction counter to the next count in its orderly count
sequence. In response to the new contents of the instruction
counter, the next in a series of micro-logic instructions would be
withdrawn from the main memory 35 and serially fed to the
instruction decoder 59. In this manner, the respective sequential
syllables of a memory word of a program instruction would be
transferred to the instruction decoder to properly energize the
control matrix for withdrawing the appropriate program steps and/or
data from the memory. Thereafter the instruction decoder in
response to the decoded program instruction would appropriately
energize the state machine 61 to generate appropriate logic timing
signals to enable the main processor to accomplish the task
indicated by each decoded program instruction. As the various steps
of the serial program are sequentially executed an appropriate
output is generated on the printer 65.
In addition to being able to operate off-line, the remote terminal
21 is capable of operating on-line and communicating with the
central processor 11 as shown in FIG. 1. This communication with
the central processor is controlled by the line-discipline
processor 41. The line discipline processor 41 is preferably a
stored program machine and may be similar in structure and
operation to the main processor 33. The function of the line
discipline processor is to establish line discipline in accordance
with stored micro-logic for controlling the assembly, editing,
formatting and parity generation-check of messages to be transitted
to, and as received from, the central processor 11 for the main
processor 33.
The line discipline processor 41 (FIG. 3) is preferably similar in
structure and operation to the main processor 33. An auxiliary or
message memory 43 is arranged to store messages to be sent to, and
received from the central data processor 11 and to store a series
of micro-logic instructions for controlling the operation of a data
comm processor 75 of the line discipline processor 41. The message
memory 43 may, for example, comprise a rotatable memory having a
read-write portion for storing messages and a read-only memory for
storing micro-logic instructions. A head selection matrix, not
shown, which is responsive to the contents of a memory address
register 77 is used to control the accessing of the message memory
43 for withdrawing micro-logic instructions and messages stored
therein. The memory address register 77 of the line discipline
processor 41 controls the access to, and reading of the micro-logic
instructions from the message memory 43 to a decode register 79.
The micro-logic instructions withdrawn from the message memory 43
are decoded in the decode register 79 with the output of the decode
register 79 controlling a state machine 81 in accordance with the
contents of the decoded program step. In this manner the decode
register 79 controls the generation of appropriate logic gating
signals for controlling the operation of the data comm processor
75, which may comprise a full adder and appropriate gating for
manipulating data in accordance with decoded micro-logic
instructions.
As is known in the art, the state machine 81 generates appropriate
timing signals to control the operation of logic gates for example
85, 87 and 89 which control the exchange of information between the
decode register 79 and the data comm processor 75. The operation of
the state machine 81, which may comprise a counter, may be further
controlled by appropriate control signals designated T.sub.x and
R.sub.x which designate a function of the transmit or receive state
of the line discipline processor 41 and buffer 47.
When the main processor 33 has a message to be transmitted to the
central processor, the message to be transmitted is originally
assembled by the main processor 33 in a specific area of the memory
35. After monitoring and determining the condition of transmit and
receive flag registers 91 and 93 respectively, the main processor
selects an appropriate time and transfers the message from memory
35 of the main processor 33 to the message memory 43 of the line
discipline processor 41 for example via the arithmetic unit 51 and
the decoder 59. Thereafter the main processor is free to return to
its off-line task, and the line discipline processor 41 awaits the
receipt of a poll from the central processor to initiate the
transmission of the message stored in the message memory 43. The
sequence and format of inquiry and response messages transmitted
between the line discipline processor 41 and the central data
processor 11 have been discussed hereinabove in detail in
conjunction with Table I and FIGS. 1, 2 and 3.
When the line discipline processor 41 receives an inquiry message
from the central processor 11, the appropriate R.sub.x signal,
i.e., a signal for example, signifying communication line carrier
detect, actuates a gate 95 thereby initiating the operation of the
state machine 81 in the receive mode. The received inquiry message
is transferred bit serially from the modem 17 to the buffer storage
47 as it is received serially from the line. The information stored
in the buffer 47 is then compared in a comparator 101 with an
expected message format previously stored, for example, in a
message store 103, which may comprise any memory, for example, an
array of flip flops arranged to store encoded information in the
form of the expected message format as hereinabove described in
conjunction with Table I.
As shown, a pair of logic gates 105 and 107 in conjunction with
suitable timing signals, for example t.sub.o through t.sub.5, may
be employed to transfer or couple the contents of the respective
stages of the buffer storage 47 and the expected message store 103
to the comparator 101. In this manner the respective binary bits of
the appropriate portions of the received message and the expected
message store may be compared bit by bit to check and determine the
equivalence therebetween. Also, the respective bits of the received
message comprising the parity bit and the address bits may be
compared to determine whether parity of the received message checks
and whether the message as received is addressed to the receiving
terminal.
In the event the parity and address portions of the received
message compare with that information or data stored in the
expected message store, the output of the comparator 101 would be
logically true and a gate 109 would appropriately signal the data
comm processor 75 of the line discipline processor 41. In response
to this indication of comparison, the data comm processor 75 of the
line discipline processor appropriately sets the memory address
register 77 to withdraw from the message memory 43 an appropriate
positive acknowledgement if it was determined that the line
discipline processor 41 is properly conditioned to respond to the
inquiry message, i.e., either a poll or select inquiry. Thereafter
the message to be transmitted to the central processor 11 may be
read from the message memory 43 via the logic gate 89 with an
appropriate timing signal to the buffer store 47 for transmission
to the central processor 11 via the communication line 22.
In connection with the above description, it is to be understood
that only the remote terminal to which a particular inquiry message
is addressed such as 21 responds by sending a positive or negative
acknowledgement to the central processor via the communication
line. In this manner the central processor 11 is able to establish
and maintain a sequence of inquiry messages thereby providing
orderly data transmission.
In accordance with the principles of this invention, the terminal
21 for example, is to be modified to become a monitor for message
traffic from the central processor 11 to the terminals 23 or 25 as
well as from the terminals 23 or 25 to the central processor.
Referring to FIG. 3 and the previous description, the terminal 21,
once it determines that a message is not addressed to it will not
perform an operation on this message nor send a positive or
negative acknowledgement signal in the normal operation of the
system. Consistent with the objects of this invention, the terminal
21 is to be transformed into a monitor such that all messages
regardless of their address will be monitored, but still not acted
on. The terminal being used as a monitor will not function in a
terminal computer mode. As has been previously discussed, all
terminals on line with the same modem whether serially in a single
group or in a plurality of parallel groups, i.e., in the multi-drop
mode receive all messages from the central processor 11 but will
act only on those messages having their address. In the following
discussion, the terminal 21 is modified as a monitor, and the
terminal 23 which is downstream from the terminal 21, will operate
in the normal manner as a transmitter and receiver of messages.
Referring to the flow diagram of FIG. 4, all memory buffers of the
terminal 21 will be cleared starting with the main memory buffer
(not shown) and proceeding to the buffer storage 47. A portion of
the message memory 43 is used for micro-logic instructions utilized
in normal machine operation and for example, a message memory of at
least 256 words may normally have only 64 words available for line
traffic storage. However, in a monitor situation, 192 words are
provided for use by the terminal computer for line traffic storage.
This operation is referred to as redesignation, in the flow
diagram.
In the monitor mode, the gate 109, in FIG. 3, will signal the data
comm processor 75 that a message has been received and the
comparison with the expected message store is positive. This is
accomplished, even though the message is not addressed to the
monitor terminal 21, by suppressing the comparison in comparator 10
thereby providing a logically true reading at the input to gate
109. A monitor mode gate 160 is provided between the gate 105 and
the comparator logic 101 to couple messages from the buffer storage
47 directly through gate 109 to the message memory 43 when the
monitor mode is in operation thus providing an appropriate signal
at the other input of the gate 160. This step is indicated as
suppress comparison on the flow chart of FIG. 4.
Contrary to normal machine operation, a response withdrawn from the
message memory 43 by memory address register 77 giving an
appropriate positive acknowledgement to a received message is
undesirable, since the terminal 21 is now performing a monitoring
function. Any response to message inquiries is suppressed by means
of a monitor mode input switch 163 which is normally supplying a
ground to one input of the gate 89. During the monitoring mode,
this switch is opened thereby inhibiting any output to the central
processor 11 through the gate 89.
All line traffic data including noise signals, for the terminals
served by modem 17 will now be received by the buffer storage 47 of
the monitor and transferred to the message memory 43. When the
message memory is full, or at any other time the monitoring
operator may desire after at least one character of data appears on
the communication line, an interrupt signal can be initiated. This
may be accompolished by depressing an interrupt key on the keyboard
37. Storage of data will cease and the contents of the message
memory will be transferred into the main memory 35 and then printed
in the sequence that each character appeared on the communication
line.
Transmitted information from the terminal 23, in our example,
presents special monitoring problems which are solved with the
present invention. Transmitted information in the context of this
application refers to data transmitted from a downstream terminal,
one other than the monitoring terminal, to the central processor.
Referring now to FIG. 5, there is shown logic circuitry for
handling received and transmitted information through the
monitoring terminal computer. Circuit modifications are necessary
to monitor transmission when terminal 21 is in the monitoring mode.
Transmitted information from "downstream terminals" is, normally,
not sampled for address checks by the terminal 21. The logic
circuitry disclosed performs a routing function by transferring the
transmitted data in (TRDATAI) from "downstream terminals" to the
received data line (RCDATA), as well as providing a variety of
alternate modes. More specifically, a signal transmitted from a
downstream terminal will enter a NAND gate 130, provided for signal
isolation, and then to an amplifier 131 to restore its signal
level. This message from the terminal 23, in our example, will then
proceed to be transmitted (TRDATAO) through the modem 17 and to the
central processor.
Data transmitted from a downstream terminal will also be routed
through a pair of NAND gates 132 and 133 to enter the terminal 21
received data line (RCDATA). The NAND gates, throughout the system,
perform an isolating function to prevent signal interference as
well as providing for proper signal inversion. The transmitted data
also enters a NAND gate 134 the output of which is one input into a
three-input NAND gate 135. Receive data input (RCDATAI) from the
modem 17 is fed through a NAND gate 138, again for isolation, and a
second NAND gate 139 to the RCDATA line. The RCDATAI is also fed
through a NAND gate 136 and through an amplifier 137 to the next
downstream terminal.
Request to send input signal (REQSNDI) which indicates that a
downstream terminal is requesting to send information, travels
directly to the modem, to turn on the communication line carrier.
This REQSNDI signal is used in monitor 21 to inhibit the received
data in line (RCDATAI) when a downstream terminal is requesting to
send a message. This REQSNDI signal is then fed through a pair of
NAND gates 141 and 142 which are connected in series. From node C4,
which is located between the output of NAND gate 138 and the input
of NAND gate 139, the signal is then fed into the input of NAND
gate 139 permitting the RCDATA line to be controlled by the gate
133.
As can be seen, both transmit and received data are fed to terminal
computer 21 on its RCDATA line, thereby allowing the monitoring of
both transmit and receive messages but inhibiting RCDATAI when the
REQSNDI line is active. By the use of several switching points
various data lines may be isolated and sampled to solve particular
machine problems. For example, a switching point I4 is located
between the output of NAND gate 141 and the input to NAND gate 142,
and a switching point M4 is located between the output of NAND gate
132 and the input of NAND gate 133. Ground is provided at node
C.sub.4 and each of the described points and denominated,
respectively, C3, I3, and M3. To monitor both the received and
transmit lines simultaneously, point I4 may be connected to ground
I3 to provide grounding of the REQSNDI signal in the monitor
terminal. To monitor the RCDATAI line and inhibit the TRDATAI line
when the request to send is active, switching point M4 may be
connected to ground M3 thereby grounding their respective signals.
To monitor TRDATAI only, node C4 may be connected to ground C3
thereby inhibiting RCDATAI. To monitor RCDATAI only, connect
switching point M4 to ground M3 and switching I4 to ground I3
thereby inhibiting TRDATAI and REQSNDI signal in the monitor
terminal. By the proper interconnection, other data lines and
combinations may be tested.
A signal from moden 17 appearing on data carrier detector line
(DCARDETI) indicates that the modem is operating correctly and is
"on". Line DCARDETI is also one of the inputs to the NAND gate 135
with RCDATAI providing the third input at the NAND gate 135. The
first input of gate 135, as previously described, was that of
transmitted data in line TRDATAI. When all three signal appear at
the input of the gate 135 indicating that data is appearing on both
the RCDATAI line and the TRDATAI line at the same time, a flip-flop
143 will be set registering an error condition. When the error
condition has been noted and/or corrected, the flip-flop 143 can be
reset by momentarily grounding an input E4 of flip-flop 143 to
ground E3.
As is apparent from the above-discussion, complete versatility for
testing data flow is provided to the field engineer by relatively
simple gating and logic functions. Terminal interfacing and error
detection are thus enhanced at a minimum of cost and external
equipment.
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