U.S. patent number 3,700,977 [Application Number 05/116,144] was granted by the patent office on 1972-10-24 for diffused resistor.
This patent grant is currently assigned to Motorola, Inc.. Invention is credited to Gerald K. Lunn.
United States Patent |
3,700,977 |
Lunn |
October 24, 1972 |
DIFFUSED RESISTOR
Abstract
There is disclosed an improved technique for reducing or
eliminating parasitic capacitance associated with diffused
resistors in which the normal buried layer is eliminated and in
which each resistor is either fully or partially surrounded by an
isolation ring. The epitaxial layer between the resistive element
and the isolation ring is provided with a back bias either at one
end of the resistor or at the point along the resistor at which no
signal exists. In one case this may be accomplished by shorting the
epitaxial layer to the low impedance end of the resistor. In the
embodiment in which one end of the resistor is shorted to the
epitaxial layer, the resistor is polarized having a low impedance
end and a high impedance end, such that the end to which the
epitaxial layer is shorted is the end which is coupled to the low
impedance node of a circuit. In the case where the resistor is to
be coupled across nodes having equal impedance, the epitaxial layer
is provided with back bias adjacent that point along the length of
the resistor at which no signal appears. There is also disclosed a
guard circuit, which minimizes parasitic capacitance in cases where
a low resistivity epitaxial layer or a buried layer is provided.
The guard circuit is in the form of an impedance convertor having a
high impedance output applied to the high impedance end of the
resistor while the low impedance of the convertor is coupled to an
epitaxial layer contact adjacent this high impedance end. In the
guard circuit embodiment, an additional epitaxial layer contact is
provided adjacent the low impedance end of the resistor and is
shorted thereto so as to provide the aforementioned back bias.
Inventors: |
Lunn; Gerald K. (Scottsdale,
AZ) |
Assignee: |
Motorola, Inc. (Franklin Park,
IL)
|
Family
ID: |
22365518 |
Appl.
No.: |
05/116,144 |
Filed: |
February 17, 1971 |
Current U.S.
Class: |
257/533;
148/DIG.136; 257/545; 257/541; 257/E27.047 |
Current CPC
Class: |
H01L
27/0802 (20130101); Y10S 148/136 (20130101) |
Current International
Class: |
H01L
27/08 (20060101); H01l 019/00 () |
Field of
Search: |
;317/235,234 ;307/72,75
;321/69R |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Huckert; John W.
Assistant Examiner: Wojciechowicz; E.
Claims
What is claimed is:
1. Apparatus for reducing the effects of parasitic capacitance
associated with a resistor diffused into a semiconductive material
having a lower resistivity per unit length than that of said
resistor comprising in combination with said resistor:
means for generating a back-biasing potential at a point on said
low resistivity material adjacent said resistor, said point being
furthest removed from any portion of said resistor adapted to be
coupled to a high impedance node of a circuit;
means including semiconductive material of a conductivity type
opposite to that of said low resistivity material, diffused into
said low resistivity material in spaced adjacency to said resistor
for isolating said resistor from any capacitance coupled path to
ground outside of the area occupied by and surrounded by said
isolating means; and
means for deriving from the high impedance node of said circuit a
high impedance signal and a low impedance replica of said high
impedance signal, said high impedance signal being coupled directly
to that portion of said resistor adapted to be coupled to said high
impedance node, said low impedance replica being coupled to that
portion of said low resistivity material adjacent the portion of
said resistor adapted to be coupled to said high impedance node,
whereby parasitic capacitance associated with the low resistivity
of said first mentioned material is compensated for by said means
for deriving said high and low impedance signals.
2. Apparatus for reducing the effects of parasitic capacitance
associated with a resistor diffused into a semiconductive material
having a lower resistivity per unit length than that of said
resistor comprising in combination with said resistor;
means for generating a back-biasing potential at a point on said
low resistivity material adjacent said resistor, said point being
furthest removed from any portion of said resistor adapted to be
coupled to a high impedance node of a circuit; and
means including semiconductive material of a conductivity type
opposite to that of said low resistivity material, diffused into
said low resistivity material in spaced adjacency to said resistor
for isolating said resistor from any capacitance coupled path to
ground outside of the area occupied by said isolating means;
the high impedance node of said circuit developing a high impedance
signal, said circuit having a node at which is developed a low
impedance replica of said high impedance signal, the portion of
said resistor adapted to be coupled to the high impedance node of
said circuit adapted to be coupled to said high impedance signal,
the portion of said low resistivity material adjacent the portion
of said resistor adapted to be coupled to said high impedance node,
adapted to be coupled to said low impedance replica.
3. The apparatus as recited in claim 2 wherein said isolating means
completely surrounds said resistor, wherein said resistor has two
ends, wherein a contact to said low resistivity material is
provided in spaced adjacency to either end of said resistor between
the ends of the resistor and said isolating means, wherein said
high impedance signal is applied to one end of said resistor,
wherein said low impedance replica is applied to the contact
adjacent this one end, and wherein said back-biasing potential is
applied to the contact adjacent the other end of said resistor,
said other end being coupled to a low impedance node of said
circuit.
Description
BACKGROUND OF THE INVENTION
This invention relates to an improved diffused resistance element
and more specifically to a technique for reducing parasitic
capacitance associated with diffused resistors.
One of the problems with monolithic diffused resistors is the
problem of distributed junction capacitance which limits the use of
these resistors in high frequency circuits. In the past, islands of
resistors, isolated by a diffused isolation ring have been provided
with a buried layer primarily to eliminate stacking faults in
growing the epitaxial layer into which the resistors are diffused.
A second reason for using a buried layer is to provide a uniform
voltage plane under the resistors within the island so as to
isolate the resistors within the island from transistors positioned
outside the island on the same monolithic chip. Although this
technique has been successful in low frequency circuits, it has
been a major contributing factor to parasitic capacitance when this
configuration is used in high frequency circuits. The reason for
the high parasitic capacitance in high frequency circuits utilizing
the aforementioned technique, is the fact that the buried layer
provides a low resistance underneath the resistor, thus allowing
the distributed junction capacitance to collect or "lump" at one
point. Since the parasitic capacitance between the resistive
element and the buried layer is effectively collected or lumped at
one point, it is more effectively coupled to ground by the buried
layer. The parasitic capacitance in this prior art configuration is
thus much more of a problem than if the buried layer were not
used.
A second problem with prior art diffused resistors is the need for
back biasing to prevent a diode from being formed somewhere along
the resistor between it and the epitaxial layer into which it is
diffused. Any contact to the epitaxial layer to provide back bias
is surrounded with a region of low impedance to ground. It is this
low impedance which makes significant any parasitic capacitance
between the resistor and the epitaxial layer. Thus the placement of
this back bias contact can be critical in the reduction of
parasitic capacitance.
It has been found that the effects of parasitic capacitance can be
substantially reduced by getting rid of the buried layer or by
compensating for the buried layer by guard circuitry and by
providing that the back bias contact be adjacent that end of the
resistor which is to be connected to a low impedance node in the
circuit. By placing the back biasing contact at the low impedance
end of the resistor the effects of its low impedance region are
minimized in the vicinity of the high impedance end of the
resistor. This is significant because the effects of parasitic
impedance are felt most strongly at high impedance nodes of a given
circuit. The simplest way of providing the necessary back bias is
to short the epitaxial layer adjacent the low impedance end of the
resistor to this low impedance end. In most cases voltage delivered
to the low impedance end of the resistor will provide sufficient
back bias.
The subject invention, which includes two embodiments, thus solves
the parasitic capacitance problem by either removing the buried
layer and providing a shorting contact; or by compensating for the
buried layer by providing a guard circuit at one end of the
resistor and a shorting contact at the other end. In either case
the contact on the epitaxial layer adjacent one end of the diffused
resistor is provided with the aforementioned back bias. Whenever
the low impedance node of the circuit to which the resistor is to
be attached has a voltage sufficient to back bias the resistor
epitaxial layer junction, the contact at one end of the diffused
resistor is shorted to the portion of the epitaxial layer
immediately adjacent thereto. In any case, each resistive element
is either encircled or almost completely surrounded by an isolation
ring so as to greatly reduce the parasitic capacitance. The effect
of back biasing the epitaxial layer adjacent one end of the
resistor is to minimize the capacitive effect of back biasing the
epitaxial layer. Because of the placement of the back biasing
contact the resistive element is polarized, in the sense that there
is an end to be connected to the high impedance node in the
particular circuit, while the other end is to be connected to the
low impedance node of the circuit. In any given circuit it will be
immediately obvious that of the two nodes across which the resistor
is to be connected, one node will be a high impedance node and the
other node will be a low impedance node. In the situation when the
nodes are of equal impedance, that point along the resistor at
which no signal occurs, is the point adjacent which the epitaxial
layer is to be provided with back bias.
In a first embodiment, no buried layer and a high resistivity
epitaxial layer is used to minimize the aforementioned "lumping"
effect. When high and low impedance nodes exist in the circuit, by
connecting the low impedance node of the circuit to the low
impedance end of the resistor, and by connecting the high impedance
node of the circuit to the high impedance end of the resistor,
parasitic capacitance can be virtually eliminated if the resistance
of the epitaxial layer is higher per unit length than of the
resistor.
The second embodiment of the invention relates to the use of a low
resistivity epitaxial layer and guard circuitry which counteracts
such "lumping" that the high impedance end of the resistor is
driven directly with the signal, while the epitaxial layer adjacent
this high impedance end is driven with a low impedance replica of
the signal. For this purpose a separate contact to the epitaxial
layer is provided adjacent the high impedance end of the resistor.
By driving one end of the resistor with a high impedance signal and
driving the epitaxial layer with a low impedance replica of the
signal, a linear voltage distribution equivalent to the voltage
distribution along the resistor is formed along the epitaxial
layer-substrate junction directly underneath the resistor. This
provides that there be no voltage difference between corresponding
points along the resistor and the epitaxial layer. If there is no
voltage difference, there is no current flowing from the resistor
to the epitaxial layer-substrate junction. If there is no current
flowing, there is no loading effect and thus, any potential
parasitic capacitance between the resistor and this junction has no
effect, since there is no current flowing through the parasitic
capacitance.
The other end of the resistor in this configuration, i.e., the low
impedance end, has the low impedance end shorted to the epitaxial
region adjacent thereto, as in the first configuration so as to
back bias the resistor. This reduces any stray capacitance not
cancelled by the guard circuit. Thus, the guard circuitry minimizes
parasitic capacitance between the resistor and the epitaxial
layer-substrate junction, while the provision of the back bias to
the low impedance end further minimizes the effect of any stray
parasitic capacitance. In the second configuration, the epitaxial
layer resistivity is made sufficiently low either by use of small
buried layers within the isolation ring or by doping so that the
distributed capacitance from the epitaxial layer to the substrate
does not significantly affect the voltage distribution along the
epitaxial layer. In this manner, the resistor driven by the
aforementioned impedance convertor is completely "guarded" and the
capacitance from the resistor to the epitaxial layer has no effect.
Even if there is some departure from a linear voltage distribution
along the epitaxial layer, there is still a considerable reduction
in effective parasitic capacitance utilizing this second technique
because of the technique of providing back bias at the epitaxial
layer adjacent the low impedance end of the resistor.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide an improved
monolithic diffused resistor in which parasitic capacitance is
reduced.
It is a further object of this invention to provide an improved
monolithic diffused resistor having reduced parasitic capacitance
by providing that each diffused resistor be surrounded by an
isolation ring and that the epitaxial layer into which the
resistive element is diffused between the isolation ring and the
resistor, be provided with a back bias adjacent one end of the
resistor.
It is a further object of this invention to provide an improved
monolithic diffused resistor having reduced parasitic capacitance
by partially enclosing the resistive element with an isolation
barrier leaving one end of the resistor unsurrounded such that any
back biasing is effectively applied adjacent this unsurrounded
end.
It is another object of this invention to provide an improved
monolithic diffused resistor and guard circuitry therefore in order
to reduce the parasitic capacitance associated with a diffused
resistor.
It is yet another object of this invention to provide the
combination of an impedance converter and an improved monolithic
diffused resistor provided with epitaxial layer contacts adjacent
each end of the resistor.
Other objects of this invention will be better understood upon
reading the following description of the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a drawing of the prior art technique which provides a
plurality of diffused resistors within an island. The island is
isolated from the active components located outside the island on a
monolithic chip by an isolation ring.
FIG. 2 is a schematic diagram showing parasitic capacitance between
a resistive element within the island shown in FIG. 1 and the
buried layer and lumped capacitance between the buried layer and
the grounded header for the chip.
FIG. 3 is a diagram showing one embodiment of the improved diffused
resistor in which the buried layer is removed and in which the
resistor is surrounded by an isolation ring, the epitaxial layer
adjacent one end of the resistive element being provided with a
back bias potential.
FIG. 4 is a typical amplifying circuit showing the low impedance
and high impedance nodes across which the resistive element shown
in FIG. 3 is shown connected.
FIG. 5 is a schematic diagram showing the parasitic capacitance
developed between the resistive element of FIG. 3 and the epitaxial
layer and the distributed capacitance between the epitaxial layer
and ground.
FIGS. 6 and 7 are top views of two different embodiments of the
improved resistor showing both the case where the resistive element
is completely surrounded by an isolation ring and where the
resistive element is only partially surrounded.
FIG. 8 shows an alternate embodiment of the invention which
includes the combination of an impedance convertor and a completely
surrounded resistive element having contacts to the epitaxial layer
adjacent either end of the resistive element.
FIG. 9 is a schematic diagram of the guard circuit connected to the
resistor shown in FIG. 8 in which parasitic capacitance between the
resistive element and the epitaxial layer and between the epitaxial
layer and AC ground is minimized.
BRIEF DESCRIPTION OF THE INVENTION
There is disclosed an improved technique for eliminating parasitic
capacitance associated with diffused resistors wherein the normal
buried layer is eliminated and in which each resistor is either
fully or partially surrounded by an isolation ring. The epitaxial
layer between the resistive element and the isolation ring is
provided with back bias either at one end of the resistor or at the
point on the resistor at which no signal exists. In the case where
the epitaxial layer at one end of the resistor is provided with a
back bias. The resistor is said to be polarized so as to have a low
impedance end and a high impedance end. The end at which the
epitaxial layer is provided with back bias becomes the low
impedance end. In the case where the resistor is to be coupled
across nodes having equal impedance, the epitaxial layer is
provided with a back bias at that point along the length of the
resistor at which no signal appears. There is disclosed an
additional guard circuit which further minimizes the parasitic
capacitance. The guard circuit functions as an impedance convertor
such that the high impedance signal from the convertor is applied
to the resistor at its high impedance end while the low impedance
output of the convertor is coupled to the epitaxial layer contact
adjacent this high impedance end. An additional epitaxial layer
contact is provided adjacent the low impedance end for the
provision of back bias adjacent thereto.
DETAILED DESCRIPTION OF THE INVENTION
As mentioned hereinbefore, conventional diffused resistors suffer
from distributed capacitance to the substrate which limits the
frequency response of integrated circuit (IC) amplifiers utilizing
these resistors.
As shown in FIG. 1, conventional layout techniques put all
resistors 11, 12 and 13 in a common epitaxial layer island 14 with
a buried layer 15 underneath. The epitaxial island is surrounded by
an isolation ring 16 so as to shield the resistive elements within
the epitaxial island from the effects of active devices on other
parts of the chip 10. In FIG. 1, a P-type material 13 is shown
diffused into an N-type epitaxial layer 14 which is deposited on an
N+ type buried layer 15. In this configuration the buried layer 15
is diffused into a P-type substrate 17. Unfortunately, this
configuration maximizes the parasitic capacitance problem because
the low resistance buried layer 15 effectively connects the whole
epitaxial island 14 to AC ground.
One coupling path is through an AC decoupling circuit 18 and is
shown by a dotted line 19 going through the epitaxial island 14 to
a contact 20. The necessary V+ back bias voltage is applied to the
contact 20 so as to reverse bias the junction between the resistive
elements and the epitaxial layer to prevent transistor action.
Normally this back biasing is provided with an AC decoupling
circuit 18 and it is this circuit which provides one low impedance
path between the buried layer 15 and ground.
Since this capacitance coupled path to ground can occur when there
is strong AC decoupling to ground provided by the AC decoupling
circuit 18, the effect of this low impedance path is minimized in
the present invention by the aforementioned placement of the
epitaxial layer electrode adjacent one end of the resistor.
The other low impedance path, between the buried layer 15 and the
AC ground, is provided through the substrate 17. In normal
operation this substrate lies on a grounded heat sink or header 22
such that the buried layer has a direct capacitance coupled link to
the AC ground through the substrate. This capacitance coupled path
is shown by dotted line 21 and is caused by the aforementioned
lumped capacitance, due to the low resistivity of the buried layer
15. This low resistivity buried layer effectively couples all of
the distributed capacitance, shown along resistor 13 of FIG. 2, to
ground as follows. The low resistivity of the buried layer
effectively eliminates any resistance between the lower ends of the
distributed capacitors shown at 26. Thus, each of the little
parasitic capacitors 26 are effectively shorted together at their
lower ends by the buried layer. The buried layer provides a uniform
voltage plane which functions as the top plate of the capacitor 27.
In this case the top plate of the capacitor 27 is the bottom of the
buried layer 15 and the bottom plate is the header 22. Thus, the
buried layer 15 can be considered the top plate of a large
capacitor which directly and strongly couples the distributed
capacitance along the length of the resistive element 13 to ground.
This latter low impedance path is removed by the removal of the
aforementioned buried layer.
In summary, if there is either a strong AC decoupling or a low
resistivity buried layer, the resistive element 13 will be directly
capacitance coupled to the AC ground 25 as shown in FIG. 2. As can
be seen from FIGS. 1 and 2, the buried layer, while potentially
eliminating stacking faults in growing the epitaxial layer and
while providing a uniform potential under all of the resistors in
the epitaxial island, generates a far greater problem than it
solves, when the resistors are to be used in high frequency
circuits. In effect, the buried layer and the arbitrary placement
of the epitaxial layer contact maximizes the effect of parasitic
capacitance distributed along the resistive element.
This problem is solved by the subject invention by providing the
aforementioned back bias at a predetermined place adjacent the
resistor and by providing either a separate isolation region with
no buried layer in which the epitaxial layer is of a high
resistivity or alternately, or by retaining a portion of the buried
layer so as to make the epitaxial layer of a low resistivity and by
providing a guard circuit.
The first of these techniques is shown by the structure of FIG. 3.
In this technique, a particular resistor to have low parasitic
capacitance is isolated within the island by an isolation ring 30.
The particular resistor is shown in FIG. 3 at 31 to be diffused
into an epitaxial layer 32 which is in turn deposited on a
substrate of an opposite conductivity type 33. In one embodiment
the resistor 31 is P-type material diffused into an N-type
epitaxial island which is in turn deposited on a P-type substrate.
The isolation ring 30, in this embodiment, is P- type material and
in the configuration shown in FIG. 3, completely surrounds the
resistive element 31. At one end of the resistive element 31, in
spaced adjacency thereto, is provided a contact 34 to the epitaxial
region interior to the isolation ring 30. This is accomplished by
diffusing an N+ region 35 into the epitaxial layer 32 such that the
contact 34 can be made adjacent this one end of the resistive
element 31. This end is given a reference numeral 40 and
corresponds to the aforementioned low impedance end of the
resistor. The contact 34 is shown in spaced adjacency to the end 40
of the resistive element 31 so that the N+ region 35 can be
diffused into the epitaxial layer 32 without contacting the
P-region 36. The low impedance end 40 may be shorted to the contact
34 either by external circuitry, as shown by arrows 37, or by
providing a shorting bar 55 directly across the contacts, 34 and
38, as shown in FIG. 6. The other end of the resistive element 31
is referred to herein as the high impedance end 41 having a contact
42 thereon.
If there is insufficient voltage at the low impedance end of the
resistor to back bias the whole resistor-epitaxial layer junction,
then this bias may be provided separately at this low impedance end
by applying the necessary voltage at the contact 34. In this case
the contact 34 is not shorted to the contact at the low impedance
end of the resistor.
As shown in FIG. 4, in any given circuit, there is usually a low
impedance node and a high impedance node across which the resistor
is to be connected. This is shown by the simple amplifying circuit
of FIG. 4 composed of an NPN transistor 44 having a signal
delivered to its base, with its emitter grounded and its collector
connected through a diffused resistor to the collector supply
voltage V.sub.cc. It will be appreciated that in this circuit a low
impedance node is the collector supply voltage V.sub.cc, while the
high impedance node is the collector of the transistor 44. In most
circuits it will be apparent when a resistor is to be connected
between two nodes which node is the high impedance node and which
node is the low impedance node. If the two nodes have equal
impedance, then that portion on the resistor at which no signal
appears, is provided with a back bias at the epitaxial layer
immediately adjacent thereto. In most cases this will be the center
of the resistive element. Taking the usual case, however, the
equivalent circuit for the resistor shown in FIG. 3 is shown in
FIG. 5. Here the low impedance end is the end 40 and the high
impedance end is the end 41. As specified in FIG. 3, the epitaxial
layer adjacent the end 40 is shorted to the end 40 by placing a
conductive strip between contacts 24 and 38. This connection is
shown by line 45. As can be seen from the schematic diagram in FIG.
5, because of the high resistivity of the epitaxial layer, there is
no capacitance "lumping" because each of the distributed
capacitances shown at 26' are separated from one another by a
portion of the high resistivity epitaxial layer 32. Thus, each
capacitance 26' is only weakly coupled to ground 25 by the
distributed capacitances 27' along the epitaxial layer 32. There
is, however, a direct short, as shown at line 45, which serves to
reduce the effect of the parasitic capacitance between the
resistive element 31 and epitaxial layer 32.
The function of shoring the low impedance end of the resistor to
the epitaxial layer adjacent thereto is as follows: First, all
diffused resistors require a back biasing potential to prevent the
formation of a diode somewhere between the resistor and the
epitaxial layer. Secondly, any contact to apply this back biasing
potential will have associated with it a low impedance region.
Thirdly, the capacitance from the resistor to the epitaxial layer
is only significant if there is a low impedance path from the
epitaxial layer to ground. The problem then becomes where to put
the necessary epitaxial layer contact to minimize the effect of its
low impedance region. It will be appreciated that when the subject
resistor is connected in a circuit, one end of the resistor will
usually be connected to a high impedance node. It is important that
the effect of parasitic capacitance is felt most strongly at this
high impedance node. Therefore, by placing the epitaxial contact as
far away from this high impedance node as possible, the effects of
the low impedance region in generating capacitance between the
resistor and the epitaxial layer is minimized. Therefore placing
the contact at the low impedance end of the resistor minimizes the
effect of parasitic capacitance. Although the epitaxial layer need
not be shorted to one end of the resistor, in normal operation back
bias may be supplied by the voltage to the low impedance end of the
resistor, and this is why the epitaxial contact is shorted to this
low impedance end. Further, since the epitaxial layer 32 has a
resistance which is higher per unit length than the resistive
element 31, the series resistance to the AC ground 25 is
significant and the distributed capacitance to ground is determined
by the series combination of resistor-to-epitaxial layer
capacitance with epitaxial layer-to-substrate capacitance. In one
experimental configuration, the resistor has a resistance of 200
ohms per mil while the epitaxial layer has a resistance of 500 ohms
per mil.
Two embodiments of the configuration in which high resistivity
epitaxial layers and no buried layers are used are shown in FIGS. 6
and 7. In FIG. 6 resistive element 31 is diffused into epitaxial
layer 32 and is completely surrounded by an isolation ring 30. It
will be appreciated that the resistive element 31 and the isolation
ring have a like conductivity type with the epitaxial layer having
an opposite conductivity type. The resistor in this con-figuration
is of a P-type having a sheet resistivity of 200.OMEGA. . The
epitaxial layer 32 is N-type and has a bulk resistivity of
2.OMEGA.-cm. The isolation ring 30 is of a P-type and has an
impurity concentration of 10.sup.20 atoms/cc. It will be
appreciated that conventional methods of calculating the resistance
of the resistive element 31 are applicable in the subject technique
as well as in the prior art configurations. A discussion of the
resistance characteristics of the resistive element 31 is therefore
omitted. In this configuration a contact 38 to the resistive
element 31 and a contact 34 to the epitaxial layer 32 are provided
with a shorting bar 55 as mentioned hereinbefore. This provides the
resistor with a low impedance end 40 with the opposite end 41 being
the high impedance end of the resistor.
As shown in FIG. 7, the resistor 31' need not be entirely
surrounded by the isolation ring. As shown by the isolation region
60, one end of the resistive element 31' may be left unsurrounded.
This is the low impedance end 40' with the high impedance end 41'
being well within isolation region 60. This configuration saves on
layout space because the contact to the epitaxial layer, here shown
at 61, can be anywhere outside of the isolation region 60. The
simulated adjacency of contact 61 to end 40' is provided by the
U-shaped isolation region 60 such that the adjacency of the contact
61 to the end 40' is not critical since the rest of the resistive
element is shielded by the region 60. The end 40', in this case, is
shown with a contact 38' and it will be appreciated that either a
direct shorting bar may be attached between the contact 61 and
contact 38' or the connection therebetween may be made externally
as shown at line 62. It is open ended structure, shown by the
configuration of the isolation region 60, which gives the resistor,
shown in FIG. 7, the impedance polarity necessary for the reduction
of the parasitic capacitance. It will be appreciated that the
impurity concentrations and the conductivities are similar to those
shown in FIG. 6.
As mentioned hereinbefore, an alternate configuration, which will
reduce parasitic capacitance, is one in which the epitaxial layer
is of a low resistivity. The structure which can be used is shown
in FIG. 8 to include a completely encircling isolation ring 70
which surrounds a resistive element 71 having a like conductivity
type to that of the isolation ring 70. The resistive element 71 is
diffused into an epitaxial layer 72, which is of a low resistivity
per unit length and is indeed much lower than that of the resistive
element 71. Although a buried layer is not necessary, a buried
layer 73 is shown to be directly underneath the resistive element
71 so as to give the epitaxial layer 72 a lower resistivity. This
differs from the configuration shown in FIG. 1, because the buried
layer is very narrow and is completely within the isolation ring
70. An alternate embodiment (not shown) is to provide small N+
regions within the isolation ring 70 since it is not critical that
the buried layer 73 lie directly underneath resistive element 71.
The structure shown in FIG. 8 further differs from the structure
shown in FIG. 1 in that two contacts, 74 and 75, are provided
adjacent either end of the resistive element 71. The low impedance
end of this resistor is shown at a contact 76 which may be either
shorted to a contact 75 or connected externally to a back biasing
potential, as shown in this figure. This shorting acts in the same
manner as the shorting in the embodiment shown in FIG. 3 to reduce
the effects of back biasing the resistor. The high impedance end is
designated by a contact 77 which, as in the former cases, is not
connected directly to the epitaxial layer. The high impedance end
of the resistor is provided with guard circuitry in which the
contact 77 is provided with a high impedance version of the input
signal, as shown by the line 78, while the contact immediately
adjacent the contact 77, i.e., the contact 74, is provided with a
low impedance version of the input signal, as shown by the line 79.
The input signal, shown at 80, is coupled to an impedance convertor
81 which in general is an emitter follower type circuit involving
transistors 82 and 83, which are PNP and NPN transistors,
respectively. The emitter of the transistor 82 and the collector of
the transistor 83 are coupled through identical resistors 84 and 85
to the supply voltage, shown as V+. The high impedance output is
taken at the collector of the transistor 83 while the low impedance
output is taken at the emitter of the transistor 82. In this
configuration, the low impedance end of the resistor is shown
coupled to the power supply voltage V+. Guard circuitry such as
that shown by the emitter-follower pair may be provided separately
or may already be part of the circuit in to which the resistor is
to be placed. The equivalent circuit is shown in FIG. 9. It will be
appreciated that the resistive element 71 is driven by guard
circuitry, which in essense is an impedance convertor which lowers
the impedance of the input signal while preserving phase and all
other aspects. The impedance convertor is therefore represented as
box 90 with a +1 therein.
As shown in FIG. 9, if an epitaxial layer has a resistivity which
is made sufficiently low that the distributed capacitance from the
epitaxial layer to the substrate does not significantly effect the
voltage distribution along the epitaxial layer, then the resistive
element 71 will be completely "guarded" and the capacitance from
the resistive element to the epitaxial layer will have no effect.
Even if there is some departure from the linear voltage
distribution, there is still a considerable reduction in effective
parasitic capacitance. To achieve this significant effect, the end
to end epitaxial layer resistance must be lower than that for the
resistive element. With high resistivity epitaxial layers, the
epitaxial layer resistance is too high to give good results without
making the epitaxial island very wide. To lower the epitaxial
island resistance, as mentioned before, many small buried layer
diffusions (not shown) may be made along the length of the layer;
or a very narrow buried layer, as shown at 73, may be diffused
directly underneath the resistive element 71. Because of the low
resistivity of the epitaxial layer, there would normally be the
afore-mentioned capacitance "lumping." The guard circuitry
represented by the impedance convertor 90 compensates for what
would otherwise be an intolerable situation by driving the
epitaxial layer, immediately adjacent the high impedance end of the
resistive element 71, in such a manner that the signal voltage
developed across the parasitic capacitance, shown at 75, between
the resistor element 71 and the epitaxial region 72 is zero. Thus
the spurious current through the parasitic capacitance is also
zero. As mentioned before, if the current through a capacitor is
zero, the capacitor has no effect. By driving both the resistive
element 71 and the epitaxial layer 72 such that the voltage along
each of the elements is equal, the ends of the capacitors 75 will
have equal voltages on them. There will be no voltage drop across
the capacitors and hence none of the aforementioned current. Thus
there will be no parasitic capacitance effect with the technique
shown in FIGS. 8 and 9. If any spurious capacitance occurs it will
be coupled to the AC ground by capacitors 76. These capacitors are
not "lumped" as in FIG. 2 because the majority of the parasitic
capacitance between the resistor 71 and the epitaxial layer 72 is
compensated for by the guard circuit-impedance convertor 90,
leaving only occasional pockets of capacitance randomly spaced
along the length of the resistor to be coupled to ground.
It will be appreciated that isolation ring 70 need not fully
surround resistive element 71 but may leave the low impedance end
of the resistor 71 unsurrounded as in the case shown in FIG. 7. The
contact 75 may therefore be placed anywhere outside the isolation
ring and be provided with the appropriate back biasing
potential.
* * * * *