U.S. patent number 3,697,881 [Application Number 05/053,527] was granted by the patent office on 1972-10-10 for phase detection system for at least one digital phase-modulated wave.
This patent grant is currently assigned to Kokusai Denshin Denwa Kabushiki Kaisha. Invention is credited to Kazuo Kawai, Hisakichi Michishita, Yukio Nakagome, Sotokichi Shintani, Hidetaka Yanagidaira.
United States Patent |
3,697,881 |
Nakagome , et al. |
October 10, 1972 |
PHASE DETECTION SYSTEM FOR AT LEAST ONE DIGITAL PHASE-MODULATED
WAVE
Abstract
A phase detection system for at least one digital
phase-modulated wave, in which two products of a phase-modulated
digital signal and two reference carrier waves each having the same
frequency as the phase-modulated digital signal and a phase
difference 90.degree. therebetween are at first produced, so that a
converted value which is a function of a phase difference between
the phase-modulated digital signal and one of the reference carrier
waves is found by integrating respectively the two products or by
passing the two products in respective low-pass filters. The phase
detection of the phase-modulated wave is performed by comparing the
converted value with a reference phase. Compensation means may be
further provided to compensate phase error in the converted
value.
Inventors: |
Nakagome; Yukio (Tokyo,
JA), Kawai; Kazuo (Tokyo, JA), Yanagidaira;
Hidetaka (Ohmiya, JA), Shintani; Sotokichi
(Tokyo, JA), Michishita; Hisakichi (Tokyo,
JA) |
Assignee: |
Kokusai Denshin Denwa Kabushiki
Kaisha (Tokyo-to, JA)
|
Family
ID: |
26394833 |
Appl.
No.: |
05/053,527 |
Filed: |
July 9, 1970 |
Foreign Application Priority Data
|
|
|
|
|
Jul 10, 1969 [JA] |
|
|
44/54094 |
Sep 12, 1969 [JA] |
|
|
44/72462 |
|
Current U.S.
Class: |
329/306; 327/7;
375/332 |
Current CPC
Class: |
H04L
27/2332 (20130101) |
Current International
Class: |
H04L
27/233 (20060101); H04l 027/22 () |
Field of
Search: |
;329/50,104,110
;328/109,110,134 ;307/232 ;325/320,321,324 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Brody; Alfred L.
Claims
What we claim is:
1. A phase detection system for at least one digital
phase-modulated wave, comprising:
an input terminal for receiving a digital phase-modulated wave;
a reference phase generator having means for generating a first
reference carrier and a second reference carrier each having a
frequency substantially equal to the frequency of said digital
phase-modulated wave and having a phase difference 90.degree.
therebetween;
modulation product means coupled to the input terminal and the
reference phase generator to produce a first modulation product of
the first reference carrier and the digital phase-modulated wave
and to produce a second modulation product of the second reference
carrier and the digital phase-modulated wave;
conversion means coupled to the modulated product means to convert
the first modulation product and the second modulation product to a
converted signal indicative of a value corresponding to a phase
difference between the digital phase-modulated wave and one of said
first and second reference carriers; and
comparison means coupled to the conversion means to compare the
converted signal with one of a plurality of possible discrete phase
positions of the digital phase modulated wave so as to perform
phase-detection of the digital phase-modulated wave.
2. A phase detection system according to claim 1, in which the
conversion means comprises a pair of integrators each performing
integration for each signal element of the digital phase-modulated
wave.
3. A phase detection system according to claim 1, in which the
conversion means comprises a pair of low pass filters.
4. A phase detection system according to claim 1, in which the
system further comprises compensation means coupled to the
comparison means to subtract a phase corresponding to a transmitted
code and the reference phase from the phase position of the
phase-modulated wave to obtain a phase error and having means to
perform the phase compensation of the reference phase by the use of
the phase error.
5. A phase detection system according to claim 1, in which the
system further comprises a PCM coder arranged between the input
terminal means and the modulation product means.
6. A phase detection system according to claim 5, in which the
comparison means comprises phase-error detection means for
detecting phase-error from lower digit values of the converted
signal, a subtractor coupled to the conversion means and the
phase-error detection means for subtracting the phase-error from
all digit values of the converted signal, and demodulation means
coupled to the subtractor for performing demodulation of the phase
modulated wave by the use of higher bits only of the output digital
values of the subtractor.
Description
This invention relates to a phase detecting system for at least one
digital phase-modulated wave modulated to quantum or discrete phase
positions in accordance with information signal or signals to be
transmitted.
As the phase detection system, there are a delayed detection system
and a synchronous detection system in a broad classification. The
delayed detection system is employed for detecting a differential
phase modulated wave so that the phase position of a signal element
is compared with the phase position of an immediately preceding
signal element to detect a phase difference between two successive
signal elements. Accordingly, a delay circuit having a delay time
equal to the duration of the signal element is necessary in this
system. Moreover, it is necessary that the delay time of the delay
circuit is correctly maintained over a necessary frequency range.
On the other hand, a reference carrier generator is necessary in
the synchronous detection system to obtain a reference phase
position. In this case, the phase position of the reference carrier
is usually regulated by the use of phase-information transmitted
from the sending side or by detecting phase-information from the
received signal. In this case, transmission of the phase
information is necessary by the use of another communication
channel so that this is uneconomical and unusual. Moreover, it is
very difficult to detect phase-information from the received signal
and regulate the reference carrier generator.
An object of this invention is to provide a phase detection system
of a digital phase-modulated wave or waves capable of performing
phase detection corresponding to the delayed phase detection system
or the synchronous detection system by a single circuit without
complicated delay circuits and regulation circuits and suitable to
reduce to practice by use of digital circuitry and to form
time-divisional circuitry for a plurality of phase-modulated
waves.
Another object of this invention is to provide a phase detection
system of at least one digital phase-modulated wave capable of
performing phase detection by digital operation without use of a
reference carrier generator having a feed back loop coupled to the
digital phase-modulated wave.
In accordance with a first feature of this invention, two products
of a phase-modulated digital signal and respective two reference
carrier waves each having the same frequency as the phase-modulated
digital signal and a phase difference .pi./2 therebetween are at
first produced, so that a value which is a function of a phase
difference between the phase-modulated digital signal and one of
the reference carrier waves is found by integrating respectively
the two products or by passing the two products in respective
low-pass filters, whereby phase detection of the phase-modulated
digital signal is performed.
In accordance with a second feature of this invention, the phase of
each signal element of the phase-modulated digital signal detected
as mentioned above is temporarily stored as a stored phase, and
this stored phase is replaced by a phase position of an immediately
succeeding signal element similarly detected by the use of a phase
difference between successive two signal elements.
In accordance with a third feature of this invention, a phase
representative of digital information to be transmitted is
substracted from a phase difference between the stored phase and
the phase-modulated digital signal to obtain an error so that this
error is employed to compensate the stored phase so as to produce a
compensates stored phase of reference.
As results of the above features, the system of this invention has
following merrits:
1. Since phase information is represented by digital information,
phase information can be correctly represented by increasing the
number of digits of the digital information.
2. Even if an oscillator is employed for generating reference
carriers, it is not necessary that the frequency of the oscillator
is regulated. Accordingly, the stability of the oscillation
frequency of the oscillator is very high while feed back means is
not necessary. These are suitable to low cost of the system.
3. A plurality of phase-modulated digital signals can be
phase-detected in a time-divisional manner, so that the system can
be formed in a small size and have a low cost.
The principle, construction, operation and merits of the system of
this invention will be better understood from the following more
detailed discussion in conjunction with the accompanying drawings,
in which:
FIG. 1 is a wave form for describing an example of a digital
phase-modulated wave applied to the system of this invention;
FIGS. 2 and 9 are vector diagrams explanatory of the principle of
phase modulation in a phase-modulated wave applied to the system of
this invention;
FIG. 3 is a block diagram for illustrating an embodiment of this
invention;
FIG. 4 is a flow-chart explanatory of the operation of the system
shown in FIG. 3;
FIG. 5 is a block diagram for illustrating a part of another
embodiment of this invention;
FIGS. 6A, 6B, 7 and 8 are block diagrams each for illustrating
another embodiment of this invention;
FIGS. 10 and 11 are block diagrams each for illustrating an example
of a circuit used in the embodiment shown in FIG. 8; and
FIG. 12 shows characteristic curves explanatory of the operation of
the example shown in FIG. 11.
The principle of this invention will first be described. In this
case, phase detection of an eight-phase differential
phase-modulated wave transmitting three bits of information for
each signal element is taken as an example. With reference to FIG.
1 showing a wave form of a received signal, if the instantaneous
level, phase-position and amplitude of a signal element and the
angle frequency of the carrier are assumed respectively as S.sub.i
(t), .phi..sub.i, w.sub.c and A, the instantaneous level of an i-th
signal element S.sub.i (t) can be indicated as follows:
S.sub.i (t) = A cos(w.sub.c t + .phi..sub.i) (1)
In this case, the time t satisfies a condition 0 .ltoreq.t<T if
the duration of the signal element is indicated by "T".
Accordingly, the time t is zero at the start of the signal element
and the value T at the termination of the signal element.
In this system, a reference carrier wave having the same frequency
as the received signal is employed to detect at first a phase
difference between the reference carrier wave and the received
signal. To obtain this phase difference, a product of the reference
carrier wave and the received signal and a product of the received
signal and another reference carrier having a phase position
different by .pi./2 from that of the reference carrier wave are
performed. If the angle frequency and phase position of the
reference carrier wave are assumed as values w.sub.s and
.phi..sub.s while the amplitude of the reference carrier wave is
"1" without loss of the general meaning, the product of the
reference carrier wave and the received wave can be indicated as
follows:
A cos (w.sub.c + .phi..sub.i).cos (w.sub.s t + .phi..sub.s)
= A/2 . cos ((w.sub.c + w.sub.s)t + .phi..sub.i + .phi..sub.s)
+A/2 . cos((w.sub.c - w.sub.s)t + (.phi..sub.i + .phi..sub.s))
(2)
This product output is passed through a low pass filter so that a
second member of the equation (2) is obtained. In this case, since
the value w.sub.c is substantially equal to the value w.sub.s, the
output is substantially equal to a value A/2.cos (.phi..sub.i -
.phi..sub.s).
The second member of the equation (2) can be also obtained by
integrating the product output during a duration .tau. equal to
n/2-multiple of the period of the carrier wave. In other words, the
duration .tau. is equal to a value 2.pi./w.sub.c. n, where n is a
positive integer. Namely, the integration of a first member is as
follows:
Moreover, since a value (w.sub.c .gtoreq. w.sub.s)t is
substantially equal to zero in view of a condition w.sub.c
.apprxeq. w.sub.s, an integration of the second member is as
follows:
In a similar manner, a product of the received signal and another
reference signal having a phase position different by .pi./2 from
the reference carrier is as follows:
A cos(w.sub.c t + .phi..sub.i) cos (w.sub.s t + .phi..sub.s -
.pi./2)
= A/2 .cos((w.sub.c + w.sub.s)t + .phi..sub.i + .phi..sub.s -
.pi./2)
+A/2.cos((w.sub.c - w.sub.s)t + (.phi..sub.i - .phi..sub.s) +
.pi./2) (4)
The second member only of the equation (4) can be also obtained by
passing the product output into a low pass filter. In this case,
since a value w.sub.c is substantially equal to a value w.sub.s,
the output of the low-pass filter is as ollows:
A/2.cos((.phi..sub.i - .phi..sub.s) + .pi./2) = A/2 sin
(.phi..sub.i - .phi..sub.s)
On the other hand, if the product output is integrated during a
duration .tau., an integration of the first member of the equation
(4) is as follows:
Moreover, an integration of the second member of the equation (4)
is as follows:
.apprxeq. A/2.cos((.phi..sub.i - .phi..sub.s) + .pi./2)
= A/2.sin(.phi..sub.i - .phi..sub.s) (5)
This is an output of this integration.
If the signals indicated in the equations (3) and (5) are assumed
as follows:
y.sub.i = A .tau./2.cos (.phi..sub.i - .phi..sub.s) (6)
x.sub.i = A .tau./2.sin (.phi..sub.i - .phi..sub.s) (7)
the following relationship is satisfied.
x.sub.i /y.sub.i = tan (.phi..sub.i - .phi..sub.s)
Therefore, a phase difference .PHI..sub.i between the received
signal having a phase position .phi..sub.i and the reference
carrier wave having a phase position can be indicated as
follows:
.PHI..sub.i = .phi..sub.i - .phi..sub.s = tan.sup.-.sup.1 x.sub.i
/y.sub.i (8)
This relationship is also obtained in a case of passing into the
low-pass filter by the ratio of two outputs.
As mentioned above, the product of the reference carrier wave and
the received signal and the product of another reference wave
having a phase position different by .pi./2 from that of the
reference carrier wave are at first obtained, and values x.sub.i
and y.sub.i are obtained by integrating the products or passing the
products into low-pass filters respectively. The phase difference
.PHI..sub.i between the received signal and the reference carrier
wave is obtained by the use of the ratio x.sub.i /y.sub.i. However,
since a function tan.sup.-.sup.1 (x.sub.i /y.sub.i) is not a
univalent function, the value .PHI..sub.i is not uniquely
determined for a value x.sub.i /y.sub.i. Therefore, if the
following relationship is assumed by the use of an absolute value
.vertline.x.sub.i /y.sub.i .vertline. of the value x.sub.i
/y.sub.i, the value .PHI..sub.i can be indicated as shown in Table
1 in accordance with the positive or negative conditions of the
values x.sub.i and y.sub.i.
.PHI..sub.io = tan.sup.-.sup.1 .vertline.x.sub.i /y.sub.i
.vertline. (9)TABLE 1 x.sub.i y.sub.i Quadrant .PHI..sub.i
__________________________________________________________________________
+ + first .PHI..sub.i = .PHI..sub.io - + second .PHI..sub.i =.pi. -
.PHI..sub.io - - third .PHI..sub.i = .pi. + .PHI..sub.io + - fourth
.PHI..sub.i = 2.pi. - .PHI..sub.io
__________________________________________________________________________
The value .PHI..sub.i can be obtained as mentioned above.
Accordingly, when a value .PHI..sub.i.sub.+ 1 of (i +1)-th signal
element is similarly obtained, transmitted information can be
detected by calculating a difference (.PHI..sub.i.sub.+ 1 -
.PHI..sub.i) in a manner similar to the delayed detection
system.
In FIG. 2 and Table 2, codes and phase-positions of the eight-phase
phase modulated wave are shown. By way of example, if a phase
difference d between adjacent two signal elements is included in a
range 5/8..pi.<d<7/8..pi., transmitted information of three
bits is a code "100".
In this example, codes are coded in Gray code. However, codes may
be coded in other code configurations, such as normal binary codes.
In Table 2, phase differences between adjacent two signal elements
and Gray codes of the eight-phase phase-modulated wave are
shown.
TABLE
2 ideal decision range Multiplier m transmitted phase- of phase-
multiplying codes diffe- differenced unit phase rence 15.pi./8<d
2.pi. 0 0 0 0 or 0 0 d <.pi./8 0 0 1 .pi./4 .pi./8 d<3.pi./8
1 1 0 1 .pi./2 3.pi./8 d<5.pi./8 2 1 0 0 3.pi./4 5.pi./8
d<7.pi./8 3 1 1 0 .pi. 7.pi./8 d<9.pi./8 4 1 1 1 5.pi./4
9.pi./8 d<11.pi./8 5 0 1 1 3.pi./2 11.pi./8 d<13.pi./8 6 0 1
0 7.pi./4 13.pi./8 d<15.pi./8 7
__________________________________________________________________________
Three bits of information transmissible on each signal element
having eight possible phases or phase positions are shown in a left
most column. The phase difference d is represented with respect to
an immediately preceding signal element as a reference. A
multiplier multiplying a unit phase (.pi./4 in this case)
corresponds to a transmitted code. The multipliers are shown at a
right most column while codes corresponding to the multipliers are
shown at the left most column.
With reference to FIG. 3, an example of this invention to perform
the above-mentioned principle comprises an input terminal 1 for
receiving an input phase-modulated signal, reference signal
generator 2 for generating the reference carrier wave fa having a
frequency substantially equal to the frequency of the input signal,
a phase-shifter 3 having a phase shifting value .pi./2, modulation
product circuits 4-1 and 4-2 (e.g.; ring-modulator), integrators
5-1 and 5-2 each repeating integration operation every time .tau.
equal to an integer multiple of one half the period of the carrier
of the input signal, samplers 6-1 and 6-2 each sampling the output
of the integrator 5-1 or 5-2 for each signal element at the
termination of the integrating time .tau., a converter 7 (e.g.;
conversion table) for converting respective absolute values of the
samplers 6-1 and 6-2 to the value .PHI..sub.io defined in the
equation (9), a converter 8 (e.g.; conversion table) for converting
respective outputs of the sampler 6-1 and 6-2 and the value
.PHI..sub.io found at the converter 7 to the value .PHI..sub.i in
accordance with Table 1, a memory 9 storing respective values
.PHI..sub.i and .PHI..sub.i.sub.+ 1 of successive two signal
elements, a subtracter 10 for obtaining a difference
(.PHI..sub.i.sub.+ 1 - .PHI..sub.i) to codes in accordance with
Table 2, and an output terminal 12 for the detected code.
In operation, the input signal is applied from the input terminal 1
to the modulators 4-1 and 4-2, so that a product of the received
signal and the reference carrier wave f.sub.a is obtained at the
output of the modulators 4-1 while a product of the received signal
and another reference carrier wave f.sub.b having a phase position
different by .pi./2 from the phase position of the reference
carrier wave f.sub.a is obtained at the output of the modulator
4-2. These outputs of the modulators 4-1 and 4-2 are respectively
defined by the equations (2) and (4) and applied respectively to
the integrators 5-1 and 5-2 so as to be integrated for a time
substantially equal to an integer multiple of one half the period
of the carrier. These integration operations are performed for each
signal element in synchronism with bit timing pulses applied from
terminals 5-0. The bit timing pulses are usually transmitted from
the sending side but may be independently generated at this
receiving side. The values y.sub.i and x.sub.i defined by the
equations (3) and (5) respectively are obtained from the
integrators 5-1 and 5-2 respectively. These outputs are sampled at
the samplers 6-1 and 6-2 respectively and applied to the converters
7 and 8. The value .PHI..sub.io is obtained at the converter 7 from
a ratio of the absolute value .vertline.x.sub.i .vertline. to the
absolute value .vertline.y.sub.i .vertline.. The value .PHI..sub.io
and the sampled outputs of the samplers 6-1 and 6-2 are converted
to the value .PHI..sub.i at the converter 8. The output .PHI..sub.i
of the converter 8 is stored in the memory 9, and the difference
(.PHI..sub.i.sub.+ 1 - .PHI..sub.i) is obtained from the
substracter 10 and applied to the code 11. At the output terminal
12, a code corresponding to the difference (.PHI..sub.i.sub.+ 1 -
.PHI..sub.i) is abtained.
In the above mentioned principle, a transmitted code is detected by
the use of a difference between values .PHI..sub.i.sub.+ 1 -
.PHI..sub.i which are found for successive two signal elements
similarly to the delayed detection system. The above mentioned
value .PHI..sub.i can be applied to perform synchronous detection
as follows.
In this synchronous detection system, a phase regulation circuit
for synchronizing the phase position of a reference carrier wave
with the received signal is not employed. In the above-mentioned
detection principle, the phase position .PHI..sub.i of an
immediately preceding signal element is stored to find the
difference between this phase position .PHI..sub.i and a phase
position .PHI..sub.i.sub.+ 1 of a succeeding signal element. In
this detection system now mentioned, however, a code corresponding
to a difference .PHI..sub.i.sub.+ 1 - .theta..sub.i between a phase
position .PHI..sub.i.sub.+ 1 and a reference phase position
.theta..sub.i obtained in accordance with the received result of an
immediately preceding signal element is found in accordance with
the principle shown in Table 2. If following conditions are
satisfied, namely:
.PHI..sub.i.sub.+ 1 - .theta..sub.i = d.sub.i.sub.+ 1
d.sub.i.sub.+ 1 = m.sub.i.sub.+ 1..pi./4
where "m.sub.i.sub.+ 1 " is equal to a value 0, 1, 2, 3, 4, 5, 6 or
7, the value .PHI..sub.i.sub.+ 1 is stored after changing to a
value .theta..sub.i.sub.+ 1. In this case, it is conceivable that
the stored phase position is synchronized with the received
signal.
If a condition:
d.sub.i.sub.+ 1 .noteq.m.sub.i.sub.+ 1..pi./4
is satisfied, a phase difference is shown by a value
(d.sub.i.sub.+1 - m.sub.i.sub.+1 ..pi./4).
If the value (d.sub.i.sub.+ 1 - m.sub.i.sub.+ 1..pi./4) is assumed
a a value r.sub.i.sub.+ 1, a following condition is satisfied.
-.pi./8<r.sub.i.sub.+ 1 <.pi./8
In this case, the phase position of signal element is indicated by
a value m.sub.i..pi./4 since an eight-phase phase-modulated wave is
taken as an example. However, in a case of a N-phase
phase-modulated wave, the phase position of signal element is
indicated by a value m.sub.i..pi./N while a condition:
-.pi./N<r.sub.i <.pi./N is satisfied. In this principle, a
value .theta..sub.i.sub.+ 1 indicated by a following condition:
.theta..sub.i.sub.+ 1 =.vertline..vertline..theta..sub.i +
m.sub.i.sub.+ 1..pi./4 + K.r.sub.i.sub.- 1 .vertline..vertline.
is stored to compensate an error of phase position. In this case,
".vertline..vertline. .vertline..vertline." shows a notation of
mode 2.pi., so that if the value of a sum shown within the notation
exceeds the value 2.pi. this value 2.pi. is substracted from the
sum to obtain the value .theta..sub.i.sub.+ 1. A difference
.PHI..sub.i.sub.+.sub.1 - .theta..sub.i is found for the receiving
of each signal element by the use of the phase position
.PHI..sub.i.sub.+ 1 of the signal element and a phase position
.theta..sub.i stored as mentioned above. Moreover, a code
corresponding to the signal element is obtained from a multiplier
m.sub.i.sub.+ 1 of a unit phase corresponding to a phase difference
d.sub.i.sub.+ 1 in accordance with the principle shown in Table
2.
The above principle will be further described in details with
reference to a flow chart shown in FIG. 4. It is assumed that a
transmitted code is detected from an i-th signal element and a
compensated phase position .theta..sub.i is stored in the memory.
When an (i + 1)-th signal element is received, the phase position
thereof is found as mentioned above. In this case, a difference
.PHI..sub.i.sub.+ 1 - .theta..sub.i is at first calculated as shown
in the flow chart of FIG. 4. If the difference .PHI..sub.i.sub.+ 1
- .theta..sub.i is less than zero, a sum .PHI..sub.i.sub.+ 1 +
2.pi. -.theta..sub.i is found and applied to a register R. However,
if the difference .PHI..sub.i.sub.+ 1 - .theta..sub.i is stored in
the register R. If the contents r of the register R do not satisfy
a condition: - .pi./8<r<.pi./8, a difference r - /4 is found
and "1" is added to a counter. Thereafter, the condition:
-.pi./8<r<.pi./8 is again tested. If the condition:
-.pi./8<r<.pi./8 is satisfied, the contents m.sub.i.sub.+ 1
of the counter at this instant are coded to a code in accordance
with the principle shown in Table 2 so that the code is sent out to
the output. Moreover, a sum .vertline..vertline..theta..sub.i +
.pi./4.m.sub.i.sub.+ 1 + K.r.sub.i.sub.+.sub.1 .vertline..vertline.
is found from the contents r.sub.i.sub.+ 1 of the register at this
instant and stored, as a stored phase .theta..sub.1.sub.+ 1, in the
memory. In this case, a value K is a coefficient which meets with a
condition: 0<K<1.
In the above explanation, it is assumed that a stored phase is
already stored. However, it is not known what value is stored in
the memory when a first signal element is received. The stored
value is compensated for receiving of each signal element by
repeating the above-mentioned operations, so that the stored value
is corrected to a correct value. The speed of this correction is
determined in accordance with the value of the coefficient K. If
the coefficient K is equal to "1" as an extreme case, this phase
detection corresponds to the delayed phase direction in which phase
detection of a signal element is performed with respect to the
phase position of an immediately preceding signal element as a
reference. On the other hand, if the coefficient K is equal to
zero, a value .theta. given at first is completely synchronized
with the received signal so that this synchronized condition is
thereafter maintained.
With reference to FIG. 5, an example of a circuit performing the
above-mentioned synchronous phase detection will be described. In
this example, a memory 9 is the same as the memory 9 shown in FIG.
3 and stores the phase position of a received signal element. A
memory 14 stores the above mentioned stored phase .theta..sub.i. A
calculating circuit 13 (e.g.; conversion table) produces a
difference .PHI..sub.i.sub.+ 1 - .theta..sub.i by the use of the
value .PHI..sub.i.sub.+ 1 applied from the memory 9 and the stored
phase .theta..sub.i applied from the memory 14. If a condition:
.PHI..sub.i.sub.+1 - .theta..sub.i <0is not satisfied, the
difference .PHI..sub.i.sub.+1 - .theta..sub.i is stored in a
register 15. However, if a condition: .PHI..sub.i.sub.+ 1 -
.theta..sub.i <0 is satisfied, a value .PHI..sub.i.sub.+ 1 +
2.pi. - .theta..sub.i is stored in the register 15. A calculating
circuit 24 tests whether or not the contents r of the register 15
meet with a condition: - .pi./8<r<.pi./8 in a case of
detection of a eight-phase phase-modulated wave. If the contents r
are not included within the above range, the contents r are applied
through a gate circuit 16 to a calculating circuit 21. This
calculating circuit 21 produces a difference r - .pi./4 which is
again stored in the register 15 through a delay circuit 19 having a
very small delay time.
Moreover, the pulse from the calculating circuit 24 is applied to a
counter 22. The contents r newly stored in the register 15 are
tested by the calculating circuit 24. The above-mentioned
condition: - .pi./8<r<.pi./8 is not satisfied, the above
mentioned operations are repeated. When the condition: -
.pi./8<r<.pi./8 is satisfied, the contents r of the register
15 passes through a gate circuit 17 opened in response to the pulse
from the calculating circuit 24 and is applied to a calculating
circuit 25. On the other hand, the contents m.sub.i of the counter
22 are converted to a code in a converter 23 in accordance with the
principle shown in Table 2 to send out the code to an output
terminal 26 through a gate circuit 18. The counting state of the
counter 22 is reset at once in response to the output pulse of the
calculating circuit 24 applied through a delay circuit 20. The
calculating circuit 25 produces a sum .pi./2.m.sub.i + K.r by the
use of the contents r of the register 15 and the contents m.sub.i
of the counter 22 so as to be stored in the memory 14 and a new
stored phase .theta..sub.i.
An example of obtaining the timing pulses for controlling the
integration period of the integrators (5-1, 5-2) will now be
described. In a case where a modulation product of the received
signal and the output of the reference carrier wave is performed at
the modulator (4-1,4-2) as mentioned above, the output of the
modulator can be divided into two parts one of which has a
frequency substantially equal to the frequency of the reference
carrier wave and the other of which is a low-frequency signal
having an instantaneous level changed in accordance with only
digital information transmitted. If this low-frequency signal is
separated from the former component by a low-pass filter, the
timing pulses can be obtained so as to synchronize with
characteristic instants of the low-frequency signal since the level
of the low-frequency signal varies in accordance with digital
information transmitted. Moreover, since the output of the low-pass
filter (i.e.; the low-frequency signal) is proportional to values
x.sub.i and y.sub.i, this output of the low-pass filter can be used
in the place of the values x.sub.i and y.sub.i.
A separated channel may be employed to transmit bit timing
information for integration and sampling. Moreover, it is desirable
that the integrating time for integrating the output of the
modulator (4-1, 4-2) for each signal element is substantially equal
to an integer multiple of one half the period of the carrier as
mentioned above. However, if the period of the carrier is
sufficiently smaller (e.g.; less than one several-th) than the
duration of the signal element, integration error will be small
even if the integration time is determined irrespective of the
period of the carrier. Accordingly, the integration time may be
determined so as to be equal to or smaller than the duration of the
signal element irrespective of the period of the carrier.
Furthermore, the values of phase are represented in radians.
However, values of phase represented in degrees can be also handled
in this system.
In the above explanation, it is assumed that a phase-modulated wave
is applied to the system of this invention. However, if a plurality
of phase-modulated waves are applied to this system, common
circuitry provided after the samplers (6-1, 6-2) can be used
time-divisionaly for the phase-modulated waves. Moreover, if the
input signal is at first sampled and coded to a binary signal, all
the circuits can be formed by digital circuits. If a high speed
calculating circuit can be employed, the above mentioned modulation
product and integration can be performed by a common calculating
circuit.
With reference to FIG. 6A, an example, of this invention for
receiving a plurality of phase-modulated waves having the same
frequency comprises a reference carrier generator II which is the
same as the reference carrier generator 2, a phase shifter III
which is the same as the phase shifter 3, a scanning sampler I for
scanning input signals applied from input terminals I.sub.1,
I.sub.2, .... I.sub.n, reference carriers obtained from the
reference carrier generator II and the phase shifter III by the use
of sampling pulses applied from a control circuit VII, a coder IV
for coding the sampled output of the scanning sampler I, a memory V
for temporarily storing the coded output of the coder IV, a
calculating circuit VI for performing the above mentioned
calculation for the contents of the memory V, and the control
circuit VII for applying timing information to the circuits I, IV,
V and VI.
If a read-only memory VIII is provided for semipermanently storing
respective sampled values of the reference carriers after coded as
shown in FIG. 6B, the reference carrier generator II and the phase
shifter III can be eliminated. In this case, contents of the
read-only memory VII is repeatedly read-out without sampling and
coded for each sampling period as shown in FIG. 6A. Moreover, since
two reference carriers have only a phase difference between each
other, a common memory table can be used in a normal address
condition and a condition where addresses are shifted from the
normal address condition. In this case, however, a clock is
necessarily provided in the control circuit VII so as to
synchronize with the cycle of the reference carrier wave.
The above-mentioned explanation relates to detection operation of
an eight-phase phase-modulated wave. However, the system of this
invention can be applied to detect at least one phase-modulated
wave having 2.sup.n possible quantum phase positions for
transmitting n bit or bits of digital information on each signal
element.
In the above explanation, it is assumed that the modulation product
circuit (4-1, 4-2) produces an output signal having positive and
negative possible polarities. However, if the modulation product
circuit (4-1, 4-2) produces an output signal of single polarity,
two circuits are necessary for the modulation product circuit (4-1
or 4-2).
With reference to FIG. 7, an example of this system for commonly
phase-detecting a plurality of phase-modulated waves is provided
with a plurality of reference carrier generators II-1, II-2, ....
II-n for generating reference carrier waves respectively having the
same frequency as frequencies f.sub.1, f.sub.2, .... f.sub.n of the
phase-modulated waves, and a plurality of phase shifters III-1,
III-2, .... III-n.
With reference to FIG. 8, another example of this invention will
now be described. This example comprises, an input terminal A, a
PGM coder B, a code converter C, a reference carrier generator D,
an accumulator E, a code converter F, a code converter G for
detecting transmitted phase information, and an output terminal
H.
It is assumed that a plurality of eight-phase differential
phase-modulated waves bit-synchronized with each other and
allocated in frequency spaces 1/T Herz are applied to the input
terminal A. In this case, the time T is equal to or slightly less
than the duration of each signal element of the phase-modulated
wave. Eight quantum phases and codes to be transmitted on one of
the eight-phase differential phase-modulated waves are shown in
FIG. 9. Vectors shown in FIG. 2 indicate phase-shift from a
reference phase (i.e.; phase position of vector MMM) in response to
combination of mark (M) and space (S) of three channels or bits I,
II and III. The above mentioned eight-phase differential
phase-modulated waves are applied to the PCM coder B, which samples
the applied signal by sampling pulses of several tens kilo-Herz and
codes PCM codes of 10 bits by way of example. These PCM codes are
code-converted at the code converter C by the use of two reference
carrier waves having a phase difference .pi./2 therebetween
supplied from the reference carrier generator D. This code
conversion corresponds to phase detection in an analogue system.
The outputs of the code converter C obtained for the two reference
carrier waves respectively are applied to the accumulator E, which
accumulates separately the two outputs of the code converter C
during each signal element and ends out respective accumulated
results at the termination of each signal element to the code
converter F. This operation corresponds to integration operation of
an anlogue system. If it is assumed that respective phase
differences between one of the reference carrier waves and the
input signal and between the other of the reference carrier waves
and the input signal are values .PHI..sub.i and .PHI..sub.i
-90.degree. respectively, the two output codes of the accumulator E
correspond respectively voltages proportional to cos .PHI..sub.i
and sin .PHI..sub.i respectively. Accordingly, the two output codes
of the accumulator E can be converted to a code representative of
the value .PHI..sub.i in the code converter F as mentioned below.
The output of the code converter F is applied to the code converter
G, which detects transmitted digital information in view of the
principle of differential phase-modulation as mentioned below.
Respective parts of the example shown in FIG. 1 will be further
described in details below. The PCM coder can adopt any type of PCM
code. However, it is assumed in this case that the output code of
the PCM coder B is "a folded binary code". Moreover, it is assumed
that the folded binary code is derived therefrom as a parallel
configuration. However, if successive logical circuitry is designed
so as to perform high speed operation, the output code of the PCM
coder B may be derived therefrom in serial configuration.
The reference carrier generator D generates, for each
phase-modulated wave, two reference carrier waves of rectangular
wave form which have the same frequency substantially equal to the
frequency of the phase-modulated wave and a phase-difference
90.degree. from each other.
The code converter C converts the output of the PCM coder B in
response to respective polarities "1" and "0" of the two reference
carrier waves from the reference carrier generator D. In this case,
it is assumed for simple explanation that the number of the
phase-modulated wave is one and the number of the reference carrier
wave is also one. The most significant digit (MSD) of the PCM code
is compared with the polarity of the reference carrier wave, so
that the MSD is modified to "1" and "0" in response to the same
polarity and different polarities of the above compared digit and
wave. The PCM codes in which only the MSD is modified as mentioned
above are applied to the accumulator E.
The accumulator E accumulates the converted PCM codes during the
duration of each signal element and sends out the accumulated
results at the termination of each signal element.
As mentioned above, respective phase detection between one of the
two reference carrier waves and the input phase-modulated wave and
between the other of the two reference carrier waves and the input
phase-modulated wave as well as integration of the respective
results of the phase detections are digitally performed. The above
phase detections are time-divisionally performed for the two
reference waves by supplying alternately the two reference carrier
waves from the reference carrier generator D to the code converter
C. Moreover, two stages of registers are provided at the
accumulator E to as to be connected in cascade with the accumulator
E while the output of the two stages of registers are fed back to
the accumulator E, so that contents of a preceding one of the two
stages of registers are shifted to a successive one of the two
stages of the registers in synchronism with the switching of the
two reference carrier waves.
To handle a plurality of phase-modulated waves, a plurality of
pairs of reference carrier waves are generated from the reference
carrier generator D, and a plurality of combinations (two stages)
of registers are provided in the accumulator E similarly as
mentioned above, so that the registers are switched in synchronism
with the switching of the carrier waves.
If two signals applied from the accumulator E to the code converter
F are assumed as "x" and "y", these signals "x" and "y" can be
indicated as A.sin .PHI..sub.i and A.cos .PHI..sub.i. This code
converter F converts the values A.sin .PHI..sub.i and A.cos
.PHI..sub.i to a value .PHI..sub.i indicated as a coded digital
signal. In this case, this conversion may be performed by the use
of a conversion table of tan.sup.- .sup.1 z/y after obtaining a
quotient x/y. However, division is unsuitable to high speed logical
operation. Moreover, since the conversion table is designed for all
combinations of values x and y, the device will become a very large
size in accordance with the increase of the number of bits of the
values x and y.
To eliminate the above defect, inhibited combinations of values x
and y may be removed from the conversion table. In this case, since
the required value .PHI..sub.i is equal to a value tan.sup.-.sup.1
x/y, the value .PHI..sub.i is not varied even if the respective
values x and y are multiplied by the same multiplier. Accordingly,
if respective MSD of the values x and y are both "0", the values x
and y are both multiplied by a multiplier 2.sup.N (where "N" is an
integer) to shift by N bits so that the MSD of either the value x
or y becomes always "1". Thereafter, combinations in each of which
MSD of both the values x and y assume "0" are eliminated to
increase preciseness. In Table 3, examples of inhibited
combinations in a case where values x and y are each indicated by
three bits of binary information are shown by mark (*)
TABLE
3 Inhibited Inhibited x y x y combinations combinations 0 0 0 0 0 0
1 0 0 0 0 0 * 0 0 0 0 0 1 1 0 0 0 0 1 * 0 0 0 0 1 0 1 0 0 0 1 0 * 0
0 0 0 1 1 1 0 0 0 1 1 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 1 0 1 1 0 0 1 0
1 0 0 0 1 1 0 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 1 1 1 * 0 0 1 0 0 0 1 0
1 0 0 0 * 0 0 1 0 0 1 1 0 1 0 0 1 * 0 0 1 0 1 0 1 0 1 0 1 0 * 0 0 1
0 1 1 1 0 1 0 1 1 0 0 1 1 0 0 1 0 1 1 0 0 0 0 1 1 0 1 1 0 1 1 0 1 0
0 1 1 1 0 1 0 1 1 1 0 0 0 1 1 1 1 1 0 1 1 1 1 * 0 1 0 0 0 0 1 1 5 0
0 0 * 0 1 0 0 0 1 1 1 0 0 0 1 * 0 1 0 0 1 0 1 1 0 0 1 0 * 0 1 0 0 1
1 1 1 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 0 1 0 1 1 1 0 0 1 0 1 0 1 0 1 0
1 1 0 1 1 0 1 1 0 1 1 1 1 1 0 0 1 0 1 1 1* 0 0 0 1 1 1 0 1 1 0 0 0
* 0 1 1 0 0 1 1 1 1 0 0 1 * 0 1 1 0 1 0 1 1 1 0 1 0 * 0 1 1 0 1 1 1
1 1 0 1 1 1 0 0 1 1 1 0 1 1 1 0 0 1 0 1 1 1 1 0 1 1 1 0 1 0 1 1 1 1
0 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1
__________________________________________________________________________
An example of the code converter F to perform the above-mentioned
operation shown in FIG. 10 comprises a shift register 21 shifting
signals x and y applied from terminals 20-1 and 20-2 respectively,
a conversion table 22 formed by a semipermanent memory by way of
example, and a modifier 23 modifying the output of the conversion
table 22 by the use of the shifted information from the shift
register 21.
As mentioned above, the output of the code converter F for one of
the phase-modulated waves becomes codes each indicative of a phase
difference between the input phase-modulated wave and either one of
the two reference carrier waves. If it is assumed that each of the
output codes of the code converter F is formed by eight bits of
binary information, one complete phase cycle 360.degree. can be
represented by 256 steps. Accordingly, each of the quantum phase
positions is precisely indicated by the use of a minimum value
360.degree./256 (.apprxeq. 14.degree.). In a case where the input
phase-modulated wave has eight quantum phase positions, the
contents of the eight bits of binary information vary for each
signal element by a value equal to an integer multiple of a unit
quantum phase 45.degree. except the combination of polarities MMM
of three channels as shown in FIG. 9. Moreover, a phase difference
between adjacent two signal elements effectively varies in
accordance with a frequency difference between the input
phase-modulated wave and the two reference carrier waves.
Accordingly, this phase difference .PHI..sub.i can be indicated as
follows in a case of eight quantum phases.
.PHI..sub.i = K..pi./4 + .theta..sub.i = (K + n).pi./4 +
(.theta..sub.i - n..pi./4)
where
K: an integer 0. 1, 2, 3, 4, 5, 6 or 7 determined in accordance
with the principle shown in FIG. 9;
.theta..sub.i : a phase difference between the phase-modulated wave
and the two reference carrier waves; and
n: an integer determined so as to make a value (.theta..sub.i
-n..pi./4) less than the unit phase .pi./4. Accordingly, the phase
difference .theta..sub.i can be indicated by the use of a value
less than the unit phase .pi./4. Since an angle less than the unit
phase .pi./4 can be indicated by lower value five bits in a pure
binary code, the drift of the phase can be detected from the lower
value five bits while a shift value between any two of the eight
quantum phase positions and equal to an integer multiple of the
unit phase .pi./4 can be indicated by the upper value three
bits.
With reference to FIG. 11, an example of the code converter G will
be described. In FIG. 11, a signal e.sub.4.sup.8 shows that this
signal e consists of five digits from a fourth digit to an eight
digit by way of example. The input of this code converter G applied
from the code converter F is shown as a signal a.sub.1.sup.8 and
applied to a cascade arrangement of a subtracter S.sub.1, a code
converter C.sub.1 and an accumulator I.sub.1. This cascade
arrangement is smoothing means for compensating the above-mentioned
phase fluctuation less than the unit phase .pi./4. The accumulator
I.sub.1 performs an integration operation as mentioned above, and
digits b.sub.4.sup.8 from output digits b.sub.1.sup.11 of this
accumulator I.sub.1 are fed back to the subtracter S.sub.1, in
which the digits b.sub.4.sup.8 are subtracted from the digits
a.sub.1.sup.5. Digits b.sub.1.sup.3 and digits b.sub.9.sup.11 are
neglected without feedback to the subtracter S.sub.1. However, the
digits b.sub.1.sup.3 are shifted by three digits to higher digits
so that the feed back value is multiplied by one-eighth. As the
subtraction of the digits b.sub.4.sup.8 from the digits
a.sub.1.sup.5 at the subtracter S.sub.1, an error c.sub.1.sup.5
from a desired value of compensation is obtained from the
subtracter S.sub.1 as a positive value since the digits
a.sub.1.sup.8 show only positive values. However, if negative
digits are desirable to raise the convergent speed of the
compensated output b.sub.1.sup.11, the digits c.sub.1.sup.5 are
converted to negative digits at the code converter C.sub.1. If it
is assumed that the digits c.sub.1.sup.5 are indicated by a pure
binary code and the error shown by the digits c.sub.1.sup.5
increases, the digits c.sub.1.sup.5 vary from a state "0 0 0 0 0"
to a state "1 1 1 1 1" and then restores to the state "0 0 0 0 0".
In this case, the convergent speed of the output digits
b.sub.1.sup.11 becomes higher in a case where a range from a state
"0 0 0 0 0" to a state "0 1 1 1 1" is positive while a range from a
state "1 0 0 0 0" to a state "1 1 1 1" is negative. Accordingly, if
the digits c.sub.1.sup.5 are included in the range from the state
"0 0 0 0 0" to the state "0 1 1 1 1", the digits c.sub.1.sup.5 are
applied to the accumulator I.sub.1 without code-conversion in the
code-conversion in the code converter C.sub.1. In this case, the
accumulator I.sub.1 successively adds the error signals
(c.sub.1.sup.5) until convergence. However, if the digits
c.sub.1.sup.5 exceed the state "1 0 0 0 0", the digits
c.sub.1.sup.5 are converted to a code which corresponds to a sum of
the digits c.sub.1.sup.5 and a number "2016" indicated by a decimal
representation. In other words, while the digits c.sub.1.sup.5 more
than the states "1 0 0 0 0" correspond to numbers sixteen to
thirty-one indicated by a decimal representation, the digits
c.sub.1.sup.5 are converted to any of numbers minus 16 to minus 1.
To perform this operation, since the accumulator I.sub.i is
designed so as to have eleven bits of code configuration,
complements for the full range (i.e.; 2048 of decimal
representation) of the 11 bits of information are produced in the
code converter C.sub.1 if the error is negative. The 11 bits of
code configuration at the accumulator I.sub.1 consists of eight
bits covering 2.pi. radians and three bits for shifting by three
bits as feed back. Accordingly, if the error is a number "31", this
error is converted at the code converter C.sub.1 to a number 31 +
2016 = 2047. In this case, "1" is subtracted from the contents of
the accumulator I.sub.1. As mentioned above, the contents of the
accumulator I.sub.1 is accumulated in the positive direction until
a value + 15 of the error and in the negative direction until a
value - 16 of the error. Accordingly, phase error included in the
output of the code converter F is effectively compensated in the
compensation means comprising the circuits S.sub.1, C.sub.1 and
I.sub.1.
Since the reference carrier generator D is provided independently
against the input phase-modulated wave, the reference carrier wave
and the input phase-modulated wave have usually a frequency
difference df. In this case, the above mentioned phase difference
.PHI..sub.i drifts in a speed 2.pi..df.t. If the phase difference
.PHI..sub.i increases as mentioned above, the above mentioned
compensation means cannot compensate the error since the
compensation operation of the compensation means is delayed as
shown in FIG. 12. If the drift is negligible in comparison with the
unit phase .pi./4, it is not necessary to compensate this drift.
However, if the frequencies of the reference carrier wave and the
input phase-modulated wave are incorrect, the drift must be
compensated. A cascade arrangement comprising a subtractor S.sub.2,
a code converter C.sub.2, an accumulator I.sub.2 and a code
converter C.sub.3 is means for compensating this drift. The
subtractor S.sub.2, the code converter C.sub.2 and the accumulator
I.sub.2 .sub.forms compensating means similar to the cascade
arrangement of the circuits S.sub.1, C.sub.1 and I.sub.2 mentioned
above to compensate a drift component in the digits c.sub.1.sup.5.
In this case, however, the code converter C.sub.2 produces
complements for a range 256 different from the range of the code
converter C.sub.1. In other words, since the output e.sub.1.sup.8
of the accumulator I.sub.2 is formed by eight bits and the full
range of this eight bits corresponds to the number 256, the output
g.sub.1.sup.8 of the subtracter S.sub.2 becomes a number "31 + 224
= 255" in a case where the output f.sub.1.sup.5 is equal to a
number 31. The compensated output e.sub.4.sup.8 is applied to a
code converter C.sub.3, in which the digits e.sub.4.sup.8 are
converted to negative information so that the digits e.sub.4.sup.8
are subtracted from the digits b.sub.4.sup.11 at an adder A.sub.1
if the direction of the drift is negative. For this purpose, a
number "224" is added to the digits e.sub.4.sup.8 at the converter
C.sub.2 similarly to the converter C.sub.2 if the digits
e.sub.4.sup.8 are included in a range from 16 to 31.
As mentioned above, the digits b.sub.4.sup.11 obtained after normal
compensation operation by the circuits S.sub.1, C.sub.1 and I.sub.1
and the digits h.sub.1.sup.8 obtained after drift-compensation
operation by the circuits S.sub.2, C.sub.2, I.sub.2 and C.sub.3 are
added to each other at the adder A.sub.1, so that phase-drift and
phase-error caused by the reference carrier wave generated
independently to the input phase-modulated wave can be detected
completely without no delay by the use of compensation technique
mentioned above. It is very difficult to perform digitally in a
high precise manner this detection operation of phase-error by an
automatic phase control circuit having a feed back loop if the
number of digit is small.
The above-mentioned correcting digits i.sub.1.sup.8 obtained from
the adder A.sub.1 correctly indicates phase error. Accordingly, the
phase error and phase drift included in the digits a.sub.1.sup.8 is
eliminated by subtracting the correcting digits i.sub.1.sup.8 from
the input digits a.sub.1.sup.8 at a subtracter S.sub.3.
However, noise included in the input phase-modulated wave causes
slight jitter at each quantum phase position. Since the digits
j.sub.5.sup.8 and the polarity combinations of three bits included
in a signal element of the phase-modulated wave are shown in Table
4, the jitter caused by the noise is eliminated by adding digits
R.sub.1 to the digits j.sub.5.sup.8 at an adder A.sub.2 so as to
perform addition of a value .pi./8 and to produce digits
l.sub.2.sup.4 shown in Table 4.
TABLE
4 Polarity j.sub.8 j.sub.7 j.sub.6 j.sub.5 l.sub.4 l.sub.3 l.sub.2
l.sub.1
__________________________________________________________________________
combinations 0 0 0 M M M 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 M M S 0 0
1 1 0 0 1 1 0 1 0 0 0 1 0 0 M S S 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 M
S M 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 0 S S M 1 0 0 1 1 0 0 1 1 0 1 0 1
0 1 0 S S S 1 0 1 1 1 0 1 1 1 1 0 0 1 1 0 0 S M S 1 1 0 1 1 1 0 1 1
1 1 0 1 1 1 0 S M M 1 1 1 1 1 1 1 1 0 0 0 0
__________________________________________________________________________
a delay circuit DEL is provided so that output digits m.sub.3.sup.1
indicate an immediately preceding signal element. Accordingly, when
the digit m.sub.3.sup.1 is subtracted from digits l.sub.2.sup.4 at
a subtracter S.sub.4, differential phase modulation component is
eliminated, so that digits n.sub.1.sup.3 represent a
fixed-reference phase-modulated signal.
Since the digits n.sub.1.sup.3 are pure binary codes while tee
phase-modulation of the input differential-phase modulated wave is
performed by Gray code, the digits n.sub.1.sup.3 are converted to
Gray code to obtain an correct output.
If a plurality of phase-modulated waves are applied to the input
terminal A, the accumulators I.sub.1 and I.sub.2 and the delay
circuit DEL must be added more circuits in proportion to the
increase of the number of the phase-modulated waves in the code
converter G.
The above mentioned example mentioned with reference to FIGS. 8, 10
and 11 can be also applied to demodulate a phase-modulated wave or
waves having 2.sup.n quantum phase positions for transmitting
n-bits of binary information by each signal element as well as the
phase-modulated wave of eight-quantum phase. Moreover, if a
fixed-reference phase modulated wave or waves is/are to be
demodulated, the delay circuit DEL and the subtracter S.sub.4 may
be eliminated so that the output of the adder A.sub.2 is directly
applied to the code converter C.sub.4.
* * * * *