Multimode Counting Device

Abstract

A multimode counting device that utilizes number incrementing and number decrementing signals to change the value of a stored number. The counting device includes a storage register and switching or gating circuitry that causes the device to switch between a first mode of operation for altering a stored number having a positive polarity and a second mode of operation for altering a stored number having a negative polarity. The device also includes additional gating circuitry responsive to the stored number and to signals in transmission to the storage register to initiate a change in the operating mode when the stored number is unity and a signal that will cause that number to become zero is in transmission to that register instead of waiting until the stored number actually reaches zero.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

Electronic counting devices.

2. Brief Description of the Prior Art

Multimode counting devices are known. Any device capable of utilizing number incrementing and number decrementing signals to change the value of a stored number that can have either a positive or a negative polarity must be constructed to operate in two modes. That is, a number incrementing signal or signal that will cause the actual value of the stored number to be increased must increase the magnitude, or absolute value of the stored number when the stored number has a positive polarity, but it must decrease the magnitude of the stored number when that number has a negative polarity. Similarly, a number decrementing signal, or signal that decreases the actual value of the stored number, must decrease the magnitude of that number when the stored number has a positive polarity, but it must increase the magnitude of that number when the stored number has a negative polarity.

Conventional multimode counting devices include a storage register, means for transmitting number changing signals to the storage register, and means for switching the operation of the counting device from one mode to another. The storage register is constructed to provide an output indicating the value of the stored number. When the value of the stored number is zero, the storage register provides an output that enables the mode switching means to respond to the next number changing signal received by the counting device and change the operating mode of the device accordingly. If this next received number changing signal is a number incrementing signal, the stored number will have a positive polarity, and the mode determining apparatus provides an output that will cause the counting device to operate in a first mode for changing positive polarity numbers. Similarly, if this next received number changing signal is a number decrementing signal, the stored number will have a negative polarity and the mode determining apparatus provides an output that will cause the counting device to operate in a second mode for changing negative polarity numbers.

In designing a counting and number storing device, it is desirable to maximize the rate at which the device can receive number changing signals. The rate at which signals can be received by the above-described device is limited by the fact that a first signal must propagate to the storage register, the value of the number stored in the storage register must be changed in response to this received number changing signal, the storage register must produce an output indicating the value of the stored number, and this output must propagate to and enable or activate the mode switching means, before a second number changing signal can be received by the counting and number storing device. If signals are received at a faster rate, the mode determining means would not be ready to respond to the signal received by the counting device immediately following the number changing signal that causes the value of the stored number to be zero and an error will occur.

SUMMARY OF THE INVENTION

The subject invention comprises a counting and number storing device that can receive number changing signals at a faster rate than can the prior art counters because it is constructed to produce a signal that enables mode determining means to switch the mode of operation at a time when it is known that the stored number will have a zero value, but before that zero value is actually obtained. In addition to mode determining means, the device includes number storing means, means for receiving number changing signals and transmitting those signals to the number storing means, and means for providing a count direction signal that indicates whether a number changing signal in transmission to the number storing means will cause the magnitude of the stored number to be incremented or decremented.

The number storing means includes gating means responsive to the value of the stored number and the count direction signals for providing an output signal that enables the mode determining means to change the operating mode of the counting and number storing device. The gating means is also connected to receive number changing signals in transmission to the number storing means. An enabling signal output is provided when the gating means receives signals indicating that the magnitude of the stored number is unity and that the next number changing signal to be received by the number storing means will decrement the magnitude of the stored number. This enabling signal allows the mode determining means to receive and respond to the next number changing signal received by the counting and number storing device. Since the number changing signal that will cause the magnitude of the stored number to be zero is the signal that caused the enabling signal to be transmitted to the mode determining means, this next number changing signal received by the device will be the signal that will change the magnitude of the stored number from zero to either plus or minus unity. The mode determining means receives and responds to this signal, and provides an output that will cause the device to operate in a first mode for changing a positive polarity number if it is a number incrementing signal, and provides an output that will cause the device to operate in a second mode for changing a negative polarity number if it is a number decrementing signal.

Since an enabling signal is provided to the mode determining means before the value of the stored number reaches zero, number changing signals can be received by the counting device of this invention at a faster rate than they can be received by the prior art counting devices. There is no need for a first number changing signal to be received by the number storing means and change the value of that stored number before a second number changing signal can be received by the subject counting and number storing device. It is only necessary to determine that a number changing signal has been received by the counting and number storing device that will cause the stored number to have a zero value when the number storing means of this device receive and respond to that signal.

To insure that the number changing signal received and used by the enabled mode determining means to determine the operating mode of the counting device is actually the number changing signal that will change the value of the stored number from zero, the gating means for transmitting an enabling signal to the mode determining means is connected to receive number changing signals being transmitted to the number storing means at a point downstream from the point at which the mode determining means receives those signals. The gating means is constructed to provide an enabling signal only when the number changing signal that will cause the stored number to have a zero value passes this downstream position. This prevents the premature transmission of an enabling signal to the mode determining means that would allow the mode determining means to receive the number changing signal that will cause the stored number to have a zero value instead of the number changing signal that will cause the stored number to change from zero to either plus or minus unity.

BRIEF DESCRIPTION OF THE DRAWINGS

Further objects, features and advantages of this invention, which is defined by the appended claims, will become apparent from a consideration of the following description, and the accompanying drawing in which:

The FIGURE is a circuit diagram of one embodiment of the multimode counting and number storing device in this invention.

DETAILED DESCRIPTION OF THE DRAWING

The FIGURE illustrates a multimode counting and number storing device 10 that includes number storing means 12, means 14 for receiving number changing signals and for transmitting those signals to the number storing means 12, and means 16 for determining the operating mode of the device 10. The device 10 also includes gating and storing means 18 that provide count direction signals that indicate whether each number changing signal in transmission to the number storing means 12 will increment or decrement the magnitude of the stored number.

The number storing means 12 includes four conventional decade storage registers 20, 22, 24, and 26. Each register is constructed to store a decimal digit of value 0-9 in a binary code form. Each register includes a terminal labelled "CK" for receiving signals hereinafter referred to as clock signals. The value of the digit stored in a register is changed by each clock signal received by that register. All clock signals transmitted to the registers 20-26 are identical. The direction in which a stored digit is changed is determined by a count direction signal transmitted to the storage registers along line 28 and received by those registers at terminals labelled "MC". Gating and storing means 18 provides either a first or a second count direction signal, depending on the nature of the number changing signal received by the device 10 and the polarity of the stored number. A first count direction signal will cause the value of the stored digit to be increased by the next received clock signal. A second count direction signal will cause the number stored by a decimal register to be decreased upon the receipt of the next clock signal. It is a characteristic of the decade registers 20-26 that a count direction signal must be received a predetermined amount of time before a clock signal in order to qualify those registers to respond to the clock signal in a proper manner.

Registers 20, 22, 24, and 26 stored progressively more significant digits. That is, the least significant digit is stored in register 20, which is thus constructed to receive each clock signal transmitted to the storing means 12. Signals transmitted along line 30 to the storing means 12 are placed in proper form for reception by register 20 by an inverter 32. Registers 22, 24, and 26 do not receive every clock signal transmitted to the number storing apparatus since they store more significant digits. AND gates 34, 36, and 38 control the transmission of a clock signal to these registers. Each of these AND gates will transmit a signal to its associated decade register only upon the receipt of a clock signal and signals from the terminals labelled "U/D" of each register storing a less significant digit.

Each register includes gating means responsive to the value of the stored digit and to the count direction signals for controlling the transmission of signals from the "U/D" terminal. An output signal is provided from the "U/D" terminal of a register only when the digit 9 is stored in that register and a count direction signal is received that will cause the next clock signal to increment the value of the stored number, and when the digit 0 is stored in that register and a count direction signal is received that will cause the next clock signal to decrement the value of the stored number.

A gate such as gate 36 controlling the transmission of clock signals to the register 24 will transmit a clock signal to that register only upon the receipt of a clock signal and output signals from the "U/D" terminal registers 20 and 22. This insures that a clock signal will change only the appropriate digits of a stored number. For example, suppose the magnitude of the stored number were 2,798 with the digits 2, 7, 9, and 8 stored in the registers 26, 24, 22, and 20, respectively. The receipt of a count direction signal directing the magnitude of the stored number to be increased and a clock signal would change only the digit in register 20 and change the magnitude of the stored number to 2,799. However, the receipt of another count direction signal directing the magnitude of the stored number to be increased would cause registers 20 and 22 to provide output signals from their "U/D" terminals and qualify gates 34 and 36, respectively, so that the next clock signal would change the digits stored in registers 20, 22, and 24 to give the stored number a magnitude of 2,800. Similarly, if the stored number had a magnitude of 1,901, and a count direction signal directing the magnitude of the stored number to be decreased were received, the next clock signal would change only the value of the digit in register 20 to give the stored number a magnitude of 1,900. However, another signal directing the magnitude to be decreased would cause registers 20 and 22 to provide output signals from their "U/D" terminals to gates 34 and 36 so that the next clock signal would change the digits stored in registers 20, 22, and 24 and give the stored number a magnitude of 1,899.

In addition to qualifying gates 34-38, the output signals from the "U/D" terminals of decimal registers 22, 24, and 26 are transmitted to a gating means 40 along lines 42, 44, and 46, respectively. The binary signals representing the digits stored in register 20 are transmitted to a One Detector 50 which is a known gating device responsive to the binary code of the stored digit and designed to provide an output signal along line 48 only when the digit stored in register 20 has a magnitude of unity. Gating means 40 thus receives signals along lines 42, 44, 46, and 48 when the magnitude of the stored number is unity and a count direction signal has been received by the storage registers 20, 22, 24, and 26 that directs those registers to decrease the magnitude of the stored number in response to the next received clock signal. Gating means 40 provides an output along line 52 only when signals are received on lines 42, 44, 46, 48, and 54, but no signal is received along line 56. The receipt of a signal along line 54 and lack os a signal along line 56 indicates that a clock signal is in transmission to the decimal storage registers and that it has passed a predetermined point 58 in its travel to those registers. Gating means 40 thus provides an output signal when it is determined that a clock signal is in transmission to the storage registers 20-46 that will cause the magnitude of the stored number to be zero, but before the stored number actually obtains that zero value.

The output signal from gating means 40 is transmitted to a flip-flop 60 which also receives clock signals along line 62. Flip-flop 60 provides an output that enables the mode determining apparatus 16 to respond to number changing signals received by the device 10 and change the mode of operation of that device if appropriate.

It is noted that gating means 40 could also provide an output signal along line 52 when the stored number has a magnitude of 9991 and a count direction signal that directs the magnitude of the stored number be increased by the next clock signal is received by the registers 20-26. But since this value is at the extreme of the count range, it can be considered an illegal state and ignored. It would be an obvious matter for one skilled in this art to design count registers in which the "U/D" terminals of the illustrated registers are replaced by two output terminals, a first for providing signals which qualify gates controlling the transmission of clock signals to registers containing more significant digits, and a second for providing output signals to gating means 40. An output signal would be transmitted from this second terminal only when the magnitude of the stored digit is zero and a count direction signal is received that directs the magnitude of the stored digit to be decremented by the next received clock signal. This modified design would thus eliminate the transmission of an erroneous signal from gating means 40 when the magnitude of the stored number reaches 9991. However, it would only extend the range of the counting device to 9999. Since this range extension is so slight, the illustrated decade storage registers are used in the preferred embodiment of this invention because they are commercially available and can be obtained at less cost than can the above-described modified registers.

The mode determining apparatus 16 receives number changing signals from lines 64 and 66 of the receiving and transmitting apparatus 14, and responds to these signals upon the receipt of an appropriate enabling signal from flip-flop 60. As has been described above, a signal is transmitted to the mode determining means 16 which enables those means to respond to the first number changing signal received by the device 10 after it receives a number changing signal that will cause the stored number to have a value of zero. This signal following the zero causing signal will cause the value of the stored number to have a value of either plus or minus unity. If it is a number incrementing signal which will give the stored number a positive polarity, the mode determining means responds to this signal by providing an output to gating means 18 that will cause the device 10 to operate in a first mode for changing a positive polarity number. Similarly, if the number changing signal following the zero causing signal is a number decrementing signal which will thus give the stored number a negative polarity, mode determining means 16 provides an output to gating means 18 that causes the device 10 to operate in a second mode for changing a negative polarity number.

In order to provide operation in the proper mode, AND gate 68 produces an output only upon receipt of a number changing signal and an enabling signal from flip-flop 60. AND gate 68 provides a high output along line 70 and a low output along line 72 upon receipt of a signal from flip-flop 60 and a number incrementing signal. It provides a low output along line 70 and a high output along line 72 upon receipt of a signal from flip-flop 60 and a number decrementing signal. The outputs from AND gate 68 are transmitted to a sign flip-flop 74. This flip-flop provides a high output along line 76 and a low output along line 78 in response to the receipt of a high output along line 70. It will continue to provide these outputs along lines 76 and 78 until a high signal is received along line 72 and a low signal is received along line 70, whereupon it will provide a low output along line 76 and high output along line 78. This output state will also be maintained by flip-flop 74 until further signals switching its output state are received.

The signals transmitted along lines 76 and 78 determine the nature of the count direction signal produced by gating means 18. Gating means 18 is constructed to provide first count direction signals that cause the magnitude of the stored number to be incremented, and second count direction signals that cause the magnitude of the stored number to be decremented. The particular output signal provided by gating means 18 is determined by the number changing and count direction signals received by gating means 18. Gating means 18 stores received signals, provides an output determined by the signals received, and continues to provide that output until it receives either a subsequent count direction signal or a subsequent number changing signal that will cause the output of gating means 18 to be changed. When gating means 18 receives a high signal along line 76, it provides a first count direction signal in response to each number incrementing signal it receives and a second count direction signal in response to each number decrementing signal it receives. A high signal received along line 76 thus causes gating means 18 to operate in a first mode for changing the magnitude of a positive polarity number. When gating means 18 receives a high signal along line 78, it is constructed to provide a second count direction signal in response to each number incrementing signal it receives and a first count direction signal in response to each number decrementing signal it receives. A high signal transmitted along line 78 thus causes the gating means to operate in a second mode for changing the magnitude of a negative polarity number.

Number incrementing and number decrementing signals are received by the counting and number storing device 10 along lines 64 and 66, respectively. These signals are received by the transmitting apparatus 14 which generates a clock signal for each received number incrementing and number decrementing signal. The receiving and transmitting apparatus 14 includes delays 80 and 82 for receiving number incrementing and number decrementing signals, respectively. These delay devices delay the transmission of number changing signals to the gating means 18 sufficiently so that the mode determining means 16 will have time to receive each number changing signal and change the operating mode of the device 10 in the appropriate case before the number changing signal causing the mode shift is received by the gating means 18. Delays 80 and 82 thus prevent the production of an erroneous count direction indicating signal for the number changing signal that causes the device 10 to shift from one mode of operation to another. Signals from the delay device 80 and 82 are transmitted to an OR gate 84. OR gate 84 provides an output signal upon receipt of a signal from either delay 80 or delay 82. The output signals from OR gate 84 are all identical and will be referred to hereinafter as clock signals. The clock signal generated for a number incrementing signal is indistinguishable from that generated for a number decrementing signal.

Clock signals are transmitted from OR gate 84 to delays 86 and 88. In combination, these delays delay the transmission of a clock signal to allow sufficient time for the storage registers 20-26 to receive and respond to the count direction signal associated with the clock signal being delayed so that the clock signal will change the magnitude of the stored number in the appropriate direction upon receipt of the delayed clock signal. Delays 86 and 88 also delay the transmission of a clock signal sufficiently so that gating means 40 will receive a clock signal along line 56 and the signals from the registers 20 to 26 that indicate the state the storage registers will have upon receipt of that clock signal at substantially the same time. This insures that no clock signal other than the signal that will actually cause the stored number to have a value of unity can qualify gating means 40 and cause the transmission of an enabling signal to the mode determining means 16.

In order to prevent a long number changing signal from providing an enabling signal and then gating itself rather than the next following number changing signal into the mode determining means, it is necessary to determine that the zero causing clock signal has propagated past the point at which the mode determining means 16 receives number changing signals, before transmitting an enabling signal to those mode determining means. Gating means 40 thus only provides an output signal along line 52 when a clock signal is received along line 54, but no signal is received along line 56. Delay 88 separates the leading and trailing edges of a clock signal so that a signal will be received by gating means 40 along line 56 for a sufficient time during which no signal is received along line 54 to allow gating means 40 to respond to that condition.

In operation, the counting and number storing device 10 receives number incrementing and number decrementing signals along lines 64 and 66 respectively. The receiving and transmitting apparatus 14 produces an identical clock signal for each received number changing signal. Each number changing signal is transmitted to the gating means 18 which produces a count direction signal in accordance with the nature of the number changing signal and the polarity of the stored number. A count direction signal determines whether its associated clock signal will increment or decrement the magnitude of the stored number. Both the count direction signal and its associated clock signal are transmitted to the number storing means 12. The clock signal is delayed in transmission to allow sufficient time for the number storing means 12 to receive and respond to the count direction signal so that the magnitude of the stored number will be changed in the appropriate direction by the clock signal.

Gating means 40 provides an output when it is determined that the stored number has a magnitude of unity and a clock signal is in transmission to the storage registers 20-26 of the number storing means 12 that will cause the stored number to be zero. That is, storage registers 20-26 provide signal outputs to the gating means 40 along lines 42-48 when the magnitude of the stored number is unity, and when a count direction signal is received that will cause the registers to decrement the magnitude of the stored number upon receipt of the next clock signal. Gating means 40 also receives clock signals being transmitted to the number storing means 12. The transmission of clock signals to gating means 40 is delayed sufficiently so that the clock signal to be next received by the storage registers 20-26 is received by the gating means 40 along line 54 at substantially the same time that gating means 40 receives signals indicating the magnitude of the stored number and the direction the magnitude will be changed by the next received clock signal. Gating means 40 provide an output signal along line 52 when signals are received along lines 42-48 and 54, and no signal is received along line 56.

The clock signal that will cause the stored number to have a value of zero causes gating means 40 to provide an output signal that enables the mode determining means 16 to respond to the next number changing signal received by the device 10. This next signal is the signal that will change the value of the stored number from zero to either plus or minus unity. This signal, therefore, determines the polarity of the stored number and the operating mode of the device 10. To provide a change in the operating mode, the output from gating means 40 is transmitted to flip-flop 60 which transmits an enabling signal to AND gate 68 upon receipt of this signal and a clock signal along line 62. AND gate 68 in cooperation with flip-flop 74 determines the operating mode of the device 10. AND gate 68 provides an output only in response to the receipt of both a number changing signal and an enabling signal from flip-flop 60. Number changing signals can, therefore, be received by the device 10 at a rate selected so that an enabling signal produced by one number changing signal will be received by AND gate 68 at substantially the same time that that gate receives the next number changing signal.

The counting and number storing device thus is capable of receiving number changing signals at a faster rate than prior art devices because a first number changing signal need not be received by the storage registers 20-26 and change the magnitude of the stored number before the second number can be received by the counting device as is the case with the prior art devices. A first signal need only propagate past point 58 before a second number changing signal can be received by the counting and number storing device 10, and no error in sign will be able to occur.

Claims

Having thus described an embodiment of this invention, what is claimed is:

1. In a multimode counting and number storing system utilizing number changing signals to change the value of a stored number, said system including:

number storing means, said number storing means providing magnitude signals indicating the magnitude of the stored number;

means for transmitting number changing signals to said number storing means;

means for generating a count direction signal that indicates whether a number changing signal in transmission to said number storing means will cause the magnitude of said stored number to be incremented or decremented;

mode determining means for switching the mode of operation of said system between a first mode for altering a positive polarity number, and a second mode for altering a negative polarity number,

the improvement comprising:

enabling means responsive to said count direction signal and said magnitude signal for providing an output signal that enables said mode determining means to switch the operating mode of said system upon the receipt of signals indicating that said stored number has a magnitude of unity and that a signal that will cause said stored number to have a value of zero is in transmission to said number storing means, a change in the operating mode thereby being initiated at a time when it is determined that said stored number will have a value of zero, and before the stored number actually obtains said zero value.

2. The multimode system set forth in claim 1 in which said enabling means comprises gating means for transmitting said enabling output signal to said mode determining means upon the receipt of signals by said enabling means indicating that the magnitude of said stored number will be decremented by a signal in transmission to said number storing means and that the magnitude of said stored number is unity.

3. The multimode system set forth in claim 1 in which:

said means for generating count direction signals provides a direction signal for each number changing signal in transmission to said number storing means;

and in which said enabling means includes:

gating means connected to receive said count direction signals, and said number changing signals; and

means for delaying the transmission of at least one of said signals to said gating means so that each number changing signal and its associated direction signal will arrive at said gating means at substantially the same time to permit only a signal that will cause the stored number to have a zero value to cause said enabling means to transmit an enabling signal to said mode determining means.

4. The multimode system set forth in claim 3 in which:

said enabling gating means also receives said magnitude signals; and

said delay means delays the transmission of signals to said gating means so that a signal indicating the magnitude of said stored number to be unity, and the number changing signal that will change the stored number from unity both arrive at said gating means at substantially the same time to prevent an erroneous transmission of an enabling signal.

5. The multimode counting and number storage device set forth in claim 1 in which:

said mode determining means receives number changing signals from said transmitting means and enabling signals from said enabling means, and provides an output that causes the said system to operate when enabled by an enabling signal that is in accordance with a received number changing signal;

said enabling means includes gating means connected to receive signals from said transmitting means at a position downstream from the position at which said mode determining means receives signals from said transmitting means; and

said enabling gating means transmits an enabling signal only when no signal is received from said downstream position, said enabling means thereby preventing said mode determining means from responding to any number changing signal that will cause said stored number to have a zero value and causing said system to operate in a mode determined by said zero causing signal instead by the number changing signal following said zero causing signal.

6. A method of determining the proper counting mode for changing a stored number of a particular polarity in response to number changing signals comprising the steps of:

transmitting number changing signals in a sequence to a number storing means constructed to change the value of the stored number in response to said received number changing signals;

generating signals indicating the magnitude of the stored number;

generating a count direction signal for each number changing signal in transmission to the said storing means that indicates whether the number changing signal will cause the magnitude of the stored number to be incremented or decremented;

initiating the generation of a mode determining signal when the magnitude of the stored number is unity and a number changing signal is in transmission to said storing means that will cause the magnitude of the stored number to be zero; and

generating said mode determining signal in accordance with the number changing signal immediately following the number changing signal that will cause the value of the stored number to be zero, said mode determining signal causing counting to be performed in a first mode for altering a positive polarity number when said following signal is a number incrementing signal and causing counting to be performed in a second mode for altering a negative polarity number when said following signal is a number decrementing signal.