Micro-program Control System

Abstract

A micro-program control system for computing apparatus provides a time shared concurrent utilization of a fixed, or semi-fixed memory containing a plurality of micro-programs. Micro-instructions of each micro-program are read out in repetitive, sequential manner from the memory and entered into control registers associated with the respective micro-programs. During the time interval in which a micro-instruction of one micro-program is read out, executed and the next address for that micro-program determined, a micro-instruction for another micro-program is read from the memory for implementation. Both the utility of the memory, and the speed of the overall data processing, are thereby improved.

Description

DISCLOSURE OF THE INVENTION

This invention relates to computing systems and, more specifically, to a micro-program control system for use in information processing arrangements.

A micro-program control system refers to a class of systems wherein control of arithmetic, logic, or other operations performed by an information processing system is implemented by micro-programs, each comprising different sequences of basic micro-operations. That is, micro-instructions are stored in a fixed or semi-fixed memory for subsequent read out and execution in accordance with the respective microprograms. Such a control system has a number of advantages, e.g., it is simple in arrangement and fabrication, and is readily susceptible to change in design. However, when compared with a wired logic control system formed solely of electronic logic circuitry, a micro-program control system suffers the following drawbacks:

1. Where the sequence of control is subject to change, that is where a conditional jump or transfer is selectively effected depending upon the result of previous arithmetic operations, the conditional jump of a microprogram requires a relatively prolonged period of time for complete execution. Thus, at such times, micro-program control systems exhibit low control efficiency, i.e., they slow down a computing process below the cycle time capability of the fixed or semi-fixed memory. High speed memory operation,attainable with recent semiconductor integrated circuit development and associated technologies, cannot therefore be efficiently utilized.

2. An appreciable storage capacity is required for a typical memory which stores micro-programs. Should an increased demand be placed upon the performance of such micro-programs, as to perform complex operations by utilizing a micro-program requiring a great number of micro-instructions, even greater fixed or semi-fixed memory capacity would be necessary. The micro-program memory would then become a major contributor to the total cost of a computing system, and this may not be economically realistic.

It is therefore an object of this invention to provide a micro-program control system which substantially improves the utilization of a fixed or semi-fixed memory which stores micro-programs, and which thus improves control efficiency.

It is another object of the invention to provide a micro-program control system which permits relatively efficient utilization of a memory containing a micro-program when a conditional jump or transfer is to be effected.

It is a further object of the invention to provide a micro-program control system wherein a memory, capable of storing a great number of micro-programs, is operated on a relatively inexpensive basis in relation to the computational efficiency effected.

It is still another object of the invention to provide a micro-program control system which effectively uses the high speed performance of a semi-fixed memory formed by semiconductor integrated circuit techniques.

It is still a further object of the invention to provide a micro-program control system in which a fixed or semi-fixed memory, storing micro-programs, is utilized for simultaneously implementing and using a plurality of micro-programs.

The above and other objects of the present invention as realized in a specific illustrative digital processing arrangement wherein a single fixed or semi-fixed memory stores a number of micro-programs which are selectively executed on a time division basis. In one embodiment of the present invention, read-out of the memory is successively effected for each of the plural micro-programs, at constant repetitive intervals, with the micro-instructions so read-out being executed individually. A sequence control circuit is provided to determine the next address to be interrogated in each micro-program from the result of the execution of prior micro-instructions. Thus, the sequence control circuit decides whether a jump or a sequential operation is to be performed next in a particular micro-program and, accordingly provides the address of the next micro-instruction to be read out. This next address is entered into the system to access the next stored micro-instruction in that particular micro-program at an appropriate time interval. In this manner, a single micro-program memory is shared for the concurrent execution of a plurality of stored micro-programs on a time division basis. Thus, while the individual microprograms are processed at the same rate as in prior art control systems, the utilization of the memory as a whole is improved in efficiently, thereby achieving the equivalent of high speed control.

The above and other objects, features and advantages of the invention will become apparent from the following description of an illustrative embodiment thereof with reference to the drawings, in which:

FIG. 1 is a schematic diagram illustrating a prior art micro-program control system;

FIG. 2 is a schematic diagram of the micro-program control system according to one embodiment of the present invention;

FIG. 3 is a block diagram showing an example of an arithmetic unit used in the system of FIG. 2,

FIG. 4 is a detailed wiring diagram showing an example of a sequence control unit used in the system of FIG. 2, and

FIG. 5 is a timing chart illustrating the operation of the micro-program control system of the invention. In the drawing, like reference numerical designations in different figures identify like structural elements.

Referring now to the drawing, and in particular to FIG. 1 thereof, there is shown a typical micro-program control system of the prior art. The system includes a fixed or semi-fixed memory 1 which stores micro-programs. A selected micro-instruction, stored at an address specified by an address register 2, is read from the memory 1 into a read-out or output register 3. The micro-instruction in the register 3 is transferred to an arithmetic unit 4 for execution, that is, to perform an arithmetic operation. The address information in the address register 2 is then supplied to an "add-one" circuit 5 to augment the original address by one. The updated address is then supplied to the address register 2 through an AND-gate 6 and an OR-gate 7. During a next memory 1 interrogation cycle, the information stored in the memory 1 at the original address plus one is read out. In this manner, micro-instructions located in the memory 1 at immediately following addresses can be sequentially accessed.

In addition to such a sequential read-out, the system is subject to a jump or transfer operation. To provide discrimination of one from the other of these modes of operation, there is provided an AND-gate 9 having a first input 8 and a second input 10. The first input 8 may be connected with the arithmetic unit 4 to receive a signal indicating whether the result of the arithmetic operation performed is positive, negative or zero. Alternatively, it may be connected with a particular register (not shown) associated with the system for detecting the state of a particular bit therein. The second input 10 is connected to the read-out register 3 to detect the presence of "jump" or "transfer" bit in this register.

When the conditions for a transfer are met, the AND-gate 9 produces a binary one output which is directly supplied to one input of an AND-gate 11 and to the other input of an AND-gate 6 after inversion. It will be seen that if the transfer condition is not met, the AND-gate 6 is opened to allow the passage of the output of the add-one circuit 5 to the OR-gate 7. Conversely, when the transfer condition is satisfied, the address stored in the output register 3 at that point in micro-program processing is fed through a terminal 12 to an AND-gate 13, or the instruction code of the instruction read out from a main memory to be executed and the content of the address register 2 in which the most significant bits are set to zero are supplied through a terminal 14 to AND-gate 15. This instruction code represents the address of a specified micro-program to be read out next. To select an instruction from either the terminal 12 or 14, a particular bit in the read-out register 3 is directly supplied via a terminal 16 to the second input of the AND-gate 15 and, after inversion, to the second input of AND-gate 13. An output from the selected AND-gate 15 or 13 is thus supplied to OR-gate 17 through AND-gate 11 which is opened when the transfer condition is met. Accordingly, the transfer address data is supplied to the address register 2.

The effectiveness of a micro-program control system is predicated upon its ability to perform the conditional transfer function as well as to executing a program through successive read-out of sequential addresses. Where a conditional transfer is involved, the address for the next micro-instruction to be read out remains undetermined until the result of an arithmetic operation is available, as mentioned above. A relatively prolonged period of time is therefore required until the address for the next micro-instruction is decided as a result of the execution of the preceding micro-instruction. Thus, execution of a micro-program sequence disadvantageously proceeds in a relatively slow manner, even when a micro-program memory capable of high speed operation is used.

By contrast, in the micro-program control system of the invention as illustrated in FIG. 2, information read from a memory 1 storing a number of micro-program is supplied to a plurality of arithmetic operation control units 4 at constant repetitive intervals, three such units 4a, 4b and 4c being shown in FIG. 2. To this end, a switching gate 18 is connected to the output of the memory 1, and a timing pulse signal from a pulse generator 19z is supplied to a ternary ring counter 19 so that successive cyclic gate signals may be obtained from three output terminals 19a, 19b and 19c of the counter to distribute information read out from the memory 1 to the arithmetic units 4a, 4b and 4c in a repeated sequence.

In response to the results of arithmetic operations performed in the arithmetic units 4, a sequence control unit 20 is operable to decide the next addresses to be accessed for the respective micro-programs, which addresses may be supplied through the address register 2 to the memory 1 in synchronism with the switching operation of the switching gate 18 so as to correspond with the first, second and third micro-programs, respectively.

Each of the arithmetic units 4a, 4b and 4c is not novel per se, but may be of any conventional arrangement. In the example shown, the three units are assumed to be of an identical construction, one of these units being shown in detail in FIG. 3. With reference to FIG. 3, information from two information buses 21 and 22 is supplied to an arithmetic circuit 24 in which basic logical operations such as addition, subtraction, multiplication, shift or the like are performed, and the computational result is supplied by the circuit 24 to a bus 23. A general purpose register 25 is provided and includes plural (for example, 16 individual registers, which are separately specified by register specifying circuits 26, 27 and 28. Read-out and write-in operations are performed between the register specified by the specifying circuit 26 and the bus 21 through gates 29 and 30, respectively. Similarly, read-out and write-in operations are performed between the register specified by the specifying circuit 27 and the bus 22 through gates 31 and 32, respectively, and information on the bus 23 is written into the register specified by the specifying circuit 28 through a gate 33.

A main memory is provided to store ordinary (MACRO) instructions and data. One such instruction stored in the main memory 34 is executed by performing a micro-program comprising a plurality of micro-instructions. When both gates 35 and 36 are open, information on the buses 21 and 22 is stored in an address register 37 and in a write-in or input register 38, respectively, for subsequently writing the content of the register 38 into the main memory 34 at the address specified by the address register. In addition, when both gates 35 and 39 are open, information at the address specified by the address register 37 are read through the gate 39 onto the bus 22. The control over the arithmetic circuit 24, specifying circuits 26, 27 and 28 and the gates 29, 30, 31, 32, 33, 35, 36 and 39 is effected by information (micro-instructions) stored in a control register 40 associated with each arithmetic unit. The control register 40 is supplied with these micro-instructions read out from the memory 1 via the switching gate 18.

The bit arrangement of a micro-instruction, that is, the digital content stored in the control register 40, is shown in Table 1 and comprises forty bits. The first four bits of these represent by their combination the type of arithmetic operations (operation code) to be performed by the arithmetic circuit 24. Specifically, in Table 1, the designation NOP represents no operation; BAD the binary addition of information on the buses 21 and 22 and supply of the addition result to the bus 23, BSU the binary subtraction between information on the buses 21 and 22 and supply of the result to the bus 23; AND making a logical product of information on the buses 21 and 22 and supply of the result to the bus 23; HAD performing a half-add (exclusive OR) operation in information and supply of the result to the bus 23; OR making a logical sum of the information and supply of its result to the bus 23; AD1, AD2 and AD4 the addition of 1, 2 and 4, respectively to the information on the bus 21 and supply of the result to the bus 23; SB1, SB2 and SB4 the subtraction of 1, 2 and 4, respectively, from the information on the bus 25 and supply of the result to the bus 23; and SFT a ring shift, LSFT a shift to the left, and RSFT a shift to the right. The four bits in the portion 41A of the control register 40 which represent the type of arithmetic operations are supplied through lead wires 42 to the arithmetic circuits 24 to condition it for the arithmetic operation specified.-------------------------------- -------------------------------------------TABLE -1 Type of Register Arith. specifying operation Gates circuits Test Address (26) (27) (28) Bit No. 1 - 4 5 - 13 14-17 18-21 22-25 26-28 29-40 No. of bits 4 9 4 4 4 3 12 bit controlled 0 NOP No. gate No. 0 NOP 1 BAD 5 35 1 UCJMP 2 BSU 6 39 2 ALLO 3 AND AND 7 36 3 + 4 HAD 8 43 4 - 5 OR 9 29 5 OVF 6 AD1 10 30 6 carry 7 SB1 11 31 8 AD2 12 32 9 SB2 13 33 10 AD4 11 SB4 12 SFT 13 LSFT 14 RSFT 15 _________________________________________________________________________ _

a gate controlling portion 41B of the control register 40, which comprises nine bits from the fifth to thirteenth bit, is connected to control the gates 35, 39,36, 43,29,30,31,32 and 33 in the sequence of bit number, respectively, each bit separately controlling a different gate. A gate 43 is provided (FIG. 4) to determine whether the address stored in the address portion of the control register 40 or a part of the information stored in the main memory 34 is to be used for a conditional transfer.

The bits from 14 to twenty-fifth bit, or those contained in a register specifying portion 41C of the control register 40, are used to specify a selected one of the 16 individual registers contained in the general purpose register 25. The first four bits in the specifying portion 41C (those numbered 14 to 17) are supplied in combination to the specifying circuit 26 to specify one of the 16 registers. The next four bits (numbered 18 to 21) are supplied to the specifying circuits 27 to specify another register, and the last four bits (numbered 22 to 25) are supplied to the specifying circuit 28 to specify a still different one of the 16 registers.

The three bits numbered 26 to 28 in the control register 40 represent a test portion 41D thereof, the combination of these three bits providing a transfer condition. When this transfer condition coincides with the result of an arithmetic operation performed in the arithmetic circuit 24, the transfer condition is satisfied and a transfer operation is effected. In the example shown, there are given six different transfer conditions. NOP never satisfies such a condition, so that no transfer is effected, UCJMP represents the case where the condition is always satisfied, and ALLO a transfer operation when the result of an arithmetic operation comprises bits which are all zeros. The symbol "+ " represents a transfer operation when the result of an arithmetic operation has a positive polarity, and the symbol "- " a transfer operation when the result of an arithmetic operation has a negative polarity. OVF represents a transfer operation when there is as overflow, and "carry" a transfer operation when there is a carry from the number of bits allocated to one word. The remaining 12 bits numbered 29 to 40 of the control register 40 constitute an address portion 41E which represents the address to which the transfer is to be continued.

Illustrative detail for the sequence control unit 20 of FIG. 2 is shown in FIG. 4. The control unit 20 specifies the next address when a conditional transfer is or is not effected depending upon the transfer condition in the read-out (control register) and upon the result of arithmetic operations by a respective arithmetic units 4a, 4b, or 4c controlled by stored micro-instructions. The sequence control unit 20 comprises three sequence control circuits 44a, 44b, and 44c, of an identical construction, arranged in a manner corresponding to the respective arithmetic units 4a, 4b and 4c. It should be noted that a reference character comprising a number followed by a letter such as a, b or c represents a component associated with different arithmetic unit 4a, 4b or 4c, respectively. Each circuit includes a register and is operable to supply the address register 2 with either the address to which transfer is to be continued, or a sequential address.

In each of the sequence control circuits 44a, 44b and 44c, information from the common add-one circuit 5 is supplied to sequential addressing registers 46a, 46b and 46c through AND-gates 45a, 45b and 45c, respectively. These registers are connected through AND-gates 47a, 47b and 47c and OR-gate 48a, 48b and 48c, respectively, and through a common OR-gate 49 with the address register 2.

The output from the address portion 41E of the respective control registers 40a, 40b and 40c associated with the arithmetic units 4a, 4b and 4c, respectively, are supplied to the terminals 12a, 12b and 12c, and thence through AND-gates 13a, 13b and 13c and OR-gates 17a, 17b and 17c, respectively, to AND-gates 50a, 50b and 50c, respectively. From the buses 22c, 22b and 22c associated with the respective arithmetic units 4a, 4b and 4c, the instruction code portion of the information thereon is supplied to the terminals 14a, 14b and 14c, respectively, and thence through AND-gates 15a, 15b and 15c to the OR-gates 17a, 17b and 17c, respectively. Gates 43a, 43b and 43c are controlled by the fourth bit in the gate portion 41B of the respective control registers 40a, 40b and 40c, and the output from these gates are directly applied to the other input of the AND-gates 15a, 15b and 15c and also applied, after inversion, to the AND-gates 13a, 13b and 13c.

Thus it will be understood that when gate 43a, for example, is opened, an instruction code (the instruction code of an instruction stored in the main memory 34a) is supplied from the bus 22a to the AND-gate 50a. On the other hand, when the gate 43a is closed, the content in the address portion 41E of the control register 40a is supplied to the AND-gate 50a.

A conditioning bit from the test portion 41D of the control register 40a is applied via a terminal 10a to one input of an AND-gate 9a, the other input of which receives an output from the arithmetic circuit 24a through a terminal 8a. The output of circuit 24a represents a particular status for the result of the arithmetic operation performed, that is, the status above in connection with the test portion 41D. When the arithmetic out-put coincides with the conditioning bit from the test portion 41D, i.e., when the transfer condition is met, the AND-gate 9a opens and its output is supplied to one input of the AND-gate 50a so that when a timing pulse, discussed later, is furnished to its other input, the AND-gate 50a is opened, thereby allowing either the content of the address portion 41E of the control register 40a or information on the bus 22a to be supplied through the AND-gate 50a to the address register 2. The inverted output of the AND-gate 9a is connected to one input of the AND-gate 47a, so that when the transfer condition is not satisfied, the content of the register 46a is supplied through this AND-gate 47a to the address register 2.

It will be appreciated that the sequence control circuits 44b and 44c are similar in construction and operation to the sequence control circuit 44a. Thus, these circuits include the AND-gates 9b and 9c which, like the AND-gate 9aare supplied with the output from the corresponding test portion and the output from the respective arithmetic circuits which represents a particular status for the result of an arithmetic operations performed thereby. The output of the AND-gate 9b and 9c are directly applied to the AND-gates 50b, 50c, and also applied, after inversion, to the AND-gates 47b, 47c.

Output pulses repeatedly obtaining at a given interval from a terminal 19a of the ring counter 19 are supplied to the AND-gates 45b, 47c and 50c. The output pulses from the counter terminal 19b are supplied to the AND-gates 45c, 47a and 50aand output pulses from the terminal 19c are supplied to the AND-gates 45a, 47b and 50b. These AND-gates open only when timing pulses from the terminals 19a, 19b and 19c are supplied thereto. As shown, in FIG. 2 and 4, the content of the address register 2 is adapted to be supplied to the micro-program memory 1, and to the add-one circuit 5.

The pulse generator 19z produces pulses at times t.sub.1, t.sub.2, t.sub.3 and so forth, as shown in FIG. 5A. The terminal 19a of the ring counter 19 provides pulses at times t.sub.1, t.sub.4, t.sub.7 and so on, as shown in FIG. 5B, and the terminals 19b and 19c provide pulses at times t.sub.2, t.sub.5, t.sub.8 and so on, and at times t.sub.3, t.sub.6, t.sub.9 and so on, respectively, as shown in FIGS. 5C and 5D. FIG. 5E depicts a microinstruction 51a.sub.1 for a first micro-program, having the bit arrangement set forth above, which is stored in the control register 40a at time t.sub.1, and which is read out at the time t.sub.2. The arithmetic circuit 14a operates in accordance with the content of this micro-instruction (such an operation being symbolic shown at 52a.sub.1 of FIG. 5F), and at the end of the clock period beginning at t.sub.2, the matter of whether or not the transfer condition (given by test register 40 portion 41D) is satisfied is determined. When the transfer condition is satisfied, the status of the fourth gate bit in the gate portion 41B of the micro-instruction 51a.sub.1 selectively conditions the gate 43a, thereby enabling the selected AND-gate 15a or 13a to pass the information on the bus 22a or the address information in the address portion 41E of the micro-instruction 51a.sub.1 therethrough and through the OR-gate 17a and AND-gate a to be stored in the address register 20.

It should be understood that when the information is transmitted through the AND-gate 15a, an instruction code has previously been read out onto the bus 22a from the memory 34. If the transfer condition is not met, the content of the register 46a is read out for storage in the address register 2. Such stored information for the address register 2 is shown at 53a.sub.p64pt.sub.1 in FIG. 5G. Further, at time t.sub.2, a micro-instruction 51b.sub.1 for the second micro-program is read out from the memory 1 into the control register 40b (FIG. 5H). It is noted that each register is arranged so that the information entered at its input side appears at its output side after a time delay of one clock period, this being effected by any conventional gating or shifting circuitry.

At time t.sub.3, the content 53a.sub.1 of the address register 2 is read out. A signal 54a.sub.1 which comprises the address 53a.sub.1 plus one (effected by the add-one circuit 5) is stored in the register 46a (FIG. 5I). Correspondingly, as a consequence of the arithmetic operation 52b.sub.1 (FIG. 5J) corresponding to execution of the micro-instruction 51b.sub.1 from the control register 40b, an address signal 53b.sub.1 from the AND-gate 50b or 47b is stored in the address register 2 at the end of the clock period beginning at t.sub.3. Also t.sub.3, a micro-instruction 51c.sub.1 of the third micro-program is read out from the memory 1 and stored in the control register 40c (FIG. 5K).

At the next clock time t.sub.4, the content 53b.sub.1 of the address register 2 is read out, augmented by one by the circuit 5, and the resulting signal 54b.sub.1 stored in the register 46b (FIG. 5L). Also during this interval, the control register 40c is read out. Depending upon the result of the corresponding arithmetic operation 52c.sub.1 (FIG. 5M), that is, depending upon whether or not the transfer condition is satisfied, signal 53c.sub.1 from either the AND-gate 50c or 47c is stored in the address register 2. While the above operations are being effected, the next micro-instruction 51a.sub.2 of the first micro-program is read out from the memory 1 and entered into the control register 40a (FIG. 5E).

During the following clock interval t.sub.5, as a result of the arithmetic operation 52a.sub.2 for the micro-instruction 51a.sub.2, the output 53a.sub.2 from either AND-gate 50a 47a is supplied to the address register 2 FIG. 5G). The digital word 53c.sub.1 is read out from the address register 2, and that information is supplemented by one in the manner discussed previously, with resulting signal being stored in the register 46c. Also, concurrently therewith, the next micro-instruction 51b.sub.2 of the second micro-program is read out from the memory 1 and entered into the control register 40b (FIG. 5H).

Similarly, at clock time t.sub.6 and as a result of the arithmetic operation symbolically shown at 52b.sub.2 for the micro-instruction 51b.sub.2 from the control register 40b, the output 53b.sub.2 from either AND-gate 50b or 47b is stored in the address register 2. The information 53a.sub.2 is read out from the address register 2, and after being increased by one, is stored in the register 46a as 54a.sub.2. Also during this clock interval, the next micro-instruction 51c.sub.2 of the third micro-program is read into the control register 40c. Such processing repeatedly continues in the above described manner.

Focusing on one micro-program, for example, the first micro-program, it will be seen that the micro-instruction 51a.sub.1 is read out at t.sub.1 (FIG. 5E), executed at t.sub.2 (52a.sub.1 of FIG. 5F), and the results of this execution checked to determine whether the transfer condition is satisfied. At clock time t.sub.3, the address 53a.sub.1, used to identify and read out the next micro-instruction 51a.sub.2 of a program sequence, is supplied to the address register 2. This next instruction is read-out from the memory 1 at the next clock time t.sub.4, and so on.

It is observed that even if the memory 1 has a rapid cycle time which corresponds to a single time interval e.g., t.sub.1 -t.sub.2 or the like, a further period of time from t.sub.2 to t.sub.4 is required in order to fully execute the micro-instruction. This relatively long interval is necessary to determine whether or not the transfer condition is met, and to thus determine the next address for execution. This means that the memory 1 cannot be efficiently utilized to read out the next micro-instruction 51a.sub.2 of one micro-program immediately at the end of the clock period beginning at t.sub.1. To the contrary, the memory 1 must be left inoperative during the time interval from time t.sub.2 to time t4. Such an inefficient mode of operation, employing only a single micro-program, has characterized prior art micro-program control systems. It will therefore be appreciated that an increase in the operational speed of the memory 1 does not result in a substantial improvement of the overall signal processing throughput rate.

However, in the micro-program control system according to the present invention, a plurality of micro-programs or, in the present example, the first, second and third microprograms, are controlled in a time sharing manner. When the micro-instruction 51a.sub.1 of the first micro-program has been executed, the next address is stored in the address register 2. During the subsequent period of time before the next micro-instruction 51a.sub.2 of that program sequence is read out, the micro-instruction 51B.sub.1 of the second micro-program is read, followed by the micro-instruction 51c.sub.1 of the third micro-program. Thus, when the micro-instruction 51b.sub.1 of the second micro-program is executed and before the next micro-instruction 51b.sub.2 is read out, the micro-instruction 51c.sub.1 of the third micro-program is read out. Subsequently, the second micro-instruction 51a.sub.2 of the first micro-program is read-out, and this process repeatedly continues in similar fashion. In this manner, the memory 1 always reads-out a micro-instruction for one or another of the first, second and third micro-programs during each clock cycle, thus achieving efficient memory utilization.

In addition, since the multiple utilization of the micro-program memory 1 is effected in a time sharing manner, with memory operation being repeated at a predetermined definite time interval, there is no need for a complex arrangement to check and obviate interruptions in the computing process, as is required for typical prior art multiple programming configurations. The present system can be readily operated under the direction of a relatively simple executive control arrangement.

While three multiplexed micro-programs were employed in the embodiment described above for purposes of illustration, any number more than one may be utilized. It will be appreciated that this number can be increased as the cycle time of the memory 1 becomes faster.

Also, the arithmetic units 4a, 4b and 4e, illustrated as having an identical construction, may in fact differ. These arithmetic units may be controlled by different bit arrangements in the control registers 40. Further, a single memory 34 may be used for all of the micro-programs. In addition, as is apparent from the above description of system operation with reference to FIG. 5, the arithmetic operations performed during execution of micro-instructions, as shown at 521.sub.1, 52b.sub.1, 52c.sub.1 3 52a.sub.2, 52b.sub.2 . . . , are effected in successively offset period of time, so that one arithmetic circuit 24 may be shared by a plurality of micro-programs in a time division manner. In this instance, registers such as general purpose registers 25 and control registers 40 may be separately provided for each of the micro-programs.

The above system arrangement is merely illustrative of the principles of the present invention, numerous variations and adaptations thereof will be readily apparent to those skilled in the art without departing from the spirit and scope of the present invention.

Claims

1. A micro-program control system for electronic computing apparatus for effecting data processing in time-shared fashion in accordance with a preselected number of micro-programs comprising: a memory having at least said preselected number of micro-programs stored therein, an address register, timing means for cyclically controlling said apparatus for said plural micro-programs, a plurality of output registers controlled by said timing means for storing micro-instructions for said respective micro-programs, read out from said memory at the memory addresses cyclically identified by the contents of said address register, first address updating means for providing a first next instruction address based on the memory address identified by the current contents of said address register, a plurality of additional registers for said respective micro-programs, gate means controlled by said timing means for loading said additional registers with the first next instruction addresses for said respective micro-programs, second address updating means for selectively providing in response to a micro-instruction stored in each of said output registers, a second next instruction address based on one of the prior processed micro-instructions and the instruction obtained as a result of previous data processing, and control gating means controlled by said timing means and a logical combination of the prior-processed micro-instruction and the result of data processing effected in accordance therewith for loading said address register with either of said first next instruction address and the

2. A micro-program control system as in claim 1 wherein said first address updating means adds a fixed increment to the current contents of said

3. A micro-program control system as in claim 1 further comprising arithmetic means controlled by the contents of an associated one of said output registers, and means responsive to signals characterizing said arithmetic means for selectively signaling the incidence of a program instruction transfer condition for a selected one of the stored micro-programs, said signaling means having the output thereof connected

4. A micro-program control system as in claim 1 further comprising plural arithmetic means, said output registers being respectively associated with said arithmetic means, each of said output registers having a first portion thereof connected to the corresponding arithmetic means for defining the functional operation performed thereby, a second portion thereof for selectively identifying a transfer operation, and a third portion thereof containing an address in said memory, said control gating means including logic means connected to each of said arithmetic means and its associated output register for selecting between said first and second

5. A micro-program control system as in claim 4 wherein the contents of said address portion of each of said output registers is supplied as an

6. A combination as in claim 5 further comprising additional memory means, and means for selectively connecting the contents of said additional

7. A combination as in claim 6 wherein said second address updating means comprises plural next address selecting circuit means each associated with a different micro-program, each next address selecting circuit means including first and second coincidence means for selectively passing said first next instruction address or said second next instruction address respectively, one of said first and second coincidence means being opened during a selected cyclically repeating time interval by said timing means, logic means for enabling a selected one of said first or second coincidence means responsive to the presence or absence of micro-instruction transfer requirement, means for supplying a selected second next instruction address to said second coincidence means, means for supplying said first next instruction address to said first

8. A combination as in claim 7 further comprising disjunctive logic means for connecting the outputs of said first and second coincidence means for each of said next address selecting circuit means with said address

9. A micro-program control system as in claim 1 wherein said timing means comprise a pulse generator, and plural stage ring counter means having a clock input thereof connected to said pulse generator, the outputs from the several stages of said ring counters means being distributed to said

10. A micro-program control system as in claim 4 further comprising switched gate means controlled by said timing means for selectively distributing the micro-instructions read out from said memory to said

11. A method for effecting micro-program control of electronic computing apparatus which includes a memory, an address register, an address updating circuit, plural arithmetic circuits and timing circuitry for cyclically subdividing the control of said computing apparatus into a plurality of clock phases depending upon the number of micro-programs to be simultaneously executed on a time shared basis, comprising the steps of reading out a micro-program instruction for a first one of said micro-programs being executed during each clock phase, effecting execution during that clock phase of an instruction for a second micro-program read from the memory during a preceding clock phase, and impressing a next address for a third one of the micro-programs in said address register during that clock phase, said address representing a selection between a sequential updating of the previous address for said third micro-program and a transfer for said third micro-program, said memory thereby being interrogated to read out a new micro-instruction during each clock phase.