U.S. patent number 3,678,198 [Application Number 04/250,119] was granted by the patent office on 1972-07-18 for circuit for generating a series of cipher pulses.
Invention is credited to Kurt Ehrat.
United States Patent |
3,678,198 |
Ehrat |
July 18, 1972 |
CIRCUIT FOR GENERATING A SERIES OF CIPHER PULSES
Abstract
15. A message transmission installation comprising at least two
stations each capable of acting as a transmitter and receiver, each
station comprising apparatus capable of acting as a transmitter and
receiver of information, a mixer, and a circuit for generating
reproducible series of code pulses having a long period, said
circuit comprising a binary counting chain having at least 20
members, connections connecting each of said members to a
respective mixer, a plurality of shift register elements
constituting a shift register chain, connections connecting each
mixer to a respective shift register element, to a previous shift
register element in the chain and to a switching distributor the
state of which is determined by a switching criterion, the
arrangement being such that the mixers mix the information content
of one counting member of the counting chain with the information
of one shift register element and this mixed information is
delivered to the next shift register element if the state of the
switching distributor is in accordance with the switching state of
the corresponding member of the counting chain, and that the
information of one shift register element is delivered to the next
shift register element unchanged if the state of the switching
distributor differs from the switching state of the corresponding
member of the counting chain.
Inventors: |
Ehrat; Kurt (Zurich,
CH) |
Family
ID: |
4182624 |
Appl.
No.: |
04/250,119 |
Filed: |
January 8, 1963 |
Foreign Application Priority Data
Current U.S.
Class: |
380/43; 380/265;
331/78 |
Current CPC
Class: |
H04L
9/0662 (20130101); G06F 7/584 (20130101); G06F
2207/583 (20130101); G06F 2207/581 (20130101) |
Current International
Class: |
G06F
7/58 (20060101); H04L 9/18 (20060101); H04L
9/22 (20060101); H04l 009/00 () |
Field of
Search: |
;178/22 ;331/78
;328/37 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Farley; Richard A.
Claims
What is claimed is:
1. A circuit for generating reproducible series of cipher pulses
having a long period, said circuit comprising a binary counting
chain having at least 20 members, connections connecting each of
said members to a respective mixer, a plurality of shift register
elements constituting a shift register chain, connections
connecting each mixer to a respective shift register element, to a
previous shift register element in the chain, and to a switching
distributor the state of which is determined by a switching
criterion, the arrangement being such that the mixers mix the
information content of one counting member of the counting chain
with the information of one shift register element and this mixed
information is delivered to the next shift register element if the
state of the switching distributor is in accordance with the
switching state of the corresponding member of the counting chain,
and that the information of one shift register element is delivered
to the next shift register element unchanged if the state of the
switching distributor differs from the switching state of the
corresponding member of the counting chain.
2. The circuit of claim 1, wherein said mixers are modulus 2
mixers.
3. The circuit of claim 1, wherein each mixer is composed of
substantially equal numbers of AND-gates and OR-gates.
4. A circuit for generating reproducible series of cipher pulses
having a long period, comprising at least 20 counting members
constituting a binary counting chain, at least 20 mixers each
connected to a respective counting member, a plurality of shift
register elements constituting together with the mixers a shift
register chain, the mixers and the shift register elements being
connected alternately in series, at least one binary divider stage
coupled to at least one point of the shift register, and at least
one further mixer the input of which is connected to the output of
a respective binary divider stage and the output of which is
connected to at least one further shift register element, the
arrangement being such that, the mixers mix the information content
of one binary divider stage with the information of one shift
register element at a time and deliver the mixed information to the
next shift register element.
5. The circuit of claim 4, wherein said mixers are modulus 2
mixers.
6. The circuit of claim 4, wherein the code pulse program is
obtained from said further mixer and is derived from the
information content of the divider stage and the shift register
stage.
7. The circuit of claim 4, wherein the shift register chain is
divided into a plurality of self contained shift register
chains.
8. The circuit of claim 7 and further comprising at least one
interchanger circuit for interchanging the flow of information of
one shift register chain to another shift register chain,
interchangement taking place at least between any element of one
shift register chain with any element of another shift register
chain.
9. A circuit for generating reproducible series of cipher pulses
having a long period, comprising at least 20 counting members
constituting a binary counting chain, at least 20 mixers each
connected to a respective counting member, a plurality of shift
register elements constituting together with the mixers a shift
register chain, the mixers and the shift register elements being
connected alternately in series, at least one binary divider stage
coupled to at least one point of the shift register, at least one
further mixer the input of which is connected to the output of a
respective binary divider stage and the output of which is
connected to at least one further shift register element, a
plurality of gate circuits, and a plurality of coincidence
detectors, the gate circuits and coincidence detectors being
interconnected between the counting members and the mixers in such
manner that, in the case of coincidence between the switching
states of two freely selected members of the counting chain and
elements of the shift register, a switching pulse is delivered at
the output of the coincidence detector, different sized groups of
coincidence detectors being associated through the gate circuits in
such manner that switching processes are initiated through the
outputs of the gate circuits whenever there is simultaneous
delivery of switching pulses by all the coincidence detectors
belonging to the relevant group.
10. The circuit of claim 9, wherein the shift register chain is
divided into a plurality of self-contained shift register
chains.
11. The circuit of claim 10, and further comprising at least one
interchanger circuit for interchanging the flow of information of
one shift register chain to another register shift register chain,
interchangement taking place at least between any element of one
shift register chain with any element of another shift register
chain.
12. A circuit for generating reproducible series of cipher pulses
having a long period, comprising at least 20 counting members
constituting a binary counting chain, at least 20 mixers each
connected to a respective counting member, a plurality of shift
register elements constituting together with the mixers a shift
register chain, the mixers and the shift register elements being
connected alternately in series, at least one binary divider stage
coupled to at least one point of the shift register, at least one
further mixer the input of which is connected to the output of a
respective binary divider stage and the output of which is
connected to at least one further shift register element, a
plurality of gate circuits, a plurality of coincidence detectors,
the gate circuits and coincidence detectors being interconnected
between the counting members and the mixers in such manner that, in
the case of coincidence between the switching states of two freely
selected members of the counting chain and elements of the shift
register, a switching pulse is delivered at the output of the
coincidence detector, different sized groups of coincidence
detectors being associated through the gate circuits in such manner
that switching processes are initiated through the outputs of the
gate circuits whenever there is simultaneous delivery of switching
pulses by all the coincidence detectors belonging to the relevant
group, at least one binary counter, means for imprinting the
information content of at least one plurality of shift register
stages into the binary counter at intervals whereby the binary
counter runs in the rhythm of the counting steps up to its maximum
number, means operable by the binary counter when it reaches its
maximum number to initiate a switching process to imprint the
information content present at that moment at the shift register
stage as a new binary number into the binary counter.
13. The circuit of claim 12, wherein the shift register chain is
divided into a plurality of self-contained shift register
chains.
14. The circuit of claim 13, and further comprising at least one
interchanger circuit for interchanging the flow of information of
one shift register chain to another shift register chain,
interchangement taking place at least between any element of one
shift register chain with any element of another shift register
chain.
15. A message transmission installation comprising at least two
stations each capable of acting as a transmitter and receiver, each
station comprising apparatus capable of acting as a transmitter and
receiver of information, a mixer, and a circuit for generating
reproducible series of code pulses having a long period, said
circuit comprising a binary counting chain having at least 20
members, connections connecting each of said members to a
respective mixer, a plurality of shift register elements
constituting a shift register chain, connections connecting each
mixer to a respective shift register element, to a previous shift
register element in the chain and to a switching distributor the
state of which is determined by a switching criterion, the
arrangement being such that the mixers mix the information content
of one counting member of the counting chain with the information
of one shift register element and this mixed information is
delivered to the next shift register element if the state of the
switching distributor is in accordance with the switching state of
the corresponding member of the counting chain, and that the
information of one shift register element is delivered to the next
shift register element unchanged if the state of the switching
distributor differs from the switching state of the corresponding
member of the counting chain.
Description
This invention relates to mixing and calculating circuits for
generating reproducible series of cipher pulses having a long
period, which forms constituents of cipher pulse generators. Cipher
pulse generators are used in ciphering messages, particularly
messages which are transmitted in the form of pulses.
In the ciphering of such messages, the individual pulses (or
combinations of pulses) are first mixed at a transmitter with as
random as possible a series of corresponding pulses (or
combinations of pulses), called the cipher pulses (or cipher pulse
combinations) and are transmitted in the form of the new pulses
obtained by the mixing. At the receiving end, the original message
is reproduced with the aid of a second identical series of cipher
pulses. The said cipher pulse series must be generated in identical
form at the transmitter and receiver. This purpose is served by the
likewise identical cipher pulse generators which are present at the
transmitter and receiver.
The cipher pulse series (code pulse program), and hence also the
actual cipher pulse generator, must satisfy specific requirements
in order reliably to exclude the possibility of the message being
deciphered along the transmission path by unauthorized persons.
First of all, the period of cycle length of the cipher pulse series
-- i.e., the period of time within which the cipher pulse series
does not repeat itself -- must be sufficiently great to make it
impossible for the entire cipher pulse series to be reproduced
sufficiently quickly to be of use, even when the most rapid
electronic means are used. Furthermore, the distribution of the
pulses within the cipher pulse series should be random
(statistical) to the utmost possible extent. The cipher pulse
series must also be created according to such complicated rules
that it is impossible from a knowledge of the series to deduce the
state of the individual circuit elements of the cipher pulse
generators. Furthermore, the cipher pulse series must be
reproducible -- i.e., a quite definite and unequivocal pulse series
must be produced for a specific initial state of a cipher pulse
generator.
According to the present invention there is provided a circuit for
generating reproducible series of code pulses having a long period,
said circuit comprising a binary counting chain having at least 20
members, connections connecting each of said members to a
respective mixer, a plurality of shift register elements
constituting a shift register chain, connections connecting each
mixer to a respective shift register element, to a previous shift
register element in the chain and to a switching distributor the
state of which is determined by a criterion, the arrangement being
such that the mixers mix the information content of one counting
member of the counting chain with the information of one shift
register element at a time and this mixed information is delivered
to the next shift register element if the state of the switching
distributor is in accordance with the switching state of the
corresponding member of the counting chain.
The mixers used may advantageously be so-called modulus 2 mixers.
However it is also possible to use, instead of such modulus 2
mixers, AND-gates and OR-gates known from the logical art, equal
numbers of AND-gates and OR-gates being advantageously used in each
case. In both cases -- that is to say, both where modulus 2 mixers
are used and also when equal numerical quantities of AND-gates and
OR-gates are used, the average frequency of occurrence of the
states "0" and "1" remains approximately unchanged. Therefore, if a
negative counter-like counting chain such as that described in my
copending U.S. Pat. application, Ser. No. 227,344 filed Oct. 1,
1962 be used, wherein the frequency of occurrence of the states "0"
and "1" is approximately of equal magnitude, then the said
frequency distribution is, on average, unmodified by the
mixers.
In order to enable the invention to be more readily understood,
reference will now be made to the accompanying drawings, which
illustrate diagrammatically and by way of example some embodiments
thereof, and in which:
FIG. 1 is a block circuit diagram of a message transmission
installation with automatic ciphering and deciphering;
FIG. 2 is a simplified circuit diagram of a mixing and calculating
circuit;
FIG. 3 is a simplified circuit diagram of another mixing and
calculating circuit;
FIG. 4 shows a greatly simplified circuit diagram similar to FIG. 3
in order to explain the switching cycle;
FIG. 5 is a simplified circuit diagram of yet another mixing and
calculating circuit; and
FIGS. 6 and 7 show two circuit details, FIG. 6 showing a
coincidence detector and FIG. 7 showing a modulus 2 mixing
circuit.
Referring now to FIG. 1, there is shown a message transmission
installation in which clear message pulses KIP (clear pulse
program) emanating from a transmitter 11 pass to a modulus 2 adder
12, where they are mixed with a cipher pulse series SIP of a cipher
pulse generator SG.sub.1, and the mixture -- the enciphered pulse
program CIP -- is transmitted to a receiver, where it is mixed in a
modulus 2 adder 13 with a cipher pulse series SIP of a cipher pulse
generator SG.sub.2, whereupon the clear pulse program KIP is
recovered and fed to a message receiver 14. Since the cipher pulse
series SIP constitutes a continuously changing series of cipher
pulses, synchronization of the cipher pulses at the transmitting
end SG.sub.1 and the receiving end SG.sub.2 is necessary. This
synchronization may be controlled for example by timing pulses TI
which are generated in a clock 15 and are added to the ciphered
pulse program CIP by means of a mixing circuit 16. On the receiving
side, the timing pulses TI are then taken out again from the
ciphered message by means of a mixing circuit 17 and supplied to
the cipher pulse generator SG.sub.2 for synchronization. Each of
the cipher pulse generators consists substantially of a counter
circuit ZWS and of a mixing and calculating circuit MRS. It is
advantageous to use a counting chain such as that described in my
aforesaid Patent Application No. 227,334 because the latter fulfils
the condition that 0 and 1 pulses occur with almost equals
frequency even over short periods.
A simple type of mixing and calculating circuit, and its
co-operation with the counter circuit, will now be described with
reference to FIG. 2. Referring now to FIG. 2, a counter circuit ZWS
consists of n counting elements Z.sub.1, Z.sub.2, Z.sub.3 . . .
Z.sub.n. Each counting element has a respective connection E.sub.1,
E.sub.2, E.sub.3, . . . E.sub.n, acting as outputs from the counter
circuit ZWS and as inputs to the mixing and calculating circuit
MRS. Each of the inputs E.sub.1, E.sub.2, . . . E.sub.n is capable
of assuming the states 0 or 1. Advantageously, binary counter
circuits ZWS are used, which are connected together in the manner
described in my aforesaid copending patent application, Ser. No.
227,344 and have the principle of operation therein set forth. In
the case of such a counting chain, the switching state of
practically all the members of the counting chain changes from
counting step to counting step. Furthermore, the counting chain
reverts to its initial state only after passing through all the
possible combinations of positions.
The counting process is controlled by the timing pulses TI so that,
for example, each timing pulse initiates a counting step. The
inputs E.sub.1, E.sub.2, E.sub.3 . . . E.sub.n (outputs from the
counter circuit) are taken in the mixing and calculating circuit
MRS to input gate circuits TE.sub.1, TE.sub.2, TE.sub.3 . . .
TE.sub.n, the second inputs of which are fed from a switching
distributor SV. The outputs of the gate circuits are taken to
modulators MS.sub.1, MS.sub.2, MS.sub.3 . . . MS.sub.n, which are,
for example, modulus 2 adders, which may be constructed in the
manner shown in FIG. 7. The modulators are connected into a shift
register having shift register stages SR.sub.1, SR.sub.2, SR.sub.3
. . . SR.sub.n, substantially so that each modulator is located
between two shift register stages. By means of the timing pulses
TI, which act as shift pulses, the information in the shift
register stages is shifted in the direction of the arrow 21 (to the
right in FIG. 2), namely from one shift register stage into the
next one on its right hand side in each case and for each timing
pulse. During shifting, the shifted information is mixed in the
modulator MS with the information present at the output of the gate
TE, and the mixed information passes to the shift register stage on
the right. At the right hand end, that is to say, at its output,
the shift register chain is connected a divider circuit U, which
consists, for example, of a normal flip-flop divider stage, the
information from the output 22 of which is mixed in a modulus 2
mixer or adder MU with the information from the output of the shift
register chain and fed back via a line 23 to the input of the shift
register chain. Simultaneously, the pulse program is passed out
from the line 23 as the cipher pulse program SIP.
The principle of operation of the circuit shown in FIG. 2 is as
follows. Due to the adoption of the binary system, the switching
states of the individual members of the counting chain and of the
individual shift register stages may be either 0 or 1. These
switching states can be varied in the rhythm of the timing pulses
TI, which advance the counting in the counting chain from counting
step to counting step, and which are responsible for shifting the
switching states in the shift register chain -- that is to say, for
displacing the switching state of a shift register stage to the
next shift register stage located to the right thereof for one
timing pulse. By means of the mixers of the modulators MS.sub.1,
MS.sub.2, MS.sub.3 . . . MS.sub.n, it is possible for the switching
states of the counter stages to be mixed via the gates TE with
those of the shift register stages. Mixing occurs in every case
when the first inputs of the input gates TE.sub.1, TE.sub.2 . . .
TE.sub.n are open -- that is to say, whenever the said first inputs
are brought into the switching state 1. Control of the said first
inputs is exercised by the switching distributor SV the state of
which is determined by a switching criterion such as are indicated
by the arrows 24. For example, the circuit may function in such a
manner that from time to time all the input gates TE are
simultaneously opened, so that at that instant the switching states
of all the counter elements are simultaneously mixed with those of
the shift register stages, or that only certain input gates are
open, so that only certain switching states of counter elements are
mixed with switching states of the shift register stages.
The divider stage U likewise has two possible switching states 0 or
1 and changes its switching state whenever the switching state 1
occurs at the input 25. Continuous totalling without carrying takes
place in the said divider stage. The output 22 of the divider stage
U is mixed in the modulus 2 adder MU with the particular switching
state of the output on the right hand side of the shift register
chain, whereby a pulse series totally different from the said
output is produced in the line 23, is delivered as a cipher pulse
series SIP and is fed via the modulator MS.sub.1 to the first shift
register stage SR.sub.1. A divider stage U together with the
modulus 2 adder MU, produces a great additional complication of the
cipher pulse series, and also makes it impossible for the switching
states of the individual shift register stages to be deduced from
the cipher pulse series. It is easy to see that the cipher pulse
series SIP thus obtained has been produced according to extremely
complex rules, and also that, by the use of a negative-counter-like
chain such as that described in the Specification of the aforesaid
patent application, Ser. No. 227,344 and in conjunction with
modulus 2 mixers, an equally great probability of the occurrence of
the switching states 0 or 1, and an extremely good approximately
random pulse distribution (0 or 1) is achieved. Finally it will be
seen that, by the action of the counter circuit, the cipher pulse
series will possess an extremely long cycle period if there is a
sufficient number of counter elements.
The circuit shown in FIG. 3 is of similar construction to that
shown in FIG. 2. But in this case, additionally to the circuit of
FIG. 2, a coincidence detector circuit KDS is provided. This
circuit consists of coincidence detectors KD.sub.1, KD.sub.2,
KD.sub.3 . . . KD.sub.n and of gate circuits TD.sub.1, TD.sub.2,
TD.sub.3 . . . TD.sub.n. The circuit of an individual coincidence
detector is indicated by way of example in FIG. 6, and the
principle of operation of such a coincidence detector is as
follows:
If both inputs ED.sub.1 and ED.sub.2 (input arrows) have the same
switching state -- that is to say, the switching state of both
inputs is 1 or the switching state of both inputs is 0 -- then the
switching state 1 occurs at the output AD of the coincidence
detector. But if the two inputs ED.sub.1 and ED.sub.2 have
different switching states then the switching state 0 occurs at the
output AD. Coincidence of the switching states of the two inputs is
therefore marked by a 1 at the output AD.
In FIG. 3, the switching state of a shift register stage is
compared in each case with that of a counting element, and the
coincidence indication is fed to the gate circuit TD.sub.1 to
TD.sub.n. A sole exception is constituted by the coincidence
detector KD.sub.n, which in this case ascertains coincidences
between the switching state of the shift register stage SR.sub.2
and the shift register stage SR.sub.n. The gate circuit TD.sub.1
transmits when the switching state 1 occurs at its input -- i.e.,
when the coincidence detector KD.sub.1 delivers a 1 at its output,
which is the case when the shift register stage SR.sub.1 and
counting element Z.sub.1 exhibit the same switching state
(coincidence). The gate circuit TD.sub.2 is open or transmits when
KD.sub.1 and KD.sub.2 are simultaneously in coincidence -- that is
to say, that it is necessary simultaneously for Z.sub.1 and
SR.sub.1 on the one hand and Z.sub.2 and SR.sub.2 on the other hand
to be in coincidence. Analogously, three coincidences must be
fulfilled simultaneously in the case of gate circuit TD.sub.3, four
coincidences simultaneously in the case of gate circuit TD.sub.4,
and n (5 as shown) coincidences simultaneously in the case of gate
circuit TD.sub.n, in order to bring their outputs to switching
state 1. The outputs 31 to 35 of the gate circuits TD.sub.1 . . .
TD.sub.n act as first inputs of the input gate circuits TE.sub.1,
TE.sub.2 . . . TE.sub.n. In the form of construction illustrated in
FIG. 3, the coincidence detector circuit produces the result that
the counter state of Z.sub.1 is mixed into the shift register chain
via TE.sub.1, MS.sub.1 whenever Z.sub.1 and SR.sub.1 are in
coincidence, and furthermore that the switching state of the
counting element Z.sub.2 is mixed into the shift registers chain
(via TE.sub.2, MS.sub.2) when Z.sub.1 and SR.sub.1 and also Z.sub.2
and SR.sub.2 are simultaneously coincident. Furthermore it produces
the result that the switching state of the counting element Z.sub.3
is mixed into the shift register chain via TE.sub.3, MS.sub.3 when
Z.sub.1 and SR.sub.1, Z.sub.2 and SR.sub.2, and Z.sub.3 and
SR.sub.3 are simultaneously coincident, and so on. Groups of
coincidence detectors of different group size (1, 2, 3 detectors)
are therefore formed, so that a switching operation -- i.e., the
mixing of a switching state of a counting element into the shift
register chain is initiated via the gate circuits TD.sub.1 . . .
TD.sub.n whenever all the coincidence detectors of the group
concerned exhibit coincidence simultaneously. Since the groups of
coincidence detectors have different sizes (1, 2, 3, 4 . . . n
coincidence detectors), the frequency of the switching processes
thus initiated is also different. For example, in the case of a
totally random distribution of the switching states in the elements
of the counting chain and in the shift register stages, the average
frequency of coincidence between Z.sub.1 and SR.sub.1 would be
one-half (50 percent). Likewise of course the average frequency of
coincidence between Z.sub.2 and SR.sub.2 or between Z.sub.3 and
SR.sub.3 ; but the average frequency of simultaneous coincidence
between Z.sub.1 and SR.sub.1 on the one hand and Z.sub.2 and
SR.sub.2 on the other hand is 1:2.sup.2, and the average frequency
of simultaneous coincidence between Z.sub.1, SR.sub.1, Z.sub.2 and
SR.sub.2, and Z.sub.3 and SR.sub.3 is 1:2.sup.3, and so on. The
simultaneous coincidence of a group of three coincidence detectors
is 4 times less frequent than that having only one coincidence
detector. The switching processes which are initiated by the
outputs of the gates TD.sub.1, TD.sub.2 . . . . TD.sub.n (lines 31,
32, 33, 34, 35) thus exhibit greatly different average frequencies.
The coincidence detector circuit is a feedback circuit, which very
substantially increases the complexity of the cipher pulse series.
It is simultaneously possible for all the switching states of the
counting elements to be mixed into the shift register chain via an
input line SO to the switching distributor.
The circuit shown in FIG. 4 has a similar structure and principle
of operation to that shown in FIG. 3. It is proposed to show, with
reference to FIG. 4, an example of the switching cycle over a
plurality of timing pulses, and the generation of a cipher pulse
series SIP. For the sake of simplicity, the number of counting
elements and of shift register stages has here been restricted to
4. (This would be too few according to the invention.) The
switching cycle can easily be ascertained by the laws of logic
circuits, and is recorded in the following Table 1.
TABLE 1
Schedule of the chronological cycle of switching states of the
example according to FIG. 4.
ti 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
__________________________________________________________________________
40 ' ' ' ' ' ' 40 40 40 ' ' ' ' ' ' ' ' z.sub.1 0 1 0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1 z.sub.2 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 z.sub.3
0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 z.sub.4 0 1 1 0 1 0 1 0 1 0 0 1
0 1 0 1 0 1 sr.sub.1 0 0 0 0 0 1 1 0 1 1 0 1 1 1 0 0 0 1 sr.sub.2 0
0 0 0 0 0 1 1 0 1 1 0 1 1 1 0 0 0 sr.sub.3 0 0 0 0 0 1 0 1 1 0 0 0
0 1 1 0 0 sr.sub.4 0 0 0 1 0 1 1 0 1 1 0 0 1 0 0 1 1 0 kd.sub.1 1 0
1 0 1 1 0 0 0 1 1 1 0 1 1 0 1 1 kd.sub.2 1 0 0 1 1 0 1 0 1 1 1 1 0
1 1 1 1 0 kd.sub.3 1 0 0 1 0 0 1 1 0 0 0 1 0 0 0 1 1 0 kd.sub.4 1 0
0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 0 td.sub.1 1 0 1 0 1 1 0 0 0 1 1 1 0
1 1 0 1 1 td.sub.2 1 0 0 0 1 0 0 0 0 1 1 1 0 1 1 0 1 0 td.sub.3 1 0
0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 td.sub.4 1 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 te.sub.1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 te.sub.2 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 te.sub.3 0 0 0 0 1 0 0 0 0 1 1 0 0
0 0 0 0 0 te.sub.4 0 0 1 0 1 0 0 0 0 0 0 1 0 1 0 0 0 1 u 0 0 0 1 1
0 1 1 0 1 1 1 0 0 0 1 0 0 sip 0 0 0 0 1 1 0 1 1 0 1 1 1 0 0 0 1 0
__________________________________________________________________________
in Table 1, the switching state at the outputs of the individual
switching elements is shown as 0 or 1. The timing pulses TI, which
bring about the modification of the switching states, are indicated
schematically in the top line and are numbered from one to 18
(chronological sequence). The counting elements Z.sub.1 to Z.sub.4,
shift register stages SR.sub.1 SR.sub.4, and the divider stage U
are storing switching elements, whereas the coincidence detectors
KD.sub.1 to KD.sub.4, the gates TE.sub.1 to TE.sub.4, and the gates
TD.sub.1 to TD.sub.4 are non-storing. At the commencement of the
switching cycle recorded by way of example in the schedule, the
output
of the counting elements Z.sub.1 to Z.sub.4 are at 0,
of the shift register stage SR.sub.1 to SR.sub.4 are at 0,
of the divider stage U is at 0,
whereby the switching states of the outputs of the remaining
circuit elements are fixed by the laws of logic, namely the
outputs
of the coincidence detectors KD.sub.1 to KD.sub.4 are at 1,
the outputs of TD.sub.1 to TD.sub.4 are at 1,
and the outputs of TE.sub.1 to TE.sub.4 are at 0
whereby the switching state of SIP is found to be 0. All these
initial states are to be seen in the left hand column of the
schedule. The first timing pulse switches the counting chain
according to its inherent counting laws, all the counting elements
being switched from 0 to 1, and the informations in the shift
register being shifted. Normally, however, for the purposes of
ciphering, a start is made not with switching states 0 throughout,
but with any desired combinations of switching states.
The formation of a cipher pulse SIP will now be ascertained by way
of example with reference to FIG. 4 and to Table I. The initial
switching state of the circuit will be assumed to correspond to
that after the eight beat pulse (column between 8th and 9th beat
pulses in Table I). Therefore, under these conditions, for example,
the output of
Z.sub.1 is at 0
Z.sub.2 is at 0
Z.sub.3 is at 0
Z.sub.4 is at 1.
the output of
Sr.sub.1 is at 1
Sr.sub.2 is at 0
Sr.sub.3 is at 1
Sr.sub.4 is at 1.
this gives the output of KD.sub.1 as 0, (since no coincidence
between Z.sub.1 and SR.sub.1 ), the output of KD.sub.2 as 1 (since
Z.sub.2 and SR.sub.2 are in coincidence) and so on. The outputs of
TD.sub.1 to TD.sub.4 and of TE.sub.1 to TE.sub.4 are all found to
be 0, and if the output of U = 0, then an SIP state of 1 is
obtained (mixture of U with SR.sub.4 in MU).
The subsequent timing pulse (9th TI) changes
Z.sub.1 from 0 to 1
Z.sub.2 from 0 to 1
Z.sub.3 from 0 to 1
Z.sub.4 from 1 to 0.
(Column between 9th and 10th timing pulse in Table I).
The switching state of SR.sub.1 is shifted unchanged (since
TE.sub.2 = 0) to SR.sub.2, likewise the switching state of SR.sub.2
to SR.sub.3 (because TE.sub.3 = 0).
The switching state of SR.sub.4 (= 1) is mixed with U in MU (= 0)
and TE.sub.1 (= 0) and is shifted as 1 into SR.sub.1. The divider U
changes its switching state at the 9th TI, since the output of
SR.sub.4 was previously 1 and the gate TU is therefore open. By
this means, the output of
U becomes 1, and since
Sr.sub.4 output is again 1, the output of
Mu becomes 0 -- i.e.,
Sip = 0
a number of delay circuits, not shown, are also requisite to the
proper functioning of the circuit.
The circuit shown in FIG. 5 is again of another structure to that
in FIG. 3, but it exhibits certain modifications and additions.
Thus, the gate circuit with the gates TD.sub.1, TD.sub.2, TD.sub.3
. . . TD.sub.n in the coincidence detector circuit in FIG. 3 is
replaced by a gate circuit with gates TK.sub.1, TK.sub.2, TK.sub.3,
TK.sub.4 . . . TK.sub.n in FIG. 5. However, the principle of
operation of this gate circuit is the same as of that in FIG.
3.
Thus, for example, the gate TK.sub.1 delivers an output pulse 1,
when the coincidence detector KD.sub.10 alone has coincidence. The
gate TK.sub.2 delivers an output pulse when two coincidence
detectors (KD.sub.9 and KD.sub.10) have coincidence simultaneously,
the gate TK.sub.3 delivers an output pulse when three coincidence
detectors (KD.sub.8, KD.sub.9 and KD.sub.10) have coincidence, and
so on. The outputs of the gates in the coincidence circuit pass via
OR-gates TO.sub.1, TO.sub.2, TO.sub.3 . . . TO.sub.n, to the input
gates (as first input) TE.sub.1, TE.sub.2, TE.sub.3 . . . TE.sub.n,
where they in turn control the switching processes -- that is to
say, the mixing of the switching states of the counting elements
into the shift registers. The majority of the coincidence detectors
shown ascertain coincidence each between one counting element and
one shift register stage. By contrast, the coincidence detector
KD.sub.1 ascertains coincidence between two counting elements,
namely Z.sub.1 and Z.sub.4, whereas the coincidence detectors
KD.sub.10 and KD.sub.n each ascertain coincidence between two shift
register stages. In contradistinction to the form of construction
shown in FIG. 3, three self-contained shift register chains are
provided in the construction shown in FIG. 5 instead of only one.
The top shift register chain possesses the shift register stages
SR.sub.1, SR.sub.4, SR.sub.7, SR.sub.10 and is closed via a circuit
containing a divider U.sub.1 and a modulator MU.sub.1 back to the
modulator MS.sub.1. The central shift register chain having shift
register stages SR.sub.2, SR.sub.5, SR.sub.8, SR.sub.11 is closed
via the circuit containing a divider stage U.sub.2 and a modulator
MU.sub.2. The third shift register chain having the shift register
stages SR.sub.3, SR.sub.6, SR.sub.9, and SR.sub.12 is closed via
the circuit containing a divider stage U.sub.3 and a modulator
MU.sub.3. The cipher pulse series SIP is again derived at the
output of the modulators (MU.sub.1, MU.sub.2, MU.sub.3). In this
case therefore, it is possible to obtain simultaneously three
parallel outputs of cipher pulse series. The circuit example in
FIG. 5 moreover contains an interchanger circuit VS having
interchanger gates TV.sub.1, TV.sub.2, TV.sub.3, TV.sub.4, TV.sub.5
and TV.sub.6 and divider U.sub.4. The divider U.sub.4, which is for
example a flip-flop circuit, has two outputs, of which one is at 0
and the other at 1 at any time. Each input pulse to the divider
U.sub.4 interchanges the switching states at the two outputs. For
example, if the right hand output of the divider U.sub.4 is at 1,
then the interchanger gates TV.sub.1, TV.sub.3, TV.sub.5 are
conductive and the shift register stage SR.sub.1 passes on its
information, upon shifting, to SR.sub.4, SR.sub.2 to SR.sub.5, and
SR.sub.3 to SR.sub.6. On the other hand, if the left hand output of
the divider U.sub.4 is at 1, then the interchanger gates TV.sub.2,
TV.sub.4, TV.sub.6 are conductive and the switching state SR.sub.1
passes to SR.sub.5, that of SR.sub.2 to SR.sub.6, and that of
SR.sub.3 to SR.sub.4. The change in the switching state in the
divider U.sub.4 has thus brought about an interchange of the flow
of information in the three shift register chains. Control of the
divider U.sub.4 is exercised by a pulse at the output of the gate
TK.sub.5 in the coincidence detector circuit -- that is to say,
whenever KD.sub.10, KD.sub.9, KD.sub.8, KD.sub.7 and KD.sub.6 have
coincidence simultaneously. A further additional circuit
arrangement as compared with the construction shown in FIG. 3 is
the connection of a binary counter BZ at the output of the three
shift register chains. The binary counter BZ consists here of the
three binary counting stages ZB.sub.1, ZB.sub.2, ZB.sub.3 and
therefore possesses a counting period of 2.sup.3 = 8. The counting
steps occur in rhythm with the timing pulses TI. The principle of
operation of this binary counter is as follows:
When the maximum binary number 111 is reached, the output gate
TB.sub.4 becomes conductive (at the moment when a timing pulse TI
occurs), and the switching processes are initiated via the line SO
and the OR-gates TO.sub.1, TO.sub.2, TO.sub.3 etc., which may be
for example that the switching states of the counting elements are
mixed into the shift register chain via the input gates TE.sub.1,
TE.sub.2 etc., and furthermore that the interchanger circuit VS is
interchanged via the divider U.sub.4. But simultaneously the output
pulse of the output gate TB.sub.4, passing through the line 64 and
the input gates TB.sub.1, TB.sub.2, and TB.sub.3, causes the
switching states of the outputs of the shift register chains
(output of SR.sub.10, SR.sub.11 and SR.sub.12) to be imprinted into
the individual counting elements ZB.sub.1, ZB.sub.2 and ZB.sub.3
via lines 61, 62 and 63. This imprinted binary number is now an
initial position, from whence the binary counter BZ is stepped on
by the action of the timing pulses TI until the binary counter
again reaches the maximum binary number 111 and the process already
described is repeated. This circuit arrangement also makes a very
substantial contribution towards increasing the complexity of the
switching cycle -- i.e., to the complexity of the cipher pulse
series.
The invention is of course not restricted to the number of circuit
elements indicated in the example. For example, it would also be
possible to provide a plurality of interchanger circuits instead of
only one, and in the same way five or any desired number of shift
register chains might be provided instead of only three.
* * * * *