U.S. patent number 3,676,850 [Application Number 05/114,669] was granted by the patent office on 1972-07-11 for video display system.
This patent grant is currently assigned to Columbia Broadcasting System, Inc.. Invention is credited to David A. Goldman, Henry N. Oppenheimer.
United States Patent |
3,676,850 |
Goldman , et al. |
July 11, 1972 |
VIDEO DISPLAY SYSTEM
Abstract
Teletype information signals from two different stock exchanges
are stored in respective recirculating registers. Under the control
of timing signals, the contents of the two registers are
periodically advanced and alternately supplied to a character
generator which converts the coded teletype information into an
electronic array of corresponding letters or figures. Each array is
sequentially scanned by a controlled electrical commutator and the
scanned signals are supplied to a cathode ray tube for
reproduction. The horizontal and vertical scanning coils for the
tube are rotated 90.degree. from their usual positions such that
information signals are displayed as advancing transversely across
the face of the device.
Inventors: |
Goldman; David A. (Yorktown
Heights, NY), Oppenheimer; Henry N. (Larchmont, NY) |
Assignee: |
Columbia Broadcasting System,
Inc. (New York, NY)
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Family
ID: |
22356702 |
Appl.
No.: |
05/114,669 |
Filed: |
February 11, 1971 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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734082 |
Jun 3, 1968 |
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Current U.S.
Class: |
345/26;
345/672 |
Current CPC
Class: |
G09G
5/343 (20130101) |
Current International
Class: |
G09G
5/34 (20060101); G08b 023/00 () |
Field of
Search: |
;340/324A,152,154 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Claffy; Kathleen H.
Assistant Examiner: Kundert; Thomas L.
Parent Case Text
This application is a continuation of application Ser. No. 734,082
filed June 3, 1968 and now abandoned.
Claims
We claim:
1. Apparatus for providing a visual display of first and second
received sequences of characters represented by first and second
received sequences of character signals comprising:
timing generator means for generating a pre-determined number of
timing signals;
first and second input register means for storing and reading out
the first and second received sequences of character signals,
respectively;
first and second transfer control means for sensing the number of
received character signals present in said first and second input
register means, respectively, and for generating first and second
transfer control signals respectively indicative of the numbers of
character signals present;
first recirculating buffer means for storing a selected number of
character signals read out of said first input register means and
responsive to certain of the timing signals generated by said
timing generator means and to said first transfer control signals
for simultaneously reading out and restoring the character signals
stored therein;
second recirculating buffer means for storing a selected number of
character signals read out of said second input register means and
responsive to certain of the timing signals generated by said
timing generator means and to said second transfer control signals
for simultaneously reading out and restoring the character signals
stored therein;
gate means responsive to the readout of character signals from said
recirculating buffer registers and to selected timing signals
generated by said timing generator means for alternately
transmitting to the character generator means the character signals
read out from said first and second recirculating buffer
registers;
character generator means responsive to the character signals read
out from said first and second recirculating buffer means for
converting the character signals to an electrical array, the array
forming the character represented by the character signals being
read out;
scanning means responsive to certain other timing signals generated
by said timing generator means for scanning the array corresponding
to the character being read out;
image reproducing means responsive to the output of said scanning
means for displaying the first and second sequences of characters
in rows on a display screen, said image reproducing means including
deflection means responsive to still other timing signals generated
by said timing generator means for implementing line scanning in
the first direction and field scanning in a second direction, the
characters being sequentially presented on a display screen in rows
which are oriented in the direction of field scanning;
first offset counter means responsive to said first transfer
control signals for controlling the initial scan of said array to
thereby produce an incremental positioning in the reproduction of
the first sequence of characters by said image reproducing means in
accordance with the number of character signals present in said
first input register means; and
second offset counter means responsive to said second transfer
control signals for controlling the initial scan of said array to
thereby produce an incremental positioning in the reproduction of
the second sequence of characters by said image reproducing means
in accordance with the number of character signals present in said
second input register means.
2. Apparatus in accordance with claim 1 wherein the incremental
positionings in the reproduction of the first and second characters
is achieved by offsetting the displayed characters by a number of
scan lines, the offset being synchronized with the rate of field
scanning.
3. Apparatus in accordance with claim 2 wherein the offset of the
displayed characters is synchronized at the rate of two lines per
field scansion for particular transfer control signals and at a
rate of four lines per field scansion for different transfer
control signals.
4. Apparatus in accordance with claim 1 further comprising
coordinating circuit means responsive to said selected timing
signals for receiving character signals from said scanning means
and for transmitting selected character representative signals to
said image reproducing means such that characters represented by
the transmitted signals are displayed on different portions of the
image reproducing device.
5. Apparatus in accordance with claim 2 wherein said first
direction is the vertical direction and said second direction is
the horizontal direction.
Description
BACKGROUND OF THE INVENTION
This invention relates to television display systems and, more
particularly, to television display systems which provide a visual
display of characters represented by telegraph and the like
signals.
There have been developed recently display systems for displaying
telegraph information signals on a screen. Such systems implement
the visual reproduction of the telegraph signals on a screen by
stroke writing techniques, by scanning perforated paper tape with a
television camera and by employing high speed electronic video
switching systems. Among the many services utilizing such systems
is the stock market quotation service. Because of the ever
increasing sales transactions occurring in the major stock
exchanges, the number of brokerage offices having communications
links with the exchanges has correspondingly increased. A great
many of the larger offices already have display systems including
screens for displaying an up-to-the-minute visual indication of
stock quotation prices. However, many of the smaller offices do not
have such screens or like display devices because of the complexity
and high cost of the systems associated with the screens.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a
video display generator for producing a visual display of the
characters represented by telegraph signals which overcomes the
above-mentioned disadvantages of the prior art.
It is another object of the present invention to provide a video
display generator which provides a moving display of telegraph
information across the face of an image reproducing device.
These and other objects of the present invention are accomplished
by the video display generator of the present invention. In the
generator, character representative telegraph signals are stored in
a recirculating buffer, readout and simultaneously restored in the
buffer under the control of timing signals. The readout character
representative signals are then supplied to a character generator
which converts the information signals into an array of electrical
elements forming the characters represented by the telegraph
information signals. This array is scanned to thereby provide
character representative signals and the character representative
signals are thereupon supplied to an image reproducing device for
reproduction.
In a preferred embodiment of the invention, the deflection means of
the image reproducing device are angularly rotated such that line
scanning takes place in a substantially vertical direction, field
scanning takes place in a substantially horizontal direction and
the information is reproduced as precessing across the face of the
image reproducing device. Also, offset counting devices are
provided to produce an incremental positioning of the reproduced
information on the face of the image reproducing device in each
successive field or frame to create the effect of motion by the
reproduced information following a transfer of character
representative telegraph signals to the recirculating buffer. In
addition, the generator is provided with a pair of channels for
receiving character representative telegraph signals from two
different sources and the characters represented by the signals are
displayed on opposite halves of the face of the image reproducing
device.
BRIEF DESCRIPTION OF THE DRAWING
In the Drawings:
FIGS. 1A and 1B are a schematic block diagram of an illustrative
video display generator arranged according to the present
invention;
FIGS. 2A, 2B and 2C are schematic block diagrams of certain of the
elements in the video display generator of FIG. 1;
FIG. 3 is a block diagram illustrating the alignment between FIGS.
1A and 1B and between FIGS. 2A, 2B and 2C;
FIG. 4 is a pictorial representation of the selective magnetization
of the magnetic cores of the core matrix of the character matrix
generator of the FIG. 1 video display generator; and
FIG. 5 is a pictorial representation of the telegraph information
as it is displayed by the image reproducing device of the FIG. 1
video display generator.
DESCRIPTION OF THE PREFERRED EMBODIMENT
In the illustrative embodiment of a video display generator
arranged according to the present invention, as shown in FIGS. 1A
and 1B, telegraph information signals from two different sources,
such as, for example, the New York and American Stock Exchanges,
respectively, are supplied via teletype lines (not shown) to a pair
of level converters 10 and 12, respectively.
The telegraph information signals are supplied as pulsating d-c
signals and each character of information comprises six bits, bit 0
determinative of whether the character is a letter or a figure and
bits 1-5 determinative of the particular letter or figure. In the
level converters 10 and 12, the pulsating d-c telegraph signals are
converted into pulsating logic level signals. In particular, the
level converters reduce the peak amplitudes of the signals from
approximately 120 volts to approximately 10 or 12 volts. From the
level converters 10 and 12 the reduced amplitude telegraph signals
are transferred serially to a pair of shift registers 14 and 16,
respectively. Each register comprises 12 groups of six-bit shift
registers serially interconnected and, hence, each register is
capable of storing 12 characters. The output terminals of the six
devices, which may be, for example, conventional flip-flop
circuits, comprising the last group in each of the registers 14 and
16 are connected to a pair of gate circuits 18 and 20,
respectively. The gate circuits 18 and 20 may be conventional and,
hence, for purposes herein, each circuit comprises 6 "and" gates,
each "and" gate having one input terminal coupled to an individual
flip-flop in the last group register in the registers 14 and 16,
respectively.
The 12 groups of shift registers in the registers 14 and 16 are
further coupled to a pair of voltage generators 22 and 24,
respectively, which may be, for example, conventional adding
circuits, and hence, which develop voltage signals, the amplitudes
of which correspond to the number of groups in the registers 14 and
16 containing telegraph information. For example, where all 12
groups contain characters, the generators 22 and 24 may produce
voltage signals having amplitudes of 24 volts, respectively. Where
six of the 12 groups contain information, the amplitudes of the
generated signals may be 12 volts. From the voltage generators 22
and 24 the voltage signals are supplied to a pair of rate and
transfer control circuits 26 and 28, respectively. Depending upon
the amplitudes of the voltage signals developed by the generators
22 and 24 the control circuits 26 and 28, which may comprise
amplifier circuits preceded by voltage detection networks, develop
either so-called "15 level" signals or "7.5 level" signals and
supply these signals to a pair of character advance control
circuits 30 and 32 via a pair of conductors 75 and 74,
respectively.
Specifically, when eight or more groups in the registers 14 and 16
contain information the generators 22 and 24 develop signals having
amplitudes above, for example, 16 volts, which drive the control
circuits 26 and 28 and cause a 15 level signal to be produced. When
less than eight but at least one group in each of the registers
contains information, the generators 22 and 24 develop signals
having amplitudes below, for example, 16 volts, which drive the
control circuits 26 and 28 and cause a 7.5 level signal to be
produced. As will be explained hereinafter, the 15 level signal and
the 7.5 level signal correspond to character progression speeds and
control the horizontal positioning of the telegraph information as
it is displayed by the image reproducing device of the present
invention. Moreover, when a 15 level signal is developed, the
transfer of information out of the registers 14 and 16 takes place
at a rate which doubles the rate of transfer when the 7.5 level
signal is present, as will also be apparent hereinbelow.
In response to character present or CPFF signals generated by the
character advance control circuits 30 and 32, the control circuits
26 and 28 emit gating signals and supply these gating signals to
the other input terminals of the six "and" gates forming each of
the gate circuits 18 and 20, respectively. The character present
signals are generated when the generator components following the
shift registers 14 and 16 are available to accept another
character, as will be explained in detail hereinafter. When enabled
by the gating signals generated by the circuits 26 and 28, the gate
circuits transmit, in parallel, the bits stored in the last group
registers of the registers 14 and 16 to a pair of six-bit buffers
34 and 36.
The six-bit buffers 34 and 36, which may be of conventional
construction, supply voltage level signals corresponding to the
character bits transferred to the buffers by the gates 18 and 20,
respectively, to a pair of 32 character recirculating buffers 38
and 40. In addition, the buffers 34 and 36 supply a pair of
character available signals to the character advance control
circuits 30 and 32. This initiates a sequence of operation which
enables the 32 character recirculating buffers 38 and 40 to accept
the new six-bit characters stored in the buffers 34 and 36,
respectively. As will be explained hereinafter, 32 characters are
stored in each of the buffers 38 and 40 and continuously
recirculated and read out under control of certain timing signals.
When a new character is supplied to either buffer, the character is
stored and then readout, the oldest character in the buffer being
dropped.
To understand the operation of the 32 character recirculating
buffers 38 and 40, as well as the character advance control
circuits 30 and 32, it is necessary now to explain the timing
signal control circuitry of the video signal generator. As shown in
FIG. 1B, the generator comprises a phase locked 2 megaHertz per
second (mH/s) clock 42 which emits pulses having a pulse width of
one-half a microsecond. The clock 42, which may be, for example, a
conventional crystal oscillator, generates phase locked 1/2
microsecond pulses and supplies these pulses to a 128 bit binary
counter 44 through a conductor 45. The counter 44 may be of
conventional construction and, hence, includes seven bistable
devices A, B, C, D, E, V, u to accumulate a count of 128. The count
is reached in 64 microseconds. The number 128 constitutes the
number of bits which will be present in any given scanning line
displayed by the image reproducing device of the video display
generator, as will be more apparent hereinbelow.
Connected to the 128 bit binary counter 44 is an eight line binary
counter 46 comprising three bistable devices. The counter 46 is
advanced one position each time the counter 44 reaches a count of
128 or every 64 microseconds. As will also be explained
hereinafter, eight scanning lines of the video display are allotted
to each character of telegraph information, five lines comprising
the information and three lines comprising spaces. A 32 group
counter 48 comprising five bistable devices is coupled to the
counter 46 and is stepped each time the counter 46 reaches a count
of 8. This counter counts the number of characters displayed by the
image reproducing device and continues to count until 32 characters
are displayed during each field scansion, the same number of
characters which are stored and recirculated in the buffers 38 and
40. As thus far described, there is provided a counting arrangement
for 256 lines, each line comprising a maximum of 128 bits of
information.
Because there are 2621/2 lines in each television field scansion,
the counters 44, 46 and 48 are not reset upon a count of 256 lines.
Coupled to the 32 group counter is a bistable device 50 which is
set into the "1" state when the counter 48 reaches a count of 256.
The "1" side of the device 50 is coupled to the input terminals 52a
and 54a of a two input "and" gate 52 and a three input "and" gate
54, respectively. The other input terminal 52b of the gate 52 and
another input terminal 54b of the gate 54 are coupled together and
through a conductor 55 to a timing signal decode network 56. The
network 56, which may comprise suitable gating circuits and
amplifiers for decoding the counts accumulated in both the 128 bit
counter 44 and the eight line counter 46, generates a logic level
signal each time a count of 6 is accumulated by the counter 46.
With the simultaneous presence of the line 6 signal and the "1"
signal from the device 50, the gate 52 is enabled and generates a
reset level signal. The third input terminal 54c of the gate 54 is
coupled via a conductor 57 to the network 56 which generates a
pulse each time a count of 64 is accumulated in the counter 44.
This pulse enables the gate 54 for a period of 0.5 microseconds and
the gate emits a 0.5 microsecond reset pulse.
At the end of a count of 2621/2 lines, therefore, the reset pulse
is generated. This pulse resets the bistable device 50 and the
counters 44, 46 and 48. The reset pulse is also supplied to a
vertical sync and horizontal sync generator 58 which generates a
vertical sync signal. Upon resetting of the bistable device 50 the
gate 52 is disabled. Accordingly, the reset level signal is
generated at a count of 262 lines and is terminated at a count of
2621/2 lines.
In the vertical sync and horizontal sync generator 58, the reset
pulses are shaped and amplified and supplied as vertical sync
pulses through a conductor 59 and a branch conductor 59a to a
conventional video driver 60 and a scanning wave generator 62. The
generator 58 is also coupled to the timing signal decode network 56
through a conductor 63 and receives a T128 pulse from the network
56 each time a count of 128 is accumulated in the counter 44 or
every 64 microseconds. In the generator 58, the T128 pulse is
shaped and amplified and thereupon supplied as a horizontal sync
pulse through a conductor 64 and its branch conductor 64a to the
video driver 60 and the scanning wave generator 62,
respectively.
As thus far described, the timing signal decode network 56 is
responsive to the states of the bistable devices of the counters 44
and 46 for developing a T64 signal, a T128 signal and a line 6
signal, respectively. The network 56 also generates 23 timing
signals TO-T22 a total number of four times during each counting
cycle by the counter 44. In other words, the network 56 decodes the
states of the first five bistable devices to generate the signals
TO-T22 once every 16 microseconds, that is, from counts 0-31, =-63,
64-95 and 96-127. The decode network also generates a T120 pulse
having a pulse width of one-half microsecond, each time the counter
44 reaches a count of 120.
The last two bistable devices in the 128 bit counter 44, i.e., the
32nd bit and the 64th bit bistable devices, are labeled v and u,
respectively. As will be explained in more detail hereinbelow, the
state of the u bistable device controls the vertical display of
information on the face of the image reproducing device.
Specifically, when the u bistable device is set to the "1" state
(T64-T127), information is displayed in the lower half of the image
reproducing device. When the device is in the "0" state (T0-T63),
information is displayed on the upper half of the image reproducing
device. The state of the v bistable device also controls the
vertical display of information on the face of the image
reproducing device. In particular, when the v bistable device is in
the "0" state (T0-T31, T64-T95), information is displayed on the
upper half of either the upper half or the lower half of the image
reproducing device and when the device is in the "1" state
(T32-T63, T96-T127), information is displayed on the lower half of
either the upper half or the lower half of the image reproducing
device.
As above-mentioned with reference to FIG. 1A, when the character
bits are transferred from the gates 18 and 20 to the six-bit
buffers 34 and 36, respectively, the buffers supply a pair of
character available signals to the character advance control
circuits 30 and 32. Referring to FIGS. 2A, 2B and 2C, there is
shown in detail certain of the components of the video display
generator of the present invention. Because the upper channel and
lower channel have identical components, only the components of the
upper channel, referred to hereinafter as the New York Stock
Exchange channel, are shown in detail. The corresponding components
of the lower channel, hereinafter referred to as the American Stock
Exchange channel, are shown generally.
As shown in FIG. 2B, the character advance control circuit 30
comprises a first and gate 66. One input terminal 66a is supplied
with the reset level signal developed by the gate 52 (FIG. 1B) and
the other input terminal 66b is coupled to the six-bit buffer 34
(FIG. 1A) and receives a character available signal when the buffer
34 is loaded. The simultaneous presence of the character available
signal and the reset level signal enables the gate and the gate
supplies a pulse to the set input terminal 68a of a character
present flip-flop 68.
When set to the "1" state, the character present flip-flop 68
supplies a character present (CPFF) signal from its set output
terminal 68b through a conductor 69 to the input terminals 70a and
72a of a pair of three input "and" gates 70 and 72, respectively.
The output terminal of the character present flip-flop 68 is also
coupled to the rate and transfer control circuit 26 (FIG. 1A) via a
conductor 73 such that when a character present signal is
available, the circuit 26 is disabled. The reset level signal is
coupled from the input terminal 66a of the gate 66 to the second
input terminals 70b and 72b of the gates 70 and 72. The other input
terminals 70c and 72c of the "and" gates 70 and 72, respectively,
are coupled via the conductors 74 and 75, respectively, to the rate
and transfer control circuit 26 (FIG. 1A) which supplies either a
7.5 level signal or a 15 level signal to the gates 70 and 72,
respectively. As above-mentioned, a 7.5 level signal is generated
when less than eight but at least one group of registers in the
register 14 contains information and a 15 level signal is generated
when eight or more groups of registers in the register 14 contain
information. Depending upon whether the 7.5 level signal or the 15
level signal is supplied from the rate and transfer control circuit
26, either the gate 70 or the gate 72 will be enabled.
The output terminal 70d of the "and" gate 70 is coupled to the
input terminal 78a of the flip-flop circuit 78 which is alternately
set and reset each time the "and" gate 70 is enabled by the
simultaneous presence of the reset level signal, the CPFF signal
and the 7.5 level signal. The output terminal 72d of the "and" gate
72 and the set output side 78b of the flip-flop 78 are coupled
together and to the shift input terminal 80a of a two stage binary
counter 80. It can be seen that twice as many shift pulses will be
supplied from the "and" gate 72 to the input terminal 80a of the
binary counter 80 as will be supplied from the flip-flop circuit
78. This is true because the flip-flop circuit 78 will be
alternately enabled and disabled in response to the simultaneous
application of the reset level signal, the CPFF signal and the 7.5
level signal to the input terminals of the gate 70 whereas the
enabling of the gate 72 will correspondingly implement the
generation of a shift pulse to the binary counter 80. Hence,
counting by the counter 80 when a 15 level signal is present will
occur twice as fast as counting when a 7.5 level signal is
present.
The application of a shift pulse from either the "and" gate 72 or
the flip-flop circuit 78 to the input terminal 80a of the two stage
binary counter 80 initially resets the counter to the "0" state.
The two bistable devices comprising the binary counter 80 are
coupled to a decoding network comprising a count "0 and" gate 82, a
count "1 and" gate 84, a count "2 and" gate 86 and a count "3 and"
gate 88. As is understood in the art, the count "0 and" gate 82 is
enabled each time both stages of the counter 80 are in the "0"
states; the "and" gate 84 is enabled each time the counter 80 has
counted to 1; the count "2 and" gate 86 is enabled each time the
counter 80 has accumulated a count of 2; and the count "3 and" gate
88 is enabled each time the counter has accumulated a count of
3.
The output terminal of the count "0 and" gate 82 is connected
through a conductor 90 and its branch conductor 90a to one input
terminal 92a of an "and" gate 92 located in an offset counter
programmer 94 and to one input terminal 96a of an "and" gate 96
located in a recirculating buffer control circuit 98 (FIG. 2A). The
American Stock Exchange channel similarly includes an offset
counter programmer 100 and a recirculating buffer control circuit
102. The recirculating buffer control circuits 98 and 102 control
the storage and shifting of telegraph characters in the 32
character recirculating buffers 38 and 40, respectively, as will be
explained hereinbelow.
The output terminal of the count "1 and" gate 84 (FIG. 2B) is
connected to one input terminal 104a of a second "and" gate 104
located in the offset counter programmer 94. The output terminal of
the count "2 and" gate 86 is also connected to one input terminal
106a of an "and" gate 106 located in the offset counter programmer
94 while the output terminal of the count "3 and" gate 88 is
connected to the reset input terminal 68c of the character present
flip-flop 68. A conductor 108 couples the input terminals 92b, 104b
and 106b of the "and" gates 92, 104 and 106 together and supplies
these terminals with the reset level signal. The input terminals
92c, 104c and 106c of the gates are connected together via a
conductor 110 and to the set output terminal 68a of the character
present flip-flop 68. It can be seen that the "and" gates 92, 104
and 106 will be sequentially enabled as the counter 82 counts from
0 to 3 when a reset level signal is generated at the end of a count
of 262 lines and as long as the character present flip-flop 68 is
set.
A pair of branch conductors 108a and 110a of the conductors 108 and
110, respectively, conduct the reset level signal and the CPFF
signal to the input terminals 96b and 96c of the "and" gate 96 in
the recirculating buffer control circuit 98 and to the input
terminals 112b and 112c of an "and" gate 112 in the buffer control
circuit 98 (FIG. 2A). A conductor 111 couples the "0" side of the
flip-flop 78 to the fourth input terminal 96d of the "and" gate 96.
Only when the flip-flop 78 is set into the "1" state, does the
output signal FF78 from the "0" side of the flip-flop 78 tend to
enable the gate 96.
When the reset level signal and the CPFF signal are simultaneously
present, the "and" gate 112 is enabled and drives an amplifier 114
into conduction. The output terminal 114b of the amplifier 114 is
coupled to the output terminal 116b of an amplifier 116 and to one
input terminal 118a of an "and" gate 118. The other input terminal
118b of the "and" gate 118 is coupled via a conductor 120 and its
branch conductors 120a, 120b and 120c to the output terminal of the
"and" gate 96, the input terminal of a common emitter amplifier 122
and to the input terminals of six "and" gates 124, 125, 126, 127,
128 and 129 located in the 32 character recirculating buffer 38.
For the sake of simplicity, only gates 124 and 129 are shown.
When the count 0 signal, the reset level signal, the CPFF signal
and the FF78 signal are supplied to its input terminals 96a, 96b
and 96c and 96d the gate 96 is enabled and supplies an inhibit
signal to the input terminal 118b of the "and" gate 118 to thereby
disable the gate, to the input terminal of the common emitter
amplifier 122 and to the input terminals of the gates 124-129 to
disable these gates. The common emitter amplifier 122 inverts the
inhibit signal to provide an inhibit signal and this signal is
supplied to the input terminals of six "and" gates 130, 131, 132,
133, 134 and 135 also located in the recirculating buffer 38.
Hence, when the inhibit pulse is generated, only the gates 130-135
are enabled. These gates are enabled for a period of 32
microseconds, that is from the time it takes the counter 44 (FIG.
1B) to count to 64 or from a count of 262 lines to a count of
2621/2 lines.
The "and" gates 124-129 are associated with the information already
stored in the buffer 38 while the "and" gates 130-135 are
associated with the new character bits supplied in parallel from
the six-bit buffer 34 (FIG. 1A). In particular, the other input
terminals of the "and" gates 124-129 are coupled to the first
stages in six shift registers 136, 137, 138, 140 and 141,
respectively, each shift register comprising 32 flip-flops. The
"and" gates 130-135 are associated with the new character bits and
their other input terminals are coupled in parallel to the six
output terminals of the six-bit buffer 34 (FIG. 1A). The output
terminals of the "and" gates 124-129 and 130-135 are coupled
respectively to the input terminals of six "or" gates 142-147 which
selectively transmit the bits supplied from either the "and" gates
124-129 or the "and" gates 130-135. The bits transmitted by the
"or" gates 142-147 are thereafter supplied to the enabling input
terminals of six flip-flop circuits 148-153, respectively. The set
output terminals of the flip-flop circuits 148-153 are connected to
the enabling input terminals of the last stages in the registers
136-141, respectively, and to the input terminals 154a, 155a, 156a;
157a, 158a and 159 a of a six "and" gate circuits 154-159,
respectively, which make up a gate circuit 160.
The output terminal 118c of the "and" gate 118 is coupled through a
conductor 161 to the shift input terminals of the 32 flip-flops
making up each of the shift registers 136-141. Initially, the "and"
gate 118 is disabled by the application of the inhibit pulse to its
input terminal 118b, notwithstanding the application of the
amplified pulse to its other input terminal 118a. However, the
output terminals 114b and 116c of the amplifiers 114 and 116 are
coupled together and through a conductor 162 to the shift input
terminals of the flip-flop circuits 148-153. Accordingly, with the
simultaneous presence of a reset level signal and a CPFF signal,
the gates 130-135 of the buffer will be enabled by the inhibit
pulse and a shift pulse is generated by the amplifier 114. The
gates 130-135 will therefore pass the new character bits and these
bits will be loaded into the flip-flop circuits 148-153 and read
out. At the end of 2621/2 lines, the reset level is removed from
the input terminals of both gates 96 and 112 and these gates will
be disabled. With the disabling of the gate 96, the inhibit signal
is removed, the "and" gate 118 is enabled and the "and" gates
124-129 are enabled. By reason of the phase inversion performed by
the common emitter 122, the "and" gates 130-135 are disabled.
To implement the further shifting of information within the
recirculating buffer 38 and the reading out of information, the
recirculating buffer control unit is provided with another "and"
gate 164 having one input terminal 164a connected to a shift signal
generator 166 (FIGS. 1A and 2B) through a conductor 167 and its
other input terminal 164b supplied with the 0.5 microsecond pulse
T120 generated by the timing signal decode network 56 (FIG. 1B).
The shift signal generator supplies a "line 6" pulse to the
recirculating buffer control circuit 98 such that after a scan
period of six lines and 60 microseconds (T120), the "and" gate 164
is enabled and transmits the T120 pulse to the input terminal 116a
of the amplifier 116. The amplifier 116 supplies a shift output
pulse each time the "and" gate 164 is enabled and supplies this
pulse to the input terminal 118a of the "and" gate 118 and to the
shift input terminals of the flip-flop circuits 148-153 through the
conductor 162. Because the total number of scanned lines equals
2621/2, a total of 32 shift pulses will be supplied from the
amplifier 116.
With the application of the amplified pulse to the input terminal
118a of the "and" gate 118, a shift pulse is supplied via the
conductor 161 to the shift input terminals of the flip-flop
circuits composing the registers 136-141. With the simultaneous
generation of the two shift pulses and the enabling of the "and"
gates 124-129, the bits stored in the first stages of the registers
136-141 are transmitted by the gates 124-129, loaded into the
flip-flops 148-153, respectively, and supplied to the "and" gates
154-159, respectively. The newest bits defining a character are
simultaneously shifted into the last stages of the registers
136-141 from the flip-flops 148-153, respectively. During the
generation of the next 31 shift pulses, the bits in the registers
136-141 are shifted into the flip-flops 148-153, respectively, in
the above described manner. At the end of 32 shift pulses, the
newest information bits are stored in the first stages of the
registers 136-141 while the oldest information bits are stored in
the flip-flops 148-153. In this manner, when new information is
again transmitted by the gates 130-135, the oldest information bits
are dropped as the new information bits are loaded into the
flip-flops 148-153. The oldest bits are dropped because the
registers 136-141 are inhibited from shifting, as above
described.
The lower American Stock Exchange channel similarly contains a gate
168 comprising six "and" gates 169, 170, 171, 172, 173 and 174
having input terminals 169a-174a coupled to the output flip-flop
circuits in the 32 character recirculating buffer 40 and a shift
signal generator 176 which supplies a line 6 pulse via a conductor
178 to the recirculating buffer control circuit 102. The other
input terminals 154b-159b of the gates 154-159, respectively, are
coupled together and, via a conductor 179, to the input terminals
180a, 182a, 184a, 186a and 188a of five "and" gates 180, 182, 184,
186 and 188 in a character position control circuit 190 (FIG. 2B)
and to the "0" side of the u bistable device in the 128 bit counter
44 (FIG. 1B). Appropriate current drivers may be inserted between
the u bistable device and the gates, as is understood in the art.
When the u bistable device is in the "0" state (TO-T63), the gates
154-159 are enabled and transmit the information bits. The other
input terminals 169b-174b of the gates 169-174 respectively are
also coupled together and, via a conductor 192, to the input
terminals of five "and" gates composing a character position
control circuit 193 (FIG. 2B) and to the "1" side of the u bistable
device (FIG. 1B). These gates are enabled when the u bistable
device is in the "1" state (T64-T127). As will be explained
hereinafter, the bits transmitted by the gates 154-159 are
displayed on the upper half of the image reproducing device and the
bits transmitted by the gates 169-174 are displayed on the bottom
half of the image reproducing device.
The output terminals of the gates 154 and 169; 155 and 170; . . .
159 and 174 are tied together and coupled to the input terminals of
a character matrix generator 194 (FIG. 2C). The character matrix
generator 194 comprises a pair of decode networks 196 and 198 which
comprise conventional gating circuitry for decoding the transmitted
New York and American Stock Exchange information bits. The networks
196 and 198 are provided to decode the bits 1-5 from each gate
circuit 160 and 168 into a pair of pulses out of a possible 64
pulses. Each network is provided with 32 output terminals 196a-196n
and 198a-198n and these output terminals are coupled to the input
terminals of 32 "and" gates 200a-200n and 202a-202n. The other
input terminals of the gates 200a-200n and 202a-202n are coupled
together and are supplied with the bit 0 pulse which, as
above-mentioned, determines whether the coded information is a
letter or a figure. The gates 200a-200n are enabled when bit 0 is a
"1" or a mark and the "and" gates 202a-202n are enabled when bit 0
is a 0 or a space. Hence, if bits 0-5 correspond to a letter, only
one of the "and" gates 200a-200n is enabled. If bits 0-5 correspond
to a figure, only one of the "and" gates 202a-202n is enabled.
The output terminals of the gates 200a-200n and 202a-202n are
connected to the input terminals of a pair of current driver
matrices 204 and 206, respectively. The current driver matrix 204
comprises five columns and eight rows of current drivers and the
current drivers are selectively coupled to the "and" gates
200a-200n. For example, if the columns are labeled A, B, C, D, and
E and the rows are labeled 1-8, a pulse corresponding to the letter
A applied to an input terminal from one of the gates 200a-200n
would energize the following current drivers: A2, A3, A4, A5, E2,
E3, E4, E5, B1, C1, D1, and B4, C4, D4. In other words, the current
drivers of the matrix are energized in a pattern which corresponds
to the letter being transmitted. This will become more apparent
hereinafter.
The current driver matrix 206 comprises five columns and 15 rows of
current drivers and these current drivers are also selectively
coupled to the "and" gates 202a-202n. For example, if the columns
are labeled A, B, C, D and E and the rows are labeled 1-15, a pulse
corresponding to the figure "4" applied from one of the gates
202a-202n would energize the following current drivers: A7, B6, B7,
C5, C7, D4, D5, D6, D7, D8, D9, D10 and E7. Again, the array of
current drivers being energized corresponds to the figure decoded
by the decode network 198, as will be apparent hereinafter.
The 40 current drivers in the matrix 204 and the 75 current drivers
in the matrix 206 are coupled via the output terminals 0-39 and
0-74, respectively, to the set input windings of corresponding
magnetic cores of a core matrix 208. The cores of the matrix are
arranged in a matrix of five columns labeled A, B, C, D and E and
23 rows labeled 1-23. As shown, the current drivers of the matrix
204 are respectively coupled to the set input windings of the
magnetic cores occupying the first eight rows, 1-8, of the matrix.
The current drivers of the current driver matrix 206 are
respectively coupled to the set input windings of the magnetic
cores occupying the last 15 rows of the matrix, rows 9-23.
Therefore, the magnetic cores being magnetized correspond to the
letter or figure decoded by the decode networks 196 and 198,
respectively.
The selective magnetization of the cores of the matrix 208 to form
a letter or figure is pictorially shown in FIG. 4. When a letter,
such as the letter G is decoded, the magnetic cores are energized
in a pattern corresponding to the letter. As shown in FIG. 4, when
the letter G is decoded, the following cores are magnetized: A2,
A3, A4, A5 and A6; B1 and B7; C1 and C7; D1, D5 and D7; E2, E5 and
E6. When a figure, such as the figure 4 is decoded, the magnetic
cores are magnetized in a pattern corresponding to the figure. As
shown, when the figure 4 is decoded, the following cores are
magnetized: A15, B14 and B15; C13 and C15; D12, D13, D14, D15, D16,
D17 and D18; and E15. When a fraction, such as the fraction
three-eighths is decoded, the cores are magnetized in the pattern
corresponding to the fraction as shown in FIG. 4.
The output windings of the cores in each row of the matrix 208 are
tied together and to the input terminals of 23 "and" gates
210a-210n composing an electrical commutator 210. The read out
windings of the cores in each column are also coupled together and
tied through respective conductors 212, 213, 214, 215 and 216 to
the output terminals of the character position control circuits 190
and 193 associated with the upper New York Stock Exchange channel
and the lower American Stock Exchange channel, respectively. The
character position control circuits 190 and 193 control the
sequential read out of the information stored in the columns of the
core matrix 208. Specifically, when a signal is supplied through
the conductor 212, the signal demagnetizes the cores in column E
containing information such that signals from these demagnetized
cores are supplied to the input terminals of the "and" gates
210a-210n. Similarly, when gating pulses are supplied through
conductors 213, 214, 215 and 216, the cores in columns D, C, B, and
A, respectively, containing information will be demagnetized and
corresponding voltage signals will be supplied to the gates
210a-210n. The gates 210a-210n having bits of information supplied
thereto are sequentially enabled by the timing pulses T0-T22, as
will be more fully described hereinafter, and accordingly,
sequentially transmit the stored information.
To more fully understand the transfer of information from the core
matrix 208 to the electrical commutator 210, reference may be had
to FIGS. 1A and 2B. As above-mentioned, the character present
flip-flop 68 in the character advance control circuit 30 is set
when a character available signal is supplied from the six-bit
buffer 34. The setting of the flip-flop 68 implements the enabling
of either the gate 70 or the gate 72, the gate 70 being enabled
when a 7.5 level signal is present and the gate 72 being enabled
when a 15 level signal is present. Also, as above described, when
the "and" gate 70 is enabled, a pulse is transmitted by the gate to
the flip-flop circuit 78 to set the flip-flop. The flip-flop 78, in
turn, provides a shift pulse to the input terminal 80a of the
binary counter 80 to reset the counter. When the "and" gate 72 is
enabled, a pulse is transmitted directly to the input terminal 80a
of the counter 80 to reset the counter.
Upon the resetting of the counter 80, the count "a and" gate 82 is
enabled. Enabling of the gate 82 implements the loading of new
information bits 0-5 from the buffer 34 into the flip-flops 148-153
in the 32 character recirculating buffer 38 (FIG. 2A) and the
enabling of the "and" gate 92 in the offset counter programmer 94
(FIG. 2B). As above described, the "and" gate 92 is enabled with
the simultaneous application of the count 0 signal, the CPFF signal
and the reset level signal which is generated at a count of 262
lines and which has a pulse width of 32 microseconds (T0-T63). The
output terminal of the "and" gate 92 is coupled through a pair of
diodes 218 and 220 and corresponding conductors 221 and 222,
respectively, to the set input terminals of the last two stages in
a three stage binary counter 224. In the lower channel, the offset
counter programmer 100 is similarly connected to a three stage
binary counter 226. Accordingly, when the "and" gate 92 is enabled,
which is for the duration of the reset level signal, the last two
stages of the counter 224 are set into the "1" states such that the
counter has a count of 6. The binary counters 224 and 226 are reset
to counts of 0 respectively at the end of a count of 262 lines by
the leading edge of the reset level signal.
The output terminals of the three stages composing the counter 224
are coupled via six conductors 228 to the character position
control circuit 190 and to the shift signal generator 166. The
three stage binary counter 226 in the lower channel is similarly
connected via six conductors 230 to the character position control
circuit 194 and to the shift signal generator 176. The character
position control circuit 190 comprises the "and" gates 180, 182,
184, 186 and 188 which decode the count in the binary counter 224
into five line pulses Line 0, Line 1, Line 2, Line 3 and Line 4.
Accordingly, when the counter 224 counts from 0-4 and a u signal is
present (T0-T63) the gates 180, 182, 184, 186 and 188 are
correspondingly enabled and when the counter 224 accumulates a
count greater than 4, i.e., 5-7, the gates are disabled. The gates
180, 182, 184, 186 and 188 supply the pulses to the columns E, D,
C, B and A respectively of the core matrix 208 through the
conductors 212, 213, 214, 215 and 216, respectively, to
sequentially read out information from the cores. The output
terminals of the gates are also connected to corresponding gates in
the character position control circuit 193 in the lower channel
through the conductors 212, 213, 214, 215 and 216, respectively.
These gates are enabled when a u signal is present (T64-T127). As
above described, when the last stage u of the 128 binary counter 44
(FIG. 1B) is in the "0" state (T0-T63), a u signal from this stage
tends to enable the gates 180, 182, 184, 186 and 188. During the
count from T64-T127, a u signal is provided and this tends to
enable the gates of the character position control circuit 193 in
the lower channel.
The shift signal generator 166 is a three input "and" gate which is
enabled when a count of 6 is reached by the counter 224. When
enabled, the gate 166 supplies the line 6 signal through the
conductor 167 to the input terminal 164a of the "and" gate 164
within the recirculating buffer control circuit 98 (FIG. 2A). As
above-mentioned, the other input terminal 164b of the gate 164 is
coupled to the timing decode network 56 (FIG. 1B) which develops a
1/2 microsecond pulse T120 when a count of 120 is reached in the
counter 44. As shown in FIG. 2A, with the simultaneous application
of the T120 pulse and the line 6 signal to its input terminals 164a
and 164b, the gate 164 transmits the T120 pulse to the amplifier
116 which generates a shift pulse. This shift pulse is supplied
directly to the shift input terminals of the registers 136-141 and
through the "and" gate 118 to the shift input terminals of the
flip-flops 148-153 to implement the advancement and read out of the
stored character bits.
As above-mentioned, with the resetting of the two stage binary
counter 80 in the character advance control circuit 30, new bits of
information are shifted into the flip-flops 148-153 of the
recirculating buffer 38. From T0-T63 or 32 microseconds because of
the presence of the u signal, these bits are transmitted by the
"and" gates 154-159 of the gate 160 to the character matrix
generator 194 and stored therein. From T64-T127 because of the
presence of the u signal, the new bits loaded in the 32 character
recirculating buffer 40 of the lower channel are transmitted by the
gates 169-174 of the gate 168 to the character matrix generator 194
and stored therein. This alternate transmittal of the same bits
from the buffers 38 and 40 by the gates 160 and 168, respectively,
takes place for eight line time periods or until a line 6 signal is
generated by the shift signal generators 166 and 176.
Accordingly, when new bits are loaded into the flip-flops 148-153
of the buffer 38 and read out, these bits remain applied to the
input terminals of the gates 154-159 until a line 6 pulse is
generated. However, the line 6 pulse is generated immediately
because of the loading of a count of 6 into the three stage binary
counter 224. Accordingly, approximately 60 microseconds after new
bits are loaded into the flip-flops 148-153, the bits stored in the
first stages of the registers 136-141 are shifted into the
flip-flops 148-153 and read out. It will be noted that during this
time, that is, from T0 to T120, the bits from the upper and lower
32 character recirculating buffers 38 and 40 will have been
alternately stored in patterns corresponding to the letter or
figure corresponding to the new bits in the core matrix 208 of the
character matrix generator. The cores will not have been
demagnetized, however, since during this time, the line scanning
gates 180, 182, 184, 186 and 188 of the character position control
circuit 190 and the gates of the lower channel control circuit 193
will not have been enabled.
The three stage binary counters 224 and 226 are stepped by a T128
pulse supplied from the timing signal decode network 56 through a
conductor 235. Because the counters 224 and 226 had initially
loaded therein the number six, the first T128 pulse steps each of
the counters 224 and 226 to the number seven. The following T128
pulse steps each of the counters to 0. With a count of 0, the "and"
gate 180 in the character position control circuit 190 is enabled
for 32 microseconds (T0-T63) because of the presence of the u
signal and the magnetized cores in column E of the core matrix 208
are demagnetized. During the next 32 microseconds (T64-T127), the
cores of the matrix 208 are magnetized in an array corresponding to
the character transferred from the lower channel 32 character
recirculating buffer 40 and column E will be enabled by a
corresponding line 0 signal generated by the character position
control circuit 193.
As above-mentioned with reference to FIGS. 1B and 2C, the 23 gates
210a-210n of the commutator 210 are enabled by timing pulses T0-T22
to implement the sequential read out of the stored character
patterns. Specifically, the timing signal decode network 56
decodes, inter alia, the first five stages of the counter 44 into
23 timing pulses, T0-T22. These pulses are supplied from the
network 56 through a cable 237 to the other input terminals of the
gates 210a-210n in the commutator to thereby sequentially enable
the gates. Because the signals from column E of the core matrix 208
which correspond to the last line of the character transmitted from
the recirculating buffer 38 are present at the input terminals of
the gates 210a-210n for a period of 32 microseconds, T0-T63, these
bits are sequentially transmitted by the gates 210a-210n a total
number of two times. During the next 32 microseconds T64-T127,
column E of the core matrix 208 corresponding to the last line of
the character transmitted from the buffer 40 is enabled and these
signals are sequentially transmitted a total number of two times by
the gates 210a-210n.
The three stage binary counter 224 is then stepped to counts of 1,
2, 3 and 4 in the above-described manner by the application of the
T128 pulse and the gates 182, 184, 186 and 188 are sequentially
enabled to implement the gating of core columns D, C, B and A,
respectively, at T0-T63 and the signals read out from these core
columns are sequentially transmitted by the gates 210a-210n a total
of two times. Similarly, the lower channel three stage binary
counter 226 is stepped by the T128 pulse every 64 microseconds, the
gates of the character position control circuit 193 are
sequentially enabled at T64-T127 and the core columns D, C, B and A
are gated and the signals read out from these columns are
sequentially transmitted by the gates 210a-210n a total of two
times.
When the binary counters 224 and 226 accumulate counts of 5, 6 and
7, no transfer of information takes place. Hence, there is an
inactive period of three lines. However, when the counters 224 and
226 reach counts of 6, at T120, the contents of the recirculating
buffers 38 and 40 are advanced such that new characters from the
buffers 38 and 40 are alternately stored in the core matrix 208 of
the character matrix generator. The columns of the core matrix 208
are not gated until the counters 224 and 226 are reset to "0"
counts, respectively, as above-described.
The above sequence of operation continues until the 32 characters
stored in the recirculating buffers 38 and 40 are transmitted and
the patterns formed in the core matrix corresponding to the
characters are sequentially transmitted a total number of two
times. It will be noted that the character which was initially
loaded into the flip-flops 148-153 of the buffer 38 and the
flip-flops of the buffer 40 will not have been read out. As
above-described, a count 6 is initially loaded into both the
counters 224 and 226 such that the core magnetization patterns of
the core matrix 208 corresponding to the characters are never
enabled.
After a count of 262, the reset level signal is generated. This
reset level signal resets the three stage binary counters 224 and
226 and enables either the "and" gate 70 or the "and" gate 72 in
the character advance control circuit 30 depending upon whether a
7.5 level signal or a 15 level signal is present. If the "and" gate
70 is enabled, the gate 70 transmits a pulse which resets the
flip-flop 78. Resetting of the flip-flop 78 has no effect on the
two stage binary counter 80 such that the counter 80 remains reset.
However, resetting of the flip-flop 78 disables the "and" gate 96
in the recirculating buffer control circuit 98 such that the "and"
gate 118 and the "and" gates 124-129 remain enabled. Only when the
flip-flop 78 is set will the two stage counter 80 be advanced.
Accordingly, the count 0 "and" gate 82 will remain enabled and a 6
will be loaded into the three stage binary counter 224 through the
diodes 218 and 220. Because newest character bits are stored in the
first stage of the registers 136 and 141 and will be present at the
input terminals of the flip-flops 148-153, of the recirculating
buffer 38 (FIG. 1A, 2A), the same character bits are shifted into
the flip-flops 148-153 in the manner described above. This is
described in more detail relative to the description of the 15
level operation. It will be noted that because the character
present flip-flop remains in the "1" state, no transfer of bits
will occur between the gate 18 and the six-bit buffer 34 (FIG.
1A).
If, however, a 15 level signal is present, the "and" gate 72 will
be enabled and the two stage binary counter 80 will be stepped when
the reset level signal enables the gate 72. Stepping the binary
counter 80 to a count of 1 enables the count "1 and" gate 84. It
will be noted that because the count 0 "and" gate 82 is disabled,
the "and" gate 96 in the recirculating buffer control circuit 98 is
disabled. This precludes the transfer of new character bits into
the buffer 38. Application of the reset level signal enables the
"and" gate 112 such that a shift pulse is supplied to both the
flip-flops 148-153 and the registers 136-141 and the bits stored in
the first stages of the registers 136-141 are transferred into the
flip-flops 148-153 respectively. It will be noted that the bits
stored in the first stages of registers 136-141 are the bits which
had been shifted into the flip-flops 148-153 from the "and" gates
124-129, respectively at the start of the operation, that is, when
the character present flip-flop 68 was initially set. This is true
because there are 32 shift pulses (line 6, T120) every 2621/2 lines
and after 32 shift pulses, the characters initially loaded into the
flip-flops 148-153 will have been shifted down to the first stages
of the registers 136-141.
Setting of the count "1 and" gate implements the enabling of the
"and" gate 104 in the offset counter programmer 94. The "and" gate
104 is coupled through a diode 240 to the conductor 221 which leads
to the last stage of the three stage binary counter 224. When the
gate 104 is enabled by the reset level signal, the CPFF signal and
the count 1 signal, the gate supplies a pulse through the diode 240
to the set input terminal of the last stage flip-flop in the
counter 224 to set the flip-flop into the "1" state. The counter
224 therefore has a count of 4. Setting a count of 4 into the
counter 224 implements the enabling of the line "4 and" gate for
the time period T0-T63 (u) and column A of the core matrix 208 is
enabled. Thereafter, upon the application of the T128 pulse to its
input terminal, the three stage binary counter 224 the counter
accumulates counts of 5, 6 and 7 during which there is no transfer
of information from the core matrix 208 to the electrical
commutator. However, when the counter 224 reaches a count of 6, the
shift signal generator 166 generates a line 6 signal which,
together with a T120 signal, implements the further shifting of the
contents in the recirculating buffer 38. It will be noted that
there is a delay of four lines or 256 microseconds (4 .times. 64)
between the start of the operational cycle and the time when an
entire pattern of cores corresponding to a character is read out
from the core matrix 208.
During the third operational cycle when a 15 level signal is
present, the two stage binary counter 80 in the character advance
control circuit 30 will be stepped to a count of 2 with the
application of the reset level signal after 262 lines. Stepping of
the counter 80 to a count of 2 enables the count "2 and" gate 86
which, in turn, and together with the reset level signal enables
the "and" gate 106 in the offset counter programmer 94. The output
terminal of the gate 106 is coupled through a diode 241 to the
conductor 222 and conducted thereby to the set input terminal of
the second stage in the binary counter 224. This sets the second
stage flip-flop into the "1" state such that a count of 2 is loaded
into the counter. Accordingly, the line 2 "and" gate 184 in the
character position control circuit 190 will be enabled and will
enable column C of the core matrix 208. Again, the matrix 208 will
have stored therein a coded pattern corresponding to the character
shifted from the first stages of the registers 136-141 into the
flip-flops 148-153, respectively, upon the application of the reset
level signal. This character was initially loaded into the
flip-flops 148-153 via the gates 130-135, respectively, during the
first operational cycle, as above-described.
As the binary counter 224 is stepped every 64 microseconds by the
T128 pulse to counts of 3, 4, 5, 6 and 7, it can be seen that
three-fifths of the coded pattern of magnetized cores, that is,
columns C, B and A of the core matrix 208, corresponding to the
decoded character will be enabled and read out. During the third
operational cycle, there is a lag of six lines between the start of
the cycle and the time when an entire pattern of cores
corresponding to a character is read out from the core matrix.
During the fourth 15 level operational cycle, the counter 80 is
stepped to a count of 3 to implement the enabling of the count 3
"and" gate 88. When enabled, the gate 88 supplies a pulse to the
reset input terminal 68c of the character present flip-flop 68 to
reset the flip-flop. This signifies that the 32 character
recirculating buffer 38 is able to accept an additional character,
as above-described. As above-mentioned, the reset level signal
resets the binary counters 224 and 226 at the end of every
operational cycle. Accordingly, when the counter 80 in the
character advance control circuit 30 steps to a count of 3, the
three stage binary counter 224 has a zero count therein. Moreover,
the stages of the counter are not externally triggered into the "1"
states as during the first, second and third cycles such that the
counter retains a "0" count. With the binary counter 222 having a 0
count, the line "0 and" gate in the character position control
circuit 190 will be enabled from T0-T63 (u) and generate a line 0
signal. This signal enables the column E of the core matrix 208.
Thereafter as the counter is stepped from a count of 0 to a count
of 4, the remaining core columns D, C, B and A are enabled such
that the entire coded array corresponding to the character
initially loaded into the recirculating buffer 38 is read out.
With a 7.5 level signal present, the read out of the entire
character occurs in the seventh operational cycle. Specifically,
beginning with the two stage binary counter 80 being initially
reset to 0, the first two operational cycles begin with a count of
6 being loaded into the binary counter 224 such that a full
character is read out after a delay of two lines. During the next
two cycles, the binary counter 224 has a count of 4 loaded therein
such that one core column E of the newest character is read out and
there is a full character read out of a previously stored character
after a delay of four lines. In the fifth and sixth cycles, the
binary counter 224 has a count of 2 loaded therein such that three
core columns, E, D and C, of the newest character are read out and
there is a full character read out of a previously stored character
after a delay of six lines. Finally, in the seventh and following
cycles, no count is loaded into the counter 224 such that all five
core columns E, D, C, B and A of the newest character are read out
and there is a delay of eight lines before the next previously
stored character is read out. It may be noted that following the
seventh cycle, new character bits will be accepted by the 32
character recirculating buffer 38 such that the above described
operational sequence will occur. This is true because the character
present flip-flop 68 in the character advance control circuit 30 is
reset when a count of 3 is accumulated by the two stage binary
counter 80.
As above described with reference to FIGS. 2B and 2C, when the line
"0 and" gate 180 in the character position control circuit 190 of
the upper channel is enabled, column E of the core matrix 208 is
enabled by the line 0 signal and the core output signals are
supplied to the gates 210a-210n of the electrical commutator 210.
The timing pulses T0-T23 enable the gates 210a-210n a total number
of two times in the first 32 microseconds to implement the double
transmission of the column E core signals. During the next 32
microseconds (T64-T127) with the u flip-flop of the counter 44 in
the "1" state, the line "0" "and" gate in the character position
control circuit 193 is enabled and column E of the core matrix 208
is enabled by the line 0 signal. Again, the core output signals are
sequentially transmitted twice by the gates 210a-210n. The above
operation repeats itself as the counters 224 and 226 are stepped
from counts of 0 through counts of 4 and the core columns D, C, B
and A are enabled by the lines 1, 2, 3 and 4 signals,
respectively.
As shown in FIG. 1B, from the gates 210a-210n, the enabled core
signals are supplied to the input terminal of a masking circuit
244. The masking circuit 244, which may comprise conventional
gating circuitry, is also coupled via the conductors 179 and 192 to
the opposite output terminals of the last stage flip-flop u in the
128 bit counter 44 and via conductors 245 and 246 to the output
terminals of the next-to-last stage flip-flop v in the counter 44.
The masking circuit 244 passes the sequentially transmitted core
signals when the v flip-flop is set to the "1" state and the u
flip-flop is reset to the "0" state (T32-T63 or v.sup.. u) and
passes the core signals when the v flip-flop is set to the "0"
state and the u flip-flop is set to the "1" state, (T96-T127 or
v.sup.. u). Obviously, the durations of the core output signals
must last long enough to enable the gates and therefore, the core
output signals, to be sampled sequentially by T0 to T22 pulses.
Accordingly, from T0-T31, no signals are transmitted and from
T64-T95 no core signals are transmitted.
The masked core signals are then sequentially supplied to a pulse
shaping network 248, which may, for example, comprise an "and" gate
and which is also supplied with 1/2 microsecond pulses from the 2
mH/s clock 42 through a conductor 249. In the network 248, the 1/2
microsecond pulses are transmitted whenever a core output signal is
present at the other input terminal of the network 248. Hence, in
this manner the core signals are shaped into 1/2 microsecond
pulses.
Thereupon, the 1/2 microsecond pulses are supplied to the video
driver circuit 60 wherein the signals are combined with the
vertical and horizontal sync pulses generated by the generator 58.
From the video driver 60, the combined signals are coupled to an
image reproducing device 250, which may be, for example, a cathode
ray tube, for reproduction. As above mentioned, the horizontal and
vertical sync pulses are also supplied to the scanning wave
generator 62 which develops line deflecting and field deflecting
sawtooth waves. From the scanning wave generator 62 the line
deflecting and field deflecting sawtooth waves are supplied to the
horizontal deflection coils and vertical deflection coils,
respectively, of the scanning yoke 252 of the image reproducing
device 250. The deflection coils of the yoke 252 are rotated
90.degree. such that the horizontal deflection coils produce a
vertical scan and the vertical deflection coils produce a
horizontal scan. Specifically, the horizontal scan caused by the
vertical deflection coils occurs from right to left across the face
of the image reproducing device 250 and takes place in
approximately one-sixtieth of a second. The vertical scan caused by
the horizontal deflection coils occurs from top to bottom of the
image reproducing device 250 and consumes 64 microseconds.
Accordingly, the information is displayed as precessing from right
to left across the face of the image reproducing device 250.
FIG. 5 illustrates a typical picture provided by the image
reproducing device 250. It will be noticed that the first and third
quarters of the screen are blank. This is because of the above
described masking action performed by the masking circuit 244. Each
reproduced character occupies five vertical lines with three lines
spacing adjacent characters. The effect of smooth motion by the
reproduced characters is controlled by the offset counter
programmers 94 and 100 and by their associated three stage binary
counters 224 and 226, respectively. As above described, when new
character bits are loaded into the recirculating buffers 38 and 40,
there is an incremental displacement of two lines in the display of
the characters between consecutive field scansions when a 15 level
signal is present. Accordingly, the character progression speed is
15 characters per second. When a 7.5 level signal is present, the
incremental displacement of two lines occurs during successive
frame scansions and the character progression speed is therefore
7.5 characters per second. In this manner, either the upper display
or the lower display will appear to move across the face of the
image reproducing device at twice the speed of the other display if
a 15 level signal is present in that channel and a 7.5 level signal
is present in the other channel.
Although the invention has been described herein with reference to
a specific embodiment many modifications and variations therein
will readily occur to those skilled in the art. Accordingly, all
such variations and modifications are included within the intended
scope of the invention as defined by the following claims.
* * * * *