U.S. patent number 3,673,579 [Application Number 05/070,626] was granted by the patent office on 1972-06-27 for drawingboard ii, a graphical input-output device for a computer.
Invention is credited to Robert Michael Graven.
United States Patent |
3,673,579 |
Graven |
June 27, 1972 |
DRAWINGBOARD II, A GRAPHICAL INPUT-OUTPUT DEVICE FOR A COMPUTER
Abstract
A two-dimensional matrix of semi-conductors is arranged in
ordered array as a flat, light emitting and light sensing device
activated both electrically and by radiant energy from a penlight
to achieve a graphical input and output display by the active or
inactive condition of the light emitter with circuitry for control
of flow of graphical data into and out of the device for use in
conjunction with a digital computer.
Inventors: |
Graven; Robert Michael (Orinda,
CA) |
Family
ID: |
22096439 |
Appl.
No.: |
05/070,626 |
Filed: |
August 26, 1970 |
Current U.S.
Class: |
365/114; 341/31;
250/214LS; 345/183 |
Current CPC
Class: |
G06F
3/03542 (20130101); G06F 3/033 (20130101); G06F
3/04845 (20130101) |
Current International
Class: |
G06F
3/033 (20060101); G11c 013/04 () |
Field of
Search: |
;250/213A,214P,217SS
;340/324R,172.5 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Fears; Terrell W.
Claims
I claim:
1. A graphical input-output device for a computer comprising a
plurality of light emitter-sensor circuits juxtaposed in a common
plane and arranged in ordered array, means for electrically
activating and deactivating said light emitters, means for emitting
radiant energy for activating said light sensors, means for
connecting said emitter-sensor circuits to a computer, and means
for controlling the flow of information represented by the
activated and inactivated status of said emitters from and to said
computer.
2. The graphical input-output device for a computer as claimed in
claim 1 wherein said means for electrically activating and
deactivating said light emitters includes means for identifying by
an address each emitter-sensor circuit according to a code, means
for decoding a given address and activating said emitter at said
address, means for encoding the address of an activated emitter and
means for transmitting said encoded address to said computer.
3. The graphical input-output device for a computer as claimed in
claim 1 wherein said means for electrically activating and
deactivating said light emitters includes means for identifying by
an address various sub-pluralities of emitter-sensor circuits,
means for activating said emitters of said sub-pluralities, means
for encoding said address and means for transmitting said encoded
address to said computer.
4. The graphical input-output device for a computer as claimed in
claim 1 wherein said means for controlling the flow of information
represented by the activated and inactivated status of said
emitters comprises means for receiving information from said
computer and distinguishing between control information and address
information, and means for controlling the flow of coded and
decoded address information into and out of said plurality of
emitter-sensor circuits using said control information.
5. The graphical input-output device for a computer as claimed in
claim 1 wherein said plurality of light emitter-sensor circuits are
arranged in rows and columns, said rows defining a Y-direction or
coordinate and said columns defining an X-direction or
coordinate.
6. The graphical input-output device for a computer as claimed in
claim 1 wherein said means for activating said sensors is a
penlight comprising a write end and an erase end, a light source at
each of said ends, means for activating said light sources, means
for connecting said penlight to said means for electrically
activating and deactivating said light emitters and means for
connecting said penlight to said means for controlling the flow of
information from and to said computer.
7. The graphical input-output device for a computer as claimed in
claim 6 wherein said penlight write end comprises means for marking
a surface and said penlight erase end comprises means for removing
marks made by said means for marking.
8. The graphical input-output device for a computer as claimed in
claim 6 wherein said penlight comprises means for controlling the
intensity of said light sources.
9. The graphical input-output device for a computer as claimed in
claim 1 wherein said emitter-sensor circuit comprise means for
maintaining said light emitter in the activated state when
activated and in the deactivated state when not activated.
10. The graphical input-output device for a computer as claimed in
claim 9 wherein said means for maintaining said light emitters in
either the activated or deactivated state comprises a pnp-npn
transistor pair.
11. The graphical input-output device for a computer as claimed in
claim 1 wherein said emitter-sensor circuit comprises means for
storing information concerning the activated and inactivated status
of said emitter.
12. The graphical input-output device for a computer as claimed in
claim 1 wherein said ordered array of said light emitter-sensor
circuits comprises means for activating all of said emitters from a
common circuit, means for deactivating all of said emitters from a
common circuit and means for detecting the status of all of said
individual emitters from a common circuit.
13. The graphical input-output device for a computer as claimed in
claim 1 wherein said emitter-sensor circuits comprise means for
detecting light intensities by said light sensors and means for
controlling the light intensity emitted by said light emitters.
14. The graphical input-output device for a computer as claimed in
claim 1 wherein said emitter-sensor circuits comprise means for
individually controlling the intensity of light emitted by each of
said light emitters.
15. The graphical input-output device for a computer as claimed in
claim 1 wherein said emitter-sensor circuits comprise means for
controlling the intensity of light emitters.
16. The graphical input-output device for a computer as claimed in
claim 1 wherein said light emitter-sensing circuits comprise means
for emitting light, means for energizing said means for emitting
light and means for deenergizing said means for emitting light.
17. The graphical input-output device for a computer as claimed in
claim 16 wherein said means for energizing said means for emitting
light comprises means for detecting radiant energy and said means
for deenergizing said means for emitting light comprises means for
detecting radiant energy.
18. The graphical input-output device for a computer as claimed in
claim 16 wherein said means for energizing said means for emitting
light comprises a transistor and said means for deenergizing said
means for emitting light comprises a transistor.
19. The graphical input-output device for a computer as claimed in
claim 16 wherein said means for emitting light is a light emitting
diode.
20. The graphical input-output device for a computer as claimed in
claim 16 further comprising means for detecting the activated or
inactivated status of said mean for emitting light.
21. The graphical input-output device for a computer as claimed in
claim 1 wherein said means for controlling the flow of information
from and to said computer includes means for interrupting the flow
of information to said computer.
22. The graphical input-output device for a computer as claimed in
claim 1 wherein said means for controlling the flow of information
from and to said computer comprises a drawingboard processor unit,
means for placing information into said array, and means for
reading information represented by the activated or inactivated
status of said emitters out of said array.
23. The graphical input-output device for a computer as claimed in
claim 22 wherein said means for placing information into said array
comprises an input register having input and output lines, and an
input parts register having input and output lines, said output
lines of said input register connected to said emitter-sensor
array, said input lines of said input register connected to said
output lines of said input parts register and said input lines to
said input parts register connected to said processor unit.
24. The graphical input-output device for a computer as claimed in
claim 22 wherein said means for reading information out of said
array comprises an output register having input and output lines an
output parts register having input and output lines, and a
drawingboard output register having input and output lines, said
input lines of said output register connected to said array, said
output lines of said output register connected to said input lines
of said output parts register, said output lines of said output
parts register connected to said input lines of said drawingboard
output register and said output lines of said drawingboard output
register connected to said computer.
25. The graphical input-output device for a computer as claimed in
claim 23 further comprising means for decoding addresses defining a
particular emitter-sensor circuit of said array having an input and
an output, said output connected to said input parts register, said
input connected to said drawingboard processor unit.
26. The graphical input-output device for a computer as claimed in
claim 24 further comprising means for encoding addresses defining a
particular emitter-sensor circuit of said array having an input and
an output, said input connected to said output register and said
output connected to said drawingboard output register.
27. The graphical input-output device for a computer as claimed in
claim 22 wherein said drawingboard processor unit comprises means
for receiving coded address and control information from an
incoming signal and distinguishing said address information from
said control information, means for decoding said control
information having an input and an output, said input connected to
said means for receiving coded information, means for decoding said
address information having an input and an output, means for
interconnecting the output of said means for decoding of said
control information for control of flow of address information to
said array of said emitter-sensor circuits.
28. The graphical input-output device for a computer as claimed in
claim 26 wherein said drawingboard processor unit further comprises
means for encoding address information in accordance with the
active or inactive status of said emitter-sensor circuits of said
array and means for interconnecting the output of said means for
decoding control information and said means for encoding said
address information for control of flow of address information out
of said array of emitter-sensor circuits to said computer.
29. The graphical input-output device for a computer as claimed in
claim 22 wherein said drawingboard processor unit includes means
for associating a label with the activated or inactivated status of
emitters in said array.
30. The graphical input-output device for a computer as claimed in
claim 22 wherein said drawingboard processor unit includes means
for storing address and control information for later use in
operating said device.
31. The graphical input-output device for a computer as claimed in
claim 22 wherein said means for reading information includes means
for detecting incremental variations in graphical information
displayed in said array.
32. The graphical input-output device for a computer as claimed in
claim 30 wherein said drawingboard processor unit further comprises
a primary input register for receiving address and control
information from said computer and means for transferring said
address information into said means for storing address and control
information and means for transferring address and control
information out of said means for storing address and control
information to operate said array.
33. The graphical input-output device for a computer as claimed in
claim 1 wherein said emitter-sensor circuit comprises means for
controlling the sensitivity of said light sensors to various levels
of light intensity.
Description
BACKGROUND OF THE INVENTION
This invention relates generally to registers and in particular to
electrical calculators of the hybred type.
Various devices have been used in the past for placing graphical
data into a computer and for display of graphical data generated by
a computer.
Cathode ray tube displays have been used with a light pen having a
photo sensitive cell directed at the display on the surface of the
tube to pick out or place a point in the display.
Other devices use a flat matrix of electrical terminals which are
connected to a computer and a metal stylus also connected to the
computer which acts as a writing instrument when applied to and
traced across the surface of the matrix.
Still other devices use photosensitive materials for receiving
information but do not display information back from the same plane
of the device after it is entered or processed by the computer. Few
of the graphical input-output devices of the prior art provide
circuitry which can control the flow of graphical information into
and out of the device which is separate and apart from the
computer.
SUMMARY OF THE INVENTION
The device of the present invention is a flat graphical
input-output device for a computer using light sensors to receive
information, with light emitters juxtaposed adjacent corresponding
sensors to display information. A penlight, i.e., a "pen" or light
emitting writing instrument, is held in the hand of the operator
and is used to activate the light sensors. A processor unit is used
to control the flow of information into and out of the device for
operation with a computer. The processor unit circuitry provides
for activating, deactivating and determining the status of each
emitter in accordance with either a coded or uncoded signal. The
processor unit also is arranged to activate rows, columns and
blocks of emitters as desired.
It is, therefore, an object of the present invention to provide a
graphical input-output device for a computer.
It is another object of the present invention to provide a
graphical input-output device for a computer having individual
point control using a coded or uncoded address.
It is still another object of this invention to provide a graphical
input-output device for a computer in which the flow of information
into and out of the device is separately controlled.
It is another object of this invention to provide a graphical
input-output device for a computer in which logical information is
associated with the positional information in the graphical
display.
It is another object of this invention to provide a graphical
input-output device for a computer in which a penlight is used for
graphical input.
It is another object of the present invention to provide a
graphical input-output device for a computer in which photon output
of the penlight is controllable for shading the graphical input and
output.
It is another object of the present invention to provide a
graphical input-output device for a computer in which the photon
output of the graphical display is controllable for information
output.
It is still another object of the present invention to provide a
graphical input-output device for a computer having apparatus for
performing programmed switching routines for special displays,
operating commands and manipulation of graphical data.
Other and more particular objects of the present invention will be
manifest upon study of the following detailed description when
taken together with the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is an isometric view of the graphical input-output device of
the present invention,
FIG. 2 is a plan and elevational view of a typical emitter-sensor
pair,
FIG. 3 is a logic diagram of a typical "point" defined by a light
emitter-sensor pair,
FIG. 3A is a more detailed circuit diagram of a typical
"point,"
FIG. 4 is a symbol list defining some of the symbols used in the
drawings,
FIGS. 5A and 5B is a single line block diagram of the circuitry of
the present invention showing the interconnection of the various
control units used to operate the device,
FIG. 6 is a circuit diagram showing the connection of primary input
register, operations decoder, "B" AND and "C" AND gates, local
memory, "F" AND and "G" OR gates, and memory OR gates,
FIG. 7 is a circuit diagram of control registers SR(0) through
SR(3) of the drawingboard processor unit,
FIG. 8 is a circuit diagram of control registers SR(4) through
SR(6) of drawingboard processor unit,
FIG. 9 is a circuit diagram of the "W" control gates of the
drawingboard processor unit,
FIG. 10 is a circuit of the X-input, X-output and X-parts registers
as connected to the drawingboard,
FIG. 11 is a circuit diagram of the Y-output register and the XY-,
Z'-, and the Z-registers for transmitting the graphical information
to the computer,
FIG. 12 is an elevational view of a typical penlight used to place
information into and erase information from the graphical device of
FIG. 1 along with details of circuitry for connecting it to the
device,
FIG. 13 is a circuit diagram of the input character gates register
of the drawingboard processor unit,
FIG. 14 is a circuit diagram of an instruction logic device used to
measure incremental variations in the graphical display,
FIG. 14A is a circuit diagram of a typical timing chain device used
in FIG. 14,
FIG. 14B is a circuit diagram of a device to direct X- and Y-adders
to add or subtract one binary digit from the address,
FIG. 15 is a diagram of typical pulse wave forms of the timing
device of FIGS. 14, 14A and 14B.
FIG. 16 is a circuit diagram of a corner of the array showing a
typical "point" and its interface with peripheral circuitry to the
board.
FIG. 17 is a circuit diagram showing the X-decoder in greater
detail,
FIG. 18 is a circuit diagram showing the Y-decoder in greater
detail,
FIG. 19 is a circuit diagram showing the X-encoder in greater
detail,
FIG. 20 is a circuit diagram showing the Y-encoder in greater
detail.
DESCRIPTION OF THE PREFERRED EMBODIMENT
With reference to FIG. 1, the graphical input-output device of the
present invention comprises, basically, a write and display board
20, i.e., input-output drawingboard 20, which is mounted on an
electronic and power supply cabinet 21 having a control panel 22 on
the front thereof.
A penlight 23 is electronically connected to board 20 by two or
more conductors 86 and 86', 24 and 25 for control of the light
output of the penlight as will be described below, and for control
of information placed in the board. Board 20 further comprises
modular emitter-sensor circuit units or "points" 26 shown typically
in FIGS. 2 and 3 arranged in an array 35 (FIG. 1) of horizontal and
vertical rows and columns respectively.
Referring to FIG. 2, a modular emitter-sensor pair or "point" 26 is
shown in plan and elevation and comprises a compartment in block 27
containing local circuitry, on the top surface of which is mounted
a light emitter 28 and a light sensor 29 along with other light
sensors further described below. Light emitters 28 may be any light
emitting means such as an incandescent or neon glow lamp, however,
the present device is arranged to utilize a semi-conductor device
such as a light emitting diode common in the art.
Light sensor 29 is, as used in the present embodiment, a
semi-conductor device sensitive to electromagnetic radiation.
To protect emitter 28 and sensor 29 from damage, a transparent
surface 30 is disposed over the entire surface of array 35.
FIG. 3 illustrates a simplified logic diagram for a typical "point"
i.e., emitter-sensor pair circuit 26. Such a "point" 26 comprises
an X-sense diode 31 connected on its anode side to X-conductor 32
and a Y-sense diode 33 connected on its anode side to Y-conductor
34. The cathode sides of X- and Y-sense diodes 31 and 32 are
connected in common to the output of AND gate 36 and the output of
light sensor 29 through pointing circuit 50.
Light emitting diode 28 and one of the inputs to AND gate 36 are
connected to the output of memory circuit 37. The other input of
AND gate 36 is connected to READ conductor 38 while the two inputs
to memory circuit 37 are connected to WRITE conductor 39 and ERASE
conductor 40.
With reference to FIG. 3A, a more detailed circuit diagram of a
typical point 26 is shown.
The reference numerals of corresponding parts of the circuit of
FIG. 3 and 3A are identical.
The identification of each circuit element and its value, where
applicable, is listed in Table 1. The number-letter combination
under "Type" is the present industrial standard designation for the
semi-conductor device used.
Table 2 is a listing of the values for resistors 172 and 173
necessary to change the state of the bi-stable circuit of FIG. 3A.
The sensitivity range is generally descriptive. The measured values
would range from about 100 foot-candles for an "intense" light to
about 0.5 foot-candles for "shadow" light.
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TABLE 1
Ref. No. Type or Value Purpose 160 2N2219 Computer write transistor
161 2N2219 Computer erase transistor 162 1N 2175 Optical write
transistor 163 1N2175 Optical erase transistor 164 2N3135 Bi-stable
pnp transistor (for memory) 165 2N2219 Bi-stable npn transistor
(for memory) 166 2N2219 Driver transistor 29 1N2175 Optical
pointing transistor 167 2N4409 Inverting driver transistor 28
MVE100 Light emitting diode 169 1N643 Bias diode 170 1N643 Bias
diode 171 1N56AG Isolating diode 33 1N56 AG Y-sense diode 31 1N56
AG X-sense diode 172 10 K Enable sensitivity resistor 173 10 K
Disable sensitivity resistor 174 100 ohms Light emitting diode
(LED) current limiting resistor 175 10 K Transistor 166 current
limiting resistor 176 10 K Bias resistor 177 1 K Transistor 167
current limiting resistor 36 SN7402 NOR gate
__________________________________________________________________________
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Table 2
Value of Resistors Light Level 172 and 173 1 K Intense 10 K Room
lamp 100 K Dim 1 Meg Shadow
__________________________________________________________________________
From FIG. 3A, WRITE conductor 39 enters circuit 26 through
transistor 160 while ERASE conductor 40 enters the circuit through
transistor 161 for computer control of the WRITE-ERASE function.
The same function can be performed using penlight 23 by activating
light sensor 162 to write or light sensor 163 to erase.
Memory is achieved through bi-stable transistors 164 and 165 which
"lock in" the "on" or "off" status of the point, i.e., whether or
not a current is flowing through light emitting diode 28.
To activate the point, penlight 23 is pointed at light sensing
transistor 162 and light sources 88 (FIG. 12) are energized to
shine on sensor 162 causing a current to flow through the
transistor, applying a voltage to one side of light emitting diode
28 causing a current to flow therethrough.
To deactivate the point, penlight 23 is pointed at light sensing
transistor 163 and light sources 88' are energized to shine on
sensor 163 reducing its resistance to a value sufficient to lower
the voltage across light emitting diode 28 to limit the current
therethrough sufficient to turn diode 28 off.
For consistency and understanding of the drawings, FIG. 4 defines
the symbols used in the drawings.
OR gate 41 of FIG. 4 is a semi-conductor device having two or more
inputs and one output. A signal, i.e., a voltage pulse, on either
of the inputs on the left will appear on the output (right) side of
the device. AND gate 42 of FIG. 4 is a semi-conductor device having
two inputs, both of which must be activated, i.e., have a voltage
on the input conductors, for a signal to appear on the output
side.
"D" type flip-flop 43 is a bi-stable semi-conductor device having a
signal input 44 and a "clock" input 45, a reset input 46 and two
logical complimentary out-put conductors 47 and 48.
Activation of clock input 45 will permit a signal on input 44 to
pass to output conductors 47 and 48.
Activation of reset input 46 causes all flip-flops 43 to return to
a logical zero or "off" position.
Inverting amplifier 49 is a device common in the art for producing
the logical compliment of a digital signal.
With respect to the entire system, FIGS. 5A and 5B, shown on two
sheets, is a single line block diagram showing the interconnection
of the basic electronic switching units which serve to control the
flow of information into drawingboard 20 and also to and from the
computer (not shown)through drawingboard 20 for the manipulation of
the data contained therein.
The computer that is used in conjunction with the device of the
present invention can be any digital computer common in the art
which can receive, manipulate and transmit information coded in a
manner to identify individual bits of information, for example, in
the form of voltage pulses on various combinations of conductors or
lines leading into and out of the present device.
The blocks in FIGS. 5A and 5Brepresent switching circuits which
comprise basically combinations of ANDand ORgates and flip-flop
devices with the exception of local memory 106 which may be any
type of device common in the art which can temporarily store
information. A magnetic core memory common in the art would be one
example.
With particular reference to FIG. 5A, there is illustrated the
circuits associated with drawingboard 20 used to place information
into the board and read information stored in the board.
Basically, drawingboard 20 comprises a 16 by 16 array 35 of
"points" 26 having sixteen X-conductors 32 (FIG. 3 and 3A) arranged
parallel and equally spaced in a common plane with sixteen
Y-conductors 34 arranged parallel and equally spaced normal to
X-conductors 32 in said common plane.
A "point" 26 is connected at the intersection of each X- and
Y-conductor 32 and 34, respectively.
Array 35, therefore, comprises 256 "points" 26 arranged in 16
horizontal and 16 vertical rows and columns, with each "point" 26
comprising the elements of the circuit of FIG. 3A. FIG. 16 shows
array 35 comprising read, write and erase gate registers 154, 155
and 156, respectively, whose outputs are connected to conductors
38, 39 and 40 through read, write and erase point AND gates 157,
158, and 159, respectively.
Thus activation of any of the conductors 38, 39 or 40 will cause
data in array 35 to be, respectively, read written, or erased by
the computer (not shown) from array 35.
It will be noted that through the use of penlight 23, as previously
discussed and shown in FIG. 3A, an individual "point" 26, may be
read, written or erased by appropriate photoactivation of
transistors 29, 162 or 163, respectively.
To the left and bottom of array 35 (FIG. 5A) are input sides 53Y
and 53X. To the right and top of array 35 are the output sides 54Y
and 54X.
The input circuitry for the device of the present invention
comprises, for the X-sense (X-coordinate), X-input register 56
whose output is connected to X-input side 53X, X-input parts
register 57 whose output is connected to the input side of X-input
register 56 and whose various inputs are connected to drawingboard
processor unit 100 (FIG. 5B).
The output of X-address decoder 58 is connected to the input of
X-input parts register 57 while the input side of X-address decoder
58 is connected through XCD gates 115 to drawing board processor
unit 100 (FIG. 5B).
In a like manner for the Y-sense (Y-coordinate), the output side of
Y-input register 60 is connected to input side 53Y of array 35
while the input side of register 60 is connected to the output side
of Y-input parts register 61. The output of Y-address decoder 62 is
connected to the input side of Y-input parts register 61 while the
inputs of both Y-address decoder 62 (through YDC gates 120) and
Y-input parts register 61 are connected to drawingboard proccessor
unit 100.
The output circuitry for the device of the present invention
comprises, for the X-sense (X-coordinate), X-output register 64
whose input is connected to X-output side 54X, X-output parts
register 65 whose input is connected to the output of X-output
register 64.
It will be noted that the output of X-output register 64 is also
connected to the input of X-address encoder 66 whose output is
connected both to multiple input OR gate XOOR 150 and XEC gates
register 81 (FIG. 17).
In a like manner, for the Y-sense (Y-coordinate), the input side of
Y-output register 68 is connected to Y-output side 54Y, while its
output side is connected to the input side of Y-output parts
register 69.
It will also be noted that the output of Y-output register 68 is
connected to the input of Y-address encoder 70 whose output is
connected both to multiple input OR gate YOOR 151 and YEC gates
register 124 (FIG. 18).
Both X- and Y-output parts registers 65 and 69 are connected to
drawingboard output register 73 whose output is connected to the
computer (not shown).
All registers, it will be noted, are connected to drawingboard
processor unit 100.
DRAWINGBOARD PROCESSOR UNIT
FIG. 5B shows the interconnection of the various block circuits
contained in the drawingboard processor unit 100.
Basically, drawing board processor unit 100 comprises a primary
input register 101, whose output is variously connected to
operations decoder 102, "C" AND gates register 103, "B" ANDgates
register 104 and instruction logic circuit 152.
Operations decoder 102 is variously connected to local memory 106,
"F" AND gates register 107, "address code" status register SR(0)
108, "input part" status register SR(1) 109, "output parts" status
register SR(2)110, "read status" status register SR(3)111, "labels"
status register SR(4) 112, "location storage"status register
SR(5)113, and "memory buffer"status register SR(6) 114 and
instruction logic circuit 152.
Drawingboard processor unit 100 further comprises, input character
gates register 116, "W" gates register 117, "G" OR gates register
118, and memory OR gates register MOR 119.
To describe the device of the present invention in detail, certain
conventions will be used to organize the material. The letters
"A"through "Z" are used to identify the lines or circuits
interconnecting the various circuit units or blocks. For example,
line A(1) designates line "1" of circuit "A," X(0- 7)designates
lines "0" (zero)through "7" of circuit "X."
Certain abbreviations may be used which will be self evident such
as "XIP" for X-inputs parts register; "YOP" for Y-output parts
register and "SR" for status register.
Since certain commands are required for various control functions,
these are designated by the command number contained in a circle
when shown on the drawings and preceded by an asterisk "*" when
discussed in the specification. For example, a command identified
by "03" in a circle on a drawing is identified as "*03" in the
specification.
The arrows which are incorporated into the circuit lines represent
the flow of information or data through drawingboard 20 and
processor unit 100 in accordance with the direction of the
arrow.
As for detailed discussion of the circuit units of the present
invention, it is apparent to one skilled in the art that the use of
AND gates, OR gates and flip-flop devices in switching circuits is
common in the art and the function of each individual circuit
element can be followed by such person without further detailed
explanation.
To describe in detail the individual circuit units of drawingboard
processor unit 100, reference is made to FIG. 6 and beginning in
particular to primary input register 101.
Primary input register 101 comprises a plurality, sixteen in the
present embodiment, of flip-flop circuit units 121 having outputs
A(0) through A(15). The input signal enters register 101 in a
manner such that the first five "bits," A(0) through A(4) of
information are an encoded "command" signal; the next three "bits,"
A(5), A(6), and A(7) are an encoded instructional signal also
identified as lines I(0), I(1) and I(2), respectively; and the
remaining eight "bits" are an encoded X-Y address signal for a
particular "point" 26, four "bits"for the X-address and four "bits"
for the Y-address.
Operations decoder 102 comprises a set of input OR gates 122, a
decoder unit 105 common in the art which converts the "on" or
"off"status of either lines A(0-4) or E(0-4) to a pulse or signal
on any one of 00 to 37 (octal) outputs on 32 lines (decimal).
Command lines *01 through *37 are connected to the registers for
control of array 35 The detailed operation of each command is
described supra.
"B" AND gates register 104 is used to bypass coded adderess
information around local memory 106 while "C" AND gates register
103 is used to place coded address information into local memory
106.
The output of lines A(7) (also identified as line I(2)) and A'(7)
of the instructional coded section of primary input register 101
are used to gate the flow of information through "C" and "B"gates
registers 103 and 104 respectively. The signal on line A'(7) is the
logical compliment of the signal on line A(7).
Local memory 106 can be any memory unit common in the art for
storing "bits" of information such as a magnetic core matrix and
the like common in the art.
Local memory OR gates register MOR 119 comprises eight OR gates
which control the flow of information from memory 106, instruction
logic circuit 152 and "B" AND gates register 104 into lines X'(0-3)
and Y'(0-3).
"F" AND gates register 107 comprises all AND gates 134 and "G" OR
gates register 118 comprising all OR gates 135 are used to control
the flow of information into "memory buffer" status register SR(6)
114 (FIG. 5B).
With reference to FIGS. 7 and 8, there is shown the detailed
circuit diagram for status registers SR(0) through SR(6) reference
numerals 108 through 114, respectively.
Basically, each status register comprises a column of bi-stable
flip-flop devices 125 and a column of AND gates 126.
Typically, two command lines 127 and 128 are connected to flip-flop
devices 125. Line 127 is connected in common to the "clock" input
terminals of each flip-flop device 125 for the purpose of
transferring the status of the "signal" input lines into the
register, and the other command line 128 is connected in common to
the "reset" input of flip-flop devices 125 to reset all flip-flop
devices to a logical zero or "off" status.
It will be noted that AND gates 126 are used to gate information
out of the status registers upon appropriate activation of lines
RSW(0-7) of status register SR(3) 111.
Status registers SR(0-6), reference numerals 108 through 114, are
identified as shown in Table 3 as follows:
---------------------------------------------------------------------------
TABLE 3
Ref. Abbrev. Title Function No.
__________________________________________________________________________
108 SR(0) Address Codes Stores address codes 109 SR(1) Input parts
Stores input parts codes 110 110 SR(2) Output Parts Stores output
parts codes 111 SR(3) Read Status Stores "read Status" codes 112
SR(4) Labels Stores "labels" codes 113 SR(5) Location Storage
Stores "location Storage" codes 114 SR(6) Memory Buffer Stores
"memory buffer" codes
__________________________________________________________________________
With reference to FIG. 13, there is shown the detailed circuit
diagram for character gates register 116 which comprises 32 AND
gates 130.
Register 116 converts the coded address of a typical "point"26 on
lines X'(0-3) and Y'(0-3) to activation of lines X(0-15) and
Y(0-15) by appropriate activation of lines XIC(0-1), and YIC(0-1).
For example, concurrent activation of lines Y'(2) and XIC(1) will
cause line X(14) to be activated.
FIG. 9 illustrates a detailed circuit diagram of "W" gates register
117 which comprises eight lower OR gates 132 and eight upper OR
gates 133. The lower OR gates 132 have input and output lines as
tabulated in Table 4. The upper OR gates 133 have input and output
lines as tabulated in Table 5.
TABLE 4
Output Input Lines Lines L(0), M(0), O(0), P(0), Q(0), R(0) W(0)
L(1), M(1), N(1), O(1), P(1), Q(1), R(1) W(1) L(2), M(2), N(2),
O(2), P(2), Q(2), R(2) W(2) L(3), M(3), N(3), O(3), P(3), Q(3),
R(3) W(3) L(4), M(4), N(4), O(4), P(4), Q(4), R(4) W(4) L(5), M(5),
N(5), O(5), P(5), Q(5), R(5) W(5) L(6), M(6), N(6), O(6), P(6),
Q(6), R(6) W(6) L(7), M(7), N(7), O(7), P(7), Q(7), R(7) W(7)
TABLE 5
Output input Lines Lines Y(8), Y(0), X(8), X(0), R(8), S(0) W(8)
Y(9), Y(1), X(9), X(1), R(9), S(1) W(9) Y(10), Y(2), X(10), X(2),
R(10), S(2) W(10) Y(11), Y(3), X(11), X(3), R(11), S(3) W(11)
Y(12), Y(4), X(12), X(4), R(12), S(4) W(12) Y(13), Y(5), X(13),
X(5), R(13), S(5) W(13) Y(14), Y(6), X(14), X(6), R(14), S(6) W(14)
Y(15), Y(7), X(15), X(7), R(15), S(7) W(15)
DRAWINGBOARD
With reference now to FIGS. 10 and 11, FIG. 10 is a logic diagram
of the input and output register circuits for drawingboard 20. The
input and output register circuits in the Y-direction are identical
to those in the X-direction and, therefore, are not repeated in the
drawing. Discussion of the X-input and output circuitry applies as
well to the Y-input and output circuitry. FIG. 11 is a circuit
diagram of drawing board output register 73 as well as a circuit
diagram of Y-output register 68 and Y-output parts register 69.
Referring to FIG. 10, X-input parts gate register 57 comprises a
set of sixteen X-parts ANDgates 75 and a set of sixteen X-parts OR
gates 76.
One side of the input to AND gates 75 is connected consecutively in
groups of four, to lines X'(O-3). The other side of the input to
AND gates 75 is connected in common, in groups of four, to lines
XIP(0-3). It can be seen, using this arrangement, that by selective
activation of lines X'(0-3) and XIP(0-3), only one line or a
combination of lines X(0-15) can be activated. Thus, combined with
the Y-direction, one point or combination of points will be
activated.
Input register 56 comprises sixteen bi-stable flip-flop devices 77
which act to control the flow of the information on the output
lines 78 of input parts register 57 into array 35.
Command lines *01 and *02 for the X- and Y-coordinates are used to
control the flow of such information. Command lines *10 and *11
(FIG. 5A)are used to reset X-input register 56 and Y-input register
60, respectively, to a logical zero of "off"status.
X-output register 64, similar to X-input register 56 comprises
sixteen bi-stable flip-flop devices 79 which act to control the
flow of information out of array 35.
Line ROR to X- and Y-output registers 64 and 68 from OR gate 145
(FIG. 12) is used to control the flow of output information.
Command lines *13 and *14 (FIG. 5A) are used to reset X-output
register 64 and Y-output register 68, respectively, to a logical
zero or "off" status.
X-output parts gate register 65 comprises all AND gates 80. It will
be noted that one side of the input to AND gates 80 is connected in
common, in groups of four, to lines XOP(0-3). Thus by appropriate
activation of lines XOP(0-3), information is gated out of X-output
register 64 into drawingboard output register 73 (FIG. 11).
Referring to FIG. 11, drawingboard output register 73 comprises XY
OR gates register 82, Z-OR gates register 83 and Z-output register
84 which is connected to Y-output parts gate register 69 and
X-output parts gate register 65 at the input side of XY OR gate
register 82.
Z-output register 84 comprises sixteen bi-stable flip-flop devices
85 used to transfer information from its input side to the computer
(not shown). Command line *06 is used to control the flow of the
information to the computer while command line *15 is used to reset
all the bits of output register 84 to a logical zero or "off"
state.
With reference to FIG. 5A and in particular to X-address decoder
58, Y-address decoder 62, X-address encoder 66 and Y-address
encoder 70, the circuitry for these devices is common in the art
and comprises AND gates YDC 120, XDC 115, YEC 124 and XEC 81 and
inverting amplifiers such that the "on" and "off" status
combination of four input lines into address decoders 58 and 62
causes activation of only one of 16 output lines of the decoder,
and for encoder 66 or 70, activation on one of 16 input lines
causes a particular combination of "on-off" states of four output
lines of the encoder.
Typically in FIG. 19 is shown X-address decoder 58 connected to XDC
gates register 115. XDC gates register 115 comprises four AND gates
59 whose outputs are connected to X-address decoder 58.
One input side of AND gates 59 is connected individually to line
X'(0-3) while the other side is connected in common to line XDC
from status register SR(0) 108.
In a similar manner, FIG. 20 shows Y-address decoder 62 connected
to YDC gates register 120. YDC gates register 120 also comprises
four ANDgates 63 whose outputs are connected to Y-address decoder
62.
One input side of ANDgates 63 is connected individually to lines
Y'(0-3) while the other side is connected in common to line YDC
from status register SR(0)108.
Typically, in FIG. 17 is shown X-address encoder 66 with output
connected to multiple input OR gate XOOR 150 and AND gates register
XEC 81 comprising all AND gates 67. It will be noted that the four
outputs of X-address encoder 66 are connected individually to one
input side of AND gates 67 while the other side is connected in
common to line XEC coming from status register SR(0) 108.
In a similar manner, with reference to FIG. 18, the output of
Y-address encoder 70 is connected to multiple input OR gate YOOR
151 and individually to one input side of AND gates 74 of AND gates
register YEC 124. The other side of AND gates 74 is, similar to
that for register XEC81, connected in common to line YEC coming
from status register SR(0) 108.
With reference to FIG. 12, therein is shown an elevational cross
section of a typical penlight 23 and its associated circuitry.
Penlight 23 comprises a writing end 87, and erase end 87' each end
having transparent light guides 89 and 89' to focus light emitted
by light source 88 and 88', respectively, onto array 35.
Light sources 88 and 88' are supported on sliding supports 90 and
90', which are biased toward ends 87 and 87' by use of helical
springs 91 and 91', respectively.
Attached to each support 90 and 90' are a set of electrical
contacts 92 and 92' which are used to connect light sources 88 and
88' to a source of electrical power when either end 87 or 87' is
pressed against surface 30 of drawingboard 20.
Additional electrical contacts 93 and 93' are provided permitting
connection of penlight 23 to erase-write circuit 94 and instruction
transmit circuit 95 through conductors 24 and 25.
An inking cartridge or writing instrument 96 is attached to support
90 at write end 87 while an eraser 97 is attached to support 90' at
erase end 87'.
All parts of the penlight are enclosed in a housing 98 of a
dimension suitable for an operator to use as a writing or erasing
instrument.
Erase-write circuit 94 comprises two "on-off" switches 138 and 139
to connect penlight 23 to OR gates 140 and 141 which allows
penlight 23 to control drawingboard array 35 using erase array line
(EOR) 129 and write array line (WOR) 131. Command lines *05 and *04
allow the computer (not shown) to instruct array 35 to erase and
write through OR gates 140 and 141, thus permitting both man and
machine to alter the information displayed in array 35.
Circuit 95 comprises "point" OR gate (POR) 142 whose input side is
connected to lines 24 and 25 from penlight switches 93 and 93',
respectively. "Point-one-shot" (POS) flip-flop 147 whose input is
connected to the output side of OR gate POR 142 has its output side
connected to "READ"OR gate (ROR) 145 and interrupt OR gate
(IOR)144. The input side of (ROR) gate 145 is also connected to
command line *03 through inverting amplifier 137 and line 153 from
circuit 152.
Circuit 95 also comprises OR gate 143 having its input side
connected to Y-output OR gate (YOOR) 151 and X(output OR gate
(XOOR) 150, XY-point AND gate (XYP) 146 whose one input side is
connected to the output side of OR gate 143, whose other input side
is connected to the output of (POR) 142, and whose output is
connected to interrupt OR gate 144 (IOR) whose input side is
connected to the output of (POS) flip-flop 147, whose other input
side is connected to XY-point AND gate (XYP) 146 has its output
connected to mode switch 149.
Inverting amplifier 137 is provided at the input of command line
*03 while another inverting amplifier 148 is provided for the
output of (IOR) gate 144 to produce the logical compliment of the
signals entering the amplifier.
It will be noted that a switch 149 is provided at the input side of
amplifier 148 to permit the operation of array 35 by use of
penlight 23 without the use of a computer (not shown).
It can be seen that a signal will occur on lines 24 and 25 whenever
either write end 96 or erase end 97 is pressed against surface 30
of drawingboard 20 activating, respectively, either switch 93 or
switch 93'. This signal will then pass through "point" OR gate
(POR) 142 to activate the "point-one-shot" (POS) flip-flop 147 and
one side of XY-point AND gate (XYP) 146.
A signal will appear at OR gate 143 if any X- or Y-bit, i.e.,
flip-flop, is in the logical "one" state in X-output register 64 or
Y-output register 68, and will pass on to XY-point AND gate (XYP)
146.
Both AND gate 146 and (POS) flip-flop 147, connected as noted above
to interrupt OR gate (IOR) 144, allows an interrupt signal to be
sent to inverting amplifier 148 provided switch 149 is in the
"line" position.
The connection scheme of circuit 95 provides interrupt signals on
line I(1) for any one of the following conditions:
a. When penlight 23 is used to point at a single point 26 being
held fixed against surface 30, or
b. When penlight 23 is used to draw a line by pressing end 87
against surface 30 and moving it along the surface thereof to send
a series of "point" address signals to the computer (not
shown).
By placing switch 149 in the "local" position, a display of graphic
material can be written in or erased from array 35 without
informing the computer (not shown) that an action has been
taken.
Whenever command line *03 is activated by the computer (not
shown)to read data in the drawingboard, the signal will pass
through inverting amplifier 137 to read array OR gate (ROR) 145. In
a similar manner, any pointing action by penlight 23 resulting in
the triggering of monostable flip-flop 147, will also send a signal
through read array OR gate (ROR)145 to transfer the status of
points 26 that are currently being selected from array 35 to
X-output and Y-output registers 64 and 68, respectively. This is
achieved by the fact that the output side of gate (ROR) 145 is
connected in common to the clock input terminals of the flip-flops
forming X- and Y-output register 64 and 68 respectively.
It will be noted in FIG. 12 that a potentiometer 52 is provided in
the circuit with power source 99 in order to control the brightness
or intensity of the radiant energy flux from typical light source
88. Penlight 23 can thus be used to input "shading" information
into array 35 using appropriate brightness or intensity measuring
circuits common in the art such as photosensitive transistors and
analog to digital voltage converters, whose digital output can be
stored in a memory common in the art.
Conversely, the brightness or intensity of light output from light
emitting diodes 28 can be regulated by the use of any current
controlling means such as a field effect transistor in place of
resistor 174 (FIG. 3A). In particular, the bias voltage on the
control terminal (gate or base) would determine the amount of
current that is allowed to pass through light emitting diode 28.
The control terminals are then connected in common to all points 26
of array 35 and the voltage on the conductor to the common
connection is determined by a video amplifier, digital to analog
converter or other means common in the art.
Whereas the present embodiment illustrated in FIG. 3A provides for
two discrete states ("on" and "off") of light emitting diode 28,
provision can be made, as described above, for a third dimension of
graphical input and output in the form of "point" 26 brightness or
intensity.
FIG. 16 is a circuit diagram of one corner of drawingboard 20
showing sides 53X, 53Y, 54X, and 54Y which act as an interface
between array 35 and X- and Y-input registers 56 and 60 and X- and
Y-output registers 64 and 68.
From FIGS. 5Aand 10, it will be noted that lines *03, *16, (WOR)
131 and (EOR)129 are shown collectively entering array 35 in the
upper left hand corner. These lines are shown individually in FIG.
16, which is a section of the lower left hand corner of array 35 at
point X(0)-Y(0), running along input sides 53X and 53Y.
READ command line *03, WRITE line 131 from WOR 141 and ERASE line
129 from EOR 140 are each connected respectively to AND gates RX(0)
and RY(0), WX(0)and WY(0), and EX(0)and EY(0), for point 26
corresponding to an address of X(0)-Y(0). Similar AND gates are
provided in the X- and Y-direction for other "points" 26
coordinates.
The input of ANDgates RX(0) and RY(0) are respectively connected to
the output of X'(0) and Y'(0) flip-flops of X- and Y-input
registers 56 and 60.
It will be noted that the outputs of AND gates RX(0), WX(0), RY(0)
and WY(0) are, typically, connected to input inverting amplifiers
180, 181, 182, and 183, respectively, while the output of AND gates
EX(0) and EY(0) are connected, respectively, to OR gates EOX(0) and
EOY(0). The other input to OR gates EOX(0) and EOY(0)is connected
in common to command line *16 whose function is to erase all
information from array 35.
Typically, read point AND gate RP(0,0) 157, write point AND gate
WP(0,0) 158 and erase point AND gate EP(0,0) 159 have one of their
inputs connected, respectively, to lines 185, 186 and 187
originally coming from AND gates RX(0), WX(0) and EX(0), while the
other input is connected, respectively, to lines 188, 189 and 190
originally comming from AND gates RY(0), WY(0) and EY(0).
The output of AND gates RP(0,0), WP(0,0)and EP(0,0) is connected,
respectively, to READ line 38, WRITE line 39 and ERASE line 40 in
turn connected to "point" circuit 26 which is the same circuit as
shown in FIG. 3 and 3A.
Thus, for information to pass through any of AND gates RP(0,0),
WP(0,0) or EP(0,0), any of lines 185, 186 or 187 in the X-direction
must be activated concurrently with any of lines 188, 189 or 190 in
the Y-direction.
Output information in the X-direction is conveyed by line 32, which
is connected to all other "points" 26 with an X-coordinate of X(0),
up to the X'(0)flip-flop of X-output register 64 through X-output
inverting amplifier 192.
Output information in the Y-direction is conveyed by line 34, which
is connected to all other "points" 26 with a Y-coordinate of Y(0),
over to the Y'(0) flip-flop to Y-output register 68 through
Y-output inverting amplifier 193.
OPERATION
Penlight Writing
To operate the graphical input-output device of the present
invention using penlight 23 for information input, the operator
holds penlight 23 (FIG. 12) with write end 87 against surface 30
over array 35 of drawingboard 20 over a particular "point" 26 and
presses down with the tip of pen 96 until the contacts of switch 92
are closed causing a current from power source 99 to activate light
source 88 in turn resulting in radiant energy or light to be guided
and focused by light guide 89 and shine on light sensitive
transistors 162, 163, or 29 (FIG. 3A).
Activation of write transistor 162 by the electromagnetic or
radiant energy from penlight 23 as indicated by the curved arrow
pointing toward transistor 162, will cause transistor 165 to become
activated resulting in a current flowing through resistor 174,
transistor 164 and light emitting diode 28 causing diode 28 to emit
light as indicated by the curved arrow pointing away from diode 28,
under which condition the "point" is considered as having been
"written."
Current will continue to flow through light emitting diode 28 once
the light from penlight 23 has activated transistor 162 due to the
latching ability of transistor pair 164, 165.
Alternatively, a second or indirect method of writing is also
available. If switch 149 of circuit 95 (FIG. 12) is in the "local"
position and switch 139 of circuit 94 is in the "on" position, then
activation of penlight contacts 93 will cause a current to flow in
conductors 25 to activate OR gate WOR 141 whose output is the
"write" command line 131 to array 35. The purpose of this path is
to provide means for checking the operation of array 35.
Penlight Erasing
In a similar manner, electromagnetic or radiant energy activation
of erase transistor 163 causes transistor 165 to become deactivated
which in turn deactivates transistor 164, thereby reducing the
current through resistor 174 and light emitting diode 28 to turn
diode 28 "off" at which time the point is considered as having been
"erased."
Similarly a second erase path also provides further means for
checking the operation of array 35.
Penlight Pointing
Activation of transistor 29 (FIG. 3A) by electromagnetic or radiant
energy will cause a current to flow through diodes 31 and 33,
resulting in a change of voltage and flow of current on X-sense and
Y-sense conductors 32 and 34.
The closing of penlight contacts 93 will cause a signal to be
impressed on WRITE conductor 25 which will pass through pointing OR
gate POR 142 to activate pointing one-shot flip-flop POS 147 which,
in turn, sends a signal through read output register OR gate (ROR)
145 which then transfers the address of the particular point being
pointed at into X- and Y-output registers 64 and 68.
If switch 139 of circuit 94 (FIG. 12) is in the "off" position and
switch 149 of circuit 95 is in the "line" position (FIG. 12), then
an interrupt signal is sent to the computer through interrupt OR
gate IOR 144, mode switch 149 and inverting amplifier 149 along
line I(1).
In response to the interrupt signal, the computer (not shown) may
then receiver the X- and Y-address information from X- and Y-output
registers 64 and 68 through drawingboard output register 73.
The computer can then return the address signal back to array 35
through primary input register 101 along with any desired command
such as read (*03), write (*04) or erase (*05).
For example, referring to FIG. 16, if the operator wishes to "read"
a "point" 26 on array 35, he uses penlight 23, as described above,
to point at the particular "point." The X- and Y-address of the
point is sent to the computer as described above and returned to
drawingboard 20 through drawingboard processor unit 100 along with
a "Read Drawingboard" command signal *03.
The X- and Y-address signal is decoded as will be described and
appears at one input of "read input" AND gates RX(0-15) and
RY(0-15) from X- and Y-input registers 56 and 60.
Since the other input side of AND gates RX(0-15)and RY(0-15) are
connected in common to READcommand line *03, activation of line *03
gates the status of X- and Y-input registers 56 and 60 into array
35. The coincidence of signals on lines 185 in the X-direction and
188 in the Y-direction will be detected through the matrix of AND
gates RP(0,0) through RP(15, 15) to activate typical READconductor
38 for each individual point 26 circuit.
In a similar manner, if the operator wishes to write a "point" 26
on array 35, he uses penlight 23, as described above, pointing with
write end 87 with switch 139 of circuit 94 in the
"off"position.
The X- and Y-address of the point is sent to the computer as
described above and returned to drawingboard 20 through
drawingboard processor unit 100 along with a "Write Drawingboard"
command signal *04.
The X- and Y-address signal is decoded as will be described and
appears at one input side of AND gates WX(0-15) and WY(0-15)from X-
and Y-input registers 56 and 60.
It will be noted from FIG. 12 that WRITE command line *04 is shown
in circuit 94 connected to one input of OR gate WOR141 whose output
is connected to line 131 which in turn is connected to the other
input side of ANDgates WX(0-15) and WY(0-15) (FIG. 16). Thus
activation of line 131 by line *04 gates the status of X- and
Y-input registers 56 and 60 into array 35. The coincidence of
signals on lines 186 in the X-direction and 189 in the Y-direction
will be detected through the matrix of AND gates WP(0,0) through
WP(15,15) to activate typical WRITE conductor 39 for each
individual "point" 26 circuit.
Also, in a similar manner, if the operator wishes to erase a
"point"26 in array 35, he uses penlight 23, as described above,
pointing with erase end 87' with switch 138 of circuit 94 in the
"off" position.
The X- and Y-address of the point is sent to the computer as
described above and returned to drawingboard 20 through
drawingboard processor unit 100 along with an "Erase
Drawingboard"command signal *05.
The X- and Y-address signal is decoded and appears at one input
side of AND gates EX(0-15) and EY(0-15) from X- and Y-input
registers 56 and 60.
It will be noted from FIG. 12 that ERASE command line *05 is shown
in circuit 94 connected to one input side of ORgate EOR 140 whose
output is connected to line 129 which in turn is connected to the
other input side of AND gates EX(0-15) and EY(0-15) (FIG. 16). Thus
activation of line 129 by line *05 gates the status of X- and
Y-input registers 56 and 60 into array 35. The coincidence of
signals on line 187 in the X-direction and 190 in the Y-direction
will be detected through the matrix of AND gates EP(0,0) through
EP(15,15) to activate ERASE conductor 40 for each individual
"point" 26 circuit.
It can be seen that those "points" 26 pointed at will appear as
addresses returned from the computer which are to be erased, read
or written.
It can also be seen that with appropriate programming of the
computer, either only those "points" pointed at can be erased or
specific "points" having a mathematical relationship to the point
being pointed at can be erased, read or written.
In order to erase all information from array 35 "Erase Array"
command line *16 (FIG. 16) is connected in common to the other
input side of OR gates EOX(0-15)and EOY(0-15) 184. Activation of
line *16 activates all lines 187 and 190 in turn activating all
ERASE lines 40 by virtue of the coincidence of activation of the
two inputs to the entire matrix of AND gates EP(0,0) through
EP(15,15).
Computer Input to Drawingboard
Output information from the computer (not shown) enters the
input-output devices of the present invention first through primary
input register 101 (FIGS. 5 and 6) of drawingboard processor unit
100 as previously described.
The address signal, in the form of a pattern or combination of
voltages on eight lines, enters the upper half of register 101,
passes through either "B" AND gates register 104 to memory ORgates
register MOR119 (called "Direct Addressing")or "C" AND gates
register 103 through local memory 106 (called "Indirect
Addressing")to memory OR gates register MOR119. From MOR 119 the
signal passes to X- and Y-input parts register 57 and 61,
respectively, and X- and Y-address decoders 58 and 62,
respectively, also to status registers SR(0-4), reference numerals
108 through 112 and to character gates 116.
The signal for activating a particular "point" 26 may then follow
any one of three routes from the memory OR gates MOR 119 to the X-
and Y-input parts registers 57 and 61.
By the first route, status register SR(1) 109 provides an X- and
Y-input signal on lines XIP(0-3) and YIP(0-3) to go directly to X-
and Y-parts registers 57 and 61, respectively, which allows the
coded address to activate any of the sixteen X- and any of sixteen
Y-input lines to array 35 in groups of four.
By the second route, status register SR(0) 108 allows an X- and
Y-input decoded signal from X-address decoder 58 and Y-address
decoder 62 to arrive at the X- and Y-input parts register OR gates
76 and 72, respectively, activating only one of each of the 16 X-
and sixteen Y-input lines to array 35 by activating lines XDC
and/or YDC.
By the third route, status register SR(0) 108 allows X- and Y-input
character lines XIC(0-1) and YIC(0-1) from character gates register
116 to activate any of the sixteen X- and sixteen Y-input lines
X(0-15) and Y(0-15) to X- and Y-input parts OR gates registers 76
and 72 respectively in groups of eight.
Drawingboard Output to Computer
Information contained in drawingboard 20 according to the "on" or
"off" status of light emitting diodes 28 is transmitted to the
computer by the use of commands described supra.
The flow of "point" 26 address information can also follow several
routes:
It can flow from X- and Y-output register 64 and 68, to X- and
Y-address encoders 66 and 70, respectively, where it is encoded
into a pattern or combination of voltages on eight lines O(8-15) in
accordance with signals on lines XEC and YEC from status register
SR(0) 108.
It can flow from X- and Y-output registers 64 and 68, to X- and
Y-output parts registers 65 and 69, respectively, where it is
encoded in accordance with signals on lines XOP(0-3) and YOP(0-3)
from status register SR(2)110 and thence to drawingboard output
register 73.
Information can flow from local memory 106 through "F" AND gates
register 107, through "G" OR gates register 118, through status
register SR(6) 114 to "W" OR gates register 117 to Z-OR gates
register 83 of drawingboard output register 73 where it is
collected and sent to the computer.
Command System
To further describe the use and operation of the graphical
input-output device of the present invention, primary control of
the flow of information is determined by signals on command lines
*01 through *37. The functions of the commands are as follows:
*00 "No Operation:" All command lines are inactive, i.e.,
"off."
*01 "Jam X-input Register:" The status of the X-address part of
primary input register 101 is transferred to X-input register
56.
The X-address information passes through "B" AND gates register 104
if A(7) (also identified as I(2)) is inactivated or "C" AND gates
register to local memory 106 if A(7) (also identified as I(2)) is
activated. The information can then follow three paths as
previously described under "Computer Input To Drawingboard."
a. if lines XIP(0-3) of status register SR(1) 109 are activated,
then the address information is decoded by X-input parts AND gate
register 75 of X-parts register 57.
b. If line XDC in status register SR(0) 108, is activated, then the
address information is decoded by X-address decoder 58.
c. If lines XIC(0-1) from status register SR(0) to input character
gates register 116 are activated, then the address information is
decoded by input character gates register 116.
*02 "Jam Y-input Register:" The status of the Y-address part of
primary input register 101 is transferred to Y-input register
60.
In a manner similar to command *01, Y-address information passes
through "B" AND gates register 104 if A(7) (also identified as
I(2)) is inactivated or "C" AND gates register 103 to local memory
106 if A(7) (also identified as I(2)) is activated. The information
then follows one of three paths previously described under
"Computer Input to Drawingboard. "
a. If lines YIP(0-3) of status register SR(1)109 are activated,
then the address information is decoded by Y-parts AND gates
register 71 of Y-parts register 61.
b. If line YDC in status register SR(0) 108 is activated, then the
address information is decoded by Y-address decoder 62.
c. If lines YIC(0-1) from status register SR(0) to input character
gates register 116 are activated, then the address information is
modified by input character gates register 116.
*03 "Read Drawingboard:" Selects and interrogates points 26 on
array 35 as to whether emitters 28 associated with a "point" 26 are
activated or not activated.
*04 "Write Drawingboard:" Selects and activates those points on the
array 35 addressed by the intersection of the bit patterns in the
X- and Y-input registers 56 and 60.
*05 "Erase Drawingboard:" Selects and deactivates those points on
array 35 defined by the intersection of the bit patterns in the X-
and Y-input registers 56 and 60.
*06 "Jam Output Register:" Transfers the status of X- and Y-output
registers 64 and 68 to Z-output register 84 of drawingboard output
register 73 depending upon the activated or inactivated condition
of status registers SR(0) through SR(6), reference numerals 108
through 114.
a. If lines XEC and YEC of status register SR(0) 108 are activated,
and SR(2) 110 is not activated, then the X- and Y- addresses are
encoded by X- and Y-address encoders 66 and 70 and transferred into
Z-output register 84.
b. If lines XOP(0-3) and YOP(0-3) of status register SR(2) 110 are
activated, and SR(0) 108 is not activated, then X- and Y-output
parts registers 65 and 69 will encode the X- and Y-addresses,
respectively.
*07 "Read Memory:" Transfers the contents of the location selected
by the address input lines C(0-7) to the data output lines E(0-15)
of local memory 106.
*10 "Clear X-input Register:" Resets all flip-flop devices in
X-input register 56 to the "off" or logical zero status.
*11 "Clear Y-input Register:" Resets all flip-flop devices in
Y-input register 60 to the "off" or logical zero status.
*12 "Clear input Register:" Resets primary input register 101 to
the "off" or logical zero status.
*13 "Clear X-output Register:" Resets all flip-flop devices in the
X-output register 64 to the "off" or logical zero status.
*14 "Clear Y-output Register:" Resets all flip-flop devices in
Y-output register 68 to the "off" or logical zero status.
*15 "Clear Output Register:" Resets all flip-flop devices in the
Z-output register 84 to the "off"or logical zero status.
*16 "Clear Array:" Sets all points 26 in array 35 to the "off,"
inactivated or logical zero status.
*17 "Clear Array, X-, Y-, S-, I- and O-registers:" Sends pulses
through all OR gates 123 of operations decoder 102 (FIG. 6)
reseting all connected registers to the "off" or logical zero
status.
*20 "Jam Status Register SR(0):" Transfers status of lines X'(0-3)
and Y'(0-3) to lines YIC(0-1), XIC(0-1), XEC, YEC, XDC and YDC of
status register SR(0) 108.
*21 "jam Status Register SR(1):" Transfers status of lines X'(0-3)
and Y'(0-3) to lines XIP(0-3) and YIP(0-3).
*22 "jam Status Register SR(2):" Transfers status of lines X'(0-3)
and Y'(0-3) to lines XOP(0-3) and YOP(0-3).
*23 "jam Status Register SR(3):" Transfers status of lines X'(0-3)
and Y'(0-3) to lines RSW(0-7).
*24 "jam Status Register SR(4):" Transfers status of lines X'(0-3)
and Y'(0-3) to the input side of AND gates 126 of status register
SR(4)112 to allow a "lavel" to be associated with an X- and
Y-address (FIG. 8).
*25 "jam Status Register SR(5):" Transfers the status of lines
O(8-15) to the input side of ANDgates 126 of Status Register SR(5)
113, assuming lines XEC and YEC of SR(0) 108 are in the activated
status. The leading edge of the pulse on these command lines
transfers the information into binary storage elements 125 while
the trailing edge locks the information into the register for later
analysis in accordance with the usual method of using the "D" type
flip-flop device.
*26 "Jam Status Register SR(6):" Transfers the status of lines
G(0-15) from "G" OR gates register 118 by pulsing the clock input
terminals of flip-flop devices 125 into SR(6).
*27 "write Memory:" Transfers the status of data lines W(0-15) into
the location in memory 106 represented by the status of address
lines C(0-7) by energizing write amplifiers (not shown) or
equivalent circuits common in the art, located in local memory
106.
*30 "Clear Status Register SR(0):" Resets all flip-flop devices in
SR(0) 108 to the "off" or logical zero status.
*31 "Clear Status Register SR(1):" Resets all flip-flop devices in
SR(1) 109 to the "off" or logical zero status.
*32 "Clear Status Register SR(2):" Resets all flip- flop devices in
SR(2) 110 to the logical zero or "off" status.
*33 "Clear Status Register SR(3):" Resets all flip-flop devices in
SR(3) 111 to the "off"or logical zero status.
*34 "Clear Status Register SR(4):" Resets all flip-flop devices
SR(4) 112 to the "off" or logical zero status.
*35 "Clear Status Register SR(5):" Resets all flip-flop devices in
SR(5) 113 to the "off" or logical zero status.
*36 "Clear Status Register SR(6):" Resets all flip-flop devices in
SR(6) 114 to the "off" or logical zero status.
*37 "Clear Memory:" Resets all parts of memory 106 to the reset or
logical zero status.
Increment Apparatus and Operation
Apparatus
For a graphical display of information in the form of a line, i.e.,
a locus of points defining a line, it is desirable to be able to
sequentially read the activated points into the computer (not
shown).
FIG. 14 is a circuit diagram of "I" logic circuit 152 useful for
such a purpose.
Circuit 152 comprises a base address register 200 having eight
input AND gates 201 with input lines A(8-15)connected to the input
of AND gates 201, an X-adder 203 and Y-adder 204 having their input
connected to the output of base address register 200, X-adder input
corresponding to lines A(8-11) and Y-adder input corresponding to
lines A(12-15), and relative address register 205 comprising eight
flip-flop devices 206 whose inputs are connected to X- and Y-adders
203 and 204 and whose output is connected to memory OR gates 119
(FIG. 6) by lines H(8-15) to address array 35.
X- and Y-adders 203 and 204 are circuits which are common in the
art which take a number input and either adds or subtracts "one"
from the number and gives the sum or difference as its output.
Circuit 152 also comprises status register SR(7)210 having at its
input side eight AND gates 211 whose output side is connected to
eight corresponding flip-flops 212 whose output is connected to
eight corresponding AND gates 213 constituting the output side of
SR(7) 210 which is connected to "W" gates register 117 through
lines S(0-7) and thence to Z OR gates 83.
Connected to both SR(7) 210 and relative address register 205 is
timing chain circuit 215 whose purpose is to trigger the gating of
information through the registers. The circuit for timing chain 215
is shown in FIG. 14A and comprises ten serially connected
monostable flip-flops 217 through 226 having output lines labelled
T(0-9) respectively.
It will be noted that the other outputs of flip-flops 218 through
225 are connected to the input side of OR gate 227 whose output is
connected to three serially connected monostable flip-flops 230
through 232 defining a sub-timing chain 229 with outputs labelled
T(a), T(b), and T(c).
FIG. 14B is a circuit diagram of add-subtract sequence logic unit
238.
Unit 238 comprises eight sequence dual input AND gates 239 whose
input side is connected to lines T(1-8) and whose other input side
is connected in common to line T(a). The output lines of ANDgates
239 are labelled T(1)a through T(8)a and are connected variously to
an input of multiple input sequence OR gates 240, four in number,
the upper two having output lines labelled U(0-1) going to X-adder
203 and the lower two having output lines labelled U(2-3) going to
Y-adder 204.
A function of logic unit 238 is to sequentially instruct the adders
to increment or decrement by one binary digit the address of the
"point" 26 around which the sequence is taking place.
A signal on line U(0) (from lines T(1)a, T(2)a and T(8)a) directs
X-adder 203 to add one to the "point" address.
A signal on line U(1) (from lines T(4)a, T(5)a and T(6)a) directs
X-adder 203 to subtract one from the "point"address.
A signal on line U(2) (from lines T(2)a, T(3)a and T(4)a) directs
Y-adder 204 to add one to the "point"address.
A signal on line U(3) (from lines T(6)a, T(7)a and T(8)a) directs
Y-adder 204 to subtract one from the "point" address.
Thus, depending on which of lines T(1a-8a) is activated, one binary
digit is added to or subtracted from the address of the
"point"around which the sequence is taking place.
Sequence AND gates "c" 241 have one input connected to T(c) and the
other input connected variously to T(1-8) and has its outputs
labelled T(1c-8c).
Referring again to FIG. 14, interrupt OR gate 207 is provided whose
input is connected to line A(6) from primary input register 101 and
also to lines XUNFand XOVF from X-adder 203 and lines YUNF and YOVF
from Y-adder 204, and line I(1) from circuit 95.
Another OR gate 208 is provided in circuit 152 which is used to
activate command line *06 when line T(9) is activated in order to
transfer the status of the Z OR gates 83 to Z-output register 84 as
described previously.
Operation:
To begin the process of reading out the addresses of a locus of
points, line T(0) is activated by a pulse on line I(O) from the
computer to gate the initial X- and Y-address information into base
address register 200.
Activation of line T(0) of timing chain circuit 215 begins the
search sequence to interrogate all points immediately adjacent the
addressed point.
It will be noted from FIG. 14A and as shown in timing diagram (FIG.
15) that the sub-timing chain 229 subdivides each timing chain
pulse T'(1-8) into three sub-pulses such that the main timing chain
pulse has within it a subtiming chain pulse 235, 236 and 237
corresponding to the output pulse of one-shot flip-flops 230, 231
and 232 respectively, on lines T(a), T(b) and T(c).
It will be noted that line T(a) is connected to sequence decoder
238 and thence to X- and Y-adders 203 and 204, T(b) is connected to
the "clock" input of flip-flops 206 of register 205 and T(c) is
connected to sequence decoder 238 and thence to the clock inputs of
flip-flops 212 of SR(7) 210.
Sequence AND gates "c" 241 are similar to sequence AND gates "a"
239 in that they produce a pulse at their outputs when timing chain
pulses T(1-8) and the sub-timing chain pulses T(a), T(b) and T(c)
coincide.
The function of activation of T(a) is to direct X- and Y-adders 203
and 204 to either add "one," subtract "one" or leave unchanged the
X- and Y-address of a particular point 26.
Around a particular point 26 will be eight immediately adjacent
points which will be labelled according to the points of a compass
beginning counterclockwise from east "E" to "NE" etc. Table 6 is a
tabulation of one cycle of the search routine which is executed for
each point during the increment operation.
TABLE 6
Loc- ation Time Operation T(0) Address X, Y, in base register E
T(1) a. Add 1 to X in base register 200 b. Store X plus 1, Y in
register 205 c. Read drawingboard ROR NE T(2) a. Add 1 to X, and 1
to Y in base register 200 b. Store X plus 1, Y plus 1 in register
205 c. Read drawingboard ROR N T(3) a. Add 1 to Y in base register
200 b. Store X, Y plus 1 in register 205 c. Read drawingboard ROR
NW T(4) a. Subtract 1 from X, add 1 to Y in register 200 b. Store X
minus 1, Y plus 1 in register 205 c. Read drawingboard ROR W T(5)
a. Subtract 1 from X in base register 200 b. Store X minus 1, Y in
register 205 c. Read drawingboard ROR SW T(6) a. Subtract 1 from X,
subtract 1 from Y in register 200 b. Store X minus 1, Y minus 1 in
register 205 c. Read Drawingboard ROR S T(7) a. Subtract 1 from Y
in base register 200 b. Store X, Y minus 1 in register 205 c. Read
drawingboard ROR SE T(8) a. Add 1 to X, subtract 1 from Y in
register 200 b. Store X plus 1, Y minus 1 in register 205 c. Read
drawingboard ROR T(9) Transfer contents of SR(7) through "W" gates
117 to Z-output register 84
__________________________________________________________________________
Assuming the XDC and YDC bits of SR(0) are activated, then as each
point is sequentially selected by the timing chain 215 and read
from array 35, its state is stored in Status Register SR(7) 210.
After the states of the eight surrounding points have been
collected in SR(7) 210, then the contents are transferred on lines
S(0-7) to "W" gates 117 as noted in Table 6 at time T(9) and thence
to drawingboard output register 73 (Z-output register 84).
Upon conclusion of a search routine, the address of the adjacent
activated points may be used to begin the next search routine.
When the locus of points ends at a border or side of array 35,
overflow and underflow signals will occur in either the X- or
Y-adders 203 and 204, respectively. When an underflow or overflow
occurs in either the X- or Y-direction, one of lines XUNF, XOVF,
YUNF or YOVF will be activated to cause a signal to be impressed on
line I(1) at the output of OR gate 207 to terminate the increment
operation.
However, if the operator wishes, he may ignore an overflow and use
the truncated address to start at the first column or row again.
For example, the address of a point in the last column would have a
binary X-address of "1111." adding "1" gives an X-address of
"10000;" truncating the overflow bit gives "0000," which is just
the X-address of a point in the first column.
The other three boundary conditions namely; decrement X from 0000
to X equals 1111; increment Yfrom 1111 to Y equals 0000; and
decrement Yfrom 0000 to Yequals 1111 behaves similarly.
* * * * *