U.S. patent number 3,668,650 [Application Number 05/057,586] was granted by the patent office on 1972-06-06 for single package basic processor unit with synchronous and asynchronous timing control.
This patent grant is currently assigned to Contrologic, Inc.. Invention is credited to Fuh-Lin Wang.
United States Patent |
3,668,650 |
Wang |
June 6, 1972 |
SINGLE PACKAGE BASIC PROCESSOR UNIT WITH SYNCHRONOUS AND
ASYNCHRONOUS TIMING CONTROL
Abstract
A basic processor unit for use in a data processing system is
disclosed. The unit comprises in combination, a data storage unit
including a plurality of registers, input and output buses, a data
processing unit, a timing control including a timing element
adapted to operate in a synchronous or an asynchronous mode, means
for controlling the asynchronous operation of the timing element,
decoding means and suitable interconnections between the various
components. The present processor unit is so designed as to enable
it to be connected to another similar unit, in series and/or in
parallel whereby to increase either the number of bits per facility
or the number of facilities or both. An improved data processing
system utilizing the present processor is also disclosed.
Inventors: |
Wang; Fuh-Lin (Wappinger Falls,
NY) |
Assignee: |
Contrologic, Inc. (New York,
NY)
|
Family
ID: |
22011520 |
Appl.
No.: |
05/057,586 |
Filed: |
July 23, 1970 |
Current U.S.
Class: |
713/600; 713/401;
713/502; 711/172 |
Current CPC
Class: |
G06F
15/16 (20130101); G06F 15/8007 (20130101) |
Current International
Class: |
G06F
15/80 (20060101); G06F 15/16 (20060101); G06F
15/76 (20060101); G06f 013/00 (); G06f
015/16 () |
Field of
Search: |
;340/172.5 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Henon; Paul J.
Assistant Examiner: Chapnick; Melvin B.
Claims
1. A basic processor unit for use in a data processing system
comprising in combination:
a data storage unit including a plurality of registers and the
input and output gating for said registers;
an output bus and an input bus;
a data processing unit including an arithmetic unit and the gating
for said arithmetic unit, said data processing unit having an input
connected to said data storage unit through said buses and an
output connected to said output bus;
a timing control including a timing element adapted to operate in a
synchronous or an asynchronous mode;
means for controlling the asynchronous operation of said timing
element;
decoding means having an input connected to a control source;
means for externally connecting said buses;
at least one register of said data storage unit connected to said
input bus;
at least one register of said data storage unit connected to said
output bus;
and means for connecting the output of said decoding means and the
output of said timing control to said data storage unit and said
data processing
2. The invention in accordance with claim 1 wherein said timing
control includes an oscillator having a feedback path; a
multi-phase time signal generator comprising a plurality of
bistable elements; and a counter adapted to advance with each
oscillation of said oscillator; said oscillator including a first
delay device having an output connected to said counter and an
input connected to a multiple input logic gate having at least one
input for each phase, each input of said gate being connected to a
second logic gate, said second logic gates each having on input
connected to the feedback path of said oscillator, a second input
connected to the means for controlling said asynchronous mode, and
a third input connected to the corresponding phase of said
multi-phase time signal generator; and a second delay device having
an input connected to the output of said first delay device and an
output connected to said
3. The invention in accordance with claim 1 wherein said arithmetic
unit has an initial carry input and a final carry output, at least
one bistable element operationally connected to said final carry
output, and gating for
4. The invention in accordance with claim 3 further including a
second bistable element, said second element operatively connected
to the output of the most significant bit of said arithmetic unit
and gating for the output of said second bistable element adapted
to be enabled and disabled.
5. The invention in accordance with claim 4 further including a
logic element having an input connected to each bit of said output
bus and an output operatively connected to a third bistable element
whereby to detect the presence of either zero or non-zero resultant
from said arithmetic unit and gating for the output of said third
bistable element adapted to
6. The invention in accordance with claim 1 wherein said input bus
and said output bus each have at least one bit corresponding to
each bit of said registers; said input bus bits are connected to
the corresponding output bus bits through a buffer; and means for
external connections for all bits
7. The invention in accordance with claim 1 further comprising a
first operand register having an input connected to said input bus
and output connected to said data processing unit and a second
operand register having a first input connected to said input bus,
a second input connected to said output bus and an output connected
to said data processing unit.
8. The invention in accordance with claim 1 further comprising a
second output bus having a bit corresponding to each bit of said
registers; a second input bus having a bit corresponding to each
bit of said registers; and a second buffer interconnecting each bit
of said second output bus to
9. The invention in accordance with claim 8 further comprising a
third
10. The invention in accordance with claim 1 wherein said data
processing unit further includes a bit manipulation unit for logic
operations and a
11. The invention in accordance with claim 1 wherein said data
processing unit includes a logic gating for shifting its output one
bit to the left or one bit to the right and said output bus
includes a bit position corresponding to the shift left and shift
right outputs of said data
12. A processor unit comprising in combination a first basic
processor unit and a second basic processor unit, each said basic
processor unit comprising:
a data storage unit including a plurality of registers and the
input and output gating for said registers;
an output bus and an input bus;
a data processing unit including an arithmetic unit and the gating
for said arithmetic unit, said data processing unit having an input
connected to said data storage unit through said buses and an
output connected to said output bus;
a timing control including a timing element adapted to operate in a
synchronous or an asynchronous mode;
means for controlling the asynchronous operation of said timing
element;
decoding means having an input connected to a control source;
means for externally connecting said buses;
at least one register of said data storage unit connected to said
input bus;
at least one register of said data storage unit connected to said
output bus;
means for connecting the output of said decoding means and the
output of said timing control to said data storage unit and said
data processing unit; and,
means connecting the bits of the first basic processor unit output
bus in parallel to the corresponding bits of the second basic
processor unit output bus whereby the total number of data
processing units and data
13. A processor unit comprising in combination a first basic
processor unit and a second basic processor unit, said processor
unit having twice the number of bits of said basic processor units
individually, each said basic processor unit comprising:
a data storage unit including a plurality of registers and the
input and output gating for said registers;
an output bus and an input bus;
a data processing unit including an arithmetic unit and the gating
for said arithmetic unit, said data processing unit having an input
connected to said data storage unit through said buses and an
output connected to said output bus;
a timing control including a timing element adapted to operate in a
synchronous or asynchronous mode;
means for controlling the asynchronous operation of said timing
element;
decoding means having an input connected to a control source;
means for externally connecting said buses;
at least one register of said data storage unit connected to said
input bus;
at least one register of said data storage unit connected to said
output bus;
and means for connecting the output of said decoding means and the
output of said timing control to said data storage unit and said
data processing unit;
wherein each of said arithmetic units includes:
an initial input carry and a final output carry, a first bistable
element operatively connected to said final output carry, and
gating for the output of said bistable element adapted to be
enabled or disabled;
a second bistable element, said second element operatively
connected to the output of the most significant bit of said
arithmetic unit, and said gating for the output of said second
bistable element adapted to be enabled or disabled; and
logic gating for shifting the output of said data processing unit
one bit to the left or right;
each of said output buses includes a bit corresponding to the shift
left or shift right output, the overlapping bits of said output
buses are connected together whereby the resultant combined output
bus has only one shift left bit position and one shift right bit
position;
and said first and second bistable elements of the least
significant basic processor unit are disabled, and the control
source and timing control of
14. A data processing system comprising:
a main storage memory including storage elements, at least one data
register, at least one address register, and control logic;
a first processor connected to said storage memory to receive and
transmit data instructions therefrom;
a first control memory including storage elements, at least one
data register, at least one address register, and control
logic;
means interconnecting said first processor and said first control
memory;
means interconnecting said first control memory and said first
processor;
a second processor connected to said storage memory to receive and
transmit data instructions therefrom;
a second control memory including storage elements, at least one
data register, at least one address register, and control
logic;
means interconnecting said second processor and said second control
memory;
at least one input-output control connected to said second
processor; and
said first and second processors are free of direct
interconnection
15. The data processing system in accordance with claim 14 wherein
each of said processors includes at least one basic processor unit,
said basic processor unit comprising:
a data storage unit including a plurality of registers and the
input and output gating for said registers;
an output bus and an input bus;
a data processing unit including an arithmetic unit and the gating
for said arithmetic unit, said data processing unit having an input
connected to said data storage unit through said buses and an
output connected to said output bus;
a timing control including a timing element adapted to operate in
synchronous or asynchronous mode;
means for controlling the asynchronous operation of said timing
element;
decoding means having an input connected to a control source;
means for externally connecting said buses;
at least one register of said data storage unit connected to said
input bus;
at least one register of said data storage unit connected to said
output bus;
and means for connecting the output of said decoding means and the
output of said timing control to said data storage unit and said
data processing unit;
wherein, said means for controlling the asynchronous operation of
said timing element is connected to the main memory and the first
control memory;
said decoding means is connected to the output of the data register
of said first control memory; and
said means for externally connecting said buses is connected to the
data register of said main memory.
Description
BACKGROUND OF THE INVENTION
In U.S. Pat. No. 3,315,235, issued to R. J. Carnevale et al., on
Apr. 18, 1967 a data processing system is disclosed which utilizes
a so-called central processor unit or CPU as well as a main memory,
input-output (I/o) channels and input-output devices and controls.
A problem in the assembly of computers such as that shown in the
referenced patent is the so-called "part number problem." That is,
the problem associated with using a great variety of different
parts to form the whole rather than repeating the same parts
several times. It should be obvious that with mass production
techniques, even the most complicated component part can usually be
manufactured most economically when mass produced.
It is well known that the main memory can always be built with a
very low part number whether it is made by magnetic cores or solid
state circuits since the memory may be built up by combining a
plurality of identical units. The I/o devices themselves and their
control logic are, in general, rather irregular and in actuality,
are commercially produced by a large number of manufacturers with
appropriate interfaces for their particular usage. The CPU and I/o
channel (which in reality is similar to a simple CPU with a lower
performance and less capable arithmetic unit than the CPU) are the
most difficult and complex components of the data processing system
and heretofore these components have been produced utilizing a
large part number.
In view of the above, it is the principal object of the present
invention to provide a basic processor unit which may be used as a
repetitive piece part for constructing more complex processor units
for use either as a CPU or I/o channel in a data processing system
such as that disclosed in U.S. Pat. No. 3,315,235.
A further object is to provide a new and novel data processing
system which may be implemented with the proposed basic processor
unit.
SUMMARY OF THE INVENTION
The above and other beneficial objects and advantages are attained
in accordance with the present invention by providing a basic
processor unit for use in a data processing system comprising, in
combination, a data storage unit including a plurality of registers
and the associated input and output gating therefor; an output bus
and an input bus; a data processing unit including an arithmetic
unit and the gating therefor, the data processing unit having an
input connected to the data storage unit through the input buses
and an output connected to the output bus. The basic processor unit
further comprises a timing control including a timing element
adapted to operate in a synchronous or an asynchronous mode and
means for controlling the asynchronous operation of the timing
element. The processor unit further includes decoding means having
an input connected to a control source; means for externally
connecting the input and output buses; and means for connecting the
output of the decoding means and the output of the timing control
to the data storage unit and the data processing unit. To this end,
the data storage unit includes at least one register connected to
the input bus and at least one register connected to the output
bus.
The timing control which comprises the heart of the basic processor
unit includes a delay line oscillator having a feedback path; a
multi-phase time signal generator comprising a plurality of
bistable elements; and a counter adapted to advance with each
oscillation of the oscillator. The oscillator includes a first
delay line having an output connected to the counter and an input
connected to a multiple input logic gate having at least one input
for each phase. Each input of the gate is connected to a second
logic gate and each of the second logic gates has a first input
connected to the feedback path of the oscillator, a second input
connected to the means for controlling the asynchronous mode of the
timing control and a third input connected to the corresponding
phase of the multi-phase time signal generator. The timing control
further includes a second delay line having an input connected to
the output of the first delay line and an output connected to the
multi-phase time signal generator.
The present invention also contemplates a data processing system
including processor units formed from basic processor units of the
type described above. To this end, the system utilizes a main
storage memory and first and second processor units, each of which
is connected directly to the main storage memory. A separate
control memory including storage elements, data registers, address
registers and control logic is provided for each processor and is
interconnected with both the main memory and its associated
processor. Suitable input-output controls are connected to one of
the processors and there is no connection between the two
processors.
BRIEF DESCRIPTION OF THE ASSOCIATED DRAWINGS
In the accompanying drawings:
FIG. 1 is a block diagram of the basic processor unit (BPU) of the
present invention;
FIG. 2 including subfigures 2a, 2b and 2c comprise schematic
representations of typical logic components for the arithmetic
logic and shift (ALS) unit of the BPU;
FIG. 3 is a simplified schematic of the control flip flops of the
BPU;
FIG. 4 is a simplified schematic of a delay line oscillator such as
that utilized in the timing control of the BPU;
FIGS. 4a and 4b are wave forms of the signals generated by the
delay line feedback oscillator of FIG. 4;
FIG. 5 is a schematic representation of the
synchronous-asynchronous timing control utilized by the present
BPU;
FIGS. 6a and 6b are block diagram illustrations of the method of
connecting two BPUs to increase respectively, the word length and
number to facilities available over a single BPU; and
FIGS. 7a and 7b are block diagrams, respectively, of a typical,
presently available data processing system and the proposed data
processing system of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
In the following discussion and the associated drawings, NOR logic
has been used throughout for simplicity except where, in the
interest of clarity, different symbols are used for the same
technology. Similarly, the customary circles indicating inversion
have been omitted, again in the interest of simplification and
clarity.
GENERAL DESCRIPTION OF BASIC PROCESSOR UNIT
The basic processor unit (BPU) 10 of the present invention is
illustrated in schematic form in FIG. 1 Accordingly, the BPU 10
includes two facility blocks and three control blocks. The first
facility block 12 is a data storage block and comprises a plurality
of registers each of which is designated by the reference numeral
14. The number of registers 14 is determined by the performance
required, and in most cases, will include at least on register for
each of the following functions: location of program operand;
address; accumulator; and address modification. It should be
apparent that additional registers may be added for increased
performance or certain of the registers may be eliminated as
required. The number of bits required for each register is
determined by the address length and the operand length of the
computer formed from the BPU.
In addition to the data storage block 12, the facility section of
the present BPU further comprises a data processing block 16. The
data processing block 16 includes two operand registers 18 and 20
and an arithmetic-logic-shift (ALS) unit 22 as well as control flip
flops 24. The operand registers 18 and 20 serve as a buffer between
the ALS 22 and the general purpose registers 14 of the data storage
block 12. Operand registers 18 and 20 may thus be eliminated at the
cost of simplicity of control.
The ALS unit 22 performs addition and logic operations and its
output can be shifted one bit either to the left or right.
Subtraction can be obtained by reading the complement of the second
operand into the operand register 20. Although certain details of
the ALS will be discussed in more detail forthwith, it should be
noted that the ALS unit 22 is basically a combination of well known
and well defined components such as those discussed in more detail
in U.S. Pat. No. 3,315,235.
The control flip flops 24 of the data processing block 16 are used
to store system conditions such as overflow, sign and non-zero. If
desired, other conditions can be added to the data processor 16 by
adding additional flip flops.
Both facility blocks, that is, data storage block 12 and data
processing block 16, are fed by input buses at least one of which
is able to receive information externally. Accordingly, as shown,
an external input bus 26 is provided along with an internal input
bus 28. The number of bits of the input buses 26 and 28 is
determined by the number of bits of each register 14 used in a BPU.
As shown schematically, each register 14 has one connection 30 to
the external input bus 26 and a second connection 32 to the
internal input bus 28. The connections between the registers 14 and
input buses 26 and 28 are made to the corresponding bit positions.
That is, the first bit of the first register is connected to the
same bus bit as the first bit of the second, third, fourth . . .
registers; the second bit of the first register is connected to the
same bus bit as the second bit of the second, third, fourth . . .
register; and so on. The external input bus 26 is also connected to
the control flip flops 24 through connection 34 as will be
described in more detail forthwith and each bit of the operand
register 20 is connected to the external input bus 26 through
connection 36. Each bit of the operand register 18 is connected to
the internal input bus through connection 38. The outputs of each
bit of the operand registers 18 and 20 are connected to the ALS
unit 22 through connections 40 and 42, respectively.
A first output 44 of the ALS 22 comprises a connection to an
external output bus 46. In fact, each bit of the ALS 22 is
connected to three bits of the output data bus to account for left
and right shifting. This feature is described in more detail in
conjunction with the discussion of FIG. 2c which will be described
forthwith. Each bit of the ALS 22 is also connected to a
synchronizing bus 48 through connection 50. As will be explained in
more detail in connection with FIG. 2a, the output 44 will be gated
onto the external output bus 46 to indicate when carry propagation
is completed.
An additional connection 52 is provided between the ALS 22 and
control flip flops 24. As will be described in connection with FIG.
3, connection 52 is used to set the control flip flops 24 according
to the results of the operation in the ALS 22. As will also be
discussed in more detail in connection with FIG. 3, the output of
the control flip flops 24 is connected to the output bus 46 through
connection 54. The external output bus 46 is also connected to the
input of operand register 20 through connection 56. Connection 56
serves to provide complements to operand register 20 for
subtraction in the ALS.
Referring briefly to the data storage block 12 once again, it will
be noted that each of the registers 14 has a connection 58 to the
external output bus 46 as well as a connection 60 to the internal
output bus 62. A third connection 64 is provided between the output
of each register 14 and an address bus 66. The address bus 66 has a
pad 68 adapted to be connected to the main memory and control
memory with which the processor formed from the BPU of the present
invention is to be associated. Similarly, the output bus 46 has
associated therewith pad 70 for external connection. With the
illustrated embodiment, address information is transmitted from the
registers through address bus 66 and pad 68. At the sacrifice of
performance, the address bus could be tied into the output bus
46.
Buffers 72 and 74 are provided interposed between the external
output and input buses 46 and 26 and the internal output and input
buses 62 and 28, respectively. In the illustrated embodiment, the
buffers 72 and 74 are shown as inverters. Actually, the buffer may
take the form of any device capable of providing power and/or
correcting polarities to generate a distinction between input and
output signals. Thus, in place of inverters, the buffers may be in
the form of amplifiers, special drivers, etc.
In addition to the data storage block 12 and data processing block
16 which provide the facilities for the BPU of the present
invention, there are also three control function blocks including a
control word decoder 76, timing control logic 78 and command
generator 80.
The control word decoder 76 comprises a set of decoders the number
of which is determined by the control word to be utilized which, in
turn, is controlled by the number and operations of the general
purpose registers 14, the number and operations of the operand
registers (in the present case two, operand register 18 and operand
register 20), the type of operations to be performed in the ALS 22
and the selection of the sensing of control flip flops 24. In other
words, the longer the control word, the more operations available
The control word decoder 76 may, for example, take the form of that
shown in FIG. 4 z of U.S. Pat. No. 3,315,235 to Carnevale et al.
Such decoders are well known and defined in the art.
A second control function block of the BPU 10 is the timing control
logic 78 which generates a series of pulses which are combined with
the output of the control word decoder 76 to form inputs to the
command generator 80. The outputs 82 and 84 of the command
generator 80 are connected, respectively, to each of the components
of the data storage block 12 and the data processing block 16. The
command generator 80 also has an output 86 to the synchronizing bus
48. As will be described in greater detail hereinafter, the
synchronizing bus 48 is used for inter-unit connection between BPUs
in a multi-BPU processor and for connecting the BPU with the main
memory, the control memory, and the I/o controls of data processing
system with which the BPU is to be associated. A connection 90 is
provided between the timing control 78 and synchronizing bus 48 for
purposes which will also be described forthwith.
To complete the general description of the BPU 10, attention is
called to the control bus 92 which extends between an external
interconnection 94 and the control word decoder 76. The pad 94 is
adapted for interconnection with a control memory or control word
generator of an associated data processing system. The control bus
92 receives the control word and transmits the same to the control
word decoder 76 where the control word is interpreted and the
result is used along with the output of the timing control logic 78
in generating the commands from the command generator 80. The
format of the control word will determine the logic structure of
the control word decoder 76 and command generator 80. To save
connections at pad 94, the control word is preferably binary
coded.
In the following paragraphs, a more detailed description of the
various blocks of FIG. 1 will be provided with reference being made
to FIGS. 2-6.
Data Storage Block 12
As was previously mentioned, the data storage block comprises a
plurality of registers 14. The registers 14 comprise conventional
arrangements of components which are well known and, accordingly,
the details of this unit may be omitted from the present
description.
Data Processing Block 16
As in the case of the data storage registers 14, the operand
registers 18 and 20 comprise conventional arrangements of
components and need not be discussed herein.
The details of the ALS unit are set forth in FIG. 2 and the
associated subfigures 2a, 2b and 2c.
Adder pp In FIG. 2 a typical adder 96 is illustrated. One bit, 98
and 100, of operand registers 18 and 20, respectively, is shown.
One ("IN") output 102 is connected to one input terminal of logic
gates 104 and 106. The other output ("ON") 108 is connected to one
terminal of gates 110 and 112. Similarly, the "IN" output 114 of
bit 100 is connected to the other terminal of gates 112 and 104,
and the "ON" output 116 of bit 100 is connected to the other
terminal of gates 106 and 110. The outputs of gates 104 and 110 are
tied to one input of gate 118 and, similarly, the outputs of gates
106 and 112 are tied to one output of gate 120. The other terminals
122 and 124 of gates 118 and 120, respectively, are connected to
the output carry signal of the next lower stage (as will be
explained in connection with FIG. 2a). The outputs of gates 118 and
120 are tied together and represent the sum of bits 98 and 100 of
the two operands.
For completeness, the symbols "N" and "P" are inserted in the
various associated figures to show the proper polarization of the
various signals under true conditions when positive NOR logic gates
are used exclusively.
Carry Generation
Carry generation, that is, the inputs 122 and 124 to gates 118 and
120, are obtained with a so-called double-track arrangement, as
shown in FIG. 2a. A CARRY OUT (P) is automatically propagated on
line 122 if both operands are one. If both operands are zero, no
carry [CARRY OUT (P)] is automatically generated on line 124. These
signals are inverted and sent to the next higher stage under the
names CARRY IN (N) and CARRY IN (N), respectively. If one operand
is one and the other operand is zero, then a CARRY OUT (P) is
generated only if a CARRY IN (N) from the next lowest stage is
present. This is represented schematically in FIG. 2a which can be
considered temporarily as the next lower stage to FIG. 2. Each
stage of the carry utilizes six gates 126 (a-f). The terminals of
the various gates are connected as follows:
Gate Operand 98 Operand 100
__________________________________________________________________________
126A 1 1 126B 0 1 126C 1 0 126D 0 0 126E 0 1 126F 1 0
In addition, a CARRY IN (N) 128 from the next lower stage is
provided as inputs to gates 126b and 126c, and a NO CARRY IN [CARRY
IN (N)] is provided as additional inputs to gates 126e and 126f.
The outputs of gates 126a, 126b, and 126c are tied together and
similarily, the outputs of gates 126d, 126e and 126f are tied
together and fed to an "OR" logic gate 132 as well as carries 122
and 124 which, as was previously stated, are inverted and go to the
next highest stage of the adder. The output 134 of gate 132 is
connected to the synchronizing bus 48 to indicate the carry
completion.
Logic
The logic portion of the ALS 22 is illustrated in FIG. 2b. In it,
each stage of the logic unit comprises five gates 136 (a-e). Gate
136a is connected to the one output of the corresponding bits 98
and 100 of operands 18 and 20, respectively. Gate 136a performs AND
operations. Gates 136b and 136c are connected, respectively, to the
one and zero outputs of the corresponding bits 98 and 100 of
operand registers 18 and 20, and zero and one outputs of the same
bits as shown. Their outputs are tied together and provide the
exclusive OR (EXO) function. Gate 136d and inverter 136e are
connected to the zero outputs of bits 98 and 100 and provide the OR
logic. The outputs of the various logic gates are tied together and
connected to the output bus 46.
Shift
The shift function of ALS 22, which in the present illustrated
embodiment is a single bit shift in either direction, is
illustrated in FIG. 2c where the (i)th stage of the unit is shown.
Three identical sets of gates 138 (a and b), 140 (a and b), and 142
(a and b) are utilized. The inputs to the gates are the carries 122
and 124 and the combined outputs 144 of gates 104 and 110 (see FIG.
2) and 146 of gates 106 and 112. The output 148 of gates 138 is
connected to the (i- 1)th bit position of the output bus; the
output 150 of gates 140 is connected to the (i)th bit; and the
output 152 of gates 142 is connected to the (i+1)th bit. Thus,
left, right or no shift may be accomplished by providing the proper
inputs to the sets of gates 138, 140 and 142. It should be apparent
that for greater than one bit shifting, a gate matrix may be
employed in place of the simple logic circuitry illustrated in FIG.
2c.
Control Flip Flops 24
The control flip flops 24 are used for overflow check, non-zero
check and sign check in accordance with standard practice. The
logic circuitry for the flip flops is shown in FIG. 3. Referring
briefly to FIG. 1, it may be noted that the inputs 34 and outputs
54 of the control flip flops 24 are tied, respectively, to the
input bus 26 and output bus 46 for the storing and restoring of
their settings. This arrangement is desirable in that it allows
program interrupt.
Referring to FIG. 3, three flip flops 154, 156 and 158 are provided
labeled, respectively, non-zero, overflow and sign. The non-zero
flip flop 154 is connected to the various bits of the output bus 46
through gates 160 and 162. The overflow flip flop 156 is fed from
the input bus 26 through gate 164, the output bus 46 through
inverter 166 and gate 168, and the FINAL CARRY [CARRY IN (N) ] 124
from the most significant stage of the carry (see FIG. 2a) through
gate 170. The sign flip flop 158 is fed from the input bus through
gates 172 and 174.
The setting and resetting of the three flip flops 154, 156 and 158
are done by three signals, SET FF, RESTORE FF and RESET FF, which
are generated by the command generator 80.
Control Word Decoder 76
As was previously mentioned, the control word decoders 76 of the
present BPU may take the form, for example, of that shown in FIG. 4
z of U.S. Pat. No. 3,315,235 to Carnevale et al. and thus no
detailed explanation is required.
Timing Control Logic 78
The timing control logic 78 of the BPU utilizes a feedback
oscillator using a delay line. A simplified schematic
representation of a delay line oscillator of the type utilized is
illustrated in FIG. 4. The oscillator 178 includes a first logic
gate 180 connected in series with an inverter 182 which in turn is
connected in series with a first delay line 184 and a second
inverter 186. Logic gate 180 and the output of inverter 186. Logic
gate 180 and the output of inverter 186 are connected to a second
delay line 188 which is connected in series with another inverter
190. The wave forms of the outputs a, b and c of oscillator 178 are
set forth in FIG. 4a. Referring to FIG. 4a, it may be noted that
when a low going start signal is applied to gate 180, the output
(a) of gate 180 is high. The signal is inverted by inverter 182 so
that the output (b) of delay line 184 is a low signal 192 displaced
by the delay imposed by delay line 184. The low signal 192 is again
inverted by inverter 186 and presents a high signal for the second
input of gate 180 causing the output (a) of gate 180 to go low. The
output of inverter 186 is also re-inverted by inverter 190 after
the time delay imposed by the second delay line 188. Thus, the
output of inverter 186 will recycle the oscillator 178 unless the
start signal has been switched to high.
The above general scheme is utilized in he actual timing control of
the present BPU which is illustrated in FIG. 5. Before discussing
FIG. 5, however, a few general words in connection with the timing
control required for the BPU may be in order. In the BPU, each
control word is acted upon in four time intervals, as shown in FIG.
4b. During synchronous operation, the time intervals are equal and,
by making the delays imposed by delay lines 184 and 188 equal, the
intervals may be expressed in units of delay. The first time
interval, T1, is used for addressing the memory. The second
interval, T2, is used for reading information into a register 14
and for processing data in the ALS 22. During the third time
interval, T3, the result is stored in a register for readout and
during the fourth interval, T4, the data processing for that
command word is accomplished and the unit is placed in condition
for receiving the next control word. During asynchronous operation,
the time intervals are not necessarily equal and/or may further
vary between cycles.
To obtain the four time interval cycle, any binary counter may be
utilized. However, in order to avoid the use of decoders for time
interval generation, as would be required by a straight binary
counter, a group of six flip flops, arranged as shown in FIG. 5, is
utilized. Accordingly, flip flops 192 (a-d) are arranged in double
deck fashion with flip flops 194 (a and b) as shown.
When an external start signal is applied to the synchronizing bus
90 through external connector 88, flip flop 192a is set through
gate 196a. A suitable inverter 198 must be provided to invert the
signal which is customarily present as a high signal at the
interface 88 of the synchronizing bus 90. When flip flop 192a is
set, a first pulse is generated to gate 198a. This signal starts
the oscillator in the manner previously described if the other
input 204a of gate 198a is low. In this connection, gates 198
correspond to gate 180 of FIG. 4; gate 200 corresponds to inverter
182 of FIG. 4; and the remaining components of the oscillator of
FIG. 5 have been given he same reference numerals as the
corresponding parts of the oscillator of FIG. 4.
As soon as the output of inverter 190 goes low, flip flop 192b will
be set and flip flop 192a will be reset terminating time interval
T1 and generating T2. In a similar fashion, T3 and T4 can be
generated. Flip flops 194a and 194b serve as a counter to insure
that only the next following of the upper flip flops 192 is set
thereby maintaining the desired sequence. The timing pulses (T1,
T2, T3 and T4) are transmitted from the timing control logic to the
command generator through connection 202. As will be noted, gates
198 each have associated therewith an additional input 204 (a-d).
It should be apparent that the oscillator of FIG. 5 can only
operate in the manner described so long as the input signal 204 to
gate 198 is a low signal. If the input 204 to a gate 198 becomes a
high level signal, the time interval generated by that gate will be
delayed. The inputs 204 to gates 198 are generated by that portion
of the system affected during the particular time interval. That
is, during the memory addressing time, permit will come from one of
the memories. During the readin from the memory or other equipment,
permit will come from the main memory or the other equipment;
during the readout, permit will come from the ALS and during the
storage and terminating intervals, permit will be issued by one of
the memories.
Command Generator 80
The command generator 80 is a conventional unit well known and
defined in the art. Such a command generator, for example, is
disclosed in the Carnevale et al. patent previously referred to.
The command generator 80 provides four basic commands: readin,
readout, reset and commands for the ALS 22. The command generator
in a piece of combinational logic which is used to generate all
commands to conduct data transfer and ALS operations. The inputs to
the command generator are the outputs of the control word decoder
76 and timing control logic 78, as was previously described.
Combined BPU Processor
The basic processor unit 10 which has heretofore been described has
inherent limitations in that the number of registers and the number
of bits available in the registers are predetermined. Because of
this, the length of the associated operands are necessarily
limited. However, the BPU 10 is so designed as to allow its
combination with one or more additional BPUs so that the number of
bits can be increased without increasing the number of facilities,
merely by increasing the length of the facilities, or alternately,
the number of facilities can be increased without increasing the
number of bits per facility.
In both cases, the increased capacity is attained solely by
coupling a first BPU to another identical BPU.
Accordingly, in FIG. 6a, a first BPU 10a is provided along with an
identical second BPU 10b. Both the BPUs 10a and 10b are identical
to the BPU 10 depicted in FIG. 1 and described above. In this
arrangement, the capacity of the combined processor unit (PU) 206
is twice that of a single BPU 10. To achieve the increased word
length, the external output data buses 46a and 46b of the BPUs (10a
and 10b) are put together and treated as a single data bus 208.
Similarly, the address buses (66a and 66b) of the BPUs (10a and
10b) are put together (without connections) and treated as a single
address bus 210. The synchronizing buses 48a and 48b are tied
together (bit position by bit position) in parallel to form a
single synchronizing bus and, similarly, the control buses 92a and
92b are tied together in parallel to form a single control bus.
It should be realized from a study of FIG. 2c that each wire of the
output data bus 46 has a bit position assigned to it. In addition,
there must be two extra wires to provide the shift left and shift
right facility. Therefore, the total number of bit positions of two
combined output data buses is equal to twice the number of bits of
each BPU register plus 4. Since only two extra bit positions are
required for the shifting facility, there must be an overlap of two
bit positions in the combined data bus. Accordingly, two wires 212
and 214 of the data bus 46a of BPU 10a must be mechanically tied to
two wires of the data bus 46b of the other BPU 10b. When this is
accomplished, the resultant combined data bus will still have the
two excess wires required for shift left and shift right
facility.
As shown in FIG. 6a, the control buses 92 of the BPUs are tied to
one another bit position by bit position. For simplicity, only a
single line was drawn to show these connections. Referring briefly
to FIG. 3, one will note that the overflow flip flop 156 and sign
flip flop 158 each has associated therewith an inverter (220 and
222, respectively) which provides an additional input to the
associated output logic (224 and 226, respectively). The function
of the inverters 220 and 222 is to enable or disable the gating out
of their associated flip flops, as determined by the control word.
Since overflow can only be determined by the most significant bit
of the processor unit, only the most significant BPU (in this case
10a) may be selected for flow sensing by the control word.
Accordingly, pins 228 and 230 of BPU 10b would not be connected to
the control memory to be associated with the processor and,
therefore, are shown blank in FIG. 6a.
Another, and possibly easier, way of looking at this problem is
that overflow can only occur at the most significant BPU of a
combined BPU processor. Therefore, there is no need for overflow
facility in BPU 10b because any "overflow" would be carried into
BPU 10a.
Similarly, it is customary for the most significant bit of the
operand to be used to represent the sign of the operand.
Accordingly, there is no need for any BPU other than the most
significant BPU to represent the sign of the operand or resultant
which can be gated onto the output bus. Therefore, the control word
selects only the most significant BPU 10a.
From the above, it should be apparent that sufficient output
terminals must be provided on the BPUs so that carry information
can be transmitted from the less significant BPU 10b to the most
significant BPU 10a. Of course, if a third BPU were connected to
BPU 10b to further increase the word length facility of the total
processor unit, it, too, would have to have sufficient terminals so
that its carry cold be transmitted to BPU 10b and so on. In a
similar manner, where there is initial carry, all but the last
significant BPU must be inhibited from receiving the initial carry
signal and, accordingly, suitable terminals must be provided on the
BPUs to receive the necessary biasing voltage to inhibit initial
carry.
In FIG. 6b, an alternate method of joining two (or more)BPU's is
illustrated wherein increased facility is obtained without
increasing the number of bits. This type of arrangement would be
desirable, for example, where a floating point is required thereby
necessitating the use of two adders. In this arrangement, the
corresponding bits of the data buses 46a and 46b and address buses
66a and 66b are mechanically tied together. The synchronizing buses
48a and 48b and the control buses 92a and 92b, however, are
maintained separately. The control word can now be twice as long as
that which could be accommodated with a single BPU since the number
of facilities is doubled rather than made longer, as was the case
in the arrangement in FIG. 6a. The problems discussed in
conjunction with FIGS. 6a relating to overflow, sign, carry,
initial carry, etc., do not arise with the arrangement of FIG.
6b.
It should be obvious that neither the arrangement of FIG. 6a nor
that of 6b is limited to merely two BPUs and, in fact, any desired
number of BPUs may be combined in the manners shown. Further, it
should also be apparent that the arrangements of FIGS. 6a and 6b
can be combined with one another so that by using sufficient BPUs
and PU with both increased word length and increased facility to
any desired degree may be obtained.
Because the BPU of the present invention is designed to be
microprogrammed through a control memory and because both
conventional CPUs and I/o channels are merely data processors, it
should be readily apparent that with proper microprogramming the
BPU or a suitable combination of BPUs may be adapted to replace the
conventional CPU or I/o channel. Alternately, with suitable
microprogramming a PU made up of sufficient BPUs may provide the
heart of a unique data processing system, as will now be
described.
Data Processing System
In order to best understand the data processing system of the
present invention, a brief discussion of presently existing data
processing systems may be useful. Accordingly, in FIG. 7a, a block
diagram of a typical so-called third generation general purpose
computer is illustrated. Such a data processing system is described
in detail in U.S. Pat. No. 3,315,235.
The prior art data processing system 232 utilizes a main memory 234
as a primary storage. The contents of the main memory can be read
out repeatedly without causing any change therein. When desired,
the contents of the main memory can be changed by new information
obtained either from the input devices 236 or the central processor
unit 238, as will be described forthwith.
A central processing unit (CPU) 238 is the heart of the third
generation computer since all instructions to the computer must
first be decoded in the CPU and then executed in the CPU itself or
in an I/o channel 240. If an instruction is to be executed in the
CPU itself, the CPU will execute a series of machine cycles or
micro-instruction which generate the necessary commands to conduct
the data transfer and/or manipulation in the predetermined sequence
designed for that instruction. The operations may or may not
involve the main memory 234.
In the event a microprogram is utilized in this system, the
microprogram is stored in a control memory 242. In place of the
control memory 242, the CPU may be designed utilizing logic gates
to perform the required operations obviating the need for the
control memory and its microprogram. However, since
microprogramming can compensate for irregularities in the CPU
logic, it is most common and increasingly popular at the present
time to utilize a separate control memory rather than rely on logic
gates for executing instructions.
The various input-output (I/o) instructions used in a program are
also stored in the main memory and must pass through the CPU before
being sent onto the I/o channel 240 which in turn will issue orders
to the I/o control 244 for subsequent execution by the various I/o
devices 236. The purpose of utilizing I/o channel 240 is to prevent
the CPU 238 from being bogged down awaiting the completion of
operations by an I/o device. That is, the principal purpose of
using I/o channels is to obtain, as much as possible concurrent or
simultaneous operations between the CPU processing and the I/o
processing. However, when high level I/o languages such as FORTRAN
or macro-instructions are used, the compiled or assembled results
will contain a greater number of machine instructions, yet only a
portion of them are the machine level I/o instructions and, hence,
the degree of concurrency is, at best, limited.
As shown in FIG. 7a, an I/o channel 240 may be designed to handle a
single I/o device or several devices at a particular instant. To
achieve concurrency, a channel has its own registers to store the
vital information of I/o instruction. The I/o control 244 is
interposed between the I/o channel 240 and the I/o devices 236 so
that the interfaces between the I/o channel 240 and devices 236 and
instruction formats can be greatly simplified. With the I/o control
244 interfacing the I/o devices 236 to the I/o channel 240, as far
as the I/o channels are concerned, the various devices 236 are
substantially all alike.
Referring now to FIG. 7b, a block diagram for the presently
proposed data processing system is illustrated. As will be noted,
in accordance with the present system, the CPU and I/o channels of
the prior art system are replaced by processor units (PU). Although
only two PU's 248 and 250 are shown in FIG. 7b, it will become
apparent from the following description that the present system is
by no means limited to two processors and the number of processors
utilized will be determined by the ultimate function of the total
system.
EAch of the processors 248 and 250 comprises at least one, but
possibily more than one, of the previously disclosed and described
BPUs. The processors thus comprise either the single BPU 10 of FIG.
1 or a combination of BPUs as set forth in FIGS. 6a and/or 6b. With
appropriate microprogramming each of the processors is capable of
executing those instructions associated with the I/o devices as
well as those instructions not associated with the I/o devices PUs
248 and 250 are identical in logic structure and have the same
capabilities although they may be micro-programed differently. That
is, the PU 250 of FIG. 7b differs from the I/o channel 240 of FIG.
7a in that PU 250 is capable of doing the so-called normal data
processing as well as I/o processing. Similarly, PU 248 which is
not associated with the I/o devices is capable of doing the
so-called normal data processing of the CPU 238 of FIG. 7a as well
as I/o processing.
In the disclosed system of FIG. 7b, PU 248 is provided and used to
execute those instructions not associated with the I/o devices 252.
This PU may be called a data processor since it handles the
computations and data manipulations. The operations of PU 248 are
conducted by its own control memory 254. PU 250 has connected to it
at least one I/o control 256 and the associated I/o devices 252. PU
250 is conducted by a second control memory 258 and in the
described embodiment may be termed an I/o processor. The
determination of which of the PUs (248 or 250) operates on a
specific instruction is determined by the instruction operation
code. For instance, the most significant bit of the operation code
can be used to select the proper control memory (254 or 258). It
can also be used to gate the remaining part of the instruction word
to the selected control memory and the associated PU (248 or 250).
As soon as an instruction word is sent to PU 250, control is
returned to the instruction fetch which is a function of PU 248.
While PU 250 is executing the I/o instruction, PU 248 is ready to
fetch the next instruction. Concurrent operations are thus
obtained. The primary storage is a main memory 260 which is
connected to both PUs (248 and 250).
There are no operation code decoders used in processors (248 and
250) of the present system 246. A large portion of the operation
code is used as the starting address of the microprogram (in either
of the control memories 254 and 258) to be used for executing that
particular instruction. Microprograms are written so that no
sharing of micro-instruction locations exist between instructions
and the last micro-instruction is used to pass control to the
instruction fetch.
In the typical case, the micro-instructions of a microprogram are
in sequence. However, both a conditional transfer of control and
unconditional transfer of control must be allowed. The
unconditional transfer of control may be carried out easily by
providing a partial next address or the complete next address in
each micro-instruction word. As was previously mentioned, the
control word used for the BPU is a part of the micro-instruction
word. The conditional transfer of control may be executed by
modifying the next address based on the results of the control flip
flop (24 of each BPU) sensing. The control word uses a fixed format
of coding and completely specifies the operations to be carried out
by a PU.
Because of the above, one distinction which may readily be noted
between the present system and that typified by the prior art
system of FIG. 7a is that there is no direct connection between the
data processing PU 248 and the I/o PU 250 in the new system whereas
there is a direct connection between the CPU 238 and I/o channel
240 of the prior art system. The new system thus enables the
complete I/o statements or macros to be sent to the I/o processing
PU 250 for execution without compilation. Of course, it still
depends on the microprogram of the I/o processor control memory 258
to interpret these statements or macros but the whole procedure
will be done inside the I/o processor 250 and, hence, a much higher
degree of concurrency can be obtained.
Stated another way, the proposed system 246 utilizes a
multi-processor approach in that the I/o processor 250 is not
subordinate unit of the data processor 248. Additional PUs can be
added to the system 246. Each additional PU would require its own
control memory. A small portion of the operation code of an
instruction is used to select a certain control memory and it is
also used to gate the remaining part of the instruction word to the
relevant PU and its control memory. Only one processor (PU 248 of
FIG. 7b) is responsible for the entire instruction fetch of a
program.
As was previously stated, the PU's (248, 250 and any additional
units that may be desired) are all built from an identical basic
logic structure, the BPU of FIG. 1. Because of this, any one
processor made with the same number of BPUs connected in the same
fashion as any other processor, may be interchangeable with the
other processor. It is the control memories, and more particularly
the microprograms stored in the control memories, which determine
the specific function of a particular processor.
While a particular form of my invention has been illustrated and
described herein, various modifications may be made without
departing from the spirit and scope of my invention. Accordingly, I
do not intend that the invention be limited except as by the
appended claims.
* * * * *