Apparatus For Indicating Numerical Information

Abstract

A multidigit decimal number display apparatus comprises a predetermined plurality of numeral display elements corresponding to a plurality of individual digit display positions each capable of selectively indicating a minus sign or any desired Arabic numeral. The apparatus displays the digits of the decimal number on a time-sharing basis in accordance with data identifying the digits of the decimal number and registered in a main circulation shift register. Means are provided for generating a logical state pattern signal identifying the stages of the main register containing data identifying the decimal number. Means responsive to the logical state pattern signal effects cancellation of zeros in all display positions exceeding the most significant digit of the decimal number. Further means responsive to the logical state pattern signal generates an enabling signal identifying the display position immediately preceding the display position for the most significant digit of the decimal number. The enabling signal is also responsive to the state of the decimal number as plus or minus to activate the immediately preceding display position to display a minus sign in accordance with that state. Each display element comprises a plurality of light-emitting segments having a minus-in-square configuration wherein the horizontal middle segment is activated to provide the minus sign indication.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to an apparatus for displaying numerical information and, more specifically, to such an apparatus in which a plus or minus sign indication is provided in such a position as to be most readily perceived with respect to the digits of its associated number, as displayed.

2. Description of the Prior Art

It is conventional today to process numerical information in electronic data processing apparatus; the resultant numerical information, or output data, produced by the apparatus is then typically provided to some subsequent utilization device. In particular, a display device may receive the output numerical information and convert it for a visual display for observation by an operator. Such visual display devices may be of various types, such as indicating tubes, cathode-ray tubes, sheets of paper on which information is printed by means of a printer, etc.

For the purpose of display of numerical information containing plurality of digits, a predetermined plurality of indicator, or display, elements or portions, each operable to display a digit, are provided in line to form the display system or indicator. In general, there is provided a number of indicator elements or portions which exceeds the number of digits in the largest decimal numbers anticipated to be displayed. Hence, the display of a decimal number frequently requires less than the total number of such elements or portions. In those instances, the remaining elements or portions of more significant position than the digit of greatest significance in the number displayed are caused to display a "zero."

Heretofore, a plus or minus sign of the decimal number has usually been indicated by means of a surplus display element specifically provided for display of such a sign, and which is positioned immediately before the most significant digit display element or portion of the display system.

Display of the sign in such a position, however, makes it difficult for the operator to observe the sign and relate it to the decimal number, especially in the case of a decimal number of only a few digits, relative to the total number of available digit positions. Such an arrangement for displaying the sign has typically been used heretofore due to the difficulty presented in providing for a display of the sign in a position immediately before the most significant digit of the decimal number since the number of digits of the decimal numbers varies. The difficulty is especially aggravated in the case that the decimal number is registered in a circulation shift register for supply of the information required for display of the number by the indicator. Thus, it has long been recognized to be advantageous and desirable to indicate or display the plus or minus sign immediately before the most significant digit of a given decimal number, but the prior art has failed to provide a simplified scheme to do so, irrespective of the number of digits of the decimal number. The present invention achieves that purpose.

In effecting such a display of the plus or minus sign, the zeros in the digit positions exceeding the most significant digit of the number to be displayed should be blanked out. Many systems have been proposed heretofore for suppressing or preventing the display of the undesired zero in the more significant digit positions. A system for cancelling such zeros is fully disclosed in the Japanese Pat. application, Ser. No. 44/11309 entitled "Information Output system," and may be advantageously employed for this purpose, the inventor of the invention covered by that application being the inventor of the subject matter of the present application.

Indication, or display, of the plus or minus sign in the appropriate one of the plurality of possible positions immediately before the most significant digit of a given decimal number requires a corresponding plurality of sign display elements for displaying such sign, each being positioned immediately before every numeral display element. These indicator elements for display of the sign, however, may be incorporated into the numeral display elements.

Many types of numeral display devices have been used as display elements. One type of them is a device having a plurality of light-emitting members each having the shape of a given Arabic numeral, for example, and being selectively controlled so as to emit light independently. A light-emitting member having the shape of a plus or a minus sign also is provided in each such device. Another type of device has a plurality of light-emitting segments arranged in a generally square configuration and including a segment or segments forming either a plus sign or a minus sign interiorly thereof, referenced hereinafter as a plus-in-square or minus-in-square indicator, or display element. In such a segment-arranged device, display of an Arabic numeral, for example, is effected by causing the emission of light in segments selected in accordance with the numeral to be indicated. In this type of device, the plus- or minus-shaped segment or segments are advantageously utilized to provide a plus or a minus sign.

SUMMARY OF THE INVENTION

Briefly stated, the invention comprises a decimal number indicator, or display means, comprising a plurality of serially arranged numeral indicator, or display, elements wherein each element is capable of selectively displaying any desired numeral, and a plurality of plus or minus sign display elements positioned immediately before every numeral display element. As hereinafter appears, each digit or numeral display element may also provide for display of the plus or minus sign, and thus the display element for the latter is merely the display element immediately before that one employed for display of the most significant digit of the numbers to be displayed. A group of serially arranged numeral indicator elements display a decimal number in accordance with information defining that decimal number which has been stored in a register, typically in a suitable digital code. A means is further provided for generating an enabling signal representative of the position of the plus or minus sign indicator element immediately before the most significant digit of the decimal number to be displayed. This enabling signal is applied to the indicator so as to energize the plus or minus sign indicator element which is immediately before, -- i.e., immediately precedes, the most significant digit of the displayed number. Thus, a plus or minus sign is indicated immediately preceding the displayed decimal number.

The enabling signal is generated by logic means responsive to a logical state pattern signal which is representative of the digit positions in the register which store the digital information of the decimal number to be displayed. As noted, such a plus or minus signal indicator element may be incorporated into and jointly built with a numeral indicator element. Thus in a preferred embodiment of the invention, a plurality of indicator elements each constituting a digit and being capable of indicating a plus or minus sign as well as numerals is provided to form an indicator having an indicating capacity of a desired number of digit positions. By employing a segment-arranged numeral indicating element or device having the segments arranged in the form of a minus-in-square, a horizontal middle segment and/or a vertical middle segment may be advantageously utilized to indicate a plus or minus sign.

Therefore an object of the invention is to provide an improved apparatus for displaying multidigit numerical information.

Another object of the invention is to provide such an apparatus for displaying a plus or minus sign which may be observed with extreme ease in relation to the displayed multidigit number, regardless of the number of digits in the number.

A further object of the invention is to provide such an apparatus wherein a plus or minus sign is displayed immediately preceding a displayed, multidigit number, regardless of the number of digits of the decimal number.

Still another object of the invention is to provide such an apparatus wherein the zeros heretofore provided in the digit positions exceeding the most significant digit of the displayed decimal number are cancelled and a plus or minus sign is displayed immediately preceding the most significant digit of the displayed number.

It is a further object of the invention to display a plus or minus sign immediately preceding the multidigit number by driving a plus or minus sign indicator as a function of an enabling signal representative of such digit position.

It is still a further object of the invention to provide a simplified scheme for generating an enabling signal representative of the digit position immediately preceding the displayed multidigit numerical information.

It is still a further object of the invention to provide a simplified indicator for displaying a plus or minus sign immediately preceding the displayed multidigit numerical information.

Still a further object of the invention is to display a minus sign immediately preceding a multidigit decimal number by using a horizontal middle segment of a segment-arranged numeral indicating device having the segments arranged in the form of minus-in-square out of a group of a plurality of such indicating devices forming a multi-digit decimal number indicator.

These objects and other objects and features of the invention will be apparent and more fully understood from the following description of the invention made with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a structure of a segment-arranged numeral display device for use in an apparatus in accordance with this invention;

FIG. 2 is a block diagram of an embodiment of the invention;

FIG. 3 is a block diagram of a logic decision circuit included in the embodiment shown in FIG. 1;

FIG. 4 shows waveforms employed in generating a logical state pattern signal to which reference is had in explanation of the operation of the apparatus of the invention; and

FIG. 5 is a block diagram showing the logic circuit between a main register of FIG. 2 and an auxiliary register of FIG. 3 for generating the logical state pattern signal.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In FIG. 1 is shown a numeral indicating element or device suitable for employment as one of a plurality of such devices in an indicator or display apparatus operated in accordance with the invention. The indicator of FIG. 1 comprises a plurality of light-emitting segments arranged in a minus-in-square configuration to which reference was made previously. The apparatus of the invention may, of course, employ any suitable type of numeral indicating devices, several alternative forms of which have previously been mentioned in the description of the prior art. Thus, the specific device of FIG. 1 is shown only for purposes of providing a specific example of one form of apparatus constructed in accordance with the invention.

The numeral indicating device 10 shown in FIG. 1 comprises three horizontal segments 1a, 1b, and 1c and four vertical segments 1d, 1e, 1f, and 1g. The segments are each of an elongated, approximately rectangular construction and are arranged in the noted minus-in-square configuration in FIG. 1. As is apparent with reference to FIG. 1, the middle horizontal segment 1a may advantageously and conveniently be utilized, when selectively illuminated, to provide a minus sign in accordance with the invention.

A plurality of incandescent lamps 3a through 3g corresponding to the segments 1a through 1g are positioned directly adjacent to and centrally of the respectively corresponding segments 1a through 1g. Energization of the lamps causes uniform, independent illumination of the corresponding segments and thus by selectively energizing the lamps, the corresponding, selectively illuminated segments define a numeral in a relatively continuous configuration for observation by an operator. The numeral indicating device 10 comprises a single common lead 4 connected to one terminal of the lamps 3a through 3g and a corresponding plurality of individual leads 2a through 2g each connected to the other terminal of the corresponding lamps 3a through 3g.

FIG. 2 shows a block diagram of the numeral display apparatus of the invention employing the above-mentioned numeral indicating device 10. It is to be noted that in this embodiment the display is made on a time-sharing basis. Display systems operating on a time-sharing basis are well known to those skilled in the art. Synchronized control in the operation of a system on a time-sharing basis, such as that of FIG. 2, is well known in the art and thus specific illustration of the synchronization control circuitry has been omitted in FIG. 2.

The numeral indicating or display apparatus of FIG. 2 comprises a pulse distributor 30, a numeral indicating portion 20, a main register 50 and control circuit means connected therebetween. Numeral indicating portion 20 comprises a plurality of serially arranged numeral indicating devices 10a through 10n. The number of the indicating devices 10a through 10n is selected in accordance with the maximum desired number of digit or numeral positions to be displayed by the indicator 20. Each of the numeral indicating devices 10a through 10n includes a common lead 4 shown extending vertically upwardly and a group of individual, selectively energized leads 2a through 2g shown extending vertically downwardly from each of the individual indicating devices, some of the intermediate ones of the leads 2a through 2g being represented only by dotted lines for ease of illustration.

Connected to the respective indicating devices 10a through 10n are provided a corresponding plurality of transistors 5a through 5n. Each of these transistors 5a through 5n is connected at its emitter to the common lead 4 of the corresponding digit indicating device, at its collector to a common power bus in turn connected to a positive voltage source terminal 6, and at its base to respectively corresponding output terminals of a pulse distributor 30. In accordance with the time-sharing mode of operation of the display apparatus of the invention, the pulse distributor 30 serves to distribute pulse signals to the bases of the transistors 5a through 5n to enable them individually and in sequence in a repeating or cyclical fashion in the sequence of from the least significant digit to be displayed to the most significant digit and thus in the sequence of from transistor 5a to transistor 5n, respectively.

The corresponding ones of the individual leads 2a through 2g are connected in common to the respectively corresponding leads 7a through 7g. Thus, each of the segments 1a through 1g of all of the individual indicators 10a through 10n are connected in common to the respectively corresponding ones of the common leads 7a through 7g. For example, all of the leads 2a are connected in common to the lead 7a, and the like.

Corresponding to the common leads 7b through 7g there are provided a plurality of transistors 8b through 8g. A special circuit is provided for the lead 7a corresponding to the middle horizontal segment 1a which provides the minus sign in each indicator and will be discussed hereafter. Each of the transistors 8b through 8g is connected at its collector to the corresponding one of the common leads 7b through 7g, at its emitter in common to the collector of transistor 9 and at its base to the respectively corresponding ones of the output leads 11b through 11g of decoder 40.

Decoder 40, as described more fully hereafter, decodes the digital information characterizing a numeral to be displayed and stored in register 50 for supply to the energizing network for the indicator elements. In accordance with these functions, decoder 40 includes the aforementioned output leads 11b through 11g in addition to an output lead 11a associated with the minus sign indication, and four input leads 12 connected to corresponding outputs of the least significant digit storage element 50a of the main register 50.

Main register 50 stores in each of its stages 50a through 50n digital information identifying the numeral, or digit, which is to be displayed in the corresponding digit position of the indicating apparatus 20. Particularly, as herein disclosed, the register 50 stores the digital information in a four-bit binary code supplied through the input leads 12 from the least significant element 50a of the register 50 to the decoder 40. The decoder 40 decodes the digital information thus received and converts it to an output signal in a new code formation. The new code is represented by the combined effect of the presence of absence of output signals on the output leads 11a through 11g. The code signals thus presented on the leads 11a through 11g cause the corresponding transistors 15 and 8b through 8g to be enabled and thus, in turn, to effect the energization of the thus selected lamps to cause illumination of the corresponding segments of the indicator devices 10a through 10n and thus the display of the desired, corresponding decimal number in the appropriate numeral indicating devices, all in accord with the time-sharing operation.

The main register 50, in general, has a capacity of the same number of digits as the numeral indicating portion 20, each digit storage element being denoted as 50a, 50b,..., 50n from the least to the most significant digit. Each digit storage element stores an information unit, or word, comprising a specific decimal number in accordance with, for example, a four-bit binary-decimal code. Numerical information in the main register 50 is circulated in a direction from the most significant to the least significant bit and thus in a rightward direction in FIG. 2. The circulation or shifting is effected in accordance with timing pulses supplied to the register 50 such that each word registered in each stage of the register ultimately proceeds to the least significant state 50a such that the order of presentation is from the least significant to the most significant digit positions. The digital word, or number information, arriving at the least significant digit storage element 5a is fed at a next shift time to the most significant digit storage element 50n through a connection 501. Such circulation or shift of the information is made in synchronism with the distribution of the pulse signals in the pulse distributor 30. Transistors 5a to 5n are selectively and sequentially enabled to permit energization of the corresponding display elements 10a to 10n on a time-sharing basis. Accordingly, the transistor of the group 5a to 5n corresponding to the i-th digit from the least significant digit of the number to be displayed is enabled just at the time that the digit word, or number information, in the i-th digital storage element from the least significant digital storage element 50a of the number to be displayed and which has been registered in the main register 50, is introduced or shifted into the least significant digital storage element 50a.

The transistor 9 is connected at its base to an output lead 13 of a sign determination circuit 60, the emitter of the transistor 9 being connected to a negative voltage source terminal 14. The circuit 60 determines the number of digits and the sign, i.e., plus or minus, of the number registered in the main register 50 and provides corresponding output control signals on the output leads 13 and 19, respectively. The circuit 60 plays a very important role in the disclosed embodiment of the invention and will be explained in more detail subsequently.

Transistor 15, previously noted to be associated with the middle horizontal segment 1a is connected at its collector to the common lead 7a, at its emitter to a negative voltage source terminal 16, and at its base to an output lead 18 from an OR-gate 17. The OR-gate 17 has two input leads, one being connected to the output lead 11a of the decoder 40 and the other being connected to another lead 19 of the decision circuit 60.

The decision circuit 60 is shown and described in more detail with reference to FIG. 3. The decision circuit 60 comprises an auxiliary register 70, a plus-or-minus decision circuit 80, an AND-gate 90, an inverter 100 logic OR-gates 85 and an inhibit gate 81. The shift register 50 of FIG. 2 is furthermore shown in FIG. 3 in greater detail than in FIG. 2 to indicate its operative relationship with the decision circuit 60; it is to be understood, however, that this is the identical register 50 of FIG. 2. The output from the shift register 50 furthermore is seen to include four outputs from the individual bit positions comprising the first three of stage 50n and the last or least significant bit of the stage 50a.

The structure and function of the decision circuit 60 is considered in greater detail in conjunction with the discussion hereinafter of the circuit of FIG. 5 as to which it will be noted identity exists as to the register 70, the logic OR-gates 85, the inhibit gate 81, the auxiliary register 70 and their respective interconnections. The circuit of FIG. 3 is therefore considered here only briefly. The auxiliary register 70 is a circulation shift register having the same number of stages as the number of stages in the main register 50, each stage comprising a bit storage element and corresponding to the stages of register 50; thus, they are denoted as 70a, 60b,..., 70n, respectively corresponding to the stages 50a to 50n and thus from the least to the most significant digit. The logical state information is derived from the three most significant bit positions of stage 50n and the least significant position of 50a of the register 50 through the four input OR-gate of the network 85 and applied through the two input OR-gate of that circuit to the most significant stage 70n of the auxiliary register 70. The logical state information stored in every bit storage element in the auxiliary register 70 is advanced in succession to the least significant bit storage element 70a in the order of from the logical state information stored in the least significant bit storage element 70a to that stored in the most significant bit storage element 70n. The logical state information arriving at the least significant bit storage element 70a is fed through a lead 701, inhibit gate 81 and a two input OR gate of the logic circuits 85 to the most significant bit storage element 70n for the purpose of recirculating the logical state information in the auxiliary register 70.

The information registered in the auxiliary register 70 comprises a logical state pattern that is representative of the discrimination of the digit positions in the main register 50 wherein there is stored the data, or numerical information, of the number to be displayed. Assume, for example, that a number registered in the main register 50 includes two digits, and at a given moment the data for the said number is stored in the two stages of the register 50 comprising the least significant digit storage element 50a and the next significant digit storage 50b. At that time, the information registered in the auxiliary register 70 is a logic state pattern comprising the logic designation "1," or one, in the least significant bit storage element 70a and also in the next successive significant bit storage element 70b, and with the logic designation "0," or zero, in the remaining, successively more significant bit storage elements, as shown as A in FIG. 4. As seen from the illustration, the information registered in the auxiliary register 70 is representative of the digit positions, or stages of the main register 50, in which the data representing the number to be displayed is stored. An output signal is obtained on output lead 13 of the decision circuit 60 only when a logic "1" is presented in the least significant bit position 70aof the register 70.

As previously noted, each of the registers 50 and 70 circulates, or shifts, the information contained in the stages thereof from the most significant to the least significant position such that all of the stored data in the register 50 is presented in succession at the least significant stage 50a. Correspondingly, a logic "1" condition is presented in the least significant bit storage element 70a of the auxiliary register 70 only when there is also presented data identifying a numeral to be displayed, at that same time period, in the least significant stage 50a of register 50. With reference to FIG. 2, therefore, transistor 9 is enabled by the output signal on lead 13 from the decision circuit 60 and in turn enables transistors 8b through 8g only during those times in which data is presented to the decoder 40 identifying a numeral to be displayed.

Assume that a decimal number to be displayed contains m digits and that the main register 50 has a capacity of n digits. Where m<n, in prior art display apparatus the numeral zero would be displayed by the numeral display devices of the display system 20 which correspond to the n-m more significant digits which, in relation to the main register 50, corresponding to the n-m more significant data storage stages. In the embodiment as shown in the FIG. 2, however, such zeros in the said n-m more significant digit position are inhibited from being indicated as a function of the logic state pattern signal A in the auxiliary register 70. The logic state pattern signal A shown and discussed above with reference to FIG. 4 may be produced in accordance with the system comprising the subject matter of Japanese Pat. application, Ser. No. 44/11309 entitled "Information Output System". The system of that other application is described herein in sufficient detail to understand its operation in the context of the display system of this present invention.

In FIG. 5, there is shown in block diagram form the system of the above-noted application. The system includes a main register 50 and an auxiliary register 70, such as shown and discussed in relation to FIGS. 2 and 3, respectively, and logic means which interconnect the registers 50 and 70. Each of the stages 50a through 50n is indicated by dotted lines to contain the storage of four bits identifying a single digit or numeral to be displayed in accordance with the bit data stored therein. The logic means comprises a first logic means 85 responsive to the presence of, or storage of, a digit in any of the stages of the main register in accordance with the storage therein of a digit of the stored decimal number other than zero by detecting a preselected set of four consecutive bit positions. The logic means 85 also serves to write the resultant information from the detection into a bit position in the auxiliary shift register 70, thereby to designate in the latter the positions of digits in the corresponding positions or stages, of the main register 50. A second logic means 81 is connected between the stage 70b, the next to the least significant stage 70a, and the most significant stage, particularly the stage 70n, for circulating the information stored in the stages of the auxiliary shift register 70 in synchronism with the circulating of the information stored in the stages of the main shift register 50 and for rewriting, or shifting and storing, the information thus stored into the adjacent bit positions of the auxiliary register 70. The rewriting, or restoring, of the information, however, is inhibited by the second logic means 81 with respect to and thus as a function of the stored information corresponding to the least significant digit of the decimal number registered in the stages of the main shift register 50. During the repetition of the circulation, a bit pattern signal or logic pattern signal A as shown in FIG. 4 is effectively generated by the auxiliary register 70. The logic "1" states in the logic state pattern are indicative of the digit positions of the digital number to be displayed, as registered in the main register 50. The bit pattern or logical state pattern signal thus developed is applied to the display system 20 through a control circuit 95 so as to prevent the undesired "0" display from being effected in the digit positions of the display exceeding the position of the most significant digit of the numeral to be displayed.

Referring again to FIG. 3, the plus-or-minus decision circuit 80, the AND-gate 90, and inverter 100 cooperate with the auxiliary register 70 to generate an enabling pulse on the output lead 19 to effect the display of a minus sign in the display position next adjacent to the most significant digit position, the plus or minus decision circuit 80 operating to determine the plus or minus state of the number to be indicated and to supply to the AND-gate 90 a control signal indicating the state of the decimal number as being minus, i.e., a minus signal. The AND-gate 90 includes as inputs the output lead from decision circuit 80 comprising the noted minus signal and two input leads 702 and 703, the lead 702 being supplied through the inverter 100 from the output of the least significant digit storage element or stage 70a while the lead 703 is connected to the most significant digit storage element 70n of the auxiliary register 70.

The signal thus provided on lead 702 is the converse of the logic state pattern signal A, i.e., NOT A or A, and is shown at B in FIG. 4. The signal presented on the lead 703 from state 70n is a signal delayed by one digit time with respect to the signal A and is shown at C in FIG. 4. The AND-gate 90 therefore responds to the presence of a minus indication signal or output from the plus-or-minus decision circuit 80 and the signal B comprising the NOT of the signal A, i.e., A, and the delayed signal C to produce an output comprising the signal of waveform D in FIG. 4; the waveform D will be recognized to provide a logic "1" or true output of a one digit time duration and one digit time position in advance of the most significant digit position of the number to be indicated.

Thus, again with reference to FIG. 3, and also in relation to FIG. 2, there is provided on the output lead 19 of the circuit 60 the signal D which, applied through gate 17 and lead 18 to the base of transistor 15, provides for enabling the transistor 15 when, and only when, the decimal number to be displayed, and which is registered in the main register 50, is a minus state number and when, and only when, the stored information of the most significant digit of the decimal number to be displayed, has arrived at or been shifted to the most significant digit position or storage 50n of the main register 50. The enabling of the transistor 15 as thus effected serves to energize the common lead 7a and the corresponding leads 2a, and through the remaining logic circuitry, effects the display of a minus sign by the indicating element which immediately precedes the indicating element then effecting the display of the most significant digit of the decimal number then being displayed by the numeral display system 20.

The system disclosed may, of course, accommodate the particular situation wherein of a given decimal number to be indicated, the digits thereof may potentially occupy or correspond to all of the digit positions which can be accommodated by the numeral display system 20. In view thereof, it is preferred to provide a display device capable of displaying only a minus sign and positioned immediately preceding the most significant digit position of the numeral display system 20. Such a display device may be of far simpler construction, of course, or may be identical to the other display elements. The signal required for energizing this minus sign display device, such as a signal for energizing a lamp to provide that minus display, may readily be generated by the output of an AND gate which comprises the logical product of the following three signals; a timing pulse occurring at a time when the stored digital information of the most significant digit or numeral of the digital number to be displayed, in this instance, is shifted to or arrives at the least significant digit storage element 50a of the main register 50; the signal A; and the presence of an output from the plus-or-minus decision circuit 80. It is noted that under these circumstances, the logic state pattern A indicates a logic "1" in all bit positions or stages; thus, no output is presented in output lead 19 for energizing the noted minus sign display segments of the numeral display devices.

As a specific example of the operation of the system of the invention, there is discussed hereafter the display of the digital number "-20. " In accordance with the foregoing description of operation of the system, the digital information identifying the number 20 has been registered in the main register 50 and is shifted or circulated through the stages of the main register 50 as a function of the timing pulses. Simultaneously with and during the time that the digital information identifying the least significant digit of the number to be displayed, i.e., the logical state pattern information of "0," is stored in the least significant digit storage element or position 50a, the transistors 5a and 8b through 8e, inclusive, and transistor 9 are enabled or turned on. There results the illumination of the segments 1b through 1g, inclusive, in the numeral display device 10a, thereby displaying the numeral "0" for observation by an operator.

Following that time interval, the above-noted shifting occurs such that during the next digit time, data identifying the logical state information of the digit "2" is shifted into and stored in the least significant digit storage element 50a. The digit "2" in the example is both the successively next significant digit and also the most significant digit of the decimal number to be displayed. In this digit time, therefore, the transistor 5b is enabled by the register 50 and the transistors 8b, 8c, 8e, and 8f, and the transistors 9 and 15 are enabled, resulting in illumination of the segments 1b, 1c, 1e, 1f, and 1a in the numeral display device 10b. The numeral "2" is thereby displayed by the device 10b for observation by the operator.

In the subsequent or next successive time period following that during which the numeral "2" was displayed as above described and thus during the digit time period in which the logical state information of the numeral "2" is stored in the most significant digit storage element 50n, the transistor 5c is enabled by the appropriate output of pulse distributor 30 and the transistor 15 is enabled as a function of the signal D described hereinabove in relation to FIG. 4. There results the illumination of the middle horizontal segment 1a in the device 10c effecting the display of a minus sign for observation by the operator.

The speed or repetition rate at which the display elements are selectively energized in accordance with this time-sharing basis of operation, is, of course, selected to assure visual persistence for ease of observation by the operator.

In case a number to be indicated is a plus number, no sign is indicated in the embodiment as disclosed in the foregoing description. Thus it is seen that no such sign immediately before the indicated number means the number is plus.

Though a light-emitting segment-arranged type numeral indicating device has been employed in the embodiment as disclosed herein, it is obvious to those skilled in the art that a common numeral indicating device such as a Nixie tube, which has an electrode for indicating a minus sign may also be utilized in the system in accordance with the invention. In this connection, it is to be pointed out that by employing, for example, a segment-arranged numeral indicating device having the segments arranged in the form of a plus-in-square and by employing a suitable additional circuit it is possible to indicate a plus sign as well as a minus sign immediately before the most significant digit of the indicated decimal number. Though in such a preferred embodiment as disclosed herein the numeral indicating device is capable of indicating a minus (or plus and minus) sign as well as the numerals, this should not be construed by way of limitation. Further, it will be appreciated that a plurality of separate indicating devices for displaying only a minus sign or either or both plus and minus signs, may be provided in positions immediately preceding and corresponding to every numeral display device and may be selectively activated in accordance with the system of the invention.

Accordingly, the term "state" is used hereinafter to signify the positive or negative state of the decimal number to be displayed and the term "sign" is employed to designate either or both of the positive and negative sign indications. As noted, the display of the sign for the purposes of the invention is sufficient if it be only minus, since in the absence of a sign display the number is understood to be positive, and the opposite likewise is true. In some applications, however, display of both positive and negative signs may be desired and the system of the invention clearly contemplates any of these specific display techniques for indicating the sign.

The embodiment as disclosed herein also employs the auxiliary register 70 for the purpose of generating the signal A and delaying by one digit time the signal A to obtain the signal C. However, this should not be construed by way of limitation. Alternatively, a delay device having a capacity of one digit time delay may also be utilized.

According to the invention, a minus sign is indicated immediately before the most significant digit of a given number, assuming that it is a minus number, irrespective of the number of digits of the said number to be indicated. Therefore, discrimination of the number to be indicated being plus or minus is readily perceived by the operator of the machine having the numeral indicating or display apparatus in accordance with the invention. Another advantage is that the invention is applicable to conventional numeral display devices operating on a time-sharing basis without any extensive modification.

While specific preferred embodiments of the invention have been described it will be apparent that obvious variations and modifications of the invention will occur to those of ordinary skill in the art from a consideration of the foregoing description. It is therefore desired that the present invention be limited only by the appended claims.

Claims

What is claimed is:

1. An apparatus for displaying numerical information comprising:

a register for registering data identifying a decimal number to be displayed,

display means for displaying said decimal number, said display means having a predetermined plurality of display positions for displaying digits of a decimal number in corresponding predetermined positions and for displaying a sign indication in each of a predetermined plurality of positions respectively related to said digit display positions,

means responsive to said data registered in said register for controlling said display means to display the decimal number registered therein,

means for generating an enabling signal identifying a display position related to the display position for the most significant digit of the decimal number to be displayed, and

means responsive to the state of said decimal number and to said enabling signal for controlling said display means to display a sign indication in a position related to the most significant digit of the decimal number.

2. An apparatus as recited in claim 1 wherein each of said plurality of display positions of said display means is operable to display selectively an individual digit of a decimal number or a sign indication.

3. An apparatus as recited in claim 2 wherein said means for generating an enabling signal generates a signal indicative of a digit position which is one digit position more significant than the most significant digit position of the decimal number displayed by said display means.

4. An apparatus as recited in claim 1 wherein:

said display means comprises a plurality of display elements defining said display positions, and

each of said display elements is operable to display selectively an individual digit of a decimal number or a sign indication.

5. An apparatus as recited in claim 4 wherein there is further provided a further display element immediately preceding the most significant digit display element of said display means, said further display element being selectively operable for displaying a sign indication for a decimal number having a most significant digit displayed in said most significant digit display element.

6. An apparatus as recited in claim 4 wherein each display element comprises a plurality of selectively activated display segments arranged in a configuration for indicating any desired digit in accordance with selective activation of predetermined segments.

7. An apparatus as recited in claim 6 wherein at least one of said segments may be selectively activated to display a sign indication.

8. An apparatus as recited in claim 7 wherein said segments are in the form of minus-in-square and a horizontal middle segment is used as a minus sign.

9. An apparatus as recited in claim 7 wherein said segments are in the form of plus-in-square and a horizontal middle segment is used as a minus sign.

10. An apparatus as recited in claim 9 wherein a horizontal middle segment and a vertical middle segment are used as a plus sign.

11. An apparatus as recited in claim 1 wherein said register for data identifying the decimal number to be displayed comprises a circulation shift register.

12. An apparatus as recited in claim 1 wherein said display means is operable on a time-sharing basis to sequentially and repetitiously display each digit and the sign indication of the decimal number on a time-sharing basis.

13. An apparatus as recited in claim 1 wherein said display means comprises:

a plurality of display elements selectively operable to display corresponding individual digits of the decimal number,

a plurality of sign display elements positioned in preceding relationship with respect to corresponding digit display elements, and

said means responsive to the state of said decimal number and to said enabling signal is operable to selectively activate the sign display element immediately preceding the digit display element corresponding to the most significant digit of the decimal number.

14. An apparatus as recited in claim 1 wherein there is further provided means responsive to said register for inhibiting the display of a zero digit in each digit position exceeding the most significant digit of the displayed decimal number.

15. An apparatus as recited in claim 1 further comprising means for generating a logic state pattern signal identifying digit positions of said register wherein data identifying the digits of the decimal number to be displayed is stored.

16. An apparatus as recited in claim 15 wherein there is further provided means responsive to said logic state pattern signal for identifying digit positions exceeding the most significant digit position of the decimal number to be displayed and for cancelling the display of a zero digit in those digit positions.

17. An apparatus as recited in claim 15 wherein said means for generating said enabling signal is responsive to said logic means for generating said logic state pattern signal to identify the display position for the sign indication of the decimal number.

18. An apparatus as recited in claim 15 wherein there is further provided means for detecting the state of the decimal number to be displayed.

19. An apparatus as recited in claim 15 further comprising means for delaying said logic state pattern signal by one digit position to identify the sign display position.

20. An apparatus as recited in claim 15 wherein said means for generating an enabling signal includes:

means responsive to said logic state pattern signal to produce a further logic state pattern signal of inverted form and delayed by one display position in time relative thereto, and

means for detecting the state of the decimal number to be displayed, said logic state pattern signal defining a logic "0" in all digit positions of the main register wherein data identifying the digits of the number to be displayed is registered.

21. An apparatus as recited in claim 16 wherein said means for generating the enabling signal comprises means for logically combining said logic state pattern signal, wherein that signal presents the logic "1" for each stage of the main register wherein data identifying the numerals to be displayed is stored, a signal comprising said logic state pattern signal in inverted form and delayed by one display position in time, and a signal identifying the state of the decimal number to provide a logic sum of these signals as the enabling signal.