Local Controller For Traffic Control System

Abstract

A local controller for use in a traffic control system is provided with all solid-state means for displacing the local traffic cycle relative to a master traffic cycle and for effecting the smooth transition between alternate displacements. The traffic cycle length is determined by measuring the period between the phase coincidence of two signals having a slight difference in frequency.

Description

BACKGROUND OF THE INVENTION

In traffic control systems, local controllers placed at intersections or along a roadway serve to sequentially accord the right-of-way to vehicular and pedestrian traffic in an initial traffic direction and then subsequently in another traffic direction before returning the right of way to the original direction and repeating the procedure. The time required for the local controller to complete a cycle is referred to as the traffic cycle length and is usually on the order of 40 to 120 seconds. The cycle length is usually timed by a cycle generator in a master controller which controls several local controllers, or in the individual local controllers by generating and then measuring the time lapse between the phase coincidence of two sinusoidal signals, one of which is gradually shifting in phase with respect to the other.

If the traffic cycle length is considered as being 100 percent of the time lapse between adjacent phase coincidences of the two signals generated by the cycle generator, the point in the cycle at which the right-of-way is accorded to a particular path of traffic may be expressed as a percentage of the cycle length. Two such points that are of particular interest are generally referred to in the art as the "offset" point and the "split" point. The "offset" point represents the time (usually expressed as a percentage of the traffic cycle) at which the local cycle zero occurs while the right-of-way is accorded in an initial direction and transfer of right-of-way is initiated to a second direction. The "split" point determines the time (again represented as a percentage of the traffic cycle) at which the transfer of right-of-way is initiated from the second direction to the initial direction, for example. Thus, depending on the complexity of the intersection sought to be controlled, there may be one or more split points but only a single offset point. Once the offset and split point or points are determined, the time interval between adjacent points, that is the time between the offset and the first split point, a particular split point and the next split point, or the last split point and the offset point, is distributed in accordance with a prearranged cycle or in accordance with traffic conditions in a manner such as is described in the commonly assigned U.S. Letters Pat. No. 3,267,424 for a TRAFFIC ACTUATED CONTROL SYSTEM.

By properly adjusting and staggering the offsets of the various local controllers located along a particular roadway, vehicular traffic along the roadway may proceed in an efficient manner with a minimum number of pauses. Similarily, at an intersection the percentage of the traffic cycle accorded in one direction as compared to that accorded a conflicting direction may be determined by the prevailing traffic conditions so as to provide for the most efficient flow of traffic through the intersection. Since traffic conditions may vary from day to day (as for example between weekdays and weekends or holidays) and from hour to hour (as for example between rush hours and nonrush hours) it should be apparent that it is most essential to efficient traffic flow that control be exercised by traffic engineers over the traffic cycle length as well as the offset and split points of the various local controllers comprising the traffic grid and that these factors may have to be varied from time to time in accordance with the prevailing traffic conditions.

It has been found in the field of traffic control that three basic displacement conditions for the offset and split points may be efficiently employed in a traffic control system. For convenience of description, these three basic displacement conditions will be referred to as "average" which may prevail when traffic flow is substantially equal or within a predetermined difference in value; "inbound" which may prevail when the inbound traffic flow exceeds the outbound traffic flow by a predetermined value; and "outbound" which may prevail when the outbound traffic flow exceeds the inbound traffic flow by a predetermined value. It should be noted that the mentioned displacements are basic and each may be further broken down into further degrees depending, for example, on the total amount of traffic on the entire roadway. Thus, the displacement for light traffic under any particular condition (average, inbound or outbound) may vary from the displacement for medium or heavy traffic under the same particular conditions.

When the traffic pattern along the roadway changes so that a change in offset is necessary in the local controller in order to maintain the most efficient flow of traffic, it is desirable that the transition from the prevailing offset to the required offset be gradual (that is over several traffic cycles) rather than abrupt so as to prevent any disproportional allotment of the traffic cycle to one particular path of vehicular traffic while causing an unusually heavy buildup of traffic in the remaining traffic directions.

Heretofore, in order to obtain this desired gradual change in offset resort has been made to mechanical and electromechanical devices including motors and cam drives which require periodic repair, maintenance, and replacement of worn parts in order to operate with the necessary accuracy required for traffic control purposes. Further, such devices are generally adversely affected by changes in weather conditions, and are costly and time-consuming to produce, repair and replace.

SUMMARY OF THE INVENTION

It is, therefore, a principal object of the present invention to provide an improved local controller for use in a traffic control system which utilizes all-solid-state electronic components for displacing or offsetting the zero point of the local traffic cycle with respect to a master time cycle and for generating a split point signal at a predetermined percentage point of the master cycle.

A further object is to provide such a local controller wherein although the switching of selection between offsets may occur abruptly by remote control, for example, the transistion between selected offsets in response to such selection occurs gradually over one or more traffic cycles through solid-state electronic means.

A still further object of this invention is to provide such a local controller that is compatible with a cycle generator adapted to provide two single-phase sinusoidal signals, one of which gradually shifts in phase relative to the other wherein the coincidence of the two signals determines length in time of the master traffic cycle.

These and other beneficial objects and advantages are attained in accordance with the present invention by providing a local controller adapted to receive two single-phase sinusoidal signals of substantially identical frequencies from a cycle generator. One of the signals, referred to herein as a cycle length signal, gradually shifts in phase with respect to the other signal referred to as the reference signal. Both the cycle length signal and the reference signal pass through sine wave to pulse converters that produce output pulses each time the associated sinusoidal signal passes through zero going positive. The reference signal pulse is then utilized to generate a sawtooth waveform by triggering a ramp generator.

The DC level of the sawtooth output of the ramp generator varies linearly between zero and a predetermined value and is compared to a preselected DC level determined by and corresponding to the desired offset in such a manner that the ratio of the preselected DC level to the maximum DC level of the ramp is equal to the desired offset represented as a percentage. A pulse is generated at the moment the sawtooth waveform builds up to the preselected level. These last referenced pulses are then compared to the cycle length pulses and coincidence indicates that the desired offset point has been reached since the ratio of the time required to reach the preselected DC level to the period of the sawtooth waveform will also be the ratio of the offset point to the cycle length.

The DC level that is compared to the sawtooth waveform is obtained as the output of an operational amplifier which is constantly increasing or decreasing linearly but never standing still. The direction of change of the amplifier output in turn is governed by logic gating that compares the actual offset pulse at any instant to the selected desired offset and drives the amplifier in the proper direction to reach the desired offset. This results in a hunting effect wherein the output of the operational amplifier oscillates about the desired offset or gradually moves toward it.

The local controller is also provided with means for generating a split point pulse relative in time to the offset point in a similar manner; means for enabling the operational amplifier output to jump from one sawtooth ramp to the next in order to enable the desired offset to be reached in the shortest time; and standby means that may be utilized to generate the desired offset and split point pulses independently of the offset hunting circuitry.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIG. 1 is a plan view of a simple intersection that may be controlled by a local controller utilizing the present invention;

FIG. 2 is a block diagram of a traffic control system utilizing the local controller of the present invention;

FIG. 3 is a time diagram of a typical traffic cycle;

FIG. 4 is a block diagram of the offset and split point generation means of the local controller of the present invention; and,

FIG. 5 including subfigures 5(a) through 5( i) schematically illustrate the pulse and wave forms developed in the local controller of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention is illustrated in the accompanying figures wherein similar components are indicated by the same reference numeral throughout. Reference is now made in particular to FIG. 1 wherein two crossing traffic arteries are shown. For simplification, one artery, "A," is assumed to extend between north and south and to have traffic in both directions and the other, "B," between east and west and to also have traffic in both directions. A traffic signal 10 which may comprise one or more groups of traffic lights is provided at the intersection and controls the corelative motion of vehicles and pedestrians entering into the intersection defined by arteries "A" and "B." The traffic signal 10 in turn comprises a portion of the traffic control system 12 set forth in FIG. 2.

The traffic control system 12 includes a cycle generator 14 receiving input information relating to the desired traffic cycle length from a selector 16 and adapted to generate suitable signals corresponding to the chosen time cycle to a local controller 18. As shown, the traffic cycle selector 16 may be manually operated in which case the resultant cycle length generated by the cycle generator 14 would be independent of traffic conditions along the roadway or the selector input may come from a computer 20 which in turn receives information from road detectors or other means relating to traffic conditions.

The local controller 18 may be positioned along arteries "A" and "B"; at their intersection, as shown; or in some other convenient location and serves to provide the sequential control of green, yellow and red traffic signals which control the flow of traffic along the roadways or into the intersection. As shown in FIG. 2, the local controller 18 includes an offset and split generator 22 which determines the point in time within each traffic cycle as a percentage of the cycle length in which the right of way is accorded successively to traffic moving along artery "A" and then artery "B" (referred to respectively as the A and B phases) and a timing signal generator 24 which allocates the time accorded each phase into the various vehicular and pedestrian signal periods of that phase. In this regard, reference is briefly made to FIG. 3 wherein the various traffic control systems are set out in time. Thus, during the "A" phase, vehicular traffic moving along the "B" artery receives red signals while vehicular traffic along the "A" artery sequentially receives green, yellow and then red signals. The latter signal being an all-artery red signal controlled by the "A" phase at the completion of which the right-of-way is accorded to traffic moving along the "B" artery by an initial "B" green. During the same "A" phase, pedestrian traffic thereon will receive "WALK" signals parallel to the "A" artery to cross the "B" artery, with "WAIT" signals parallel to the "B" artery followed by flashing "WALK" to clear the "B" artery and "WAIT" signals parallel to the "A" artery followed by "WALK" parallel to the "B" artery across the "A" artery as right-of-way is transferred from "A" to "B." Similarly, when the right of way is accorded to traffic moving along the "B" artery, that is, when the traffic cycle is in the "B" phase, vehicular traffic along the "A" artery will at first receive a red signal while vehicular traffic along the "B" artery sequentially receives green, yellow and then red signals after which the right-of-way will be returned to traffic moving along the "A" artery by an initial "A" green. Thus, it may be observed that each green signal comprises an initial and a latter part and that a phase commences with the initial part green signal in one direction and terminates with the all-red period in the process of transfer of right-of-way from said direction to another direction. Further, the latter part green signal is for a fixed time duration while the initial part green will continue for one phase until the transfer of right-of-way to the other traffic phase is initiated by arrival of the next offset point pulse or split point pulses. In other words, in the example depicted in FIG. 3, the traffic signal will remain at "B" green until some fixed time after the split point pulse is received, at which time the traffic signal will complete "B" green and go through "B" yellow, "B" red to "A" green. The traffic signal will then remain at "A" green until the offset point pulse occurs whereafter "A" green will be completed followed by "A" yellow, "A" red and "B" green. The traffic signal will again remain at "B" green until the next split point pulse is received and so one.

Thus, the local controller 18 serves to time the length of the various components of each phase of the traffic cycle and also to determine the points within each traffic cycle at which a particular phase will end and the right-of-way will be accorded to another phase. In this regard, the point at which transfer of the right-of-way to the "B" traffic phase is initiated from the "A" traffic phase, which will be considered our initial phase, is referred to as the "offset" point, and the point in time at which the right of way is transferred from the "B" phase to the "A" phase is referred to as the "split point." If there were a third or "C" phase, the point in time at which the right-of-way is transferred from the "B" phase to the "C" phase would also be referred to as a further "split point." In accordance with established traffic engineering procedures, the displacement points (offset and split) are used to trigger the pedestrian clearance or "clear" signals which occur during the latter part of the corresponding vehicular green signal and mark the termination of these signals. Thus, after the offset and split generator 22 of local controller 18 determines the point within a cycle for the offset or a split to occur, the timing signal generator 24 serves to time the periods of the latter portion of the green signal, the total yellow, the total red (of the all-red period) and then the initial portion of the next green signal. With the exception of the latter, all the periods are defined in real time and occur in a predetermined number of seconds. The initial portion of the green period remains in effect until the offset and split generator 22 generates the next displacement point signal at which time the timing signal generator serves to time out the latter half of the next green period, and the yellow, red and initial portion of the following green period. The initial portion of the green signal thus remains until the next displacement point signal occurs, at which time the sequential periods repeat.

The offset and split points are, therefore, useful in determining the point within a particular traffic cycle at which the right-of-way is transferred to a particular phase of traffic and also the distribution of the total time of each traffic cycle among two or more traffic phases.

As was previously mentioned, the traffic control system 12, of which the present local controller 18 comprises a component, includes a master cycle generator 14 which may be located remotely and is designed to produce two single-phase sinusoidal signals, one of which referred to as the cycle length signal is adapted to shift in phase with respect to the other signal referred to as the reference signal. The offset and split generator 22 is adapted to receive these signals and to utilize the same to generate the offset and split points which are then utilized to trigger the timing signal generator 24 which, in turn, controls the traffic signal 10. In the event of a malfunction in the cycle generator, a standby circuit 17 is provided which is adapted to periodically trigger the timing signal generator 24 independently of the cycle generator.

Reference is now made to FIG. 4 wherein the offset and split generator 22 circuitry is depicted in block diagram form. The reference signal 25 of the cycle generator 14, which for the purposes of this preferred embodiment may comprise a 400-Hz. sinusoidal wave, is first passed through a sine wave to pulse converter 26 adapted to generate a negative-going pulse 28 each time the sinusoidal reference signal 25 passes through zero going in a positive direction. The resultant pulses 28 are then used to trigger ramp generator 30, thereby producing a sawtooth-shaped waveform 32, the frequency of which is identical with that of the 400-Hz. reference signal 25, namely, 400 cycles per second. The sawtooth waveform 32 is then passed through a comparator 24 which compares the voltage of each sawtooth wave to a preselected DC level (V.sub.0) and generates a negative-going pulse 36, the duration of which is determined by the period of time that the DC level of the sawtooth wave 32 remains above the preselected DC level (V.sub.O). The negative-going pulses 36 are then passed through differentiator 38 and the leading edge of each pulse 36 serves to generate the negative spikes 40 which thus occur in time at a point corresponding to that at which the sawtooth output wave of ramp generator 34 builds up to the preselected DC level V.sub.O. The train of negative-going spikes 40 are thus displaced in time from the pulses 28 generated each time the reference wave 25 passes through zero going positive by an amount represented by the ratio of the preselected DC level, V.sub.0, to the maximum voltage reached by each sawtooth wave 32. Although the offset pulses 40 are displaced with respect to the reference signal 25, they are only effective when there is coincidence between the offset pulse 40 and a pulse produced by suitably converting the cycle generator cycle length signal 42. In this regard, the sinusoidal cycle length signal 42 is passed through a sine wave to pulse converter 44 which generates pulses 46 each time the cycle length signal passes through zero. It should be noted that since the cycle length signal 42 is slowly shifting in phase with regard to the reference signal, the cycle length pulses 46 will also shift with respect to the reference signal pulses. Since the ratio of the preselected DC level V.sub.D to the maximum voltage of the sawtooth wave 32 determines the point in time of the offset pulses 40 relative to the reference signal zero point pulses 28, this level also determines the point of coincidence of the offset pulses. Thus, by properly selecting the value of V.sub.0, any desired offset may be obtained.

When the present offset is to be changed to another value as, for example, when traffic conditions along a particular artery change, it is desirable to have this change in offset occur in as smooth a transition as possible. In this regard, the local controller 18 of the present invention comtemplates the use of all-solid-state electronic means to produce the desired change. As was previously stated, the offset is directly related to the DC level, V.sub.O, that forms an input to comparator 34. Accordingly, a change in the value of V.sub.O will result in a corresponding change in the offset. The DC level, V.sub.O, is obtained as the output of an operational amplifier 52. Such amplifiers are well known in the art and are characterized by having high DC stability and high immunity to oscillation. The input to the operational amplifier 52 comprises the output of a voltage divider circuit 54 fed through resistor 56. This input is normally positive. However, switch 58 is provided which shunts a portion of the voltage divider circuit 54 to ground. When switch 58 is closed, there is a resultant negative input to the amplifier 52. The output of the amplifier 52 is fed back as an input through capacitor 62.

When switch 58 is open there will be a positive input to amplifier 52 through resistor 56 from the positive terminal 60 of the voltage divider circuit 54. The output 64 of amplifier (which is the DC level heretofore referred to as V.sub.o) is then fed back through capacitor 62 which will discharge in an attempt to maintain a balance across the capacitor. This will cause a linear decrease in the input voltage to the amplifier which will, in turn, cause the output of the amplifier to decrease in a similar linear fashion.

Conversely, if switch 58 were closed, the positive voltage at the terminal 60 of the divider circuit would be shunted to ground, thereby presenting a negative potential to the left side of resistor 56. Amplifier 52 sees this negative potential and amplifies it sufficiently so that the voltage drop across capacitor 62 will be such as to cancel out this negative potential. Thus, the output 64 of amplifier 56 will increase linearly as its input increases because of the increasing difference in potential between the voltage divider output and the change on capacitor 62. Thus, the output of amplifier 52 at any moment is increasing or decreasing and this change takes place in a linear fashion. The values of the resistor 56 and capacitor 62 will, of course, determine the rate at which the output 64 of amplifier 52 changes. For traffic control purposes, it has been found that the output 64 of the amplifier should vary from zero to its maximum value in about 3 minutes. This provides for the smooth transition between offsets in no longer than five traffic cycles where the cycles are of 60-second durations.

Switch 58 thus serves to control the direction of change of the output 64 of amplifier 52 since the output voltage increases when the switch is closed and decreases when the switch is open. Switch 58, in turn, is governed by the output 66 of flip-flop 68 which, in turn, is controlled by the offset selection circuit 70. In this regard, various DC levels V.sub.1, V.sub.2 and V.sub.3 comprise possible inputs to OR-gate 72 which are applied thereto via the terminals 74, 76 and 78. As was previously mentioned, the three chosen DC levels V.sub.1, V.sub.2 and V.sub.3 may correspond to the desired offsets for average, heavy inbound or heavy outbound traffic and, if desired, there may be more possible DC levels. The DC levels V.sub.1, V.sub.2 and V.sub.3 are each preset to a desired value in a local controller, preferably by the adjustment of potentiometers associated with the controller. Only one of the three preset voltage levels, V.sub.1, V.sub.2, or V.sub.3 is applied to the OR-gate 72 at any given time, in accordance with the traffic condition sensed by the master computer, i.e., the voltage level V.sub.1 during heavy inbound traffic, V.sub.2 during average traffic, or V.sub.3 during heavy outbound traffic. The output of OR-gate 72 which represents the DC level corresponding to the desired offset is then compared to the sawtooth output 32 of the ramp generator 30 through comparator 80. When the sawtooth wave builds up to the DC level corresponding to the level of the desired offset (i.e., V.sub.1, V.sub.2 or V.sub.3) a pulse 82 which is similar to pulse 36 is generated. Pulse 82 is differentiated through the differentiator 84 to produce a negative-going spike 86 which occurs at the desired offset point of each cycle. Spike 86 is analogous to spike 40 which occurs at the present offset point. Thus, since spike 86 represents the desired offset point of each cycle and spike 40 represents the actual offset point of each cycle the operational amplifier 52 must be driven in a direction to cause spike 40 to occur at or about the time spike 86 occurs by suitably changing the value of V.sub.0. To this end spike 86 is used to trigger a delay multivibrator 88 adapted to produce a pulse 90 the duration of which is one-half the period of the reference signal. Since in this preferred embodiment a 400-Hz. sinusoidal wave comprises the reference signal 25, the duration of the pulse output 90 of the delay multivibrator 88 is 1.25 milliseconds which is one-half the period of the reference signal. The DMV output pulse 90 is then inverted through inverter 92 and compared through AND-gate 94 with the present offset pulse 40. In this regard inversion was necessary since the output of DMV 88 is a positive pulse 90 from 0.degree. to 180.degree. and gate 94 requires a positive input from 180.degree. to 360.degree. in order to respond.

If coincidence occurs between the inverted output 96 of DMV 88 and the present offset pulse 40, the present offset 40 lags the desired offset 86. This coincidence causes signals to appear on both terminals 98 and 100 of AND-gate 94 causing in turn a zero output 66 of flip-flop 68. This signal (i.e., the zero output 66 of the flip-flop 68) serves to activate switch 58 thereby shorting out the positive terminal 60 of the voltage divider circuit 54 and causing the output 64 of the operational amplifier 52 to increase. This will continue until such time as the present offset pulse 40 leads the desired offset 86 which would result in the coincidence of the present offset pulse 40 and the output pulse 90 of the DMV 88 causing signals to appear at both terminals 102 and 104 of AND-gate 106 thereby causing flip-flop 68 to switch to its "1" state. This will remove the "zero" output 66 of flip-flop 68 causing switch 58 to open. This in turn will cause the output 64 of the amplifier 52 to decrease linearly (as previously described) until such time as the present offset pulse 40 again lags the desired offset 86. The operational amplifier will thereafter oscillate about the desired offset point until such time as the offset is again changed by adjusting the DC level input (V.sub.1, V.sub.2 or V.sub.3) to OR-gate 72.

Reference will now be made to FIG. 5 wherein the various waveform developed in the offset and split generator 22 of the local controller 18 of the present invention are shown. In FIG. 5(a) the 400-Hz. sinusoidal reference signal generated by the cycle generator 14 is shown. The period between adjacent waves is 2.5 milliseconds. The negative-going pulse output 28 of the sine wave to pulse converter 26 is shown in FIG. 5(b). These pulses (28) are used to trigger the ramp generator 30 producing the sawtooth waveform 32 appearing in FIG. 5(c). Each sawtooth wave is shown to vary between 0 volts and V.sub.max which represents the maximum voltage. V.sub.0, that is the output 64 of amplifier 52 is shown as some value between 0 and V.sub.max. For purposes of illustration a 75 percent offset has been chosen and hence V.sub.0 is three quarters the value of V.sub.max. As was stated the sawtooth wave output 32 of ramp generator 30 is compared to V.sub.0 through comparator 34 which produces a negative-going pulse 36 the duration of which is equivalent to that time which the sawtooth wave 32 remains above the valve V.sub.0. This pulse (36) is then differentiated resulting in the negative-going spikes which represent the present offset pulse 40 which appears in FIG. 5(e). A comparison of FIGS. 5(b) and 5(e) will reveal that the present offset pulse 40 is displaced from the output of the sine wave to pulse converter pulses 28 by a percentage equal to the ratio of V.sub.0 to V.sub.max.

The waveforms generated during the offset shifting function of the present invention is depicted in FIGS. 5(f) through 5(i). Thus, assume that it is desired to shift the present offset from 75 percent to 62.5 percent and that there are suitable DC level inputs (i.e., V.sub.1, V.sub.2 or V.sub.3) to OR-gate 72 to correspond to these values. Thus, the output of comparator 80 which is the pulse train 82 (shown in FIG. 5(f)) represents that portion of sawtooth wave 32 having a DC value above the desired offset level (i.e., 37.5 percent of each wave). Pulse train 82 is differentiated producing the spikes 86 which appear in FIG. 5(g). Spikes 86 are then used to trigger DMV 88 producing pulses 90 which appear in FIG. 5(h). As was previously mentioned, the duration of each pulse 90 is one-half the period of the reference wave or 1.25 milliseconds. The output 90 of DMV 88 is then inverted so as to produce pulses 96 which are 180.degree. out of phase with pulses 90. The present offset pulses 40 are then compared with pulses 90 and 96. Since the duration of pulses 90 and 96 are each one-half the period between adjacent pulses and since these two pulses are 180.degree. out of phase with each other pulse 40 can coincide only with one pulse or the other (i.e., 90 or 96) and must coincide with one. Since in the present example the actual offset pulse 40 leads the desired offset pulse 86, pulse 40 coincides with the output 90 of DMV 88 which serves to remove the "zero" output 66 of flip-flop 68 thereby opening switch 58 and causing the amplifier output to decrease. This in turn serves to shift the value V.sub.0 downwardly until, as previously described, the amplifier is caused to oscillate about the desired voltage V.sub.0.

It may be that in order for the present offset pulse 40 to shift to the desired new position in the shortest time, it will be necessary for the output of the operational amplifier 64 to shift from one ramp to the next, as for example, when the present offset is 90 percent and the desired offset is 10 percent it would be quicker to go increasingly positive through 10 percent rather than to decrease to 10 percent. Similarly, if the present offset were 10 percent and the desired offset was 90 percent it would be more expeditious to go through zero from 10 percent to 90 percent rather than to increase to 90 percent. In this regard, the present offset generator 22 is provided with means for resetting up or down to enable the operational amplifier to pass through the zero or 100 percent point of its output ramps. Thus, assume for example that the present offset is 90 percent and traffic conditions change so that it is desired to provide a new offset of 10 percent. Again, it must also be assumed that there are suitable inputs to OR-gate 72 to provide such a 10 percent offset. When the suitable input to OR-gate 72 is provided and the present offset pulse 40 is compared to the output 90 and inverted output 96 of DMV 88 coincidence will occur with the inverted signal 96 since the direct output signal 90 will extend between the 10 percent and 60 percent points while the inverted signal will extend between the 60 percent point and 10 percent point of the next wave. Signals will thus appear on terminals 98 and 100 of AND-gate 94 driving flip-flop 68 to its zero state and producing the signal 66 which will close switch 58 thereby causing the output 64 of amplifier 52 to increase as previously described. As the value V.sub.0 (which is the output 64 of amplifier 52) increases the point in time at which the offset pulse 40 is produced increases. When V.sub.0 reaches V.sub.max (See FIG. 5(c)), offset pulse 40 will coincide with the output pulses 28 of the sine wave to pulse converter 26 although displaced in phase by 360.degree.. This condition will cause signals to appear at both input terminals 108 and 110 of AND-gate 112 which in turn will trigger the slow recovery delay multivibrator 114. The output 116 of DMV 114 and the output 66 of flip-flop 66 appear as inputs to AND-gate 118 and when both are present (i.e., when V.sub.0 reaches V.sub.max) a signal 120 which is the output of AND-gate 118 will be triggered to close switch 123 thereby shorting out capacitor 62 which is equivalent to applying a high positive current to the input of amplifier 52 thereby causing its output to fall sharply and substantially instantaneously to zero. This in effect places the output 64 of amplifier 52 (i.e., V.sub.0) at the bottom of the next wave 32.

Conversely, if the desired offset point had been 90 percent at a time when the present offset point was 10 percent there would not be coincidence between the present offset pulse 40 and the inverted output 96 of the DMV 88 but rather with output wave 90. This would result in flip-flop 68 shifting to its "1" state thereby removing the "0" output 66 of flip-flop 68 from switch 58 causing that switch to open. At the same time, a "1" output signal 122 of the flip-flop 60 would be generated which would appear at one input terminal 124 of AND-gate 126. Since switch 58 was opened, the output 64 of amplifier 52 would linearly decrease in the manner and for the reason heretofore described. When V.sub.0 (i.e., the output 64 of amplifier 52) reaches 0 (or the minimum voltage of each sawtooth wave 32) the present offset pulse 40 and the output pulse 28 of the sine to pulse converter 26 would coincide thereby providing signals on both terminals 108 and 110 of AND-gate 112 causing a signal to be generated by AND-gate 112 which would trigger DMV 114. The output 116 of the DMV would then appear as an input 128 to AND-gate 126 and since the other input to AND-gate 126 (i.e., the "1" output signal of flip-flop 68) is also present at terminal 124, AND-gate 126 would transmit a signal 130 which serves to close switch 132 and thereby apply a very high negative potential (-V) to the amplifier through resistor 134, bypassing the voltage divider circuitry 54. This extremely high negative input voltage (-V) causes the output 64 of the amplifier (V.sub.0) to jump sharply and substantially instantaneously upward thereby placing the output V.sub.0 at a DC level corresponding to the top of the ramp (i.e., V.sub.max). Since flip-flop 68 is still in its "1" state, the output 64 of the amplifier 52 will continue to decrease until the desired offset point (in this case 90 percent) is reached at which time the amplifier output will hover about the corresponding V.sub.0 until such time as the offset is again changed.

As was previously mentioned, the 400-Hz. cycle reference signal 42 (which gradually shifts in phase with respect to the reference signal 25) is also passed through a sine wave to pulse converter 44 thereby producing a train of spikes 46 which also gradually shift in phase.

The offset pulse appearing on line 40 is fed into ramp generator 146 and causes a new ramp to be started every time an offset pulse appears. This ramp voltage 148 is fed into a combination comparator and delay multivibrator 154. This circuit produces a pulse of 25-.mu.sec. width when the ramp voltage exceeds its trigger level. Thus, the trigger level of circuit 154 controls the amount of delay, 0-2.5 milliseconds. The delay corresponds to a phase shift of from 0 to 360.degree. or 0-100 percent. The pulse output from circuit 154 is fed into ramp generator 146 in order to reset the ramp and to coincidence gate 162. The output from coincidence gate 162 serves to advance the positioning device of the controller.

The resulting phase shift of the offset pulse from the master zero pulse corresponds 1:1 with the delay caused by the offset ramp voltage 32 plus the delay caused by the split ramp voltage 148. If delay caused by the split ramp voltage equals zero the pulse train 156 has the same time relationship to the reference line 25 as the offset pulse train 40 and therefore gate 162 produces the local zero pulse which terminates the "A" "WALK" interval. The trigger level comparator -- one-shot 154 is controlled by the DC voltage on line 152, where, for example, 0-12 volts corresponds to 0-360.degree. phase shift. This voltage in turn is controlled by the output of OR-gate 150, the inputs of which are preset voltages Va, Vb, and Vc preferably derived from three split potentiometers associated with the local controller. Only one split potentiometer is selected at any given time, in accordance with the traffic condition sensed by the system. Thus, during heavy inbound traffic, a voltage Va is applied to the OR-gate 150, during average traffic, a voltage Vb, and during heavy outbound traffic, a voltage Vc. The output 152 of OR-gate 150 in turn is passed through AND-gate 153 which receives as an additional input indication of phase "B" green. Thus, unless the cycle is in phase "B" green, the output 155 of AND-gate 153 will be zero, thus causing the comparator 154 to fire at the start of each ramp, namely, at the offset point. In phase A all split pots are disconnected and therefore the voltage on line 152 assumes 0 volts and therefore coincidence will take place at the offset point.

Thus, in accordance with the above disclosure, an improved local controller is provided which utilizes all-solid-state electronic equipment for displacing the zero point of a local time cycle from a master cycle and for generating a split point signal at a predetermined percentage point of the master cycle.

Claims

Having thus described the invention, What is claimed is:

1. In a local controller for use in a traffic control system of the type wherein the traffic cycle is defined by the time lapse between the phase coincidences of two signals having a slight difference in frequency, one of which, referred to as a cycle length signal, gradually shifts in phase with respect to the other referred to as a reference signal, the improvement comprising:

means responsive to the said reference signal adapted to trigger a ramp generator; a ramp generator adapted to provide a sawtooth-shaped output, the frequency of which is identical to that of said reference signal; means for converting said cycle length signal to a train of pulses corresponding in frequency to the frequency of said cycle length signal; means for comparing the voltage level of the output of said ramp generator to the output of a variable voltage source and for generating an offset signal pulse each time the voltage of said ramp generator output reaches the level of the output of said variable voltage source; a variable voltage source; and means for determining the pulse coincidence of said offset signal pulses with said cycle length signal pulses whereby coincidence of said pulses defines the point within each traffic cycle bearing the same proportion to the total traffic cycle length that the output of the variable voltage source bears to the maximum DC level of the output of said ramp generator.

2. The invention in accordance with claim 1 wherein said reference signal and said cycle length signal comprise sinusoidal waves, said means for converting said cycle length signal to a pulse train comprises a sine wave to pulse converter, and said means responsive to said reference signal adapted to trigger said ramp generator comprises a second sine wave to pulse converter.

3. The invention in accordance with claim 1 wherein said variable voltage source comprises an operational amplifier and said local controller further comprises circuit means for gradually driving the output of said operational amplifier from its present offset voltage level toward a selected offset voltage level.

4. The invention in accordance with claim 3 wherein said driving means includes a positive input to said amplifier, a negative input to said amplifier, a switch shunted to ground across said positive input, a capacitor shunted across said amplifier, and means for closing said switch when said selected offset voltage level is higher than said present offset voltage level and for opening said switch when said present offset voltage level is higher than said selected offset voltage level whereby to gradually drive the output of said amplifier from said present offset voltage level to said selected offset voltage level.

5. The invention in accordance with claim 4 wherein said means for closing and opening said switch includes an offset selection circuit adapted to receive a selected one of a plurality of offset voltage levels lower than the maximum voltage of the ramp generator output, means for comparing the selected offset voltage level to the output of said ramp generator and to produce a signal when the output voltage of said generator builds to the DC level of said selected offset voltage level, and further means for comparing the output of said last-recited means with said offset signal pulse and for closing said switch if said signal leads said offset pulse and for opening said switch if said signal lags said offset signal pulse.

6. The invention in accordance with claim 5 wherein said further comparing means includes a delay multivibrator the duration of the output pulses of which are one-half the period of said reference wave energy, means for triggering said delay multivibrator when the output of said generator reaches the DC level of the output of said selection circuit, means for inverting the output of said delay multivibrator, flip-flop means having a "0" output adapted to close said switch and a "1" output adapted to open said switch, first gate means adapted to switch said flip-flop to a "1" state when the output of said delay multivibrator and offset signal pulse coincide and second gate means adapted to switch said flip-flop to a "0" state when the inverted output of said delay multivibrator and said offset signal pulse coincide.

7. The invention in accordance with claim 6 further comprising means for driving the output of said operational amplifier to zero from a maximum voltage value and means for driving the output of said operational amplifier to a maximum value from zero.

8. The invention in accordance with claim 7 wherein said means for driving the output of said operational amplifier to zero from a maximum voltage level comprises a switch shunted across said capacitor and gate means for closing said capacitor switch when said flip-flop is in the "0" state and said offset signal pulse and said reference signal sine wave to pulse converter output pulse coincide.

9. The invention in accordance with claim 7 wherein said means for driving the output of said operational amplifier to a maximum voltage value from zero comprises a negative voltage input to said amplifier and means for feeding said negative voltage input to said amplifier when said flip-flop is in the "1" state and said offset signal pulse and said reference signal sine wave to pulse converter output pulse coincide.