U.S. patent number 3,638,196 [Application Number 05/054,231] was granted by the patent office on 1972-01-25 for learning machine.
This patent grant is currently assigned to Matsushita Electric Industrial Co., Ltd.. Invention is credited to Akira Nishiyama, Tetsuo Yamaguchi, Tomio Yoshida, Hirokazu Yoshino.
United States Patent |
3,638,196 |
Nishiyama , et al. |
January 25, 1972 |
LEARNING MACHINE
Abstract
A learning machine in which threshold values corresponding to
the desired output conditions and having a dead zone therebetween
are used during the learning process for the discrimination of the
output from a memory storing a plurality of standard pattern
information, and this discriminating faculty is utilized for the
discrimination of input pattern information with respect to a
single threshold value having no dead zone. Thus, the precision of
discrimination can be remarkably improved due to the fact that the
threshold values having a dead zone are used during the learning
process, and the learning can be digitally and automatically
carried out.
Inventors: |
Nishiyama; Akira (Osaka,
JA), Yoshino; Hirokazu (Osaka, JA),
Yoshida; Tomio (Osaka, JA), Yamaguchi; Tetsuo
(Hirakata, JA) |
Assignee: |
Matsushita Electric Industrial Co.,
Ltd. (Osaka, JA)
|
Family
ID: |
26397603 |
Appl.
No.: |
05/054,231 |
Filed: |
July 13, 1970 |
Foreign Application Priority Data
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|
|
|
|
Jul 14, 1969 [JA] |
|
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44/56642 |
Jul 14, 1969 [JA] |
|
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44/56643 |
|
Current U.S.
Class: |
706/34;
192/113.1 |
Current CPC
Class: |
G06F
7/023 (20130101) |
Current International
Class: |
G06F
7/02 (20060101); G06f 015/18 () |
Field of
Search: |
;340/172.5 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Shaw; Gareth D.
Assistant Examiner: Woods; Paul R.
Claims
What is claimed is:
1. A learning machine comprising a memory for storing a plurality
of standard pattern information, a plurality of weight elements
connected to respective weight selective circuits for applying a
variable weight factor, selecting means for selecting the output
from said memory and input pattern information to be discriminated,
a threshold value selection circuit, a decision circuit for
generating an output corresponding to the relative magnitude of the
sum of outputs from said weight elements and an output supplied
from said threshold value selection circuit, and a learning pulse
generator for supplying learning pulses to said weight selective
circuits thereby varying the weight factors of said weight elements
when the output from said decision circuit does not coincide with a
desired output and driving said memory for deriving the next
standard pattern information when the output from said decision
circuit coincides with the desired output, whereby the standard
pattern information can be successively learned for the
discrimination of input pattern information.
2. A learning machine as claimed in claim 1, in which said memory
comprises a plurality of shift registers, first gate means
connected across the input and output terminals of said shift
registers, second gate means interposed between signal input
terminals and the input terminals of said shift registers, and
common selectively conducting means for causing one of the groups
of said first and second gate means to conduct while cutting off
the other group, so that said first gate means are cut off and said
second gate means are urged to conduct by said selectively
conducting means so as to successively write the standard pattern
information supplied from said signal input terminals in said shift
registers, and at the completion of the writing, said second gate
means are cut off and said first gate means are urged to conduct by
said selectively conducting means so as to successively supply the
standard pattern information stored in said shift registers to said
weight elements, and at the same time, to circulate same through
said first gate means.
3. A learning machine as claimed in claim 1, in which each said
weight selective circuit comprises a plurality of bistable
multivibrators connected in cascade, first gate means for gating
the output from said learning pulse generator and supplying a
trigger pulse to said bistable multivibrators and a plurality of
second gate means applied with different voltages representative of
weight factors, so that one of said second gate means is selected
by the output from said bistable multivibrators connected in
cascade.
4. A learning machine as claimed in claim 1, in which each said
weight element comprises gate means which controls the passage of
the voltage representative of the weight factor supplied from said
weight selective circuit in response to the standard pattern
information supplied from said memory or the externally supplied
input pattern information to be discriminated.
5. A learning machine as claimed in claim 1, in which said learning
pulse generator comprises two inverse coincidence circuits to which
the output from said decision circuit and the desired output are
applied as inputs, first pulse-generating means connected to one of
said inverse coincidence circuits, weight factor decrement control
signal generating means connected to said first pulse-generating
means for controlling the decrement of the weight factor, weight
factor increment control signal generating means receiving the
output from the other said inverse coincidence circuit for
controlling the increment of the weight factor, second
pulse-generating means receiving the output from the other said
inverse coincidence circuit and the output from said first
pulse-generating means for responding to the logical sum of the
inputs thereto for generating at least one learning pulse, and
third pulse-generating means for reading out another standard
pattern information stored in said memory upon detection of the
coincidence between the two inputs applied to said inverse
coincidence circuits.
6. A learning machine as claimed in claim 1, in which said
threshold value selection circuit comprises selecting means for
selecting one of a set of a desired output and a threshold value,
and the desired output is selected during learning so that it is
supplied as the threshold value.
7. A learning machine as claimed in claim 1, in which said
threshold value selection circuit comprises means for selecting one
of means generating a threshold value representative of a desired
output and means generating a single threshold value and supplying
the output from the selected means to said decision circuit.
8. A learning machine as claimed in claim 1, further comprising a
trigger pulse generator having pulse-generating means for
generating a pulse in response to an output pulse supplied from
said learning pulse generator, and means for stopping the operation
of said learning pulse generator for a predetermined period of time
in response to the output from said pulse-generating means.
Description
This invention relates to learning machines and more particularly
to a learning machine of the kind having such a learning faculty
that a set of given input conditions and a set of output conditions
given for the input conditions are simultaneously stored in a
memory so as to derive any desired output condition therefrom.
Learning machines of this kind are generally provided with an
adaptive logic circuit which has such a learning faculty that an
output satisfying the desired condition can be obtained for each
input condition so that a correct output response can be provided
for each input condition after learning. In addition to the above,
retraining can be done as required so as to deliver a new output
response for a new input condition.
Referring to FIG. 1 showing the basic structure of a learning
machine of this kind, it comprises a plurality of weight elements
A, B, C, . . . having respective weight factors W.sub.1, W.sub.2,
W.sub.3, . . . which may, for example, be a voltage, a summing
circuit D, a decision circuit E, an output terminal F, a terminal G
to which a desired output is applied, and a learning control
circuit H. A plurality of input signals X.sub.1, X.sub.2, X.sub.3,
. . . are applied to the respective weight elements A, B, C, . . .
and a threshold value W is applied to the decision circuit E. The
inputs X.sub.1, X.sub.2, X.sub.3, . . . may be one of a set of "1"
and "0" or one of a set of "+1" and "-1." The inputs X.sub.1,
X.sub.2, X.sub.3, . . . are multiplied by the weights W.sub.1,
W.sub.2, W.sub.3, . . . of the respective weight elements A, B, C,
. . . and the products are summed up in the summing circuit D. The
sum is compared with the threshold value W in the decision circuit
E, and the output delivered from the decision circuit E is "+1" and
"0" respectively when the sum is larger and smaller than the
threshold value W in the embodiment of the present invention
described hereinbelow.
In the learning machine having a structure as described above, when
the actual output for a certain input condition is "+1" and the
desired output is "0," the learning control circuit H adjusts the
weight factors until they are decreased to give the actual output
"0." The above procedure is repeated for all the input patterns
each consisting of a set of numerals so that all the input patterns
can be classified into two categories consisting of a class 1 and a
class 2.
However, such a system has been defective in that man must
participate in the discriminating faculty in the course of learning
and thus an extremely extended period of time is required for the
learning. Further, due to the fact that the decision circuit E acts
as a one-out-of-two decision element during the learning process,
there is a problem that correct decision cannot be expected during
the stage of discrimination when an input pattern differs slightly
from a standard pattern.
The present invention contemplates the provision of a learning
machine which is free from the above problem by virtue of the fact
that it is provided with a memory for storing a plurality of
standard patterns and a decision circuit acting as a
one-out-of-three decision element during the learning process so as
to cooperate with threshold values having a dead zone
therebetween.
It is an object of the present invention to provide a learning
machine which is provided with a memory and an automatic learning
circuit so that a plurality of standard pattern information written
previously in the memory can be automatically derived so as to
effect discrimination within a short period of time.
Another object of the present invention is to provide a learning
machine in which the classification of standard patterns in a
decision circuit during the learning process is carried out on the
basis of threshold values having a dead zone therebetween and the
discrimination is effected on the basis of only one threshold value
as heretofore so as to enhance the precision of discrimination.
The above and other objects, features and advantages of the present
invention will be apparent from the following detailed description
taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a block diagram showing the basic structure of a learning
machine;
FIG. 2 is a block diagram showing the structure of an improved
learning machine according to the present invention;
FIGS. 3 through 6 and 8 are circuit diagrams showing the detail of
parts of the learning machine shown in FIG. 2; and
FIGS. 7a and 7b are charts showing the operation of parts of the
structure shown in FIG. 6.
Referring to FIG. 2, a plurality of inputs are applied to
respective input terminals 1, 2 and 3 and are held in respective
circuits 4, 5 and 6 for any desired period of time. The circuits 4,
5 and 6 may be bistable multivibrators. A plurality of weight
factor selective circuits 7, 8 and 9 include weight elements for
multiplying the outputs from the bistable multivibrators 4, 5 and 6
by respective weight factors W.sub.7, W.sub.8 and W.sub.9. Although
there are actually n input terminals, n bistable multivibrators and
n weight factor selective circuits, only three of them are shown
herein for the sake of simplicity. The input signals applied to the
input terminals 1, 2 and 3 are either "1" or "0," and these signals
are multiplied by the respective weight factors W.sub.7, W.sub.8
and W.sub.9 so that the products appear at the output sides of the
respective weight factor selective circuits 7, 8 and 9.
A memory 10 stores successively the outputs from the bistable
multivibrators 4, 5 and 6, and at the same time, stores
successively expected outputs for standard patterns applied from a
terminal 11. A trigger pulse generator 12 controls the writing and
reading of input patterns into and out of the memory 10 during the
learning process, depending on a signal applied thereto from a
manual signal input terminal 13 or an output signal delivered from
a learning pulse generator 14 having a function which will be
described later.
A summing circuit 15 sums up the weighted values delivered from the
weight factor selective circuits 7, 8 and 9. A decision circuit 16
compares the output from the summing circuit 15 with a threshold
value W . Thus, an output "+1" appears at an output terminal 17
when the sum is larger than the threshold value W and an output "0"
appears at the output terminal 17 when the sum is smaller than the
threshold value W . A threshold value selection circuit 18 supplies
to the decision circuit 16 the threshold value W corresponding to a
desired output which may be "+1" or "0" appearing at an output
terminal 101 of the memory 10 during learning, while a threshold
value W applied to the selection circuit 18 from an input terminal
thereof is directly supplied to the decision circuit 16 during
discrimination.
The learning pulse generator 14 compares the actual output
appearing at the terminal 17 during the learning process with the
desired output appearing at the output terminal 101 of the memory
10 and sends a series of learning pulses to the weight factor
selective circuits 7, 8 and 9 to vary their weight factors only
when the actual output does not coincide with the desired output. A
weight factor decrement control signal, a weight factor increment
control signal and a learning pulse signal appear at respective
output terminals 141, 142 and 143 (FIG. 5) of the learning pulse
generator 14.
The practical structure of the memory 10, trigger pulse generator
12, learning pulse generator 14, summing circuit 15, decision
circuit 16, threshold value selection circuit 18, and weight factor
selective circuits 7, 8 and 9 which are the principal components of
the learning machine according to the present invention will be
described in detail.
The practical structure of the memory 10 is shown in FIG. 3. The
function of the memory 10 is to store standard patterns and output
signals desired for the patterns as described above. In storing the
standard patterns and the desired outputs therefor, a switch
S.sub.1 is thrown to the side of the terminals a and b to apply a
voltage of -E volts to the gates of gating transistors G.sub.1,
G.sub.2, G.sub.3 and G.sub.4 so as to urge these transistors to
conduct. The desired output supplied from the terminal 11 is
written in a memory means such as a shift register SR.sub.1 through
the transistor G.sub.1, while the components constituting the
standard pattern supplied from the bistable multivibrators 4, 5 and
6 are written in memory means such as shift registers SR.sub.2,
SR.sub.3 and SR.sub.4 through the transistors G.sub.2, G.sub.3 and
G.sub.4.
In reading out the contents written in the shift registers
SR.sub.1, SR.sub.2, SR.sub.3 and SR.sub.4, the switch S.sub.1 is
thrown to the side of the contacts c and d so that the shift
registers SR.sub.1, SR.sub.2, SR.sub.3 and SR.sub.4 are connected
in a ring with respective transistors G.sub.5, G.sub.6, G.sub.7 and
G.sub.8. On the other hand, the gates of the transistors G.sub.1,
G.sub.2, G.sub.3 and G.sub.4 are grounded and these transistors are
cut off. The contents stored in the shift registers SR.sub.1,
SR.sub.2, SR.sub.3 and SR.sub.4 are read out by the pulse supplied
from the trigger pulse generator 12 and are rewritten in the shift
registers SR.sub.1, SR.sub.2, SR.sub.3 and SR.sub.4 through the
respective transistors G.sub.5, G.sub.6, G.sub.7 and G.sub.8. The
outputs appearing at terminals 101, 102, 103 and 104 are applied to
the learning pulse generator 14 and the threshold value selection
circuit 18, and to the bistable multivibrators 4, 5 and 6,
respectively.
The practical structure of the trigger pulse generator 12 is shown
in FIG. 4. A manual signal is applied from the terminal 13 to a
pulse generator PG.sub.1 in the case of the writing of the standard
pattern in the memory 10. The pulse generator PG.sub.1 is thereby
energized to generate clock pulses. During the learning process,
the output from the learning pulse generator 14 is applied to the
pulse generator PG.sub.1 which therefore generates clock pulses. A
bistable multivibrator BS.sub.1 is provided so as to stop the
operation of the learning pulse generator 14 during the transient
period of time in which the standard pattern stored in the memory
10 is being read out. More precisely, the state of the bistable
multivibrator BS.sub.1 is inverted by the pulse supplied from the
pulse generator PG.sub.1 to stop the operation of the learning
pulse generator 14 and the bistable multivibrator BS.sub.1 is
restored to the original state by a signal applied thereto through
a delay means DE.sub.1 and a monostable multivibrator MS.sub.1.
FIG. 5 shows the practical structure of the learning pulse
generator 14 which functions to supply the learning pulses to the
weight factor selective circuits 7, 8 and 9 when the standard
pattern information stored in the memory 10 is successively read
out from the memory 10 for the necessity of learning.
The relation among a desired output for a standard pattern, an
actual output or output from the decision circuit 16, necessity of
learning, and an increase or decrease in weights due to the
requirement for learning is tabulated in Table 1.
---------------------------------------------------------------------------
Table 1
Case I II III IV Desired output +1 0 + 1 0 Actual output +1 + 1 0 0
Learning not required required required not required Increase or
decrease in -- decrease increase -- weights
__________________________________________________________________________
In the table, "+1" represents a high level at +5 volts and "0"
represents a low level at 0 volts.
Suppose, for example, that the conditions of the case I or IV are
satisfied for a standard pattern, then it is apparent that any
change in the weight factors of the weight elements in the weight
factor selective circuits 7, 8 and 9 is unnecessary. More
precisely, the inputs applied to an AND-gate A.sub.1 include the
actual output and the desired output which is passed through an
invertor I.sub.1, while the inputs applied to a NAND-gate NA.sub.1
include the desired output and the actual output which is passed
through an invertor I.sub.2. Thus, one of the three input signals
applied to the AND-gate A.sub.1 and NAND-gate NA.sub.1 is in the
low level and the two input signals applied to a NAND-gate NA.sub.2
remain in their high level with the result that a bistable
multivibrator BS.sub.3 is not actuated and no learning pulse is
generated. In the case II, the desired output is in the low level
and the actual output is in the high level. Therefore, all the
input signals applied to the AND-gate A.sub.1 are in the high
level, and a bistable multivibrator BS.sub.2, a monostable
multivibrator MS.sub.2 and the NAND-gate NA.sub.2 are operated.
When the monostable multivibrator MS.sub.2 generates one pulse, the
bistable multivibrator BS.sub.3 generates a plurality of pulses,
for example, five pulses the number of which is equal to the number
of variable stages of the weight factors, and thus five learning
pulses are supplied to the weight factor selective circuits 7, 8
and 9. In this case, a negative voltage pulse of pulse width
including the first pulse delivered from the bistable multivibrator
BS.sub.3 appears at the decrement control signal output terminal
141. In the case III, the desired output is in the high level and
the actual output is in the low level. Therefore, all the input
signals applied to the NAND-gate NA.sub.1 are in the high level so
that the bistable multivibrator BS.sub.3 and the monostable
multivibrator MS.sub.3 are operated to supply one learning pulse to
the weight factor selective circuits 7, 8 and 9 from the terminal
143. In the meantime, a negative voltage at -10 volts appears at
the increment control signal output terminal 142. B.sub.1 and
B.sub.2 are buffer circuits. When the actual output coincides with
the desired output in the course of the above operation, a signal
is delivered from an AND-gate A.sub.2 to drive the trigger pulse
generator 12 so that the same operation is repeated for the next
standard pattern. When no coincidence is reached between the actual
output and the desired output, the operation described above is
repeated.
FIG. 6 shows the practical structure of the summing circuit 15, the
decision circuit 16 and the threshold value selection circuit 18.
The summing circuit 15 includes an operational amplifier OP.sub.1
and sums up the outputs from the weight factor selective circuits
7, 8 and 9. The threshold value selection circuit 18 delivers an
output W which is supplied to the decision circuit 16 as the
threshold value. An operational amplifier OP.sub.2 in the decision
circuit 16 delivers "+1" and "0 " respectively when the output from
the summing circuit 15 is larger and smaller than the threshold
value W .
During learning, the threshold value selection circuit 18 supplies
to the decision circuit 16 threshold values having a dead zone
therebetween, while during discrimination, it supplies a threshold
value having no dead zone. The threshold value selection circuit 18
has thus a function of selecting its output depending on the
desired output. When, for example, a desired output "+1" appearing
at the output terminal 101 of the memory 10 is applied to the
threshold value selection circuit 18, it delivers an output
+.omega., while when a desired output "0" is applied thereto, it
delivers an output -.omega.. These outputs +.omega. and - .omega.
provide the threshold values employed in the decision circuit
16.
Therefore, the necessity of learning is concerned with the
magnitude of the output
from the summing circuit 15 relative to the magnitude of the
threshold value +.omega. or -.omega. corresponding to the desired
output "+1" or "0." In the case I in Table 1, there is no necessity
for learning and any increase or decrease in the weight factors of
the weight factor selective circuits 7, 8 and 9 is unnecessary
since the output from the decision circuit 16 coincides with the
desired output. This applies also to the case IV. In the case II,
the output from the decision circuit 16 is "+1," whereas the
desired output is "0." In this case, the following relation exists
between the output from the summing circuit 15 and the threshold
value -.omega.:
However, actually the following relation must hold between the
output from the summing circuit 15 and the threshold value
-.omega.:
In order to satisfy the above condition, the weight factors
W.sub.7, W.sub.8 and W.sub.9 of the respective weight elements in
the weight factor selective circuits 7, 8 and 9 must be decreased
to reduce the output from the summing circuit 15. The situation is
opposite in the case III. That is, the weight factors W.sub.7,
W.sub.8 and W.sub.9 must be increased, and the learning is
completed when the output from the summing circuit 15 exceeds the
threshold value +.omega.. By the above manner of learning process,
the case II is shifted to the case IV, while the case III is
shifted to the case I.
Since the desired output is applied to the threshold value
selection circuit 18 during learning to determine the corresponding
threshold value in the manner described above, a dead zone exists
between the threshold values +.omega. and -.omega. corresponding to
the desired outputs "+1" and "0" as shown in FIG. 7a. Thus, the
decision circuit 16 has a function of a one-out-of-three decision
element. In FIGS. 7a and 7b, the horizontal axis represents the
output
from the summing circuit 15, and the vertical axis represents the
output from the decision circuit 16.
Referring to FIG. 6 again, a switch S.sub.3 in the threshold value
selection circuit 18 is thrown to the side of the terminal a in the
case of the learning and to the side of the terminal b in the case
of the discrimination. When the switch S.sub.3 is thrown to the
side of the terminal a to connect an operation amplifier OP.sub.3
to the decision circuit 16, the threshold value W supplied from the
threshold value selection circuit 18 to the decision circuit 16
corresponds to the desired output "+1" or "0" stored in the memory
10, while when the switch S.sub.3 is thrown to the side of the
terminal b, the threshold value W supplied from the threshold value
selection circuit 18 to the decision circuit 16 is proportional to
the threshold value W . In the case of the discrimination, the
decision circuit 16 acts as a conventional one-out-of-two decision
element because there is only one threshold value as seen in FIG.
7b.
FIG. 8 shows the practical structure of the weight factor selective
circuit 7 including the weight element. The remaining weight factor
selective circuit 8 and 9 have the same structure as the selective
circuit 7. The weight factor of the weight element is variable over
five levels which are +2 volts, +1 volts, 0 volts, -1 volts and -2
volts.
Five bistable multivibrators BS.sub.4, BS.sub.5, BS.sub.6, BS.sub.7
and BS.sub.8 have the function of selecting the weight factor and
the outputs from the respective bistable multivibrators control the
conduction and cutoff of five gating transistors G.sub.9, G.sub.10,
G.sub.11, G.sub.12 and G.sub.13. More precisely, when anyone of the
bistable multivibrators BS.sub.4, BS.sub.5, BS.sub.6, BS.sub.7 and
BS.sub.8 delivers an output "1" at a level of -10 volts (herein,
the negative logic is applied), the voltage at the drain electrode
of the transistor connected to the output of the specific bistable
multivibrator appears at its source electrode. Suppose that the
input signal is applied from the bistable multivibrator 4, which
sets the potential of the gate electrode of a transistor G.sub.17
at a level of 0 volts, this transistor G.sub.17 is cut off and the
voltage appearing at the source electrode of the specific
transistor is supplied to the summing circuit 15 as the weight.
Since two or more outputs of the bistable multivibrators BS.sub.4,
BS.sub.5, BS.sub.6, BS.sub.7 and BS.sub.8 cannot simultaneously
take the value "1," only one of the five voltages representing the
respective weights should appear as the weight. Gating transistors
G.sub.14, G.sub.15 and G.sub.16 are cut off when their gate voltage
is 0 volts. Only when all of these three transistors G.sub.14,
G.sub.15 and G.sub.16 are in their cutoff state, the learning
pulses are applied from the terminal 143 of the learning pulse
generator 14 to the bistable multivibrators BS.sub.4, BS.sub.5,
BS.sub.6, BS.sub.7 and BS.sub.8 via a point A to shift the same. As
soon as the first one of the five learning pulses arrives from the
terminal 143 of the learning pulse generator 14, a decrement
control signal of negative voltage is supplied from the terminal
141 of the learning pulse generator 14. Thus, a negative potential
appears at the gate of the transistor G.sub.16 provided that one of
the bistable multivibrators BS.sub.4, BS.sub.5, BS.sub.6, BS.sub.7
and BS.sub.8 is delivering "1." As a result, the transistor
G.sub.16 conducts to short circuit the point A to ground and the
first one of the five learning pulses cannot reach the bistable
multivibrators BS.sub.4, BS.sub.5, BS.sub.6, BS.sub.7 and BS.sub.8.
A decrement control signal of 0 volts is applied as soon as the
second one of the five learning pulses appears, and the transistor
G.sub.16 is thereby cut off so that the remaining four learning
pulses are applied to the bistable multivibrators BS.sub.4,
BS.sub.5, BS.sub.6, BS.sub.7 and BS.sub.8. Consequently, the
position of the output "1" from the bistable multivibrators
BS.sub.4, BS.sub.5, BS.sub.6, BS.sub.7 and BS.sub.8 is shifted to
the lower place, and this is followed by stepdown of the weight
level by one step. When the bistable multivibrator BS.sub.4 is
delivering "1," the transistor G.sub.16 is cut off due to the fact
that 0 volts is applied to the gate thereof, and all of the five
learning pulses pass through the point A to shift the position of
"1" until it returns to the bistable multivibrator BS.sub.4 again
so that no shift can substantially occur. Similarly, an increment
control signal of negative voltage appears as soon as the learning
pulses are supplied from the terminal 143 of the learning pulse
generator 14, and since the transistor G.sub.15 is cut off unless
the bistable multivibrator BS.sub.8 is delivering "1," the position
of the output "1" is shifted to the higher place in response to the
learning pulses.
The learning machine having a structure as described above operates
in a manner as described below. Input pattern information supplied
from the terminals 1, 2 and 3 is stored in the bistable
multivibrators 4, 5 and 6, and at the same time, written in the
memory 10. The desired outputs for the input patterns are also
written in the memory 10 from the terminal 11. This operation is
repeated for standard input patterns following the above-described
input patterns so that the information of all the standard patterns
is stored in the memory 10. When it is desired to make automatic
learning on the basis of this information so as to obtain the
desired output condition, the switch S.sub.1 in FIG. 3 is switched
over to urge the transistors G.sub.5, G.sub.6, G.sub.7 and G.sub.8
to conduct and to cut off the transistors G.sub.1, G.sub.2, G.sub.3
and G.sub.4. Each time the clock pulse is supplied from the trigger
pulse generator 12 to the memory 10, the stored information is
supplied to the learning pulse generator 14 and the bistable
multivibrators 4, 5 and 6 from the respective output terminals 101,
102, 103 and 104 of the memory 10. The information supplied to the
bistable multivibrators 4, 5 and 6 is weighted by the weight factor
selective circuits 7, 8 and 9, and is passed through the summing
circuit 15 to be applied to the decision circuit 16 wherein the sum
is compared with the threshold value W and the result appears at
the output terminal 17 as an output "+1" or "0." In this process,
the switch S.sub.3 in the threshold value selection circuit 18 is
connected to the output terminal 101 of the memory 10 so that the
threshold value W corresponds to the value "+1" or "0." Thus, the
decision circuit 16 has a function similar to the function of a
one-out-of-three decision element for the threshold values having a
dead zone therebetween and the output therefrom is classified under
a severe condition compared with the classification by a
one-out-of-two decision element. The actual output and the desired
output are compared with each other in the learning pulse generator
14. When the actual output does not coincide with the desired
output, the learning pulses and control signals are supplied to the
weight factor selective circuits 7, 8 and 9 so as to bring
coincidence therebetween, whereby the learning can proceed in the
manner of error correction. When the learning proves that the
actual output coincides with the desired output, the trigger pulse
generator 12 is actuated to draw out the next information from the
memory 10 by the clock pulse and a similar operation is carried
out. As the above operation is repeated, the actual output becomes
to always coincide with the desired output thereby completing the
learning. When discriminating any input pattern after the learning
is completed, the switch S.sub.3 in the threshold value selection
circuit 18 is switched over to the side giving the threshold value
W so that the decision circuit 16 acts as a conventional
one-out-of-two decision element.
* * * * *