U.S. patent number 3,638,189 [Application Number 05/007,784] was granted by the patent office on 1972-01-25 for simplified means of skipping selectable segments of a timed program.
This patent grant is currently assigned to Beckman Instruments, Inc.. Invention is credited to Kenneth W. Barr, Larry D. Gamache, Christopher F. Miller.
United States Patent |
3,638,189 |
Gamache , et al. |
January 25, 1972 |
SIMPLIFIED MEANS OF SKIPPING SELECTABLE SEGMENTS OF A TIMED
PROGRAM
Abstract
In a programmer for controlling the operation of a plurality of
segments in a multiple segment selector system that normally
sequences all segments in series, wherein a source of low-frequency
timing pulses is applied to a digital timer which sequentially
activates the segments, a simplified means for selectively
bypassing any number of said segments comprising a source of
high-frequency timing pulses, selector means for generating a
separate disable signal for each of the segments to be bypassed,
coincidence means responsive to the activation of each of the
segments and the selector means for generating a triggering signal
upon the simultaneous occurrence of the activation of a segment and
a disable signal for such segment, and means responsive to the
occurrence of a triggering signal for switching the input of the
digital timer from the low-frequency timing pulse source to the
high-frequency timing pulse source so that the segment to be
bypassed is executed at a very high speed relative to normal
operation whereby the timer is rapidly sequenced to the next
segment.
Inventors: |
Gamache; Larry D. (Yorba Linda,
CA), Miller; Christopher F. (Diamond Bar, CA), Barr;
Kenneth W. (La Habra, CA) |
Assignee: |
Beckman Instruments, Inc.
(N/A)
|
Family
ID: |
21728128 |
Appl.
No.: |
05/007,784 |
Filed: |
February 2, 1970 |
Current U.S.
Class: |
327/269 |
Current CPC
Class: |
G01N
30/88 (20130101); G05B 19/07 (20130101); G01N
2030/8804 (20130101); G05B 2219/25382 (20130101) |
Current International
Class: |
G01N
30/00 (20060101); G01N 30/88 (20060101); G05B
19/04 (20060101); G05B 19/07 (20060101); H04q
009/00 () |
Field of
Search: |
;340/147,163,413
;179/15A ;328/75,70,72 ;235/92K ;340/168 ;307/41.141.4 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Yusko; Donald J.
Claims
We claim:
1. In a programmer for controlling the sequential operation of a
plurality of output devices wherein low-frequency timing pulses are
applied to a digital timer which sequentially activates said output
devices, the improvement comprising means for selectively bypassing
any of said output devices, said means comprising:
a source of high-frequency timing pulses, the frequency of said
source of high-frequency timing pulses exceeding the highest rate
of which said output devices can function;
logic means operatively coupled to said output devices for
generating a triggering signal when an output device to be bypassed
is activated; and
means responsive to said triggering signal for switching the input
of said digital timer from said low-frequency timing pulses to said
high-frequency timing pulses whereby said digital timer is rapidly
sequenced to activate the next selected output device.
2. In a programmer according to claim 1, the improvement wherein
said logic means comprises:
selector means for generating a separate disable signal for each of
said output devices to be bypassed; and
coincidence means operatively coupled to said output devices and
said selector means for generating said triggering signal upon the
simultaneous occurrence of the activation of an output device and a
disable signal for such output device.
3. In a programmer according to claim 2, wherein said output
devices go true when activated, and wherein said disable signal is
a false signal, the improvement wherein said coincidence means
comprises:
a plurality of two-input AND gates, one for each output device,
each of said AND gates receiving one input from a corresponding
output device and one input from said selector means;
first and second OR gates, said first OR gate receiving the outputs
of said output devices, said second OR gate receiving the outputs
of said AND gates; and
means responsive to the outputs of said OR gates for generating
said triggering signal when the outputs of said first and second OR
gates are simultaneously true and false, respectively.
4. In a programmer according to claim 3, the improvement wherein
said means responsive to the outputs of said OR gates
comprises:
first and second two-input AND gates and an inverter, said first
AND gate receiving the outputs of said OR gates, said second AND
gate receiving the output of said first OR gate and the output of
said second OR gate via said inverter, said second AND gate
generating said triggering signal, said first AND gate generating a
signal when an output device to function is activated.
5. In a programmer according to claim 4, the improvement wherein
said switching means comprises:
a latch circuit, said latch circuit being triggered to a first
state by an output from said first AND gate and being triggered to
a second state by an output from said second AND gate; and
a multiplexer responsive to said latch circuit for coupling said
low-frequency timing pulses to said digital timer when said latch
circuit is in said first state and for coupling said high-frequency
timing pulses to said digital timer when said latch circuit is in
said second state.
6. In a programmer for controlling the sequential operation of a
plurality of output devices wherein low-frequency timing pulses are
applied to a digital timer which sequentially activates said output
devices, means for selectively skipping any of said output devices
comprising:
a source of high-frequency timing pulses, the frequency of said
source of high-frequency timing pulses exceeding the highest rate
at which said output devices can function;
means for selecting which of said output devices are to function
and which are to be skipped; and
means responsive to said selecting means for switching the input of
said digital timer from said low-frequency timing pulses to said
high-frequency timing pulses whereby said digital timer is rapidly
sequenced to activate the next selected output device.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a simplified means for skipping
selectable segments of a timed program and, more particularly, to a
means for selectively bypassing any number of segments in a
multiple segment selection system that normally sequences all
segments in series.
2. Description of the Prior Art
A wide variety of different types of scientific instruments include
a programmer arrangement for operating various functions associated
with the instrument in a predetermined time sequence. One such
instrument is a process gas chromatograph which separates and
measures the components in a gas mixture by passing the mixture
through a chromatographic column in a carrier stream of gas. In
such a process gas chromatograph, a quantity of sample gas from one
or more process streams is introduced into an analyzer having a gas
chromatographic column for separating sample constituents. The
various mechanical and electrical functions of the analyzer are
performed in a predetermined time sequence. These functions may
include the operation of valves for taking samples from the process
streams at certain times, the switching of valves for injecting the
samples into the chromatographic column, the operation of valves
for controlling the various chromatographic columns during
analysis, and the control of electrical switches for actuating the
attenuators and sensors for determining the sample constituents as
they enter a detector.
A typical programmer arrangement for a process gas chromatographic
analyzer as well as other scientific instruments includes a
conventional digital timer which is programmed to actuate the
various mechanical and electrical functions in a predetermined time
sequence. However, under some circumstances, it is desirable to be
able to skip certain programmed functions. In the past, the
requirement for selectively bypassing any one or more of certain
segments of the program has required extensive decoding logic which
has, in essence, changed the program to eliminate the unwanted
segments. This has resulted in a significant increase in the
complexity of the programming system.
SUMMARY OF THE INVENTION
According to the present invention, there is provided a simplified
method and means for selectively dropping and regaining any number
of segments in a multiple segment selection system that normally
sequences all segments in series. By the addition of a simple
coincidence circuit and a multiplexer, the present circuit causes
the digital timer to operate in a "count fast" mode, thereby
effectively skipping the functions within a segment that are not of
interest. In reality, no functions are skipped but are executed at
a very high speed relative to normal operation. Since performance
of the functions, in the case of a chromatograph analyzer, cannot
follow high speeds, they effectively appear not to function.
Briefly, the present means for selectively bypassing any number of
segments in a multiple segment selection system comprises a source
of high-frequency timing pulses, selector means for generating a
separate disable signal for each of the segments to be skipped,
coincidence means responsive to the activation of each of the
segments and the selector means for generating a triggering signal
upon the simultaneous occurrence of the activation of a segment and
a disable signal for such segment, and means responsive to the
occurrence of a triggering signal for switching the input of the
digital timer from the normal low-frequency timing pulse source to
the high-frequency timing pulse source whereby the timer is rapidly
sequenced to the next segment.
It is therefore an object of the present invention to provide a
method and means for dropping and regaining segments of a timed
program at will.
It is a further object of the present invention to provide a
simplified means for selectively bypassing any number of segments
in a multiple segment selection system that normally sequences all
segments in series.
It is a still further object of the present invention to provide a
programmer for a process gas chromatograph which permits the
selective skipping of any function that is not of interest.
It is another object of the present invention to provide a
simplified means of skipping selectable segments of a timed program
by causing the programmer to count fast through a segment to be
skipped.
Still other objects, features and attendant advantages of the
present invention will become apparent to those skilled in the art
from a reading of the following detailed description of the
preferred embodiment constructed in accordance therewith, taken in
conjunction with the accompanying drawings wherein:
BRIEF DESCRIPTION OF THE DRAWING
The sole FIGURE is a block diagram of a preferred form of means for
skipping selectable segments of a timed program constructed in
accordance with the teachings of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring now to the sole FIGURE of drawings, a conventional
digital programmer for a scientific instrument such as a process
gas chromatograph may include a normal low-frequency timing pulse
generator 10 connected to the input of a standard digital timer 11
which has a plurality of outputs connected to the inputs of one or
more time selectors, generally designated 12, which have the
ability of executing some work function at the outputs thereof. For
the purpose of explanation, the drawing shows 10 time selectors
grouped into three major segments. The first time selector for each
segment is identified by the numerals 1, 2 and 3, respectively,
whereas the remaining time selectors for each segment are
identified by the letters A through G. Such a circuit may be used
as the program timer for a process gas chromatograph in which a
quantity of sample gas from three process streams are to be
analyzed. In such case, time selectors 1, 2 and 3 would initiate
the operation of the valves for taking samples of the three process
streams and the time selectors corresponding to letters A through G
would initiate the various functions required to complete an
analysis of the corresponding stream.
Normally, such conventional digital programming apparatus operates
to activate the time selectors in sequence. No provision is made
for changing the sequence or skipping certain segments of the
program.
According to the present invention, there is provided a logic
circuit, generally designated 20, and a multiplexer 21 which
permits the selective bypassing of any number of segments at will.
More specifically, logic circuit 20 includes a plurality of
two-input AND-gates 22, 23 and 24, one for each time segment which
is to have the capability of being skipped. In the present case,
since the output functions to be performed are divided into major
time segments, there is only one AND gate for each of time
selectors 1, 2 and 3. However, in a more general circuit
arrangement, in which consecutive time selectors are independently
operable, there would be an AND gate for each of such independent
time selectors.
Each of AND-gates 22 through 24 receives as one input thereto the
output of one of time selectors 1-3, respectively. The other input
to each of AND-gates 22-24 is derived from a segment selector 25
which has a plurality of stages, numbered 1-3, one for each time
segment which is to have the capability of being skipped. Segment
selector 25 may simply include a plurality of manual or electronic
switches for selectively applying to the input of the corresponding
AND gate a true or false signal depending upon whether the
particular segment is to be retained or skipped. When a particular
segment is to be included in the sequence, the corresponding stage
of segment selector 25 is placed in the true position. On the other
hand, if a particular segment is to be skipped, the corresponding
stage of segment selector 25 is moved to the false position.
Logic circuit 20 also includes first and second OR-gates 26 and 27,
OR-gate 26 receiving at its inputs the outputs of each of time
selectors 1-3, and OR-gate 27 receiving at its inputs the outputs
of AND-gates 22-24. The output of OR-gate 26 is applied to first
inputs of a pair of two-input AND-gates 28 and 29. The output of
OR-gate 27 is applied to the other input of AND-gate 28 and through
an inverter 30 to the other input of AND-gate 29. The output of
AND-gate 28 is applied to a first input of a latch circuit 31
whereas the output of AND-gate 29 is applied to a second input of
latch circuit 31. The output of latch circuit 31 is applied to the
control input of multiplexer 21 which also receives the outputs of
low-frequency timing pulse generator 10 and a high-frequency timing
pulse generator 32. Multiplexer 21 may be an electronic device for
selectively applying the output of either generator 10 or generator
32 to digital timer 11, depending upon the state of latch circuit
31.
In operation, the outputs of time selectors 1, 2 and 3 are normally
false except when they are activated by digital timer 11 to perform
their particular work function. At that time, the output of the
activated time selector goes true. In addition, AND-gates 22-24
normally receive true inputs from segment selector 25 if the
segment is to be permitted to operate.
Assume, for example, that stages 1 and 3 of segment selector 25 are
true so that time selectors 1 and 3 are to function and that stage
2 of segment selector 25 is false so that time selector 2 is to be
skipped. When time selector 1 goes true, a true signal is applied
through OR-gate 26 to the first inputs of AND-gates 28 and 29. A
similar true signal is applied to the first input of AND-gate 22.
Since stage 1 of segment selector 25 is true, the output of
AND-gate 22 goes true and a true signal is applied to OR-gate 27.
Since time selectors 2 and 3 are, during the actuation of time
selector 1, false, no signals appear at the outputs of AND-gates 23
and 24.
The true signal from AND-gate 22 passes through OR-gate 27 to the
second input of AND-gate 28. Since both inputs to AND-gate 28 are
now true, latch circuit 31 receives a true signal at its first
input thereby connecting the output of multiplexer 21 to a
low-frequency timing pulse generator 10 and the timing sequence
continues as normal. It should also be noted that the true signal
from OR-gate 27 is inverted by inverter 30 before being applied to
the second input of AND-gate 29. Since AND-gate 29 receives one
true and one false signal, its output remains false thereby
disabling the second input of latch circuit 31.
When the count in digital timer 11 activates time selector 2, its
output goes true applying a true signal through OR-gate 26 to the
first inputs of AND-gates 28 and 29. A similar true input is
applied to the first input of AND-gate 23. However, since stage 2
of segment selector 25 is false, the true signal at the first input
of AND-gate 23 is inhibited and OR-gate 27 receives a false signal
at each of its inputs. As a result, the output of OR-gate 27
remains false disabling AND-gate 28. On the other hand, the false
signal at the output of OR-gate 27 is inverted by inverter 30 which
applies a true signal to the second input of AND-gate 29. Since
both inputs of AND-gate 29 are now true, latch circuit 31 receives
a true signal at its second input and latch circuit 31 changes
state. This change of state causes multiplexer 21 to connect its
output to high-frequency timing pulse generator 32. Digital timer
11 therefore begins counting at a very high speed relative to
normal speed. Since the functions in the case of a process gas
chromatograph cannot follow high speeds, they appear not to
function. On the other hand, if a particular function must be
firmly disabled, the output of latch circuit 31 is available for
such a purpose.
Digital timer 11 continues to count at very high speed until time
selector 3 is activated. At this time, AND-gate 24 receives true
signals at both of its inputs, applying such a true signal through
OR-gate 27 to AND-gate 28. AND-gate 28 receives a second true
signal from time selector 3 via OR-gate 26. As a result, AND-gate
28 causes latch circuit 31 to revert back to its initial state
which switches multiplexer 21 back to low-frequency timing pulse
generator 10.
It can therefore be seen that in accordance with the present
invention there is provided a simplified method and means for
selectively dropping and regaining any number of segments in a
multiple segment selection system that normally sequences all
segments in series. By the addition of a simple logic circuit 20
and a multiplexer 21, the present circuit causes digital timer 11
to operate in a "count fast" mode, thereby effectively skipping the
functions within a segment that are not of interest. In reality, no
functions are skipped but are executed at a very high speed
relative to normal operation. Since the functions of many
instruments, such as a process gas chromotograph, cannot follow
high speeds, they effectively appear not to function.
While the invention has been described with respect to a preferred
physical embodiment constructed in accordance therewith, it will be
apparent to those skilled in the art that various modifications and
improvements may be made without departing from the scope and
spirit of the invention.
* * * * *